WO2014020389A1

WO2014020389A1 - Methods of forming semiconductor structures including a conductive interconnection, and related structures

Info

Publication number: WO2014020389A1
Application number: PCT/IB2013/001489
Authority: WO
Inventors: Mariam Sadaka; Bernard Aspar; Chrystelle Lagahe Blanchard
Original assignee: Soitec
Priority date: 2012-07-31
Filing date: 2013-07-08
Publication date: 2014-02-06

Abstract

Methods are used to form semiconductor structures and microelectromechanical system (MEMS) devices that include an electrical interconnection. One or more trenches are formed in a doped semiconductor substrate to form at least one doped semiconductor element defined by the one or more trenches, a substrate is attached to the doped semiconductor substrate and to the at least one doped semiconductor element, and material is removed from the doped semiconductor substrate to expose the one or more trenches and to isolate the at least one doped semiconductor element from adjacent portions of the doped semiconductor substrate. Semiconductor structures and MEMS devices including an electrical interconnection are formed by such methods. Semiconductor structures and MEMS devices include transducers formed from a doped semiconductor material.

Description

METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING A CONDUCTIVE INTERCONNECTION, AND RELATED STRUCTURES

TECHNICAL FIELD

[0001] The present disclosure relates to methods of manufacturing semiconductor structures that include one or more electrically conductive interconnections between features associated with a substrate. In particular embodiments, the present disclosure relates to methods of forming microelectromechanical system (MEMS) devices including electrically conductive interconnections therein, and to related structures and devices fabricated using such methods.

BACKGROUND

[0002] Semiconductor structures are structures that are used or formed in the fabrication of semiconductor devices. Semiconductor devices include, for example, electronic signal processors, electronic memory devices, photoactive devices, and microelectromechanical system (MEMS) devices. Such structures and materials often include one or more semiconductor materials (e.g., silicon, germanium, a III-V semiconductor material, etc.), and may include at least a portion of an integrated circuit.

[0003] MEMS devices are small devices that have both physically active features and electrically active features. The active features of MEMS devices may have micro-scale and/or nano-scale features. For example, MEMS devices may have active features having cross-sectional dimensions of about 100 μιτι or less.

[0004] MEMS devices often comprise a transducer that converts electrical energy in the form of, for example, a voltage or current into kinetic energy (physical energy) in the form of, for example, mechanical deflection or vibrations, or that converts kinetic energy into electrical energy. For example, MEMS devices include resonators that generate resonant mechanical vibrations responsive to an applied electrical signal. MEMS devices also include sensors that are used to sense physical phenomena (e.g., deflection, pressure, vibrations, etc.), by sensing variations in an electrical signal caused by the physical phenomena. Some MEMS devices may be characterized as both resonators and sensors. [0005] Many types of MEMS resonators are known in the art and include, for example, plate acoustic wave resonators, flexural mode resonators, bulk acoustic wave (BAW) resonators, surface acoustic wave (SAW) resonators, and film bulk acoustic resonators (FBARs). It is known to use MEMS resonators in timing circuits, gyroscopes, or accelerometers, for example.

BRIEF SUMMARY

[0006] This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] In some embodiments, the present disclosure includes methods of forming semiconductor structures that include an electrical interconnection. In accordance with such methods, material is selectively removed from a doped semiconductor substrate to form one or more trenches and to form at least one doped semiconductor element defined by the one or more trenches. A substrate is attached to the doped semiconductor substrate and to the at least one doped semiconductor element. Material is removed from the doped semiconductor substrate to expose the one or more trenches and to physically and electrically isolate the at least one doped semiconductor element from adjacent portions of the doped semiconductor substrate.

[0008] In additional embodiments, the present disclosure includes methods of forming a MEMS device. In accordance with such methods, trenches and a transducer cavity recess are formed in a doped semiconductor substrate to form doped semiconductor elements between the transducer cavity recess and adjacent trenches. An integrated circuit (IC) structure is attached to the doped semiconductor substrate and to the doped semiconductor elements. Material is removed from a side of the doped semiconductor substrate opposite the attached IC structure, and the doped semiconductor elements are physically and electrically isolated from adjacent portions of the doped semiconductor substrate.

[0009] In some embodiments, the present disclosure includes semiconductor structures that include a doped semiconductor substrate and a discrete doped semiconductor element physically and electrically isolated from adjacent portions of the doped semiconductor substrate by at least one trench. The doped semiconductor substrate includes a first major surface on a first side thereof and a second major surface on a second, opposing side thereof. The discrete doped semiconductor element forms an electrical interconnection between a first electrical feature associated with the first major surface of the doped semiconductor substrate and a second electrical feature associated with the second major surface of the doped semiconductor substrate.

[0010] In additional embodiments, the present disclosure includes an at least partially formed MEMS device that includes a structure including integrated circuitry and a doped semiconductor substrate attached to the structure including integrated circuitry. The structure including integrated circuitry includes at least one first conductive pad operatively coupled to integrated circuitry within the structure and second conductive pads operatively coupled to the integrated circuitry. The doped semiconductor substrate includes at least one first doped semiconductor element physically and electrically contacting the at least one first conductive pad. The doped semiconductor substrate also includes second doped semiconductor elements respectively physically and electrically contacting the second conductive pads. A conductive material formed from the doped semiconductor substrate physically and electrically connects the second doped semiconductor elements.

[0011] In additional embodiments, the present disclosure includes methods of forming a semiconductor device comprising an integrated circuit and a MEMS device operatively coupled to the integrated circuit. The methods include forming an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate. At least a portion of an integrated circuit is fabricated on the first major surface of the substrate, and a doped semiconductor material is provided on the second major surface of the substrate. Material is selectively removed from the doped semiconductor material to form a transducer of a MEMS device electrically coupled to the integrated circuit using the at least one electrically conductive via. /

[0012] ^' In additional embodiments, the present disclosure includes semiconductor structures including at least a portion of an integrated circuit formed on a first major surface of a substrate, a doped semiconductor material bonded to a second major surface of the substrate opposite the first major surface, and a conductive via extending through the substrate and electrically coupling the doped semiconductor material to the at least a portion of the integrated circuit. The doped semiconductor material is at least partially covering a transducer cavity recess formed in the second major surface of the substrate. [0013] In some embodiments, the present disclosure includes additional methods of forming a semiconductor device comprising an integrated circuit ana" a MEMS device operatively coupled to the integrated circuit. The methods include fabricating at least a portion of an integrated circuit on a first major surface of a substrate, providing a dielectric material over the at least a portion of the integrated circuit on a side thereof opposite the substrate, and providing a doped semiconductor material over the dielectric material on a side thereof opposite the substrate.

[0014] In additional embodiments, the present disclosure includes semiconductor structures comprising at least a portion of an integrated circuit formed on a first major surface of a substrate, a doped semiconductor material bonded to a second major surface of the substrate opposite the first major surface, and a conductive via extending through the substrate and electrically coupling the doped semiconductor material to the at least a portion of the integrated circuit. The doped semiconductor material is at least partially covering a transducer cavity recess formed in the second major surface of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] While the specification concludes with claims particularly pointing out and distinctly claiming what are regarded as embodiments of the invention, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain examples of embodiments of the disclosure when read in conjunction with the accompanying drawings, in which:

[0016] FIGS. 1 through 5 illustrate an example of a method that may be used to form a semiconductor device comprising a doped semiconductor element defining an electrical interconnection (e.g., via), wherein the doped semiconductor element is formed by removing material from a doped semiconductor substrate;

[0017] FIG. 1 is a simplified cross-sectional view illustrating a doped semiconductor substrate;

[0018] FIG. 2 illustrates one or more trenches formed in the doped semiconductor substrate of FIG. 1 with a doped semiconductor element defined by the one or more trenches;

[0019] FIG. 3 illustrates a first substrate attached to the doped semiconductor substrate;

[0020] FIG. 4 illustrates the doped semiconductor substrate and the first substrate after a portion of the doped semiconductor substrate has been removed; [0021] FIG. 5 illustrates a semiconductor device including the doped semiconductor substrate, the first substrate, and a second substrate attached to the doped semiconductor substrate opposite the first substrate, the doped semiconductor element defining an electrical interconnection (e.g., via) between the first substrate and the second substrate;

[0022] FIGS. 6 through 12 illustrate an example of a method that may be used to form a microelectromechanical system (MEMS) device comprising at least a portion of an integrated circuit (IC) structure and a transducer operatively coupled to the IC structure, including at least one doped semiconductor element defining an electrical interconnection formed by a similar method to that described with reference to FIGS. 1 through 5;

[0023] FIG. 6 is a simplified cross-sectional view illustrating a doped semiconductor substrate having one or more trenches formed therein and one or more first doped semiconductor elements defined by the one or more trenches, and having at least one transducer cavity recess formed therein;

[0024] FIG. 7 illustrates a semiconductor-on-insulator-type (SOI-type) substrate similar to the doped semiconductor substrate of FIG. 6;

[0025] FIG. 8 illustrates an IC structure attached to the doped semiconductor substrate of

FIG. 6;

[0026] FIG. 9 illustrates the doped semiconductor substrate and the IC structure after a portion of the doped semiconductor substrate has been removed, forming a MEMS structure;

[0027] FIG. 10 illustrates the structure of FIG. 9 after further processing, including a transducer formed from a portion of the doped semiconductor substrate;

[0028] FIG. 1 1 illustrates a MEMS device including a cap structure attached to the structure of FIG. 10 on an opposite side of the doped semiconductor substrate from the IC structure;

[0029] FIG. 12 illustrates a MEMS device including a structure or device attached to the structure of FIG. 1 1 on a side thereof opposite the cap structure;

[0030] FIG. 13 illustrates a MEMS device similar to the MEMS device of FIG. 12, showing an alternative method of connecting components of the MEMS device;

[0031] FIGS. 14 through 25 illustrate an example of a method that may be used to form a semiconductor device comprising at least a portion of an integrated circuit and a MEMS device operatively coupled to the integrated circuit, wherein a transistor of the MEMS device is fabricated from a doped semiconductor material bonded to the integrated circuit; [0032] FIG. 14 is a simplified cross-sectional view illustrating a substrate;

[0033] FIG. 15 illustrates electrically conductive vias extending partially through the substrate of FIG. 14 from a first major surface of the substrate toward a second major surface of the substrate;

[0034] FIG. 16 illustrates transistors formed at the first major surface of the substrate;

[0035] FIG. 17 illustrates conductive features fabricated over the transistors of FIG. 16 and communicating electrically with the transistors and the electrically conductive vias;

[0036] FIG. 18 illustrates a structure formed by thinning the substrate of FIG. 17 by removing material from the second major surface of the substrate;

[0037] FIG. 19 illustrates a transducer cavity recess formed in the second major surface of the substrate of FIG. 18;

[0038] FIG. 20 illustrates a semiconductor-on-insulator-type structure bonded to the second major surface of the substrate of FIG. 19;

[0039] FIG. 21 illustrates a layer of doped semiconductor material transferred from the semiconductor-on-insulator-type structure to the second major surface of the substrate;

[0040] FIG. 22 illustrates a structure formed by processing the transferred layer of doped semiconductor material as shown in FIG. 21 to form a transducer comprising a portion of the layer of doped semiconductor material;

[0041] FIG. 23 illustrates a cap structure, bonded over the second major surface of the substrate, the layer of doped semiconductor material, and the transducer comprising a portion of the layer of doped semiconductor material;

[0042] FIG. 24 illustrates electrically conductive contacts formed over the first major surface of the substrate;

[0043] FIG. 25 illustrates the structure of FIG. 24 structurally and electrically coupled to a higher level substrate using the electrically conductive contacts formed over the first major surface of the substrate;

[0044] FIGS. 26 through 32 illustrate another example of a method that may be used to form a semiconductor device comprising at least a portion of an integrated circuit and a MEMS device operatively coupled with the integrated circuit, wherein a transistor of the MEMS device is fabricated from a doped semiconductor material bonded to the integrated circuit; [0045] FIG. 26 illustrates a dielectric material over active layers of the transistors and conductive features of the structure of FIG. 18;

[0046] FIG. 27 illustrates conductive vias formed through the dielectric material and a transducer cavity recess formed in a major surface of the dielectric material;

[0047] FIG. 28 illustrates an SOI-type structure bonded to the exposed major surface of the dielectric material of the structure of FIG. 27;

[0048] FIG. 29 illustrates a relatively thin layer of material transferred from the SOI-type structure to the dielectric material over the active layers;

[0049] FIG. 30 illustrates a structure formed by processing the transferred thin layer of material shown in FIG. 29 to form a resonator comprising a portion of the thin layer of material;

[0050] FIG. 31 illustrates a cap structure bonded to the thin layer of material and extending over the resonator comprising a portion of the thin layer of material and over the first major surface of the substrate; and

[0051] FIG. 32 illustrates the structure of FIG. 31 structurally and electrically coupled to a higher level substrate using electrically conductive contacts formed over the second major surface of the substrate and in electrical contact with the conductive vias extending through the substrate.

DETAILED DESCRIPTION

[0052] The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure.

[0053] As used herein, the term "substantially," in reference to a given parameter, property, or condition, means to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met within a degree of variance, such as within acceptable manufacturing tolerances.

[0054] As used herein, any relational term, such as "first," "second," "third," "over," "on," "lower," "upper," etc., is used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.

[0055] ' The present disclosure includes methods that may be used to form semiconductor devices that include one or more electrically conductive elements to provide one or more electrical interconnections (e.g., vias) between features associated with (e.g., on, at least partially in, or connected to) two opposing sides of a substrate. In particular embodiments, the present disclosure relates to methods of forming microelectromechanical system (MEMS) devices including such electrically conductive elements, and to related structures and devices fabricated using such methods. Examples of such methods, structures, and devices are disclosed in further detail below.

[0056] FIGS. 1 through 5 illustrate a non-limiting example of a method for forming a semiconductor device that includes removal of material from a doped semiconductor substrate to form at least one doped semiconductor element. The doped semiconductor element may define an electrical interconnection (e.g., via) between features associated with two opposing sides of the doped semiconductor substrate, such as between conductive members (e.g., pads) on respective substrates attached to opposite sides of the doped semiconductor substrate, for example.

[0057] FIG. 1 is a simplified cross-sectional view illustrating a doped semiconductor substrate 100. The doped semiconductor substrate 100 may include a semiconductor material (e.g., silicon, germanium, a 111- V semiconductor material, silicon carbide, an organic semiconductor, etc.) and at least one dopant sufficient to render the doped semiconductor substrate 100 electrically conductive. By way of example and not limitation, the doped semiconductor substrate 100 may include silicon that is highly doped with one or more p-type dopants (e.g., boron) or one or more n- type dopants (e.g., phosphorous, arsenic), as is known in the art. The semiconductor material of the doped semiconductor substrate 100 may be substantially crystalline (e.g., polycrystalline or monocrystalline) or substantially amorphous (e.g., glass-like). In some embodiments, the doped semiconductor substrate 100 may be formed by implanting the dopants into a previously formed semiconductor material, such as by ion bombardment. In other embodiments, forming the doped semiconductor substrate 100 may include forming (e.g., depositing, growing) a semiconductor material that includes one or more dopants at formation. The doped semiconductor substrate 100 may at least substantially be a single, generally homogeneous material, or the doped semiconductor substrate 100 may include a multi-layer structure.

[0058] Although the entire doped semiconductor substrate 100 is shown in the drawings as being doped, the present disclosure is not so limited. For example, in some embodiments, the doped semiconductor substrate 100 may be a portion of a larger substrate (not shown), other portions of which are not doped. In some embodiments, only an upper portion (when viewed in the perspective of FIG. 1) of the doped semiconductor substrate 100 in which an electrical interconnection is to be formed (described in more detail below) may be doped so as to be electrically conductive, while a lower portion may remain substantially undoped or at least less doped than the upper portion. In some embodiments, the doped semiconductor substrate 100 may be or be a part of a multi-layer substrate, such as a semiconductor-on-insulator-type (SOI-type) substrate.

[0059] Referring to FIG. 2, one or more trenches 102 may be formed in the doped semiconductor substrate 100 to form one or more doped semiconductor elements 104 therebetween. One doped semiconductor element 104 is shown in FIG. 2 for simplicity, although any number of doped semiconductor elements 104 may be formed in the doped semiconductor substrate 100 by altering a pattern of the one or more trenches 102, depending on the number of electrical interconnections to be formed. The one or more trenches 102 may be formed by conventional material removal techniques, such as by a photolithographic masking and etching operation, as will be understood by one of ordinary skill in the art. In such embodiments, a mask (not shown) may be formed over the doped semiconductor substrate 100 and selectively patterned to form apertures through the mask in a location where the one or more trenches 102 are to be formed. After forming the patterned mask, portions of the doped semiconductor substrate 100 that are exposed through the apertures of the mask may be removed using an etching operation, such as a dry reactive ion etching operation or a wet chemical etching operation, to form the one or more trenches 102. After the one or more trenches 102 are at least partially formed, the mask may be removed. In some

embodiments, the one or more trenches 102 may remain open {e.g., filled with air), as shown in the drawings of the present disclosure. In other embodiments, the one or more trenches 102 may, optionally, be at least partially filled with a dielectric material (not shown) to mechanically support and stabilize the doped semiconductor element 104. Depending on the pattern formed by the one or more trenches 102, the doped semiconductor element 104 may be configured as, for example, one or more of a pillar, a column, a line, and an irregularly-shaped body.

[0060] As shown in FIG. 3, a first substrate 1 10 may be attached to the doped

semiconductor substrate 100. By way of example and not limitation, the first substrate 1 10 may be an integrated circuit device, a semiconductor device {e.g. , a memory device, a logic device), a carrier substrate, a printed circuit board (PCB), an interposer, a MEMS device, a MEMS cap structure, a combination thereof, or a portion thereof. The first substrate 1 10 may include a first conductive member 1 12 associated therewith, such as a bond pad, an electrically conductive line or trace, an electrically conductive via, an electrical contact, etc., which may be positioned over and in contact with the doped semiconductor element 104. The first conductive member 112 may comprise, for example, a metal, a metal alloy, or a semiconductor material (e.g., doped polysilicon). The first conductive member 1 12 may be electrically coupled to the doped semiconductor element 104 to form a continuous electrical pathway therebetween. Stated another way and depending on the material composition of the first conductive member 1 12, an interface between the first conductive member 112 and the doped semiconductor element 104 may be characterized by a metal-to-doped semiconductor connection, a doped semiconductor-to-doped semiconductor connection, a solder-to-doped semiconductor connection, or a conductive epoxy-to-doped semiconductor connection, for example. Thus, a physical and electrical connection may be formed between the doped semiconductor element 104 and the first conductive member 1 12 of the first substrate 110, as well as a physical connection between other portions of the first substrate 1 10 and the doped semiconductor substrate 100.

[0061] The first substrate 1 10 may be attached to the doped semiconductor substrate 100 using, for example, a direct bonding process, a thermocompression bonding process, a non- thermocompression bonding process, or a combination thereof. Regardless of the technique used to attach the first substrate 1 10 to the doped semiconductor substrate 100, the attachment should provide sufficient mechanical stability to avoid delamination at the attachment interface during subsequent operations, such as during a material removal operation to be described in more detail below.

[0062] In some embodiments, the first substrate 1 10 may be attached to a major surface of the doped semiconductor substrate 100 using a direct bonding operation. The direct bonding operation may form direct atomic bonds between the first substrate 1 10 and the doped

semiconductor substrate 100. The nature of the atomic bonds between the first substrate 1 10 and the doped semiconductor substrate 100 will depend upon the material compositions at the surfaces of each of the first substrate 1 10 and the doped semiconductor substrate 100.

[0063] In some embodiments, the direct bond between the bonding surface of the first substrate 1 10 and the bonding surface of the doped semiconductor substrate 100 may be established by forming each of the bonding surface of the first substrate 1 10 and the bonding surface of the doped semiconductor substrate 100 to have relatively smooth surfaces, and subsequently abutting the bonding surfaces together and initiating propagation of a bonding wave therebetween. For example, each of the bonding surface of the first substrate 1 10 and the bonding surface of the doped semiconductor substrate 100 may be formed to have a root mean square surface roughness (RRMS) of about two nanometers (2.0 nm) or less, about one nanometer (1.0 nm) or less, or even about one-quarter of a'nanometer (0.25 nm) or less. Each of the bonding surface of the first substrate 1 10 and the bonding surface of the doped semiconductor substrate 100 may be smoothed using at least one of a mechanical polishing operation and a chemical etching operation. For example, a chemical-mechanical planarization (CMP) operation may be used to planarize and/or reduce the surface roughness of each of the bonding surface of the first substrate 1 10 and the bonding surface of the doped semiconductor substrate 100.

[0064] After smoothing the bonding surfaces, the bonding surfaces optionally may be cleaned and/or activated using processes known in the art. Such an activation process may be used to alter the surface chemistry at the bonding surfaces in a manner that facilitates the bonding process and/or results in the formation of a stronger bond.

[0065] The bonding surfaces may be brought into direct physical contact with one another, and pressure may be applied in a localized area across the bonding interface. Inter-atomic bonds may be initiated in the vicinity of the localized pressure area, and a bonding wave may propagate across the interface between the bonding surfaces.

[0066] Optionally, an annealing process may be used to strengthen the bond. Such an annealing process may comprise heating the first substrate 1 10 and the doped semiconductor substrate 100 in a furnace at a temperature of between about one hundred degrees Celsius (100°C) and about four hundred degrees Celsius (400°C) for a time of between about two minutes (2 mins.) and about fifteen hours (15 hrs.).

[0067] In some embodiments, a direct bond between the first substrate 1 10 and the doped semiconductor substrate 100 may be accomplished through a bonding material (not shown) being formed on the bonding surface of one or both of the first substrate 1 10 and the doped semiconductor substrate 100. In such embodiments, the interface between the first substrate 1 10 and the doped semiconductor substrate 100 may include atomic bonds between the first substrate 1 10 and the bonding material and atomic bonds between the bonding material and the doped semiconductor substrate 100.

[0068] Referring to FIG. 4, after the first substrate 1 10 is attached to the doped semiconductor substrate 100, a portion of the doped semiconductor substrate 100 opposite the first substrate 1 10 may be removed to expose the one or more trenches 102. By way of example and not limitation, the doped semiconductor substrate 100 may be thinned by an abrasive planarization operation, such as a CMP operation. By way of another example, the portion of the doped semiconductor substrate 100 may be removed by an etching operation, such as a dry etching operation or a wet etching operation. Removing the portion of the doped semiconductor substrate 100 to expose the one or more trenches 102 may physically and electrically isolate the doped semiconductor element 104 from adjacent portions of the doped semiconductor substrate 100.

Thus, after the portion of the doped semiconductor substrate 100 is removed to expose the one or more trenches 102, the doped semiconductor element 104 may be a discrete conductive structure forming a conductive path from a first side of the doped semiconductor substrate 100 to another, opposite side of the doped semiconductor substrate 100.

[0069] As shown in FIG. 5, a second substrate 120 may be attached to the doped semiconductor substrate 100 on a side thereof opposite the first substrate 1 10. By way of example and not limitation, the second substrate 120 may be an integrated circuit device, a semiconductor device, a carrier substrate, a PCB, an interposer, a MEMS device, a MEMS cap structure, a combination thereof, or a portion thereof. The second substrate 120 may include a second conductive member 122 associated therewith, such as a bond pad, an electrically conductive line or trace, an electrically conductive via, an electrical contact, etc., which may be positioned in contact with the doped semiconductor element 104 at an opposite end thereof from the first conductive member 1 12. The second conductive member 122 may comprise, for example, a metal, a metal alloy, or a semiconductor material (e.g., doped polysilicon). The second conductive member 122 may be electrically coupled to the doped semiconductor element 104 to form a continuous electrical pathway therebetween. Stated another way, and depending on the material composition of the second conductive member 122, an interface between the second conductive member 122 and the doped semiconductor element 104 may be characterized by a metal-to-doped semiconductor connection, a doped semiconductor-to-doped semiconductor connection, a solder-to-doped semiconductor connection, or a conductive epoxy-to-doped semiconductor connection, for example. Thus, a physical and electrical connection may be formed between the doped semiconductor element 104 and the second conductive member 122 of the second substrate 120, as well as a physical connection between the remaining portions of the second substrate 120 and the doped semiconductor substrate 100. [0070] The second substrate 120 may be attached to the doped semiconductor substrate 100 in substantially the same manner described above with reference to the attachment of the first substrate 1 10 to the doped semiconductor substrate 100. However, in some embodiments, the bond between the second substrate 120 and the doped semiconductor substrate 100 may not be as strong as the bond between the first substrate 1 10 and the doped semiconductor substrate 100, such as when subsequent operations to be performed after bonding are not anticipated to place high stress on the bonding interface. Of course, in other embodiments, the bond between the second substrate 120 and the doped semiconductor substrate 100 may be formed to exhibit at least the same bonding strength as the bond between the first substrate 1 10 and the doped semiconductor substrate 100, such as by direct bonding.

[0071] As shown in FIG. 5, a semiconductor device 130 may include an electrical interconnection (e.g., a via) comprising the doped semiconductor element 104 electrically connecting the first conductive member 1 12 associated with (e.g., on, at least partially in, or connected to) a first side of the doped semiconductor substrate 100 and the second conductive member 122 associated with a second side of the doped semiconductor substrate 100 opposite the first side. As described above, the doped semiconductor element 104 may be formed by one or more material removal operations. For example and as described above, the doped semiconductor element 104 may be formed by removing material from the one or more trenches 102 in the doped semiconductor substrate 100. Thereafter, additional material may be removed from the doped semiconductor substrate 100 (e.g., the doped semiconductor substrate 100 may be thinned) to expose the one or more trenches 102 and isolate the doped semiconductor element 104 from adjacent material of the doped semiconductor substrate 100, as explained above. Although only one doped semiconductor element 104 forming one electrical interconnection is shown in FIG. 5, the present disclosure also encompasses a semiconductor device including a plurality of doped semiconductor elements 104 forming a plurality of electrical interconnections, each formed and functioning in the same or a similar manner to that described above.

[0072] FIGS. 6 through 12 illustrate an example of a method that may be used to form a MEMS device comprising an integrated circuit (IC) structure and a transducer operatively coupled to the IC structure, including at least one doped semiconductor element defining an electrical interconnection formed by a similar method to that described in FIGS. 1 through 5. [0073] Referring to FIG. 6, a doped semiconductor substrate 200 may be similar in material composition and formation to the doped semiconductor substrate 100 of FIG. 1. A plurality of trenches 202 may be formed in the doped semiconductor substrate 200, resulting in first doped semiconductor elements 204, essentially as described above with reference to the formation of the one or more trenches 102 and the resulting doped sem iconductor elements 104 of FIG. 2. In some embodiments, the trenches 202 may be at least partially filled with a dielectric material (not shown), such as to mechanically support and stabilize and the first doped semiconductor elements 204. However, in some embodiments, the trenches 202 may remain open (i.e., filled with air), as shown in the drawings of the present disclosure.

[0074] A transducer cavity recess 206 may also be formed in the doped semiconductor substrate 200 by a material removal operation, such as by a photolithographic masking and etching operation, for example. The transducer cavity recess 206 may be formed prior to, simultaneously with, or after forming the trenches 202. The- transducer cavity recess 206 is ultimately used to form at least a portion of a transducer cavity in which at least a portion of a transducer of a MEMS device is to be disposed, as will be described in more detail below. The transducer cavity recess 206 may have any desirable size and shape, and the desired size and shape may be at least partially dependent on the type of transducer to be formed. In embodiments in which the transducer to be formed comprises a resonator, the frequencies at which the resonator is to resonate may be at least partially dependent on the size and shape of the transducer cavity recess 206. Therefore, the size and/or shape of the transducer cavity recess 206 may be selected to at least partially tailor (e.g., tune) the resonance of the transducer to be formed. In some embodiments, the transducer cavity recess 206 may have a depth that is less than a depth of the trenches 202, as shown in FIG. 6. The formation of the transducer cavity recess 206 and the immediately adjacent trenches 202 may result in a second doped semiconductor element 208 proximate each lateral side of the transducer cavity recess 206.

[0075] Although only one transducer cavity recess 206 with its associated trenches 202 is shown in FIG. 6 for simplicity, the present disclosure also includes forming the doped

semiconductor substrate 200 to include a plurality of transducer cavity recesses 206. For example, the doped semiconductor substrate 200 may, in some embodiments, be a wafer comprising the plurality of transducer cavity recesses 206 and associated trenches 202. Furthermore, with reference to one lateral side of FIG. 6 for simplicity, although one first doped semiconductor element 204 and one second doped semiconductor element 208 are shown, the present disclosure is not so limited. In some embodiments, the laterally outer trench 202 may be omitted to form one second doped semiconductor element 208, thus omitting any first doped semiconductor element 204. Conversely, in other embodiments, a plurality of trenches 202 may be formed on each lateral side of the transducer cavity recess 206, resulting in a plurality of first doped semiconductor elements 204. In some embodiments, the number of trenches 202 on one lateral side of the transducer cavity recess 206 may be different from the number of trenches 202 on an opposite lateral side. Such variations will depend on the number and pattern of electrical interconnections to be formed.

[0076] In additional embodiments, the doped semiconductor substrate 200 may be or be a part of an SOI-type substrate.

[0077] For example, FIG. 7 illustrates a structure similar to that of FIG. 6, but including an SOI-type substrate 710. The SOI-type substrate 710 includes a layer of doped semiconductor material 700. The layedof doped semiconductor material 700 is bonded to a volume of bulk material 712 with an intermediate material 714 between the layer of doped semiconductor material 700 and the bulk material 712. The intermediate material 714 may be relatively thin compared to the layer of doped semiconductor material 700 and the bulk material 712. As shown in FIG. 7, a plurality of trenches 702 similar to the plurality of trenches 202 of FIG. 6 may be formed in the layer of doped semiconductor material 700. The trenches 702 may extend entirely through the layer of doped semiconductor material 700 to the intermediate material 714, which may be employed as an etch-stop layer in an etching process used to form the trenches 702. The trenches 702 may define first doped semiconductor elements 704. A transducer cavity recess 706 similar to the transducer cavity recess 206 of FIG.6 may also be formed in the layer of doped semiconductor material 700. The transducer cavity recess 706 may extend only partially into the layer of doped semiconductor material 700 to leave a portion of the layer of doped semiconductor material 700 between the transducer cavity recess 706 and the intermediate material 714, as shown in FIG. 7. The transducer cavity recess 706 and the immediately adjacent trenches 702 may define a second doped semiconductor element 708 proximate each lateral side of the transducer cavity recess 706.

[0078] The SOI-type substrate 710 may be a structure having a structural configuration like that of conventional semiconductor-on-insulator (SOI) structures, although the layer of doped semiconductor material 700 may be doped sufficiently to be electrically conductive, and the intermediate material 714 may or may not comprise an insulator, material. The bulk material 712 may comprise any number of materials conventionally used for SOI substrates. Such materials include, for example, ceramics such as oxides (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), nitrides (e.g., silicon nitride), and carbides (e.g., silicon carbide), and/or semiconductor materials (e.g., silicon, germanium, a III-V semiconductor material, etc.). The bulk material 712 may comprise an amorphous material or a crystalline material (e.g., polycrystalline or

monocrystalline material). The intermediate material 714 may comprise a dielectric material, a metal material, or a semiconductor material. As a non-limiting example, the intermediate material 714 may comprise an oxide, such as silicon dioxide.

[0079] Any of the structures described with reference to FIGS. 6 and 7 may be attached to another structure comprising at least a portion of an integrated circuit. For example, referring to FIG. 8, the doped semiconductor substrate 200 may be attached to an integrated circuit (IC) structure 210. It is noted that the doped semiconductor substrate 200 is shown in FIG. 8 inverted from the view of FIG. 6. By way of example and not limitation, the IC structure 210 may include at least a portion of an integrated circuit, such as for providing electrical signals to and/or receiving electrical signals from a MEMS transducer to be formed as described in further detail below. In other words, the IC structure 210 includes at least one active device feature formed on or over and integrated with a substrate 142. Such active device features may include, for example, transistors 144, horizontally extending electrically conductive lines 146, vertically extending electrically conductive vias 148, and conductive pads 212A, 212B, and 212C. Other active device features include, for example, capacitors and resistors.

[0080] The active device features of the integrated circuit may be fabricated on and over a surface of the substrate 142. For example, the transistors 144 may be formed in, on, and/or over a surface of the substrate 142 using processes known in the art. As a non-limiting example, the transistors 144 may comprise metal oxide semiconductor field effect transistors (MOSFETs), and may embody complementary metal oxide semiconductor (CMOS) technology. The processes often employed in the art to fabricate such transistors 144 are often referred to in the art as "front-end-of- line" (FEOL) processes, and often involve processes carried out at temperatures greater than four hundred degrees Celsius (400° C). After forming the transistors 144, one or more additional layers of electrically conductive features used to electrically interconnect various features of the transistors 144 (e.g., sources, drains, and gates of the transistors 144) may be formed over the transistors 144 on a side thereof opposite the substrate 142. The conductive features may comprise one or more of laterally extending conductive lines 146 (e.g., traces), vertically extending electrically conductive vias 148, and electrically conductive pads 212A, 212B, and 212C. The conductive features may comprise electrically conductive material regions (e.g., copper, aluminum, tungsten, etc.) that are at least partially embedded in a dielectric material 152. The one or more layers of conductive features and surrounding dielectric material 152 may be formed in a layer-by-layer lithographic process over the transistors 144. In such processes, layers of dielectric material and layers of conductive material may be deposited and selectively patterned in an alternating manner to form the various conductive features and the dielectric material 152. The processes often employed in the art to fabricate these electrically conductive features are often referred to in the art as "back-end-of-line" (BEOL) processes, and often involve processes carried out at temperatures of about four hundred degrees Celsius (400° C) or less (although, in some embodiments, one or more initial layers of metal deposited as part of the BEOL processes may comprise tungsten, which may be deposited at temperatures up to about nine hundred degrees Celsius (900° C)).

[0081] The IC structure 210 may comprise a control circuit for a MEMS device to be formed comprising the IC structure 210. When attaching the IC structure 210 to the doped semiconductor substrate 200, the IC structure 210 may be aligned with the doped semiconductor substrate 200 such that first conductive pads 212 A of the IC structure 210 physically and electrically contact the first doped semiconductor elements 204, as described above with reference to the interconnection between the doped semiconductor element 104 and the first conductive

member 1 12 of FIG. 3. Similarly, second conductive pads 212B may physically and electrically contact the second doped semiconductor elements 208. Therefore, the IC structure 210 may be operatively coupled to one or more of the first and second doped semiconductor elements 204, 208 respectively through one or more of the first and second conductive pads 212A, 212B. Remaining portions of the doped semiconductor substrate 200 may be attached to the IC structure 210 using, for example, a direct bonding process, a thermocompression bonding process, a non- thermocompression bonding process, etc., as explained above with reference to the attachment of the first substrate 1 10 to the doped semiconductor substrate 100 of FIG. 3. Third conductive pads 212C may be bond pads for connection to a higher level substrate, and, therefore, may be located in a portion of the IC structure 210 that is not attached to or covered by the doped semiconductor substrate 200. Although only one third conductive pad 212C is shown in the drawings for simplicity, the IC structure 210 may include a plurality of third conductive pads 212C. As shown in FIG. 8, previously-exposed portions of the trenches 202 and of the transducer cavity recess 206 in the doped semiconductor substrate 200 may be covered by the IC structure 210.

[0082] Although the conductive pads 212A, 212B, and 212C are referred to herein as "pads," at least some of the conductive pads 212A, 212B, and 212C may be formed as conductive lines, traces, vias, or any other convenient shape.

[0083] Referring to FIG. 9, material may be removed from the doped semiconductor substrate 200 to expose the trenches 202 at an end thereof opposite the IC structure 210 and to form a MEMS structure 240. For example, the doped semiconductor substrate 200 may be thinned by an abrasive planarization operation, such as a CMP operation. In some embodiments, the doped semiconductor substrate 200 may be thinned by at least one of a dry etching operation and a wet etching operation. In some embodiments, such as the embodiment shown in FIG. 9, conductive material 214 of the doped semiconductor substrate 200 may remain adjacent the transducer cavity recess 206. Such embodiments may be formed by removing material from the transducer cavity recess 206 to a lesser depth than from the trenches 202, as described above with reference to FIG. 6, and/or by removing material from the doped semiconductor substrate 200 to expose the trenches 202 without exposing the transducer cavity recess 206. The conductive material 214 may later be used to form a transducer (e.g., a resonator, a sensor) of a MEMS device, as will be explained in more detail below.

[0084] After the doped semiconductor substrate 200 is thinned, the resulting MEMS structure 240 may include the IC structure 210 with the doped semiconductor substrate 200 attached thereto, the doped semiconductor substrate 200 including one or more first doped semiconductor elements 204, second doped semiconductor elements 208, and the transducer cavity recess 206 formed therein. The first doped semiconductor elements 204 may be physically and electrically isolated from adjacent portions of the doped semiconductor substrate 200 by the trenches 202. In some embodiments, the trenches 202 may be at least partially filled with a dielectric material (not shown). The first doped semiconductor elements 204 may physically and electrically contact the first conductive pads 212 A of the IC structure 210.

[0085] The second doped semiconductor elements 208 on opposing sides of the transducer cavity recess 206 may be connected together by the conductive material 214 over the transducer cavity recess 206, and the second doped semiconductor elements 208 may physically and electrically contact the second conductive pads 212B of the IC structure 210. The second doped semiconductor elements 208 and the associated conductive material 214 may be physically and electrically isolated from adjacent portions of the doped semiconductor substrate 200 by trenches 202. The first doped semiconductor elements 204, the second doped semiconductor elements 208, and the conductive material 214 may each be a portion of the doped semiconductor substrate 200. The first and second doped semiconductor elements 204, 208 and the conductive material 214 may be formed by selectively removing material from the doped semiconductor substrate 200, as described above. The third conductive pads 212C may be provided in the IC structure 210 as bond pads for electrical connection to a higher level substrate, as will be explained in more detail below.

[0086] Although the conductive material 214 has been described as being formed from the doped semiconductor substrate 200, the present disclosure is not so limited. For example, in some embodiments, the transducer cavity recess 206 may be formed to substantially the same depth as the trenches 202, and/or the doped semiconductor substrate 200 may be thinned to expose the transducer cavity recess 206 in addition to the trenches 202. Thus, each of the first and second doped semiconductor elements 204, 208 may be physically and electrically isolated from adjacent portions of the doped semiconductor substrate 200, and the conductive material 214 may be omitted. In such embodiments, another conductive material (e.g., a material including a metal, a material including a metal alloy, a material including a doped semiconductor, etc.) (not shown) may be attached to the second doped semiconductor elements 208 and positioned over the transducer cavity recess 206.

[0087] For example, a substrate (not shown) including the another conductive material may be positioned over the doped semiconductor substrate 200, and portions of the another conductive material may be removed and/or electrically isolated to form a portion extending between the second doped semiconductor elements 208 and over the transducer cavity recess 206. The portion of the another conductive material extending between the second doped semiconductor elements 208 and over the transducer cavity recess 206 may physically and electrically contact the second doped semiconductor elements 208, and may eventually form a portion of a transducer of a MEMS device, as will be described in more detail below.

[0088] In some embodiments, the MEMS structure 240 of FIG. 9 may be further processed to form a complete MEMS device, as will be explained with reference to FIGS. 10 through 13. Referring to FIG. 10, after the doped semiconductor substrate 200 is thinned and the first and second doped semiconductor elements 204, 208 are isolated from adjacent portions of the semiconductor substrate 200, one or more trenches and/or holes 216 may be formed in the conductive material 214 proximate the transducer cavity recess 206 to form a transducer 220 (e.g., a resonator, a sensor). The trenches and/or holes 216 may be formed by a conventional material removal operation, such as, by way of non-limiting example, a photolithographic masking and etching operation, an ablation (e.g., laser ablation) operation, etc. Resonance of the transducer 220 may at least partially depend on the number and configuration of the trenches and/or holes 216 therein. By way of example and not limitation, the trenches and/or holes 216 may selectively reduce the structural support for the portion of the conductive material 214 proximate the transducer cavity recess 206 to cause a change in the resonance of the transducer 220. Accordingly, the number and/or configuration of the trenches and/or holes 216 may be selected to at least partially tailor (e.g., tune) the resonance of the transducer 220. The particular structure of the transducer 220 is not critical to embodiments of the disclosure, and various configurations of transducers may be employed and selected by one of ordinary skill in the art.

[0089] As non-limiting examples, the transducer 220 may comprise a resonator, such as a plate acoustic wave resonator, a flexural mode resonator, a bulk acoustic wave (BAW) resonator, a surface acoustic wave (SAW) resonator, or a film bulk acoustic resonator (FBAR). In other embodiments, the transducer 220 may comprise a jgnsor configured to electrically sense mechanical deformation of, or vibrations in, the transducer 220. In some embodiments, the transducer 220 may function as both a resonator and a sensor.

[0090] Although the trenches and/or holes 216 are described as being formed after the doped semiconductor substrate 200 is thinned, other process flows are possible. For example, the trenches and/or holes 216 may be formed in the doped semiconductor substrate 200 prior to, in conjunction with, or after forming the transducer cavity recess 206, but prior to thinning the doped semiconductor substrate 200. In such embodiments, the thinning of the doped semiconductor substrate 200 may complete the formation of the transducer 220 since the trenches and/or holes 216 are formed prior to the thinning of the doped semiconductor substrate 200.

[0091] After transducer 220 including the trenches and/or holes 216 therein is formed, a cap structure 230 may be attached to the doped semiconductor substrate 200 on an opposite side thereof from the IC structure 210 to form a MEMS device 260, as shown in FIG. 1 1. The cap structure 230 may include another transducer cavity recess 236 located and configured to be disposed adjacent the transducer 220 on a side thereof opposite the transducer cavity recess 206 formed in the doped semiconductor substrate 200. The another transducer cavity recess 236 may be formed in the cap structure 230 using one or more material removal operations, like those previously discussed in relation to formation of the transducer cavity recess 206 in the doped semiconductor substrate 200, prior to attaching the cap structure 230 to the doped semiconductor substrate 200. The resonance of the transducer 220 may be at least partially dependent on the shape and size of the another transducer cavity recess 236. Therefore, the shape and/or size of the another transducer cavity recess 236 may be selected to at least partially tailor the resonance of the transducer 220.

[0092] The cap structure 230 may be attached to the doped semiconductor substrate 200 in the same or a similar manner to that described above with reference to the attachment of the second substrate 120 to the doped semiconductor substrate 100 of FIG. 5, such as by using, for example, a direct bonding process, a thermocompression bonding process, a non- thermocompression bonding process, etc.

[0093] Optionally, the cap structure 230 may include one or more conductive pads 232 associated with a side thereof against which the doped semiconductor substrate 200 is attached. For example, each of the first doped semiconductor elements 204 may physically and electrically contact one of the conductive pads 232 of the cap structure 230. By way of example and not limitation, the conductive pads 232 of the cap structure 230 may be or include one or more of a conductive bond pad, a conductive via extending through the cap structure 230, a conductive line or trace, etc. Each of the first doped semiconductor elements 204 may, therefore, form an electrical interconnection {e.g. , via) from the first conductive pads 212 A of the IC structure 210 to the conductive pads 232 of the cap structure 230 on an opposite side of the doped semiconductor substrate 200.

[0094] The second doped semiconductor elements 208 may provide an electrical interconnection between the transducer 220 and the second conductive pads 212B, as shown in FIG. 11. Thus, depending on the configuration and intended use of the transducer 220, the second doped semiconductor elements 208 may provide an electrical interconnection for inducing resonance and/or detecting resonance in the transducer 220. Optionally, the first doped

semiconductor elements 204 may also be electrically coupled to the transducer 220, such as for inducing and/or sensing resonance in a portion of the transducer 220 coupled to the first doped semiconductor elements 204. [0095] Accordingly, each of the first and second doped semiconductor elements 204, 208 may form an electrical interconnection between conductive elements (e.g., the first and second conductive pads 212A, 212B) associated with one side of the doped semiconductor substrate 200 and conductive elements (e.g., the conductive pads 232 and the transducer 220) associated with another, opposite side of the doped semiconductor substrate 200.

[0096] In some embodiments, the cap structure 230 may comprise, for example, an oxide (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), a nitride (e.g., silicon nitride), or a carbide (e.g., silicon carbide). In some embodiments, the cap structure 230 may comprise a ceramic material. In some embodiments, the cap structure 230 may comprise a semiconductor material (e.g., silicon, germanium, a III-V semiconductor material, etc.), a metal, or a metal alloy.

Additionally, the material of the cap structure 230 may be amorphous or crystalline (e.g., polycrystalline or monocrystalline).

[0097] The transducer 220 may be hermetically sealed between the cap structure 230 and the IC structure 210. In some embodiments, the cap structure 230 may be attached to the doped semiconductor substrate 200 under vacuum, such thata low pressure (e.g., at least substantially a vacuum) is maintained within the transducer cavity recesses 206, 236. In such embodiments, the trenches 202.may, optionally, be at least partially filled with a dielectric material to inhibit collapsing of the trenches 202 under atmospheric pressure on an outside of the structure.

Furthermore, an interior surface defining the another transducer cavity recess 236 may include a getter material (not shown) thereon configured to absorb gas molecules that may diffuse into the transducer cavity recesses 206, 236 over time, thus maintaining the low pressure within the transducer cavity recesses 206, 236 for an extended period of time. I n other embodi ments, the cap structure 230 may be attached to the doped semiconductor substrate 200 in an inert gas

environment, such that inert gas is . sealed within the transducer cavity recesses 206, 236. In yet further embodiments, the cap structure 230 may be attached to the doped semiconductor substrate 200 under ambient conditions, such that air is sealed within the transducer cavity recesses 206, 236.

[0098] The MEMS device 260 of FIG. 1 1 includes the transducer 220 and the IC structure 210 operatively coupled to the transducer 220. The MEMS device 260 may be configured for attachment to another structure or device for use in a higher level electrical device or system. For example, referring to FIG. 12, the MEMS device 260 may be attached to a structure or device 250, such as, for example, a PCB, an interposer, or a semiconductor device, to form a MEMS device 270. By way of example and not limitation, the IC structure 210 of the MEMS device 260 may be attached to the structure or device 250 by way of using, a direct bonding process, a

thermocompression bonding process, a non-thermocompression bonding process, etc. In addition, a wire bonding process may be used to electrically interconnect conductive features 252 (e.g., bond pads) of the structure or device 250 with the third conductive pads 212C. In particular, wires 254 may extend respectively between the conductive features 252 of the structure or device 250 and the third conductive pads 212C. In some embodiments, a first solder ball may be used to bond a first end of each wire 254 to the conductive feature 252 of the structure or device 250, and a second, solder ball may be used to bond an opposite second end of each wire 254 to the third conductive pad 212C. Wire bonding machines for use in performing such wire bonding operations are known in the art and are commercially available.

[0099] Referring to FIG. 13, a MEMS device 280 may alternatively be formed by structurally and electrically connecting a MEMS device 260A to a structure or device 250A through bumps or balls 258 of electrically conductive material (e.g., metal, metal alloy, etc.). The bumps or balls 258 may be arranged in a so-called "ball grid array" (BGA). The bumps or balls 258 may be electrically coupled to conductive vias 218 of an IC structure 21 OA of the MEMS device 260A. The IC structure 21 OA may be at least substantially similar to the IC structure 210 described above, except that the IC structure 21 OA may include the conductive vias 218 extending through a substrate 142 thereof and the third conductive pads 212C (FIG. 12) may be omitted, as shown in FIG. 13. The conductive vias 218 may provide a continuous electrical pathway to the active device features (e.g., one or more of the transistors 144, conductive lines 146, conductive vias 148, and electrically conductive pads 212A and 212B) of the IC structure 21 OA. Stated another way, the conductive vias 218 may be electrically connected to an integrated circuit formed in the IC structure 21 OA. The conductive vias 218 may be formed by conventional methods, such as by forming a plurality of holes through the substrate 142 and filling the plurality of holes with an electrically conductive material.

[00100] The bumps or balls 258 of electrically conductive material may be structurally and electrically coupled to electrical contacts 256 (e.g., bond pads) on the structure or device 250A. The structure or device 250A may comprise, for example, a higher level substrate, such as a PCB, an interposer, or a semiconductor device. In some embodiments, the bumps or balls 258 may comprise a solder alloy, and may be structurally and electrically coupled to the conductive vias 218 and to the electrical contacts 256 using a solder reflow process. In other embodiments, the bumps or balls 258 may comprise a metal or metal alloy having a relatively higher melting point than conventional solder alloys, and may be structurally and electrically coupled to the conductive vias 218 and to the electrical contacts 256 using a thermo-compression bonding operation. Although not shown for simplicity, a dielectric underfill material may be disposed between the IC structure 21 OA and the structure or device 250A and between adjacent bumps or balls 258, as is known in the art.

[00101] Referring to FIGS. 12 and 13, each of the MEMS devices 270 and 280 may, in some embodiments, be subjected to an encapsulation operation in which the components thereof are at least partially enclosed by an encapsulant material (not shown), as is known in the art, to add structural support to the MEMS devices 270, 280 and to protect components thereof from environmental damage, for example.

[00102] FIGS. 14 through 25 illustrate a non-limiting example of a method of forming a semiconductor device that includes the formation of at least a portion of an integrated circuit and a MEMS device operatively coupled to the integrated circuit, wherein a transducer of the MEMS device is fabricated from a doped semiconductor material bonded to the integrated circuit.

[00103] FIG. 14 is a simplified cross-sectional view of a substrate 300. The substrate 300 may comprise what is referred to in the art as a "die" or a "wafer," and may be generally planar. The substrate 300 may comprise any of a number of materials conventionally used for substrates in the fabrication of integrated circuits. As non-limiting examples, the substrate 300 may comprise an oxide (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.) or a semiconductor material (e.g., silicon, germanium, a III-V semiconductor material, etc.). The substrate 300 may comprise a glass in some embodiments. In other embodiments, the substrate 300 may comprise a crystalline material (e.g., pOlycrystalline or monocrystalline material). Further, the substrate 300 may be at least substantially comprised by a single, generally homogenous material, or the substrate 300 may comprise a multi-layer structure.

[00104] Referring to FIG. 15, one or more electrically conductive vias 302 may be formed in the substrate 300. The one or more electrically conductive vias 302 may be formed in the substrate 300 from a first major surface 304 of the substrate 300 toward a second major surface 306 of the substrate 300 on an opposing side of the substrate 300. FIG. 15 illustrates four (4) conductive vias 302, although the substrate 300 may in fact include any number of conductive vias 302. The conductive vias 302 may be formed using processes known in the art. For example, via holes may be formed into the substrate 300 using, for example, a photolithographic masking and etching process. In such embodiments, a mask layer may be deposited over the first major surface 304 of the substrate 300 and selectively patterned so as to form apertures through the mask layer at the locations at which it is desired to etch into the substrate 300 to form the via holes. After forming the patterned mask layer, the regions of the substrate 300 that are exposed through the patterned mask layer may be etched using, for example, a dry reactive ion etching process to form the via holes in the substrate 300. After the etching process, the patterned mask layer may be removed, and the via holes may be filled with electrically conductive material to form the conductive vias 302. The electrically conductive material may comprise, for example, a metal, a metal alloy, or doped polysilicon. In some embodiments, the conductive material may comprise a multi-layer structure including multiple layers of different conductive materials. The conductive material may be deposited within the via holes using one or more of a deposition process (e.g., a physical vapor deposition process (PVD) or a chemical vapor deposition (CVD) process), an electroless plating process, and an electrolytic plating process.

[00105] As shown in FIG. 15, the conductive vias 302 may extend only partially through the substrate 300 in some embodiments. In other embodiments, the conductive vias 302 may extend entirely through the substrate 300 from the first major surface 304 to the second major surface 306. In some embodiments, the substrate 300 may have an average layer thickness between the first major surface 304 and the second major surface 306 (the vertical dimension from the perspective of FIG. 15) of about two hundred and fifty microns (250 μιτι) or more, about five hundred microns (500 μπι) or more, or even about seven hundred and fifty microns (750 μιτί) or more. The conductive vias 302, however, may have an average cross-sectional dimension (e.g., average diameter) such that an aspect ratio of the conductive vias 302, which is the ratio of the average length of the conductive vias 302 to the average cross-sectional dimension of the conductive vias 302, is about twenty five (25) or less, about ten (10) or less, or even about five (5) or less. It may be difficult to fabricate conductive vias 302 that have a high aspect ratio. Thus, it may be desirable to form the conductive vias 302 partially through the substrate 300, and then to subsequently thin at least a portion of the substrate 300 so as to expose the conductive vias 302 at the second major surface 306 of the substrate 300.

[00106] At least a portion of an integrated circuit may be fabricated on the first major surface 304 of the substrate 300. For example, FIG. 16 illustrates an active layer 308 formed on the first major surface 304 that includes a plurality of transistors 310. Thus, the first major surface 304 of the substrate 300 may comprise what is often referred to in the art as an "active surface" of the substrate 300, and the second major surface 306 of the substrate 300 may comprise what is often referred to in the art as a "back surface" of the substrate 300. The transistors 310 may be formed in, on, and/or over the first major surface 304 of the substrate 300 using processes known in the art. As a non-limiting example, the transistors 310 may comprise metal oxide semiconductor field effect transistors (MOSFETs), and may embody complementary metal oxide semiconductor technology (CMOS). The processes often employed in the art to fabricate such transistors 310 are often referred to in the art as "front-end-of-line" (FEOL) processes, and often involve processes carried out at temperatures greater than four hundred degrees Celsius (400° C). Thus, in such

embodiments, the conductive material used to form the conductive vias 302, which are fabricated prior to forming the active layer 308, may comprise a material that is stable through the temperature ranges to which the structure will be subjected during the FEOL processes used to form the transistors 310. For example, the conductive material used to form the conductive vias 302 may comprise doped polysilicon in such embodiments.

[00107] Referring to FIG. 17, after forming the transistors 310, one or more additional layers of electrically conductive features used to electrically interconnect various features of the transistors 310 (e.g., sources, drains, and gates of the transistors 310) may be formed over the transistors 310 on a side thereof opposite the first major surface 304 of the substrate 300. The conductive features may comprise one or more of laterally extending conductive lines 312 (e.g., traces), vertically extending conductive vias 314, and electrical contact pads 3 16. The conductive features may comprise electrically conductive material regions (e.g., copper, aluminum, tungsten, etc.) that are at least partially embedded in a dielectric material 318. The one or more layers of conductive features and surrounding dielectric material 318 may be formed in a layer-by-layer lithographic process over the transistors 310. In such processes, layers of dielectric material and layers of conductive material may be deposited and selectively patterned in an alternating manner to form the various conductive features and the dielectric material 318. The processes often employed in the art to fabricate these electrically conductive features are often referred to in the art as "back- end-of-line" (BEOL) processes, and often involve processes carried out at temperatures of about four hundred degrees Celsius (400° C) or less (although, in some embodiments, one or more initial layers of metal deposited as part of the BEOL processes may comprise tungsten, which may be deposited at temperatures up to about nine hundred degrees Celsius (900° C)).

[00108] One or more of the conductive features formed over the transistors 310 (e.g., one or more of the conductive lines 312, conductive vias 314, and electrical contact pads 316) may be electrically coupled with one or more of the conductive vias 302. Stated another way, a continuous electrical pathway may be provided between at least one conductive via 302 and one or more of the conductive features.

[00109] Referring to FIG. 18, the substrate 300 optionally may be thinned by removing material of the substrate 300 from the second major surface 306 of the substrate 300. By way of example and not limitation, one or more of an etching process, a grinding process, and a polishing process (e.g., a chemical-mechanical polishing (CMP) process) may be used to thin the substrate 300. In embodiments in which the conductive vias 302 do not extend entirely through the substrate 300, the thinning process may be carried out at least until ends of the conductive vias 302 are exposed at the second major surface 306 of the substrate 300. In some embodiments, the substrate 300 may have an average thickness after the thinning process of, for example, about seven hundred and fifty microns (750 μηι) or less, about five hundred microns (500 μηι) or less, or even about one hundred microns (100 μιτι) or less. Optionally, a carrier substrate may be temporarily bonded to the structure over the first major surface 304 of the substrate 300 to facilitate handling of the structure by processing equipment during the thinning process (and/or subsequent processing) as desired.

[00110] Referring to FIG. 19, at least one transducer cavity recess 342 may be formed in the second major surface 306 of the substrate 300. The transducer cavity recess 342 is ultimately used to form at least a portion of a transducer cavity in which at least a portion of a transducer of a MEMS device is to be disposed. The transducer cavity recess 342 may be formed in the second major surface 306 of the substrate 300 using, for example, a photolithographic niasking and etching operation. The transducer cavity recess 342 may have any desirable size and shape, and the desired size and shape may be at least partially a function of the type of transducer to be formed. In embodiments in which the transducer to be formed comprises a resonator, the frequencies at which the resonator is to resonate may be at least partially a function of the size and shape of the transducer cavity recess 342, and the size and shape of the transducer cavity recess 342 may be designed and selected to provide desirable resonant frequencies. [00111] In some embodiments, the transducer cavity recess 342 may be located proximate one or more of the conductive vias 302. Optionally, the transducer cavity recess 342 may be located between at least two conductive vias 302, as shown in FIG. 19, such that a first conductive via 302 is disposed on a first lateral side of the transducer cavity recess 342 and a second conductive via 302 is disposed on an opposing lateral side of the transducer cavity recess 342.

[00112] After forming the transducer cavity recess 342, a transducer may be formed over the transducer cavity recess 342. Referring to FIG. 20, as a non-limiting example of a method that may be used to form such a transducer, a semiconductor-on-insulator-type (SOI-type) structure 344 may be bonded over the second major surface 306 of the substrate 300 and over the transducer cavity recess 342. The SOI-type structure 344 may include a relatively thin layer of material 346 bonded to a relatively thick volume of bulk material 348 with an intermediate material 350 between the layer of material 346 and the bulk material 348. The layer of material 346 may be thin relative to the bulk material 348, and the bulk material 348 may thick relative to the layer of material 346. The intermediate material 350 may be approximately equal in thickness to the layer of material 346, or it may be thinner than the layer of material 346.

[00113] The SOI-type structure 344 may be a structure having a structural configuration like that of conventional semiconductor-on-insulator (SOI) structures, although the layer of material 346 may comprise a doped semiconductor material, such as a highly-doped semiconductor material doped sufficiently to be electrically conductive, and the intermediate material 350 may or may not comprise an insulator material. As the layer of material 346 may be formed of a doped

semiconductor material, the layer of material 346 is also referred to herein as a layer of doped semiconductor material 346. A portion of the layer of doped semiconductor material 346 may ultimately be used to form at least a portion of a transducer (e.g., a resonator or a sensor).

[00114] The bulk material 348 may comprise any of a number of materials conventionally used for SOI substrates. Such materials include, for example, ceramics such as oxides (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), nitrides (e.g., silicon nitride), and carbides (e.g., silicon carbide), as well as semiconductor materials (e.g., silicon, germanium, a III-V semiconductor material, etc.). The bulk material 348 may comprise an amorphous material or a crystalline material (e.g., polycrystalline or monocry stall ine material). The intermediate material 350 may comprise a dielectric material, a metal material, or a semiconductor material. As a non-limiting example, the intermediate material 350 may comprise an oxide, such as silicon dioxide.

[00115] The layer of doped semiconductor material 346 may have any desirable average layer thickness. As non-limiting examples, the layer of doped semiconductor material 346 may have an average layer thickness between about five nanometers (5 nm) and about five hundred microns (500 μιη), between about five nanometers (5 nm) and about one hundred microns (100 μηι), or even between about five nanometers (5 nm) and about ten microns (10 μηι). If the MEMS device to be fabricated comprises a resonator, the resonant frequencies of the resonator to be formed may be affected by the thickness of the layer of doped semiconductor material 346, and the thickness of the layer of doped semiconductor material 346 and the ultimate resonator formed from a portion of the layer of doped semiconductor material 346 may be selected accordingly.

[00116] As shown in FIG. 20, the SOI-type structure 344 may be bonded to the second major surface 306 of the substrate 300 such that the layer of doped semiconductor material 346 is disposed between the substrate 300 and the bulk material 348. Stated another way, the layer of doped semiconductor material 346 may be bonded to the second major surface 306 of the substrate 300. In some embodiments, the layer of doped semiconductor material 346 may be attached to the substrate 300 using, for example, a direct bonding process, a thermocompression bonding process, a non-thermocompression bonding process, or a combination thereof, as described above.

[00117] In some embodiments, the bonding surface of the substrate 300 may be at least substantially comprised of the same semiconductor material (e.g., silicon) as the material of the layer of doped semiconductor material 346. In such embodiments, a silicon-to-silicon surface direct bonding process may be used to bond the bonding surface of the layer of doped semiconductor material 346 to a bonding surface of the substrate 300.

[00118] Referring to FIG. 21 , after bonding the SOl-type structure 344 (FIG. 20) to the second major surface 306 of the substrate 300, the bulk material 348 of the SOI-type structure 344 (FIG. 20) may be removed leaving the layer of doped semiconductor material 346 (and optionally the intermediate material 350) behind and bonded to the substrate 300. In some embodiments, the bulk material 348 of the SOI-type structure 344 (FIG. 20) may be removed by fracturing the SOI-type structure 344 (FIG. 20) along the intermediate material 350. In other embodiments, one or more of an etching process, a grinding process, and a polishing process (e.g., a chemical-mechanical

29 r polishing (CMP) process) may be used to remove the bulk material 348 (and optionally the intermediate material 350).

[00119] In additional embodiments, the structure of FIG. 21, which includes the layer of material 346, may be formed using what is referred to in the art as a SMARTCUT® process. Such processes are described in, for example, U.S. Patent No. RE39,484 to Bruel (issued February 6, 2007), U.S. Patent No. 6,303,468 to Aspar et al. (issued October 16, 2001), U.S. Patent No.

6,335,258 to Aspar et al. (issued January 1, 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (issued June 29, 2004), U.S. Patent No. 6,809,044 to Aspar et al. (issued October 26, 2004), and U.S. Patent No. 6,946,365 to Aspar et al. (September 20, 2005), the disclosures of which are incorporated herein in their entireties by this reference. Briefly, in such methods, ions may be implanted into a wafer of bulk material (which may not comprise an SOI-type structure 344) along an ion implant plane to define a plane of weakness within the wafer. The wafer then may be attached to the second major surface 306 of the substrate 300as previously described herein in relation to the bonding of the SOI-type structure 344 to the substrate 300 with reference to FIG. 20. The wafer then may be cleaved or otherwise fractured along the ion implant plane to separate the layer of material 346 from the wafer, leaving the layer of material 346 bonded to the second major surface 306 of the substrate 300. The bonding and fracturing process may be performed at a temperature of about 400°C or less. The fractured surface of the layer of material 346 may be smoothed using a chemical-mechanical polishing (CMP) process after the fracturing process.

[00120] In yet further embodiments, the structure of FIG. 21 , which includes the layer of material 346, may be formed by bonding a wafer of bulk material (which may not comprise an SOI- type structure 344) to the second major surface 306 of the substrate 300 using, for example, a direct bonding process as previously described herein in relation to the bonding of the SOI-type structure 344 to the substrate 300 with reference to FIG. 20. The wafer then may be thinned from a side thereof opposite the substrate 300 to form the layer of material 346. The thinning process may comprise at least one of a grinding process, an etching process; and a polishing process (e.g., a chemical-mechanical polishing (CMP) process).

[00121] As shown in FIG. 22, a region of the layer of doped semiconductor material 346 proximate the transducer cavity recess 342 may be processed to form a transducer 354 over and adjacent the transducer cavity recess 342. By way of example and not limitation, trenches and/or holes 356 may be formed in or through the layer of doped semiconductor material 346 proximate the transducer cavity recess 342 to selectively reduce the structural support for a portion of the layer of material 346 to comprise the transducer 354, and/or to electrically isolate regions of the layer of material 346 comprising the transducer 354. The particular structure of the transducer 354 is not critical to embodiments of the disclosure, and various configurations of transducers may be employed. Additional processing may be employed as needed to form a transducer 354 having a desirable configuration and comprising a portion of the layer of doped semiconductor material 346. As non-limiting examples, the transducer 354 may comprise a resonator, a sensor, or both a resonator and a sensor.

[00122] Ends of the conductive vias 302 may be electrically coupled to portions of the layer of doped semiconductor material 346 that are electrically isolated from adjacent portions of the layer of doped semiconductor material 346 by the trenches and/or holes 356. For example, as shown in FIG. 22, the innermost conductive vias 302 may provide a continuous electrical pathway between one or more of the conductive features formed over the transistors 310 (e.g., one or more of the conductive lines 312, conductive vias 314, and electrical contact pads 3 16) and the transducer 354. By way of another example, another conductive via 302 may provide a continuous electrical pathway between one or more of the conductive features formed over the transistors 310 and a doped semiconductor element 358 defined by one or more of the trenches and/or holes 356, as shown in FIG. 22. Due to the electrical conductivity of the layer of doped semiconductor material 346, the doped semiconductor element 358 formed therefrom may define a conductive via between the second major surface 306 of the substrate 300 and a side of the layer of doped semiconductor material 346 opposite the substrate 300. Alternatively, the doped semiconductor element 358 may be physically and electrically coupled to a portion of the transducer 354.

[00123] Referring to FIG. 23, a cap structure 360 may be provided over the layer of material 346 and the transducer 354. The cap structure 360 may comprise another transducer cavity recess 362 located and configured to be disposed adjacent the transducer 354 on a side thereof opposite the transducer cavity recess 342 formed in the substrate 300.

[00124] The cap structure 360 may comprise, for example, a ceramic such as an oxide (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), a nitride (e.g., silicon nitride), or a carbide (e.g., silicon carbide). In other embodiments, the cap structure 360 may comprise a semiconductor material (e.g., silicon, germanium, a III-V semiconductor material, etc.) or a metal or metal alloy. Additionally, the material of the cap structure 360 may be an amorphous material or a crystalline (e.g., polycrystalline or monocrystalline) material. The transducer cavity recess 362 may be formed in the cap structure 360 as previously described in relation to the another transducer cavity recess 236 of FIG. 1 1.

[00125] The cap structure 360 may be attached to the layer of material 346 using, for example, a direct bonding process, a thermocompression bonding process, a non- thermocompression bonding process, or a combination thereof, as previously described with reference to FIG. 5.

[00126] The transducer 354 may be hermetically sealed between the cap structure 360 and the substrate 300. As described above, ithe cap structure 360 may be bonded to the layer of material 346 under vacuum, in an inert gas environment, or under ambient conditions. In embodiments where a low pressure (e.g., a vacuum) is desired, a getter material (not shown) may be located on an internal surface of the transducer cavity to absorb gas molecules and maintain the low pressure over time, as described above.

[00127] As shown in FIG. 24, bumps or balls 328 of electrically conductive metal or metal alloy optionally may be formed on the contact pads 316 over the first major surface 304 of the substrate 300. The structure of FIG. 24 may be structurally and electrically coupled to another structure or device 332 as shown in FIG. 25, such as with contact pads 334 formed in or on the another structure or device 332. The structure or device 332 may comprise, for example, a higher level substrate, such as a PCB, an interposer, or a semiconductor device.

[00128] FIGS. 26 through 32 illustrate another example of a method that may be used to form a semiconductor device comprising at least a portion of an integrated circuit and a MEMS device operatively coupled with the integrated circuit, wherein a transistor of the MEMS device is fabricated from a doped semiconductor material bonded to the integrated circuit

[00129] Referring to FIG. 26, a layer of dielectric material 422 may be provided over a structure like that shown in FIG. 18. As shown in FIG. 26, the structure over which the layer of dielectric material 422 is provided may include a substrate 400 similar to the substrate 300 of FIG. 18, electrically conductive vias 402 extending from a first major surface 404 of the substrate 400 to an opposite second major surface 406 similar to the conductive vias 302 of FIG. 18, and an integrated circuit formed over the first major surface 404 of the substrate 400. The integrated circuit may include active layers having electrically conductive features therein, such as transistors 410 similar to the transistors 310 of FIG. 18, horizontally extending electrically conductive lines 412 (e.g., traces) similar to the conductive lines 312 of FIG. 18, vertically extending electrically conductive vias 414 similar to the conductive vias 314 of FIG. 18, and electrical contact pads 416 similar to the contact pads 316 of FIG. 18. Each of these conductive features may be at least partially embedded in a dielectric material 418.

[00130] As shown in FIG. 26, the layer of dielectric material 422 may be provided over the active layers of the integrated circuit, which include the transistors 410, the conductive lines 412, the conductive vias 414, the electrical contact pads 416, and the dielectric material 418. The layer of dielectric material 422 may comprise, for example, an oxide (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or a semiconductor material (e.g., silicon, germanium, a III-V semiconductor material, etc.). The layer of dielectric material 422 may be deposited over the active layers at a temperature of about 400°C or less using any of a number of known processes for depositing dielectric material, including, for example, spin-on processes, chemical vapor deposition (CVD) processes, etc. The layer of dielectric material 422 may have an average thickness sufficient to form a transducer cavity recess therein, as discussed in further detail below. As a non-limiting example, the layer of dielectric material 422 may have an average thickness between about ten microns (10 μπι) and about five hundred microns (500 μιτι) or more.

[00131] Referring to FIG. 27, after providing the layer of dielectric material 422 over the active layers, conductive vias 440 may be formed that extend through the layer of dielectric material 422 to conductive features of the integrated circuit fabricated over the first major surface 404 of the substrate 400, such as to contact pads 416. One or more of the conductive vias 440 may be used to electrically couple a transducer of a MEMS device to be fabricated to the integrated circuit.

[00132] The conductive vias 440 may be fabricated using processes known in the art. For example, via holes may be formed through the layer of dielectric material 422 using, for example, a photolithographic masking and etching process. In such embodiments, a mask layer may be deposited over the exposed major surface of the layer of dielectric material 422 and selectively patterned so as to form apertures through the mask layer at the locations at which it is desired to etch into the layer of dielectric material 422 to form the via holes. After forming the patterned mask layer, the regions of the layer of dielectric material 422 that are exposed through the patterned mask layer may be etched using, for example, a dry reactive ion etching process to form the via holes extending through the layer of dielectric material 422. After the etching process, the patterned mask layer may be removed, and the via holes may be filled with electrically conductive material to form the conductive vias 440. The electrically conductive material may comprise, for example, a metal, a metal alloy, or doped polysilicon. In some embodiments, the conductive material may comprise a multi-layer structure including multiple layers of different conductive materials. The conductive material may be deposited within the via holes using one or more of a deposition process (e.g., a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process), an electroless plating process, and an electrolytic plating process. If present, excess conductive material may be removed from an exposed major surface 423 of the layer of dielectric material 422. For example, a CMP process may be used to remove excess conductive material.

[00133] Again referring to FIG. 27, after the conductive vias 440 are formed, at least one transducer cavity recess 424 may be formed in the major surface 423 of the layer of dielectric material 422. The transducer cavity recess 424 is ultimately used to form at least a portion of a transducer cavity in which at least a portion of a transducer of a MEMS device is to be disposed. The transducer cavity recess 424 may have any desirable size and shape, and the desired size and shape may be at least partially a function of the type of transducer to be formed. In embodiments in which the transducer to be formed comprises a resonator, the frequencies at which the resonator is to resonate may be at least partially a function of the size and shape of the transducer cavity recess 424, and the size and shape of the transducer cavity recess 424 may be designed and selected to provide desirable resonant frequencies.

[00134] The transducer cavity recess 424 may be formed in the major surface 423 of the layer of dielectric material 422 using, for example, a photolithographic masking and etching process. In such embodiments, a mask layer may be deposited over the major surface 423 of the layer of dielectric material 422 and selectively patterned so as to form an aperture through the mask layer at the location at which it is desired to etch into the layer of dielectric material 422 to form the transducer cavity recess 424. After forming the patterned mask layer, the regions of the layer of dielectric material 422 that are exposed through the patterned mask layer may be etched using, for example, a dry reactive ion etching process or a wet chemical etching process to form the transducer cavity recess 424. After the etching process, the patterned mask layer may be removed

[00135] As one non-limiting example, in embodiments in which the layer of dielectric material 422 comprises silicon oxide (Si0₂), the transducer cavity recess 424 may be etched in the silicon oxide using a wet chemical etching process in a solution comprising between about 1% and about 50% by volume hydrofluoric acid (HF), and between about 50% and about 99% by volume water (H₂0). The solution may further include ammonium fluoride NH₄F or nitric acid HN0₃ in some embodiments. The etching process may be carried out at a temperature of between about twenty degrees Celsius (20°C) and about one hundred degrees Celsius (100°C) for a sufficient time to form a transducer cavity recess 424 having desirable dimensions. As another non-limiting example, the transducer cavity recesses 424 may be etched in the dielectric material 422 using a dry plasma etching process, which may employ fluorine-based etchant species in embodiments in which the dielectric material 422 comprises silicon oxide (Si0₂).

[00136] After forming the transducer cavity recess 424, a transducer may be formed over the transducer cavity recess 424. Referring to FIG. 28, as a non-limiting example of a method that may be used to form such a transducer, a semiconductor-on-insulator-type (SOI-type) structure 430 may be bonded over the major surface 423 of the layer of dielectric material 422 and over the transducer cavity recess 424. The SOI-type structure 430 may include a layer of doped

semiconductor material 432 bonded to a relatively thick volume of bulk material 434 with an intermediate material 436 between the layer of doped semiconductor material 432 and the bulk material 434. The layer of doped semiconductor material 432 may be thin relative to the bulk material 434, and the bulk material 434 may be thick relative to the layer of doped semiconductor material 432. The intermediate material 436 may be approximately equal in thickness to the layer of doped semiconductor material 432, or it may be thinner than the layer of doped semiconductor material 432.

[00137] The SOI-type structure 430 may be a structure having a structural configuration like that of conventional semiconductor-on-insulator (SOI) structures, although the layer of doped semiconductor material 432 may be doped sufficiently to be electrically conductive, and the intermediate material 436 may or may not comprise an insulator material. A portion of the layer of doped semiconductor material 432 may ultimately be used to form at least a portion of a transducer (e.g., a resonator or a sensor). The bulk material 434 may comprise any of a number of materials conventionally used for SOI substrates. Such materials include, for example, ceramics such as oxides (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), nitrides (e.g. , silicon nitride), and carbides (e.g., silicon carbide), as well as semiconductor materials (e.g., silicon, germanium, a III-V semiconductor material, etc.). The bulk material 434 may comprise an amorphous material or a crystalline material (e.g., polycrystalline or monocrystalline material). The intermediate material 436 may comprise a dielectric material, a metal material, or a semiconductor material. As a non-limiting example, the intermediate material 436 may comprise an oxide such as silicon dioxide (Si0₂).

[00138] The layer of doped semiconductor material 432 may have any desirable average layer thickness. As non-limiting examples, the layer of doped semiconductor material 432 may have an average layer thickness between about five nanometers (5 nm) and about five hundred microns (500 μπι), between about five nanometers (5 nm) and about one hundred microns (100 μιτι), or even between about five nanometers (5 nm) and about ten microns (10 μιτι). I f the MEMS device to be fabricated comprises a resonator, the resonant frequencies of the resonator to be formed may be affected by the thickness of the layer of doped semiconductor material 432, and the thickness of the layer of doped semiconductor material 432 and the ultimate resonator formed from a portion of the layer of doped semiconductor material 432 may be selected accordingly.

[00139] As shown in FIG. 28, the SOI-type structure 430 may be bonded to the major surface 423 of the layer of dielectric material 422 such that the layer of doped semiconductor material 432 is disposed between the layer of dielectric material 422 and the bulk material 434. Stated another way, the layer of doped semiconductor material 432 may be bonded to the major surface 423 of the layer of dielectric material 422. In some embodiments, the layer of doped semiconductor material 432 may be bonded to the major surface 423 of the layer of dielectric material 422 using a direct bonding process, as described above.

[00140] In some embodiments, the bonding surface of the layer of doped semiconductor material 432 may comprise a semiconductor material (e.g., silicon), and the bonding surface of the layer of dielectric material 422 may be at least substantially comprised of the same semiconductor material (e.g., silicon). In such embodiments, a silicon-to-silicon surface direct-bonding process may be used to bond the bonding surface of the layer of doped semiconductor material 432 to a bonding surface of the layer of dielectric material 422. ^c

[00141] Referring to FIG. 29, after bonding the SOI-type structure 430 (FIG. 28) to the major surface 423 of the layer of dielectric material 422, the bulk material 434 of the SOI-type structure 430 may be removed leaving the layer of doped semiconductor material 432 (and optionally the intermediate material 436) behind and bonded to the layer of dielectric material 422. In some embodiments, the bulk material 434 of the SOI-type structure 430 may be removed by fracturing the SOI-type structure 430 (FIG. 28) along the intermediate material 436. In other embodiments, one or more of an etching process, a grinding process, and a polishing process (e.g., a chemical-mechanical polishing (CMP) process) may be used to remove the bulk material 434 (and optionally the intermediate material 436).

[00142] In additional embodiments, the structure of FIG. 29, which includes the layer of material 432, may be formed using what is referred to in the art as a SMARTCUT® process. Such processes are described in, for example, U.S. Patent No. RE39,484 to Bruel (issued February 6, 2007), U.S. Patent No. 6,303,468 to Aspar et al. (issued October 16, 2001 ), U.S. Patent No.

6,335,258 to Aspar et al. (issued January 1 , 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (issued June 29, 2004), U.S. Patent No. 6,809,044 to Aspar et al. (issued October 26, 2004), and U.S. Patent No. 6,946,365 to Aspar et al. (September 20, 2005), the disclosures of which are incorporated herein in their entireties by this reference. Briefly, in such methods, ions may be implanted into a wafer of bulk material (which may not comprise an SOI-type structure 430) along an ion implant plane to define a plane of weakness within the wafer. The wafer then may be attached to the surface 423 of the dielectric material 422 as previously described herein in relation to the bonding of the SOI-type structure 430 to the dielectric material 422 with reference to FIG. 28. The wafer then may be cleaved or otherwise fractured along the ion implant plane to separate the layer of material 432 from the wafer, leaving the layer of material 432 bonded to the surface 423 of the dielectric material 422. The bonding and fracturing process may be performed at a temperature of about 400°C or less. The fractured surface of the layer of material 432 may be smoothed using a chemical-mechanical polishing (CMP) process after the fracturing process.

[00143] In yet further embodiments, the structure of FIG. 29, which includes the layer of material 432, may be formed by bonding a wafer of bulk material (which may not comprise an SOI- type structure 430) to the surface 423 of the dielectric material 422 using, for example, a direct bonding process as previously described herein in relation to the bonding of the SOI-type structure 430 to the dielectric material 422 with reference to FIG. 28. The wafer then may be thinned from a side thereof opposite the dielectric material 422 to form the layer of material 432. The thinning process may comprise at least one of a grinding process, an etching process, and a polishing process (e.g., a chemical-mechanical polishing (CMP) process).

[00144] As shown in FIG. 30, a region of the layer of doped semiconductor material 432 proximate the transducer cavity recess 424 may be processed to form a transducer 444 over and adjacent the transducer cavity recess 424. By way of example and not limitation, trenches and/or holes 446 may be formed in or through the layer of doped semiconductor material 432 proximate the transducer cavity recess 424 to selectively reduce the structural support for a portion of the layer of doped semiconductor material 432 to comprise the transducer 444, and/or to electrically isolate regions of the layer of doped semiconductor material 432 comprising the transducer 444. The particular structure of the transducer 444 is not critical to embodiments of the disclosure, and various configurations of transducers may be employed. Additional processing may be employed as needed to form a transducer 444 having a desirable configuration and comprising a portion of the layer of doped semiconductor material 432. As non-limiting examples, the transducer 444 may comprise a resonator, such as a plate acoustic wave resonator, a flexural mode resonator, a bulk acoustic wave (BAW) resonator, a surface acoustic wave (SAW) resonator, or a film bulk acoustic resonator (FBAR). In other embodiments, the transducer 444 may comprise a sensor configured to electrically sense mechanical deformation of,, or vibrations in, a portion of the transducer 444. In , some embodiments, the transducer 444 may function as both a resonator and a sensor.

[00145] As shown in FIG. 30, one or more of the conductive vias 440 may be in physical and electrical contact with conductive features, such as contact pads 416, of the integrated circuit, and also in physical and electrical contact with portions of the layer of doped semiconductor material 432 that comprise elements or features of the transducer 444, thus providing electrical interconnection between the transducer 444 and the integrated circuit. Additional conductive vias 440 may be in physical and electrical contact with conductive vias formed from portions of the layer of doped semiconductor material 432 isolated from adjacent portions of the layer of doped semiconductor material 432 by trenches and/or holes 446. . ,

[00146] Referring to FIG. 31 , a cap structure 450 may be provided over the layer of doped semiconductor material 432 and the transducer 444. The cap structure 450 may comprise another transducer cavity recess 452 located and configured to be disposed adjacent the transducer 444 on a side thereof opposite the transducer cavity recess 424 formed in the substrate 400. The transducer cavity recess 452 may be formed in the cap structure 450 prior to bonding the cap structure 450 to the layer of doped semiconductor material 432 using processes like those previously discussed.

[00147] The cap structure 450 may comprise, for example, a ceramic such as an oxide (e.g., aluminum oxide, zirconium oxide, silicon oxide, etc.), a nitride (e.g., silicon nitride), or a carbide (e.g., silicon carbide). In other embodiments, the cap structure 450 may comprise a semiconductor material (e.g., silicon, germanium, a III-V semiconductor material, etc.) or a metal or metal alloy. Additionally, the material of the cap structure 450 may be amorphous or crystalline (polycrystalline or monocrystalline).

[00148] The cap structure 450 may be bonded to the layer of doped semiconductor material 432 using, for example, a direct bonding process as previously described with reference to FIG. 28. In other embodiments, the cap structure 450 may be bonded to the layer of doped semiconductor material 432 using a thermocompression bonding process or a non- thermocompression bonding process.

[00149] The transducer 444 may be hermetically sealed between the cap structure 450 and the layer of dielectric material 422. As described above, the cap structure 450 may be bonded to the layer of doped semiconductor material 432 under vacuum, in an inert gas environment, or under ambient conditions. In embodiments where a low pressure (e.g., a vacuum) is desired, a getter material (not shown) may be located on an internal surface of the transducer cavity to absorb gas molecules and maintain the low pressure over time, as described above.

[00150] The structure of FIG. 31 includes a transducer 444 and at least a portion of an integrated circuit operatively coupled with the transducer 444. Thus, the structure of FIG. 31 may be configured for attachment to another structure or device for use in a higher level electrical device or system. For example, referring to FIG. 32, bumps or balls 454 of electrically conductive metal or metal alloy optionally may be formed over the second major surface 406 of the substrate 400, and the bumps or balls 454 may be in electrical contact with ends of the conductive vias 402 exposed at the second major surface 406 of the substrate 400. The bumps or balls 454 may be used to structurally and electrically couple the structure of FIG. 31 to another structure or device 456, as shown in FIG. 32. In this configuration, the substrate 400 is disposed between the transducer 444 and the structure or device 456.

[00151] By way of example and not limitation, the bumps or balls 454 of electrically conductive material may be structurally and electrically bonded to complementary electrical contacts 458 (e.g., bond pads, etc.) on the another structure or device 456. The another structure or device 456 may comprise, for example, a higher level substrate, such as a printed circuit board, an interposer, or a semiconductor device. In some embodiments, the bumps or balls 454 may comprise a solder alloy, and may be structurally and electrically coupled to the electrical contacts 458 using a solder reflow process. In other embodiments, the bumps or balls 454 may comprise a metal or metal alloy having a relatively higher melting point than conventional solder alloys, and may be structurally and electrically coupled to the electrical contacts 458 using a thermo-compression bonding process.

[00152] In the method described above with reference to FIGS. 26 through 32, the conductive vias 402 are formed through the substrate 400 to enable the structure of FIG. 31 to be bonded to another structure or device 456 (and the transducer 444 and the integrated circuit electrically interconnected with electrical contacts 458 on the structure or device 456) using a "ball grid array" (BGA) type interconnection. In additional embodiments, other methods may be used to structurally and/or electrically interconnect an integral MEMS device and integrated circuit formed as described herein to another substrate or device.

[00153] Additional non-limiting example embodiments of the present disclosure are set forth below.

[00154] Embodiment 1 : A method of forming a semiconductor device including an electrical interconnection, the method comprising: selectively removing material from a doped semiconductor substrate to form one or more trenches and to form at least one doped semiconductor element defined by the one or more trenches; attaching a substrate to the doped semiconductor substrate and to the at least one doped semiconductor element; and removing material from the doped semiconductor substrate to expose the one or more trenches and to physically and electrically isolate the at least one doped semiconductor element from adjacent portions of the doped semiconductor substrate.

[00155] Embodiment 2: The method of Embodiment 1 , further comprising attaching another substrate to the doped semiconductor substrate on a side thereof opposite the substrate.

[00156] Embodiment 3: The method of Embodiment 2, wherein attaching another substrate to the doped semiconductor substrate comprises physically and electrically contacting at least one conductive member of the another substrate to the at least one doped semiconductor element.

[00157] Embodiment 4: The method of any one of Embodiments 1 through 3, wherein attaching a substrate to the doped semiconductor substrate and to the at least one doped

semiconductor element comprises physically and electrically contacting at least one conductive member of the substrate to the at least one doped semiconductor element.

[00158] Embodiment 5: The method of any one of Embodiments 1 through 4, wherein attaching a substrate to the doped semiconductor substrate comprises attaching the substrate to the doped semiconductor substrate using at least one of a direct bonding process, a thermocompression bonding process, and a non-thermocompression bonding process.

[00159] Embodiment 6: The method of any one of Embodiments 1 through 5, wherein removing material from the doped semiconductor substrate to expose the one or more trenches comprises removing material from the doped semiconductor substrate through at least one of an abrasive planarization operation and an etching operation.

[00160] Embodiment 7: The method of any one of Embodiments 1 through 6, further comprising forming the doped semiconductor substrate to include a semiconductor material and one or more dopants at formation.

[00161] Embodiment 8: The method of any one of Embodiments 1 through 7, further comprising at least partially filling the one or more trenches with a dielectric material.

[00162] Embodiment 9: A method of forming a microelectromechahical system (MEMS) device, the method comprising: forming trenches in a doped semiconductor substrate; forming a transducer cavity recess in the doped semiconductor substrate between at least two of the trenches to form a doped semiconductor element between the transducer cavity recess and each immediately adjacent trench; attaching an integrated circuit structure (IC structure) to the doped semiconductor substrate and to the doped semiconductor elements; and removing material from a side of the doped semiconductor substrate opposite the attached IC structure to physically and electrically isolate the doped semiconductor elements from adjacent portions of the doped semiconductor substrate.

[00163] Embodiment 10: The method of Embodiment 9, wherein attaching an IC structure to the doped semiconductor substrate and to the doped semiconductor elements comprises attaching a CMOS substrate to the doped semiconductor substrate and operatively coupling a control circuit for a MEMS device of the CMOS substrate to the doped semiconductor elements.

[00164] Embodiment 1 1 : The method of any one of Embodiments 9 and 10, further comprising attaching a cap structure to the doped semiconductor substrate to the side of the doped semiconductor substrate opposite the attached IC structure.

[00165] Embodiment 12: The method of Embodiment 1 1, further comprising disposing another transducer cavity recess in the cap structure proximate the transducer cavity recess in the doped semiconductor substrate.

[00166] Embodiment 13: The method of any one of Embodiments 9 through 12, wherein forming a transducer cavity recess in the doped semiconductor substrate comprises removing material from the doped semiconductor substrate to a depth less than a depth of the trenches formed in the doped semiconductor substrate.

[00167] Embodiment 14: The method of Embodiment 13, wherein removing material from a side of the doped semiconductor substrate opposite the attached IC structure comprises allowing material of the doped semiconductor substrate adjacent to the transducer cavity recess to remain between doped semiconductor elements on opposing sides of the transducer cavity recess.

[00168] Embodiment 15: The method of Embodiment 14, further comprising forming at least one of trenches and holes in the material of the doped semiconductor substrate adj acent to the transducer cavity recess between the doped semiconductor elements on opposing sides of the transducer cavity recess.

[00169] Embodiment 16: The method of any one of Embodiments 9 through 15, wherein forming trenches in a doped semiconductor substrate comprises forming additional doped semiconductor elements between the trenches.

[00170] Embodiment 17: The method of any one of Embodiments 9 through 16, wherein attaching an IC structure to the doped semiconductor substrate and to the doped semiconductor elements comprises physically and electrically attaching conductive pads of the IC structure to respective doped semiconductor elements.

[00171] Embodiment 18: The method of any one of Embodiments 9 through 17, further comprising attaching a higher level substrate to the IC structure on a side thereof opposite the doped semiconductor substrate.

[00172] Embodiment 19: A semiconductor structure, comprising: a doped semiconductor substrate comprising a first major surface on a first side thereof and a second major surface on a second, opposing side thereof; and a discrete doped semiconductor element physically and electrically isolated from adjacent portions of the doped semiconductor substrate by at least one trench, wherein the discrete doped semiconductor element forms an electrical interconnection between a first electrical feature associated with the first major surface of the doped semiconductor substrate and a second electrical feature associated with' the second major surface of the doped semiconductor substrate.

[00173] Embodiment 20: The semiconductor structure of Embodiment 19, further comprising a first substrate comprising the first electrical feature attached to the first major surface of the doped semiconductor substrate. [00174] Embodiment 21 : The semiconductor structure of any one of Embodiments 19 and 20, further comprising a second substrate comprising the second electrical feature attached to the second major surface of the doped semiconductor substrate.

[00175] Embodiment 22: An at least partially formed MEMS device, comprising: a structure including integrated circuitry, at least one first conductive pad operatively coupled to the integrated circuitry, and second conductive pads operatively coupled to the integrated circuitry; and a doped semiconductor substrate attached to the structure including integrated circuitry and including at least one first doped semiconductor element physically and electrically contacting the at least one first conductive pad, second doped semiconductor elements respectively physically and electrically contacting the second conductive pads, and a conductive material formed from the doped semiconductor substrate physically and electrically connecting the second doped

semiconductor elements.

[00176] Embodiment 23: The device of Embodiment 22, wherein interior surfaces of the second doped semiconductor elements and the conductive material physically and electrically connecting the second doped semiconductor elements define a transducer cavity recess formed in the doped semiconductor substrate.

[00177] Embodiment 24: The device of any one of Embodiments 22 and 23, wherein the conductive material electrically connecting the second doped semiconductor elements includes at least one of trenches and holes formed therein.

[00178] Embodiment 25: The device of Embodiment 24, wherein the conductive material defines a MEMS transducer.

[00179] Embodiment 26: The electronic device of Embodiment 25, wherein the MEMS transducer comprises at least one of a plate acoustic wave resonator, a flexural mode resonator, a bulk acoustic wave (BAW) resonator, a surface acoustic wave (SAW) resonator, and a film bulk acoustic resonator (FBAR).

[00180] Embodiment 27: The electronic device of any one of Embodiments 22 through Embodiment 26, further comprising a cap structure attached to the doped semiconductor substrate on an opposite side of the doped semiconductor substrate from the structure including integrated circuitry including the integrated circuitry.

[00181] Embodiment 28: The electronic device of any one of Embodiments 22 through Embodiment 27, further comprising a higher level substrate structurally attached to the structure including integrated circuitry on an opposite side thereof from the doped semiconductor substrate and electrically coupled to electrically conductive features of the structure including integrated circuitry.

[00182] Embodiment 29: A method of forming a semiconductor device comprising an integrated circuit and a MEMS device operatively coupled with the integrated circuit, comprising: forming an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate; fabricating at least a portion of an integrated circuit on the first major surface of the substrate; providing a doped semiconductor material on the second major surface of the substrate; and selectively removing material from the doped semiconductor material to form a transducer of a MEMS device electrically coupled to the integrated circuit using the electrically conductive via.

[00183] Embodiment 30: The method of Embodiment 29, further comprising selecting the transducer to comprise at least one of a resonator and a sensor.

[00184] Embodiment 31 : The method of any one of Embodiments 29 and 30, further comprising forming a transducer cavity recess in the second major surface of the substrate, wherein selectively removing material from the doped semiconductor material comprises selectively removing material from a portion of the doped semiconductor material adjacent to the transducer cavity recess.

[00185] Embodiment 32: The method of any one of Embodiments 29 through 31, wherein providing a doped semiconductor material on the second major surface of the substrate comprises electrically coupling the doped semiconductor material to the electrically conductive via.

[00186] Embodiment 33: The method of any one of Embodiments 29 through 32, wherein providing a doped semiconductor material on the second major surface of the substrate comprises: bonding an SOI-type structure comprising the doped semiconductor material to the second major surface of the substrate; and removing a portion of the SOI-type structure and leaving the doped semiconductor material bonded to the second major surface of the substrate.

[00187] Embodiment 34 : A semiconductor structure comprising: at least a portion of an integrated circuit formed on a first major surface of a substrate; a doped semiconductor material bonded to a second major surface of the substrate opposite the first major surface, the doped semiconductor material at least partially covering a transducer cavity recess formed in the second major surface of the substrate; and a conductive via extending through the substrate and electrically coupling the doped semiconductor material to the at least a portion of the integrated circuit.

[00188] Embodiment 35: The semiconductor structure of Embodiment 34, wherein the doped semiconductor material comprises a transducer of a MEMS device

[00189] Embodiment 36: The semiconductor structure of Embodiment 35, wherein the transducer is defined by at least one trench formed in the doped semiconductor material, the at least one trench electrically isolating the transducer from adjacent portions of the doped semiconductor material.

[00190] Embodiment 37: The semiconductor structure of Embodiment 36, wherein the conductive via electrically couples the transducer to the at least a portion of the integrated circuit.

[00191] Embodiment 38: A method of forming a semiconductor device comprising an integrated circuit and a MEMS device operatively coupled to the integrated circuit, the method comprising: fabricating at least a portion of an integrated circuit on a first major surface of a substrate; providing a dielectric material over the at least a portion of the integrated circuit on a side thereof opposite the substrate; and providing a doped semiconductor material over the dielectric material on the side thereof opposite the substrate.

[00192] Embodiment 39: The method of Embodiment 38, further comprising forming a transducer of a MEMS device from a portion of the doped semiconductor material.

[00193] Embodiment 40: A semiconductor structure, comprising: an integrated circuit on a first major surface of a substrate; a dielectric material over the integrated circuit on a side thereof opposite the substrate; a semiconductor-on-insulator-type structure including a doped

semiconductor material over the dielectric material on a side thereof opposite the integrated circuit; and a conductive via extending through the dielectric material from the integrated circuit to the doped semiconductor material.

[00194] Embodiment 41 : The semiconductor structure of Embodiment 40, wherein: the dielectric material includes a transducer cavity recess formed in a surface thereof opposite the integrated circuit; and the doped semiconductor material of the semiconductor-on-insulator-type structure extends over the transducer cavity recess formed in the surface of the dielectric material.

[00195] The example embodiments of the disclosure described above do not lim it the scope of the invention, since these embodiments are merely examples of embodiments of the invention, which is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternate useful combinations of the elements described, may become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims

CLAIMS What is claimed is:

1. A method of forming a semiconductor structure including an electrical interconnection, the method comprising:

selectively removing material from a doped semiconductor substrate to form one or more

trenches and to form at least one doped semiconductor element defined by the one or more trenches;

attaching a substrate to the doped semiconductor substrate and to the at least one doped

semiconductor element; and

removing material from the doped semiconductor substrate to expose the one or more trenches and to physically and electrically isolate the at least one doped semiconductor element from adjacent portions of the doped semiconductor substrate.

2. The method of claim 1, further comprising attaching another substrate to the doped semiconductor substrate on a side thereof opposite the substrate.

3. The method of claim 2, wherein attaching another substrate to the doped semiconductor substrate comprises physically and electrically contacting at least one conductive member of the another substrate to the at least one doped semiconductor element.

4. The method of claim I, wherein attaching a substrate to the doped semiconductor substrate and to the at least one doped semiconductor element comprises physically and electrically contacting at least one conductive member of the substrate to the at least one doped semiconductor element.

5. The method of claim 1 , wherein attaching a substrate to the doped semiconductor substrate comprises attaching the substrate to the doped semiconductor substrate using at least one of a direct bonding process, a thermocompression bonding process, and a non- thermocompression bonding process.

6. The method of claim 1 , wherein removing material from the doped semiconductor substrate to expose the one or more trenches comprises removing material from the doped semiconductor substrate through at least one of an abrasive planarization operation and an etching operation.

7. The method of claim 1, further comprising forming the doped semiconductor substrate to include a semiconductor material and one or more dopants at formation.

8. The method of claim 1, further comprising at least partially filling the one or more trenches with a dielectric material.

9. A semiconductor structure, comprising:

a doped semiconductor substrate comprising a first major surface on a first side thereof and a second major surface on a second, opposing side thereof; and

a discrete doped semiconductor element physically and electrically isolated from adjacent

portions of the doped, semiconductor substrate by at least one trench, wherein the discrete doped semiconductor element forms an electrical interconnection between a first electrical feature associated with the first major surface of the¹ doped semiconductor substrate and a second electrical feature associated with the second major surface of the doped semiconductor substrate.

10. The semiconductor structure of claim 9, further comprising a first substrate comprising the first electrical feature attached to the first major surface of the doped

semiconductor substrate.

1 1. The semiconductor structure of claim 10, further comprising a second substrate comprising the second electrical feature attached to the second major surface of the doped semiconductor substrate.