WO2014014968A1 - Integrated circuits having integrated acoustic communication links - Google Patents

Integrated circuits having integrated acoustic communication links Download PDF

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Publication number
WO2014014968A1
WO2014014968A1 PCT/US2013/050772 US2013050772W WO2014014968A1 WO 2014014968 A1 WO2014014968 A1 WO 2014014968A1 US 2013050772 W US2013050772 W US 2013050772W WO 2014014968 A1 WO2014014968 A1 WO 2014014968A1
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WO
WIPO (PCT)
Prior art keywords
ultrasound
transducer
signal
circuit
acoustic
Prior art date
Application number
PCT/US2013/050772
Other languages
French (fr)
Inventor
Amit Lal
Serhan Ardanuc
Jason T. HOOPLE
Justin C. KUO
Original Assignee
Cornell University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cornell University filed Critical Cornell University
Publication of WO2014014968A1 publication Critical patent/WO2014014968A1/en
Priority to US14/273,540 priority Critical patent/US10217045B2/en
Priority to US15/880,261 priority patent/US10860916B2/en
Priority to US17/114,040 priority patent/US11681897B2/en

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0292—Electrostatic transducers, e.g. electret-type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B06B1/0607—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using multiple elements
    • B06B1/0622—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using multiple elements on one surface
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B11/00—Transmission systems employing sonic, ultrasonic or infrasonic waves
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R17/00—Piezoelectric transducers; Electrostrictive transducers

Definitions

  • Semiconductor fabrication and nanotechnology provide techniques or processes for fabricating structures, devices, and systems with features at a micro or nano scale, e.g., structures in a range of one to hundreds of nanometers in some applications. Integrated circuits and microprocessors are examples of such structures, devices and systems.
  • a semiconductor integrated circuit device having wireless ultrasonic communication links includes a semiconductor substrate, layers formed over the
  • each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements.
  • Each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
  • Implementations of the device can optionally include one or more of the following features.
  • the semiconductor substrate can be formed of a substrate material that includes silicon
  • the ultrasound transducer elements within each ultrasound transducer can include a piezoelectric material layer that includes aluminum nitride (A1N) amongst other piezoelectric materials
  • the layers formed over the semiconductor substrate and patterned to form circuit elements can be complementary metal-oxide- semiconductor (CMOS) layers.
  • CMOS complementary metal-oxide- semiconductor
  • the ultrasound transducer elements within each ultrasound transducer includes a piezoelectric material layer that can include lead zirconate titanate (PZT).
  • the ultrasound transducers can be formed in one layer of the layers over the semiconductor substrate or on the side opposing the circuitry.
  • the device can further include a reflector layer formed over the semiconductor substrate to provide a boundary to reflect an ultrasound signal from one ultrasound transducer to another ultrasound transducer.
  • the ultrasound transducers can be formed in two or more different layers over the semiconductor substrate as a three-dimensional (3D) array.
  • the layers formed over the semiconductor substrate can include (1) front- end-of-line (FEOL) layers that are formed and patterned to include the circuit elements including transistors, and (2) back-end-of-line (BEOL) layers over the FEOL layers to include wired interconnects between the ultrasound transducers and respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers.
  • FEOL front- end-of-line
  • BEOL back-end-of-line
  • the device can further include transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer, in which each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements.
  • each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements.
  • each transducer driver circuit can include a phase generation circuit to control phase delays of different ultrasound transducer elements within each ultrasound transducer.
  • the device can further include physical acoustic structures in the layers formed over the semiconductor substrate to facilitate guiding of ultrasound signals from ultrasound transducers.
  • the physical acoustic structures include metal reflectors for reflecting sound, e.g., in which one or more physical acoustic transducers can use surface acoustic waves to transmit information to one or more other physical acoustic transducers.
  • the circuit elements formed in the layers can include an field-programmable gate array (FPGA) having FPGA logic elements that are interconnected via ultrasonic communication links between the respective ultrasound transducers, wherein the FPGA is programmable by adjusting the ultrasonic communication links between the respective ultrasound transducers.
  • FPGA field-programmable gate array
  • the device can further include transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer, in which each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements, and in which the transducer driver circuits are configured to control or adjust ultrasonic communication links between the respective ultrasound transducers to effectuate various interconnects between the circuit elements for different circuit functions, thus providing a programmable circuit device.
  • each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer, in which each transducer driver
  • the device can further include a monitor circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a local condition that is reflected in a received ultrasound signal at the ultrasound transceiver, rendering the array of ultrasound transducers to function as an array of circuit sensors for monitoring the device operating conditions.
  • the monitor circuit can be configured to monitor a temperature at different locations within the device.
  • the monitor circuit can be configured to monitor conditions of physical contacts at different locations within the device.
  • the device can further include a circuit security verification circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a physical signature that is reflected in a received ultrasound signal at the ultrasound transceiver to provide an indication of whether a circuit layout of the device matches a predetermined circuit layout.
  • a circuit security verification circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a physical signature that is reflected in a received ultrasound signal at the ultrasound transceiver to provide an indication of whether a circuit layout of the device matches a predetermined circuit layout.
  • the disclosed technology integrates piezoelectric and electrostatic actuator arrays into 3D IC chips to form sonar arrays that transmit from one location in chip to another.
  • this allows for tunable sonic communication links between any two points.
  • the sonars can also be used to transmit signals from one chip to another through the common substrate, while making use of the frequency-selective nature of acoustic transducers and waveguides to communicate to multiple receivers over different frequency bands at the same time, e.g., via frequency division multiplexing.
  • Frequency division multiplexing can be implemented to carry different channels at different acoustic frequencies.
  • the integrated sonars can also be used to interrogate defects in chip interconnects over time to measure chip parameters and interfaces to determine reliability.
  • the disclosed technology can provide ultrasonic communication links in integrated circuit devices that enables programmable interconnections between circuit elements of the devices, provides local sensing of structures and operating conditions of the devices for monitoring health of the device and for controlling distribution of processing within the integrated circuit device to prolong the device lifetime, and enhances the physical security of the integrated circuit device, e.g., by using ultrasonic transducers as imaging sensors to read physical patterns and determine acoustic signatures.
  • FIG. 1A shows an architectural diagram of a conventional integrated circuit chip design and an architectural diagram of an integrated circuit chip design of the disclosed technology.
  • FIG. IB shows a diagram of the disclosed acoustic in-chip communication signaling IC chip design.
  • FIG. 1C shows a schematic illustration of an exemplary chip-scale wireless communications IC device.
  • FIG. ID shows an inset schematic from FIG. IC showing an exemplary CMOS- integrated piezoelectric transducer array of an exemplary sonar module.
  • FIG. IE shows an inset schematic from FIG. ID showing an exemplary CMOS- integrated piezoelectric transducer element.
  • FIG. IF shows an inset schematic from FIG. ID showing a cross-sectional view of the exemplary CMOS-integrated piezoelectric transducer element.
  • FIG. 2A shows a diagram of an exemplary one dimensional array of transducer elements spaced apart and used to focus on a single point.
  • FIG. 2B shows data plots of exemplary acoustic responses from an acoustic radiator source.
  • FIG. 3A shows an exemplary simulation plot of phased array acoustic radiation pressure for zero degree phase shift between elements.
  • FIG. 3B shows an exemplary simulation plot of acoustic radiation pressure for 20 degrees phase shift between elements of a phased array.
  • FIG. 3C shows a plot of the applied signal voltage for an exemplary simulation of the time domain response of an exemplary transducer element generating an acoustic pulse.
  • FIG. 3D shows an exemplary simulation plot of the acoustic radiation pressure for the initial pulse.
  • FIG. 3E shows a data plot of the signal received by an exemplary transducer element in the array.
  • FIG. 3F shows an exemplary simulation plot of acoustic radiation pressure for the traveling and reflected pulse.
  • FIG. 4A shows a cross-sectional view of a schematic illustration of one exemplary piezoelectric transducer element produced using an exemplary fabrication process.
  • FIG. 4B shows a top view of a CAD layout diagram and an image of an exemplary acoustic in-chip communication device produced using an exemplary fabrication process.
  • FIGS. 5A and 5B show an image and schematic illustration depicting an exemplary acoustic in-chip communication device in an exemplary implementation setup configuration.
  • FIG. 6A shows a data plot showing exemplary results of reflection scattering parameters for the two transducer elements in an exemplary sonar array in-chip
  • FIG. 6B shows a data plot showing exemplary results of a transmission scattering parameter for the two exemplary transducer elements in the array.
  • FIG. 7A shows a schematic illustration of an exemplary 3D chip-scale wireless communications IC device.
  • FIG. 7B shows an inset schematic from FIG. 7A showing an exemplary configuration of the acoustic propagation medium sub-layer.
  • FIG. 8 shows a diagram of an exemplary PZT transfer process to an exemplary CMOS based IC chip.
  • FIG. 9 shows a diagram of an exemplary BEOL stack including metal reflectors to optimize wave coupling to the exemplary semiconductor substrate.
  • FIG. 10 shows a process diagram of an exemplary fabrication technique to produce wireless in-chip communication devices of the disclosed technology.
  • FIG. 11A shows diagrams of exemplary delay lines including one or more inverter delay elements.
  • FIG. 11B shows a diagram of an exemplary 4-bit current splitting D/A converter.
  • FIG. llC shows a diagram of an exemplary delay line circuit followed by inverter chain buffer.
  • FIG. 11D shows a diagram of an exemplary quadrature mixing circuit for amplitude and phase shift control with two analog weights.
  • FIG. HE shows a diagram of an exemplary unit cell of an analog memory.
  • FIG. 11F shows a diagram of an exemplary analog memory for multiple phase generation.
  • Silicon-based and other semiconductor integrated circuit (IC) chips typically use conductive wires for in-chip communication links, which create several limitations in IC chip designs including spot heating, thermal cycling degradation of components, signal interference, among others.
  • Some chip-scale communications approaches to mitigating such problems associated with conductive wires include optical and/or wireless in-chip communications which have been explored in several physical domains, but complement and/or add to the traditional metal interconnects.
  • photonic interconnects have been proposed as a way to transmit digital and analog information on optical waveguides integrated into a complementary metal- oxide-semiconductor (CMOS) stack.
  • CMOS complementary metal- oxide-semiconductor
  • optical waveguide interconnects can provide very high bandwidth and low power consumption information transmission within chips.
  • CMOS compatible optical waveguides due to the internal losses of optical signals in CMOS compatible optical waveguides, and the resulting high power for optical links, much work is still needed for use of optical interconnects.
  • one of the drawbacks of the photonic links is that the links are defined by lithography in the front end of line (FEOL) or back end of line (BEOL) IC fabrication processes, which can enable adversarial interests in the IC design to physically detect function, e.g., by detecting scattered light, or tracing the optical paths.
  • FEOL front end of line
  • BEOL back end of line
  • radio-on-chip networks have been proposed for ad-hoc wireless networks on chip.
  • such radio-on-chip networks can transmit over the chip using RF radio. Due to the large signal wavelengths corresponding to common RF frequencies, such RF transmitters are point emitters operating in the near field configurations that tend to use coded signals to reduce EM interference and thus require significant power consumption.
  • FPGAs field programmable gate arrays
  • the key to determining the functionality of an FPGA is determining its bit-stream patterns with various parts of FPGAs.
  • Bit-streams can be encrypted in high-end FPGAs to protect the contents of the configuration memory.
  • the encryption key e.g., a key based on the advanced encryption standard (AES)
  • AES advanced encryption standard
  • Obfuscation is also a commonly used software technique, and can also be applied to the hardware description language used to create the design mapped to the FPGA.
  • microelectronic devices were manufactured by companies that both designed and produced the devices. At that time, manufacturing involved fine-tuning device and manufacturing process parameters, which often warranted a need for redesign involving both the research and development (R&D of the microcircuit design and the manufacturing processes.
  • R&D research and development
  • manufacturing processes are highly advanced and standardized such that multiple microelectronic device designs can be fabricated by a single, large-scale manufacturing entity. For example, separation of manufacturing and design has created a new model for microelectronic device fabrication: the foundry model.
  • the foundry model refers to the separation of a semiconductor fabrication plant operation (foundry) from an integrated circuit design operation, e.g., enabling a "fabless" semiconductor company to operate without any semiconductor manufacturing capability but rather contract production from a separate manufacturer entity (merchant foundry). While the foundry model is economically efficient for rapid development of integrated circuit devices, it is subject to device security concerns including theft of device designs and unauthorized alterations or modifications during production by the merchant foundry or other adversarial actors.
  • the technology disclosed in this patent document uses ultrasound transducers as communication transceivers for providing wireless ultrasonic communication interconnects between different circuit elements without hardwiring between circuit elements and as built- in circuit sensors for sensing circuit conditions.
  • Such ultrasonic communication uses ultrasound transducers as communication transceivers for providing wireless ultrasonic communication interconnects between different circuit elements without hardwiring between circuit elements and as built- in circuit sensors for sensing circuit conditions.
  • interconnects can significantly reduce the metal interconnects between circuit elements.
  • the disclosed technology can be used to provide programmable or reconfigurable interconnects to enable fixed circuit elements to form various functionally different circuit devices and to conceal the final circuit functions and designs from an unauthorized party and from the physical fabrication or manufacturing of the circuits.
  • the disclosed technology can also be implemented to address the above aforementioned technical problems and limitations.
  • the disclosed technology integrates ultrasound actuator arrays into 2D or 3D IC chips to form sonar arrays that transmit a directional sonic pulse from one functional unit or module in the chip to another, providing tunable sonic intra-chip communication links between any two points by adjusting the delays/phases and/or amplitudes of the sonic communication signals on transmit.
  • the ultrasound actuators can be based on piezoelectric materials or elements.
  • the ultrasound actuators can be configured using electrostatic transducers, e.g., including
  • CMUT capacitive/electrostatic materials or elements
  • CMUT capacitive micro-machined ultrasonic transducers
  • Examples of CMUT transducer elements are described in Wygant, I., "A comparison of CMUTs and piezoelectric transducer elements for 2D medical imaging based on conventional simulation models", Ultrasonics Symposium (IUS), 2011 IEEE International, Vol. 100, No. 18-21, Oct. 2011, which is incorporated by reference as part of this patent document. More generally, the disclosed technology can implement the ultrasound in-chip wireless communication links using any of piezoelectric, electrostatic, magnetic, thermal,
  • the conventional CMOS IC chip design 10 includes a bulk semiconductor portion, e.g., bulk silicon die or substrate, upon which an front-end-of- line (FEOL) portion is structured to include individual and discrete circuit elements, e.g., transistors, capacitors, resistors, etc., patterned in layers within the FEOL portion formed over the semiconductor substrate.
  • the FEOL portion of the conventional IC chip design 10 can include CMOS circuit elements for one or more digital logic circuits.
  • the conventional IC chip design 10 includes a back-end-of-line (BEOL) portion to provide the hardwiring connects within each circuit element and hardwiring interconnects between the discrete circuit elements in the FEOL portion, such as metal contacts or lines.
  • BEOL back-end-of-line
  • the BEOL includes conductive contacts such as metal lines, metal contacts or metal vias, insulating layers or materials (e.g., dielectrics), and bonding sites for chip-to-package connections.
  • the interconnects in the BEOL in the IC chip design 10 link the discrete circuit elements in FEOL to form functional circuit blocks.
  • the architectural diagram of the IC chip design 20 of the disclosed technology shown in FIG. 1A is based on a different interconnect configuration using ultrasound communication links.
  • the IC chip design 20 includes a bulk semiconductor portion, a front- end-of-line (FEOL) portion that includes discrete circuit elements, a back-end-of-line (BEOL) portion and ultrasound transducer modules (e.g., piezoelectric transducer modules).
  • FEOL front- end-of-line
  • BEOL back-end-of-line
  • ultrasound transducer modules e.g., piezoelectric transducer modules
  • the IC chip design 20 uses the ultrasound transducer modules as communication nodes to provide a significant portion of or all of inter-element communication interconnects between different circuit elements in the FEOL portion by using wireless ultrasound signaling as interconnects.
  • the BEOL portion of the IC chip design 20 provides conductive connections between the ultrasound transducer modules and circuit elements in the FEOL portion and may also include, in some implementations, certain interconnects for the circuit elements in the FEOL portion.
  • the circuit elements in the FEOL portion are largely discrete or isolated circuit elements or circuit element blocks or clusters of two or more interconnected circuit elements.
  • the ultrasound transducer modules When the ultrasound transducer modules are activated to provide desired interconnects between the circuit elements in the FEOL portion, the circuit elements in the FEOL portion form a functional IC device under the IC chip design 20 and become functional. Therefore, the ultrasound transducer modules provide ultrasonic or acoustic communication signaling capabilities of the discrete circuit elements (e.g., CMOS digital logic circuits) to
  • the IC chip design 20 includes control circuits including driver, read, and logic circuits as part of the FEOL portion that electrically communicate with the piezoelectric transducer modules via electrical connections of the BEOL portion.
  • the BEOL portion can also include metal reflectors or other components that aid in the acoustic signal propagation.
  • the IC chip design 20 is shown to have a particular structure where the FEOL portion, the BEOL portion, and the layers for the ultrasound transducer modules are formed in the shown sequential order over the substrate. This configuration of the IC chip design 20 is an example only and other configurations or structural sequences may be implemented depending the specific needs of IC designs and circuit applications.
  • An ultrasound signal tends to have a footprint and spatial extent determined by the acoustic frequency of the signal and the physical conditions of the signal path that may cause diffraction, scattering and spreading of the ultrasound signal.
  • the smallest beam spot size is dictated by the diffraction limit on the order of one half of the ultrasound signal wavelength.
  • a metal interconnect may be configured to have a smaller footprint than that of an ultrasound signal interconnect.
  • FIG. IB shows a functional diagram 30 of the IC chip design 20 of the disclosed technology illustrating wireless intra-communication in a semiconductor medium between circuit modules of the IC chip.
  • the diagram 30 shows an exemplary embodiment of the IC chip design 20 in which an array of 1, 2, ... N piezoelectric transducer modules are operable to transmit and receive directional acoustic signals carrying information to communicate between the transducer modules.
  • the wavelength of the sonic signals depends on the frequency and propagation speed of the signal, and the propagation speed depends on the medium through which the signal propagates.
  • the speed of sonic transmission in a semiconductor medium e.g., ⁇ 9xl0 3 m/s in a dielectric medium such as silicon
  • the speed of electromagnetic transmission e.g., 2.997xl0 8 m/s.
  • sonic signals can be transmitted at wavelengths in the microns for desired frequencies in the GHz range, e.g., protecting the acoustic communication signal from RF and other noise within the IC circuit.
  • the array of piezoelectric transducer modules are communicatively coupled to individual control circuit elements or blocks (e.g., of two or more circuit elements), e.g., which can be formed in the FEOL portion over the
  • the individual control circuits can include a driver circuit to generate an electric signal to the corresponding transducer module that determines the magnitude, frequency, and/or phase of the acoustic communication signal.
  • the individual control circuits can include a read circuit to receive a transduced electric signal from the corresponding transducer module that receives the transmitted acoustic communication signal.
  • the driver circuits and/or read circuits can include analog and digital circuit components (e.g., inverter delay elements, analog-to-digital converters (ADC) and digital-to-analog converters (DAC), amplifiers, etc.).
  • the individual control circuits can include a logic circuit, e.g., of digital and/or analogic logic circuit components, to provide and receive electric signals as digital waveform carrying the information to and from the driver and read circuits, respectively, which can be processed by other circuits of the IC chip.
  • the digital waveform can be a phase-coded and/or frequency-coded waveform or waveforms included in a composite waveform.
  • the logic circuits can be configured of one or more CMOS layers.
  • each of the ultrasound transducer modules of FIGS. 1A and IC is configured to generate a steerable acoustic ultrasound signal to target one or more desired ultrasound transducer modules to provide desired ultrasound interconnects for the circuit elements associated with the transmitting and receiving ultrasound transducer modules.
  • each ultrasound transducer module includes multiple ultrasound transducer elements, e.g., in a 2-D array, and operates to control the relative amplitude and phase values of ultrasound signals generated by multiple ultrasound transducer elements so that the ultrasound signals are added up to form a final composite ultrasound signal that is directed to a particular location or region in the circuit where one or more targeted receiving ultrasound transducer modules are located.
  • Each ultrasound transducer module can be operated as a transmitter and a receiver and thus is a ultrasound transducer transceiver element.
  • the driver/read and logic circuits for the ultrasound transducer modules are shown to be part of the FEOL portion in FIG. IB, but may also be in the BEOL portion or other layers.
  • the use of multiple ultrasound transducer elements for an ultrasound transducer module as a transceiver device for transmitting steerable output ultrasound signals and for receiving/detecting ultrasound signals can be implemented in various configurations, including some examples described in "Two-Port Electromechanical Model for Bulk-Piezoelectric Excitation of Surface Micromachines Beam Resonators" by Ardanuc and Lai in Journal of Microelectromechanical Systems, pp. 626-640 in Vol. 18, No.
  • the disclosed acoustic in-chip communication technology can be implemented to provide many advantages.
  • the disclosed acoustic in-chip communication can use linear and two-dimensional arrays of piezoelectric transducers to generate directional ultrasonic pulses in three dimensions for CMOS information processing and trusted integrated circuit (TIC) operation.
  • TIC trusted integrated circuit
  • exemplary phased array sonic transducers can be operated at GHz frequencies alongside and/or integrated with other analog or digital chip logic on a single IC chip.
  • the disclosed technology can be implemented in a variety of applications including medical (ultrasound) imaging, non-destructive evaluation (NDE) of IC chip components, and sonar communications.
  • these arrays have operated in the frequency range of l-30MHz for medical imaging, 100 kHz to 10 MHz for NDE, and 1-100 kHz for sonar communications.
  • the wavelength in silicon can be in an exemplary range of 9 to 0.9 ⁇ . Since the elements of a sonar array are spaced by fractions of the sonic wavelength (e.g., ⁇ /2), chip devices employing the disclosed technology can be configured with hundreds to thousands of sonar arrays, e.g., for a millimeter to centimeter sized IC chip.
  • the disclosed acoustic in-chip communication technology can provide a sonic 2D or 3D programmable interconnect framework for massively parallel computation in IC chip devices.
  • the sonic 2D or 3D IC interconnects can enable
  • encrypted pulse sequences can be used to form secure communication channels that are ad-hoc in nature, e.g., providing programmable wireless interconnections between discrete IC elements (e.g., of the FEOL portion).
  • the added interconnect capability can allow the programmers to use ultra-high fan-out and fan-in capabilities, e.g., which is often needed to implement algorithms in associative pattern recognition algorithms, such as in applications including face or feature recognition in image processing.
  • the added acoustic programmable wireless link can relieve the communications bottleneck encountered in multi-core digital systems.
  • the disclosed acoustic in-chip communication technology can provide sonar based chip-interrogation.
  • the disclosed integrated piezoelectric transducer arrays can be used to interrogate the chip or a multi-chip package to realize an integrated non-destructive evaluation (NDE) capability.
  • NDE non-destructive evaluation
  • Such interrogations can be employed for chip-scale NDE of wire-bonds, chip-to-chip interconnects, vias, etc.
  • an adversary initiated chip manipulation could be detected at a very early stage (e.g., such as by a merchant foundry for manufacturing of an IC chip design).
  • early detection of chip tampering could lead to immediate removal of memory or self-destruction for trusted use of integrated circuits.
  • IC devices generate substantial amounts of heat that can (1) lead to degradation of portions or the entire IC device and (2) lower performance (e.g., speed) of the device during operation, e.g., particularly during extensive periods of use.
  • IC devices can undergo various spot heating, in which particular locations or regions (e.g., circuit blocks) of the IC generate high heat.
  • the disclosed integrated piezoelectric transducer arrays can be used to monitor spot heating within the IC device to which the disclosed transducer arrays are employed.
  • the disclosed integrated piezoelectric transducer arrays can be used to image and thereby monitor structural defects and fractures of in-chip elements and chip-to-chip interconnection structures that can lead to device failure.
  • thermal cycling of ICs in various microchip-based devices like computers, mobile communication (smart phone devices), etc. can also cause degradation at the grease interface between IC chips and their coupled heat syncs.
  • delamination of solder balls at wire bonding interfaces is a common problems that result in premature failure of such chip-based devices.
  • sonar based chip-interrogation can be implemented to prolong the lifetime of such chip-based devices.
  • the disclosed acoustic in-chip communication technology can provide sonar based lock-key operations.
  • a lock/key system is employed to ensure activation by a known entity, and deem the chip inoperable by an adversary.
  • Current methods include MEMS gears and beams for enabling a lock, which although effective can be not as reliable due to stiction.
  • the disclosed integrated piezoelectric transducer arrays can be used to provide sonar links to read surfaces preprogrammed to reflect ultrasonic pulses through a set of programmable reflectors, triggering a device if the pulse makes it to a target receiver on chip.
  • an integrated circuit chip device with wireless on-chip [0060] In one aspect, an integrated circuit chip device with wireless on-chip
  • communications capabilities includes a semiconductor substrate capable of propagating acoustic energy signals and an array of acoustic signaling modules formed on the substrate and structured to include a sub-array of acoustic transducer elements capable of transmitting and receiving the acoustic energy signals, in which each acoustic transducer element is operable to generate an acoustic communications signal to propagate through the substrate based on an electronic control signal and to receive the acoustic communications signal an acoustic signaling module to communicate with one or more other acoustic signaling modules.
  • the device can further include a control circuit layer formed on the semiconductor substrate and under the array of acoustic signaling modules to receive an external electronic signal and produce the electronic control signal to one or more acoustic transducer elements.
  • the acoustic communications signal can be modulated by the device using one or more of amplitude modulation, frequency modulation, or phase modulation.
  • a semiconductor integrated circuit device having wireless ultrasonic communication links includes a semiconductor substrate, layers formed over the semiconductor substrate and patterned to form circuit elements including transistors, and an array of ultrasound transducers formed in the layers over the semiconductor substrate, each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements.
  • Each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
  • FIG. 1C shows a schematic illustration of an exemplary chip-scale wireless communications IC device 100 including an array of acoustic transceiver (sonar) modules 110 capable of transmitting and receiving acoustic communications signals.
  • the device 100 is structured to include a substrate 120 to provide a base for the array of sonar modules 110 and formed of a solid state semiconductor material capable of propagating acoustic energy (e.g., ultrasound signal) within the device 100, e.g., including between sonar modules 110 of the array.
  • the sonar modules 110 can be configured as thin films of aluminum nitride (A1N) and/or lead zirconium titanate (PZT) on top of a metallization layer.
  • A1N aluminum nitride
  • PZT lead zirconium titanate
  • the acoustic propagation medium 120 can include silicon, e.g., such as the silicon material of a silicon die.
  • Each or any of the sonar modules 110 can be structured to include a sub-array of individual piezoelectric transducer elements 130 (shown in FIG. ID), e.g., sometimes referred to herein as pixel elements or pixels.
  • the sub-array of individual piezoelectric transducer elements 130 can be communicatively linked to underlying electronic control circuits (shown in FIG. ID as control circuit layer 132).
  • the electronic control circuits can include driving circuits for providing the driving signals that the transducer elements 130 transduce to produce the acoustic communication signals and logic circuits to process received acoustic communication signals transduced by the transducer elements 130.
  • the device 100 can further include an acoustic reflector / mismatching layer 125 capable of reflecting or refracting the exemplary intra-device ultrasound signal, e.g., which can be used to steer the ultrasound communication signal from one or more sonar modules 110 to another one or more sonar modules 110.
  • the acoustic reflector layer 125 can be configured under the acoustic propagation medium substrate 120, as shown in FIG. IC, and/or be configured along one or more sides of the substrate 120.
  • the device 100 can further include an acoustic absorber layer 126 to absorb the exemplary intra-device ultrasound signal, e.g., preventing the ultrasound communication signal from transmission beyond the device 100.
  • the acoustic absorber layer 126 is configured along the sides of the acoustic propagation medium substrate 120.
  • the device 100 can be included in an array of devices 100 for both intra- and inter- device in-chip wireless communication signaling.
  • the device 100 can be included on a conventional integrated circuit chip, as described later in this patent document.
  • the piezoelectric transducer elements 130 of the sonar modules 110 can be configured with uniform or periodic spacing in the pixel array, e.g., including ⁇ /2 spacing.
  • each piezoelectric transducer element 130 of the sub-array (of a sonar module 110) is a fraction of a wavelength in lateral dimensions, relatively small phased arrays for sonar transmit and receive blocks can be implemented.
  • each sonar module 110 can include 10-20 pixels which are placed approximately one-half of an acoustic wave wavelength apart.
  • each pixel can be configured to a size in a range of 3-10 ⁇ , such that each sonar module 110 includes a planar size of -100 x 100 ⁇ , e.g., which is about the size of a contact pad on a CMOS chip.
  • the acoustic propagation medium substrate 120 can be configured to a height of 750 ⁇ (or 84 ⁇ in this example).
  • FIGS. IE and IF show inset schematics from FIG. ID showing the piezoelectric transducer element 130 of the device 100 in a three-dimensional view and a cross-sectional view, respectively, over a control circuit layer 132 and the substrate 120.
  • the acoustic propagation medium material of the substrate 120 can include bulk Silicon material 131.
  • the control circuit layer 132 can be structured to include one or more CMOS active layers 132 structured to include individual control circuit blocks corresponding to the individual piezoelectric transducer elements 130 of the sub-array, e.g. in which the control circuits can include one or more driving circuits, read circuits, and logic circuits including digital logic, analog logic and/or amplifiers, which are formed on the exemplary bulk Silicon layer 131.
  • a first metal layer 133 can be formed over the one or more CMOS active layers 132.
  • the bulk Silicon substrate 131, the CMOS active layers 132, and the first metal layer 133 form a FEOL region of the device 100.
  • the transducer element 130 can be structured to include more metal layers, e.g., including a second, a third, and a fourth metal layers 134a, 134b, and 134c, respectively, as shown in FIGS. IE and IF.
  • the transducer element 130 can be structured to include an electrode structure layer 136b, upon which, a piezoelectric material (e.g., A1N) layer 136a is formed.
  • the transducer element 130 can be structured to include an intermetal dielectric material 135 that is formed between the metal layers 134a, 134b, and 134c, and over the FEOL region.
  • the metal layers 134a, 134b, and 134c, the electrode structure layer 136b, the intermetal dielectric material 135, and the piezoelectric material layer 136a form a BEOL region of the device 100.
  • the metal layer structures 133, 134a, 134b, and/or 134c function both as interconnect layer(s) for electronics, and can also function as part of the disclosed technology as custom designed acoustic wave guiding, channeling, or scattering structures. In some examples, is also possible to clear the underlying regions of certain pixels of metals and route them around the pixels to allow propagation of ultrasonic signals without any obstruction.
  • the sonar modules 110 are operable to receive and convert an electrical control signal to generate an acoustic energy wave or pulse carrying a communication signal to communicate with one or more other sonar modules of the array, which can receive the acoustic communication signal and transduce it to an electrical signal.
  • the array of sonar modules 110 can operate as acoustic transmitter and receiver (transceiver) modules, which can communicate with each other by proper phasing of sonar pulses sent at desired angles, frequency division modulation, or other techniques.
  • a sonar transceiver module 110 A transduces an electrical control signal that it receives to an ultrasound signal 111 that propagates through the acoustic propagation medium 120.
  • the ultrasound signal 111 can reflect off a device boundary (e.g., such as acoustical reflector layer 125) and be incident on another sonar transceiver module 110b, as shown by the signal propagation path 111a.
  • a device boundary e.g., such as acoustical reflector layer 125
  • another sonar transceiver module 110b can be incident on another sonar transceiver module 110b, as shown by the signal propagation path 111a.
  • SAW surface acoustic waves
  • the generated ultrasound signal 111 can be a continuous or pulsed ultrasound (sonic) wave.
  • the sonic waves can be generated at frequencies from the hundreds of MHz to GHz in a silicon-based propagation medium, with the corresponding wavelengths in a range from the tens to single microns, e.g., including 90 to 9 ⁇ wavelength sonic waves at 100 MHz to 1 GHz frequencies, respectively, in a silicon medium.
  • the relatively small acoustic wavelength e.g., as compared to the thickness of the silicon medium or substrate, enables the use of the propagation medium 120 to transmit the ultrasound signals from one place to another.
  • the ultrasound beam 111 can be launched into the propagation medium 120 at a wide range of solid angles and targeted to a specific receiver sonar module 110b, e.g. any of the sonar modules in the array, by adjusting the delays/phases and amplitudes of the ultrasound pulses to each of the piezoelectric transducer elements 130.
  • a specific receiver sonar module 110b e.g. any of the sonar modules in the array
  • further accuracy in targeting can be achieved by recombining the electronic signals from the receiving transducer array with appropriate delays for the desired channel.
  • This sonic programmable communications channel can be used as a reconfigurable interconnect network that a non-desired party (adversarial interests) cannot determine with any physical scheme.
  • the sonic interconnects can be software defined, and hence protectable using many methods of software encoding.
  • the exemplary acoustic in-chip communication devices can be configured to prevent the acoustic signals from propagating out of the device, or leaking. For example, because sound waves decay very fast and they cannot propagate out of the device, it can be very hard for a non-desired user (or adversary) to listen to the acoustic channels. For example, since optimal communication uses both the configuration of the transmitter and receiver arrays, the actual acoustic signals can be obfuscated with deliberate transmitter spurious signals that match nulls in the receivers but are otherwise indistinguishable from the real signals. [0072] For example, a different modality of ultrasonic chip-scale/board-level
  • communication devices can be regarded as a large acoustic resonator, to which different transducers located at different locations couple to with varying coupling coefficients that are a function of frequency of excitation.
  • a matrix approach based on linear superposition is useful to model the linear regime of this modality.
  • Linear phased arrays can be used to focus a beam and aim it in the desired direction with characteristic radiation profiles.
  • the beam can be scanned over the target field, and the returned signal is used to form the image based on acoustic reflection/transmission characteristics or time-of-flight information.
  • scanning a beam and focusing it in a single direction allows for the choice of where to communicate data.
  • the principles of beam steering and focusing, e.g., using a linear phased array is described, which is important for the understanding of the disclosed techniques of SONAR (SOund NAvigation & Ranging) operation. Examples of beam steering and focusing of the disclosed transducer arrays based devices for ultrasound imaging applications, for example, are described in: "An Integrated Circuit with Transmit
  • FIG. 2A shows a diagram of an exemplary one dimensional array of N elements spaced d apart, used to focus on a single point T.
  • the distance from the center of the array to the target is denoted as R, and the distance from element n to the target is denoted as R n .
  • Each element is represented as an isotropic emitter. As such the wave radiating from each would be represented as in Equation (1):
  • Equation (1) A is the amplitude of the signal, k is the wavenumber, r is the spherical radius from the source, ⁇ is the frequency, t is time, and ⁇ is the time phase delay of the source. If the target point T is far enough away such that R is much greater than the inter- element spacing d, than the angle ⁇ (with respect to the positive z direction) for all the elements can be approximated as the same. This means that effectively all of the paths to the target from the elements are parallel, and the difference in path length, n n , can be found from a simple trigonometric identity. ⁇ K Rn ⁇ i ⁇ cos(S)
  • the corresponding acoustic phasor at the target point T, cot is the sum of all the wave contributions wrada of the individual elements as given by Equation (4): — « -o
  • Equation (5) By selecting a value for ⁇ , the phase delay needed at each element can be calculated. From Equation (5), it can be seen that the phase is linear between elements. However, for example, due to the cyclic nature of both Equations (4) and (5), in addition to the designed main lobe of the beam, undesirable side-lobes may appear as well. Careful design of element spacing and number of elements is implemented to treat such results. In addition to this, there can be a trade-off in terms of space and power, which is taken into account.
  • FIG. 2B(a) shows a uniform response at all angles from the source.
  • a pattern as shown in FIG. 2B(b) can be produced.
  • the amplitude is 4 times as large at the 90 degree and reduced for other angles.
  • the plots shown in FIGS. 2B(c) and 2B(d) represent patterns obtained from phase delays of 20 degree and 45 degree, respectively.
  • the exemplary simulations utilized Finite Element Modeling (FEM) software, which can provide a tool to aid in the phased-array design, especially in the presence of complex boundary conditions.
  • FEM Finite Element Modeling
  • PZFlex was used to calculate time domain responses of materials to phased acoustic excitations of piezoelectric elements on a silicon substrate.
  • each element is pulsed with wavelet pulses of either in-phase or a linearly changing phase difference between elements.
  • the exemplary resulting acoustic pressure field is plotted in FIGS. 3 A and 3B for in-phase and linearly changing phase difference (e.g., steps of 20° between neighboring elements) excitations, respectively.
  • FIG. 3A shows an exemplary simulation plot of phased array acoustic radiation pressure for zero degree phase shift between elements.
  • the inset diagram in FIG. 3A shows a zoomed view of an exemplary A1N transducer array.
  • the input excitation was 1 V at 100 MHz, yielding an ultrasonic wave with a maximum pressure of 20 kPa.
  • FIG. 3B shows an exemplary simulation plot of acoustic radiation pressure for 20 degrees phase shift between elements of the phased array.
  • the maximum amplitude of the pressure wave is 20 kPa.
  • PZFlex was also used to calculate the time domain response of a single element pulsed as well as the received signals on the neighboring pixels. For example, a voltage signal on the first pixel creates an acoustic wave, which travels through the silicon substrate and reflects off of the back surface and returns to the top surface. As it travels beam spreads out and the neighboring pixel will generate a voltage in response to the acoustic pulse.
  • FIG. 3C shows a plot of the applied signal voltage, e.g., 1 Vp-p 5 cycles of 500 MHz Sine wave, for the exemplary simulation of the time domain response of an exemplary single transducer element generating an acoustic pulse wave.
  • FIG. 3D shows an exemplary simulation plot of the acoustic radiation pressure for the initial pulse leaves from the left-most pixel of the exemplary array.
  • FIG. 3E shows a plot of the receive signal at the adjacent pixel, e.g., including a delay is 160 ns, which corresponds to the speed of acoustic waves in silicon.
  • FIG. 1 Vp-p 5 cycles of 500 MHz Sine wave for the exemplary simulation of the time domain response of an exemplary single transducer element generating an acoustic pulse wave.
  • FIG. 3D shows an exemplary simulation plot of the acoustic radiation pressure for the initial pulse leaves from the left-most pixel of the exemplary array.
  • FIG. 3E shows a plot of
  • 3F shows an exemplary simulation plot of acoustic radiation pressure for the pulse after travelling to a reflecting surface (e.g., at the bottom) and reflecting back. As shown in FIG. 3F, the beam width has widened and some of the energy is picked up by the immediately adjacent pixel.
  • Exemplary implementations of the disclosed acoustic in-chip communication technology were performed.
  • exemplary acoustic in-chip communication devices were fabricated using an RF MEMS process. Starting with a silicon substrate, the RF MEMS process involved deposition of silicon dioxide of 3.5 ⁇ . Trenches were etched into the silicon dioxide and filled with tungsten, which was then planarized using chemical mechanical polishing. The tungsten can act as an etch stop for the aluminum nitride in subsequent steps. Next, a bottom electrode was deposited and patterned for the back side electrical contact. This was followed by the deposition of the piezoelectric aluminum nitride layer.
  • the piezoelectric aluminum nitride layer was etched until reaching the tungsten layer.
  • a top layer metal was deposited and patterned for the exemplary devices.
  • a four by four piezoelectric transducer element array was laid out in this process.
  • the exemplary transducer elements were configured to be 100 ⁇ x 100 ⁇ squares separated by 200 ⁇ .
  • FIG. 4A shows a cross-sectional view of a schematic illustration of one exemplary piezoelectric transducer element fabricated using the exemplary RF MEMS process.
  • FIG. 4B shows a top view of a CAD layout diagram as well as an image of the exemplary acoustic in- chip communication device fabricated using the exemplary RF MEMS process.
  • the exemplary acoustic in-chip wireless communication device includes a 4 x 4 array of the piezoelectric transducer elements each electrically coupled to an electrical bonding pad via corresponding electrical interconnections.
  • the exemplary device includes contact pads that are electrically coupled to the ground electrode of the device.
  • the exemplary fabricated silicon die with the aluminum nitride arrays was mounted to a printed circuit board (PCB) to perform tests using an HP8753ES RF network analyzer, as shown by the image in FIG. 5A.
  • the PCB houses SMA ports to interface with RF equipment.
  • the die was mounted on the PCB on top of spacers. For example, this allows the bottom of the silicon to be exposed to air creating a large contrast in acoustic impedances resulting in a strong reflection at the bottom surface.
  • FIG. 5B shows a cross-sectional view of a schematic illustration of this exemplary setup.
  • FIG. 6A shows a data plot showing exemplary results of a transmission scattering parameter, S 21 , for the two exemplary transducer elements in the array.
  • S 21 shows that from 1.06 GHz to 1.67 GHz there is a loss of only 5 dB.
  • This exemplary implementation demonstrates exemplary bandwidth of communication between these two elements.
  • exemplary ultrasonic phased arrays in-chip communication devices can be integrated on chip to enable pulses to be transmitted from any location to another by beam steering for reconfigurable communication links.
  • Exemplary results showed acoustic coupling between the transducer elements in the array, e.g., by measuring the reflection scattering parameters of the two exemplary microfabricated, 100 ⁇ x 100 ⁇ A1N transducer elements, which are spaced 400 ⁇ away within the same 4 x 4 array.
  • the disclosed array of CMOS-integrated piezoelectric transducer (sonar) modules can be integrated into a 3D chip-stack to enable pulses to be transmitted from any location to another by beam steering.
  • An array of sonar elements can transmit sound pulses through stacks with mechanical connections.
  • FIG. 7A shows a schematic illustration of an exemplary 3D chip-scale wireless communications IC device 700 including a plurality of layers 701 of arrays of the acoustic transceiver (sonar) modules 110 capable of transmitting and receiving directional acoustic communications signals 702 in a single layer and between multiple layers.
  • Each of the layers 701 are structured to include dielectric sub-layer 720 to provide an acoustic propagation medium for the acoustic communication signal 702 (e.g., ultrasound wave) to propagate within the device 700, e.g., including between sonar modules 110 of the arrays.
  • the device 700 can include an underfill region 715 between dies and around bumps to provide continuous propagation medium transitions between the layers 701.
  • each or any of the sonar modules 110 of the device 700 can be structured to include a sub-array of individual piezoelectric transducer elements 130 (shown in FIG. ID).
  • the sub-array of individual piezoelectric transducer elements 130 can be communicatively linked to underlying electronic control circuits including driving/read circuits and logic circuits.
  • the device 700 can include a plurality of through-layer vias
  • FIG. 7B shows an inset schematic from FIG. 7A showing an exemplary configuration of the acoustic propagation medium sub-layer 720 including artificial structures as acoustic metamaterials to guide the sonic signals, e.g., effectuating the directional acoustic communication signal 702.
  • the acoustic metamaterial can function as an acoustic waveguide to promote more efficient transmission of acoustic waves from one point to another. It can also include frequency filtering functionality to transmit only ultrasonic waves of certain frequency (wavelength) or mode (shear or longitudinal waves) while attenuating or obstructing the passage of undesired frequencies or modes.
  • the disclosed technology includes fabrication methods to produce 2D and 3D in-chip wireless communication signaling devices.
  • a method to fabricate exemplary chip-scale wireless communications IC devices can include A1N deposition techniques to form the piezoelectric transducer arrays.
  • sputter deposition of A1N is implemented at low temperatures (range), e.g., to be compatible with CMOS, but may utilize optimum metals like Tantalum for best films. The deposition of A1N at low temperatures also enables the placement of A1N embedded in the metallization stack.
  • PZT thin films can be deposited though the sol-gel process, and require an anneal step which is typically at 700-800 °C. This high temperature implies that the process flow for the PZT is to be implemented after CMOS fabrication.
  • PZT films can be transferred onto CMOS-based chips using oxide-oxide bonding, oxide- metal bonding, or metal-metal bonding.
  • FIG. 8 shows a diagram of an exemplary PZT transfer process to a CMOS based IC chip, in which a PZT stack is bonded to BEOL oxide-oxide oxide bonding that can be done at low temperatures with follow on processing to enable interconnects to top conductors of the exemplary PZT stack.
  • the exemplary A1N stack with TEOS oxide layers can form a 1-D waveguide to launch pressure (P) waves, also referred to as longitudinal waves, with the motion transduced into the thickness of the wafer.
  • P pressure
  • the exemplary devices can be designed and fabricated to effectuate the longitudinal wave impedance of the silicon wafer and possible reflections and transmissions through metal layers, e.g., which can be intentionally placed in the IC design to tune the impedance of the transducer.
  • FIG. 9 shows a diagram of an exemplary BEOL stack including metal reflectors to optimize wave coupling to the semiconductor substrate.
  • longitudinal waves can be guided to prevent lateral diffraction based on the metal reflector structures positioned in the BEOL stack, e.g., such that the impedance of an exemplary copper-laden segment can have higher impedance than a TEOS-only segment.
  • the transducer electrical impedance can be calculated using an exemplary ID model, e.g., including resonances and anti-resonances, and the absolute values of the impedances can lead to calculations of Q (quality factor) and K 2 (electromechanical coupling) of the transducers.
  • Q quality factor
  • K 2 electromechanical coupling
  • the design and fabrication of the exemplary wireless in-chip communication devices can be implemented to mitigate the effects of shear and SAW waves.
  • the transducers can couple energy into shear and surface acoustic waves.
  • 67% of the energy is emitted as a surface wave if a surface transducer is used.
  • the exemplary techniques can determine the transducers design spacing by spacing the array elements in the stop-band of SAW waves. Longitudinal and shear waves can thus be used for the communication links, e.g., to minimize the coupling of energy into shear and SAW modes, as the wave motion corresponding to these modes will travel at different speeds and different directions, leading to unwanted cross-talk.
  • FIG. 10 shows a process diagram of an exemplary fabrication technique to produce wireless in-chip communication devices of the disclosed technology including piezoelectric transducer elements formed on a cantilever beam or any other structure to act as a resonator.
  • this resonator characteristic can provide frequency selectivity during both transmission and detection as the ultrasonic transducer can generate (launch) or receive acoustic waves from its anchor, allowing resonant sensing and actuation.
  • the exemplary fabrication technique can include a process 1010 to form the initial layers of materials of the piezoelectric resonator transducer.
  • AIN is formed over a silicon oxide layer over a silicon substrate, in which a Al or Ti/TiN/Al layer is formed between the silicon oxide and AIN layers, and in which tungsten is formed in a cavity of the silicon substrate and/or silicon oxide layers to form an etch stop.
  • the fabrication technique can include a process 1020 to etch into the layers of the materials and deposit an Al layer.
  • a well is etched into the AIN layer above the W etch stop and an Al layer is subsequently patterned over the portions of the AIN layer including the etched well above the W etch stop.
  • the fabrication technique can include a process 1030 to form the cantilever structure.
  • the process 1030 includes etching away a sacrificial layer to have cavities or unconstrained boundaries around the acoustic transducer element.
  • one advantage of resonant sensing is that it can perform better to detect low amplitude acoustic signals on the receiver side.
  • a portion of the AIN, silicon oxide, and silicon substrate are etched to isolate a cantilever structure underneath a portion of the silicon oxide layer and Al or Ti/TiN/Al layer below the AIN layer covered by the Al layer.
  • the materials and process steps shown in FIG. 10 are examples, and other material and/or structural designs can be implemented to fabricate the exemplary piezoelectric resonator transducer structures for the disclosed wireless in-chip communication devices.
  • FIG. 10 includes a diagram 1040 showing a cross-sectional view of an exemplary piezoelectric resonator transducer including an undoped polysilicon layer within the silicon oxide layer.
  • the disclosed technology includes devices and techniques for direct CMOS integration with the disclosed ultrasonic transducers, e.g., including the piezoelectric transducer elements configured in a layer adjacent to a layer of CMOS transmit and receive electronics on the same wafer.
  • CMOS complementary metal-oxide-semiconductor
  • such integration reduces load capacitance and inductance by minimizing interconnect and routing area and by eliminating wire bonds.
  • the reduction of the load capacitance presented by the interconnects between the electronics and the piezoelectric transducer elements can lower transmit amplitudes such that higher receive amplitudes can be obtained.
  • a reduction in area allows more transducers and electronics to be integrated in the IC device.
  • parasitic capacitances and inductances from the interconnects and routing between control circuits and transducer elements can be kept to minimum in the disclosed IC designs, such that their effect on the frequency response of the transmit and receive circuitry is negligible.
  • the transmit and receive electronics corresponding to a sonar pixel can be configured directly beneath the transducer element such that the problem of signal crosstalk between wiring carrying signals from different pixels is minimized.
  • the disclosed technology can include a variety of circuits for controlling the phase or delay of pixel excitation waveforms.
  • These exemplary delay lines can include one or more inverter delay elements, such as those shown in FIG. 11 A, in series.
  • inverter delay elements are essentially inverters whose propagation delay is adjusted by varying the supply current, the load capacitance or the supply voltage.
  • the amount of time that each delay line can delay the input signal can be adjusted by varying one or more control voltages and by the number of delay elements that are in cascade.
  • tapped delay lines where the output after each delay element is accessible may be used for finer delay resolution.
  • the delay control voltages or current sources can be generated by storing digital values on-chip in digital memory such as SRAM and using a digital-to-analog (D/A) converter to obtain the analog voltages or currents.
  • D/A converters are relatively large components that can affect the size of the electronic area consumed by the pixel.
  • An example of one of the smallest D/A converter topologies includes current splitting or current steering D/A converters, which includes a current mirror comprising N+l transistors of unit size W/L and N-l transistors of 2W/L.
  • FIG. 11B shows a diagram of an exemplary 4-bit current splitting D/A converter.
  • FIG. l lC shows a diagram of an exemplary delay line circuit followed by inverter chain buffer. For example, while minimum size inverters can be used for fine delay resolution and to minimize circuit area in each pixel, the output inverter used to drive the sonar should be large enough to drive the capacitive load that the piezoelectric elements present.
  • an inverter chain with progressively increasing inverter sizing can be used to minimize the loading effect at the buffer input, as shown in FIG. 11C.
  • phase shifting a sinusoidal waveform can be implemented to generate the necessary delays.
  • the phase shifting is implemented through a quadrature mixing scheme, e.g., including two analog weights A and B that are multiplied with waveforms sin(tot) and cos(i t), respectively, and then added for an output waveform of A - R cosCiiih .
  • this is equivalent to an output of sin ⁇ is*i 4- ), where C is A 2 -f B ⁇ and ⁇ p is tan -1 ⁇ / ⁇ ).
  • Constant amplitude phase shifting can be obtained by selecting the analog weights A and B to be C cos ip and sin -p, respectively, where C is the desired output amplitude and ⁇ is the desired output phase.
  • FIG. 11D shows a diagram of the exemplary sinusoidal phase shifting that can be implemented by a typical quadrature modulation circuit, and analog voltages that are applied to the mixer inputs.
  • the mixers can be implemented with generic Gilbert cell mixers with output nodes connected such that the summing occurs through current addition.
  • the sinusoidal voltages stn( ⁇ s>t) and cos «it ⁇ can be generated by applying a signal with frequency 2 ⁇ into a frequency divider circuit, which will output two signals at frequency ⁇ that are 90 degrees in phase apart.
  • each D/A converter can be replaced by a cell comprising of a single capacitor CI and a switch SI used to selectively write to the capacitor.
  • FIG. 1 IE shows a diagram of an exemplary unit cell of an analog memory.
  • metal-insulator-metal (MIM) capacitors may occupy layers in the metal stack above the transistor layers and below the sonar transducer layer.
  • the use of such capacitors can effectively reduce the area required for pixel electronics, despite the relatively large size.
  • the capacitor stores the analog voltages required for the sonar circuitry, e.g., either the control voltages for delay lines or the analog weights for phase control.
  • a single or a few global D/A converters can be used to generate these analog voltages for all of the pixels. For example, to set the analog weight on a pixel, the DAC is first set to the desired value and then the access switch for the appropriate capacitor is turned on.
  • the switch is turned off and the next capacitor can then be charged. Due to leakage effects, the capacitor voltage must be periodically refreshed. While a single transistor or a transmission gate can be used for the switch, various low leakage switch topologies can also be used. [0107] Several modifications can be made to this exemplary analog memory architecture to increase leakage tolerance. For example, by switching to a differential input mixer topology and using two of the capacitor based analog memory cells instead of a single one, the voltage difference of the two cells is used as the input and thus the effect of leakage can be greatly reduced. Alternatively, active analog memories which employ some form of leak compensation can be used. For even longer term storage, instead of using a capacitor, nonvolatile storage elements such as floating gate transistors can be used instead.
  • FIG. 11F shows a diagram of an exemplary analog memory for multiple phase generation, which can be integrated into the electronics for each sonar pixel.
  • the transmit path of an ultrasonic imaging system typically includes the transmit beamforming electronics followed by a high voltage pulser.
  • Multilevel pulsers can be used to send signals of different output voltages, which can be used in beamforming. As sufficient receive amplitudes can be obtained while driving the sonar transducer at amplitudes below the nominal supply voltages for transistors on advanced process nodes, a high voltage driver is not necessary.
  • shift registers or timer/counter circuits may be used to implement the transmit delays.
  • a comparator can be used at the counter outputs to generate a trigger signal once the counter reaches a certain value.
  • This exemplary trigger signal then activates a pulser circuit which outputs a single or multiple pulses at the desired voltage, pulse width, and frequency.
  • delay resolution can be improved by employing clock division with delay locked loop based circuits.
  • Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.
  • Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus.
  • the computer readable medium can be a machine-readable storage device, a machine -readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them.
  • data processing apparatus encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers.
  • the apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
  • a computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
  • a computer program does not necessarily correspond to a file in a file system.
  • a program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code).
  • a computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
  • processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.
  • a processor will receive instructions and data from a read only memory or a random access memory or both.
  • the essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data.
  • a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks.
  • mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks.
  • a computer need not have such devices.
  • Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices.
  • semiconductor memory devices e.g., EPROM, EEPROM, and flash memory devices.
  • the processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

Abstract

Methods, devices and systems are disclosed for implementing ultrasonic communications in an integrated circuit. In one aspect, the disclosed technology integrates piezoelectric and electrostatic actuator arrays into IC chips to form sonar arrays that transmit from one location in chip to another, which can allows for tunable sonic communication links between any two points. For example, the sonar elements can also be used to transmit signals from one chip to another through a common substrate, while making use of the frequency- selective nature of acoustic transducers and waveguides to communicate to multiple receivers over different frequency bands at the same time, e.g., via frequency division multiplexing.

Description

INTEGRATED CIRCUITS HAVING INTEGRATED ACOUSTIC
COMMUNICATION LINKS
PRIORITY CLAIM
[0001] This patent document claims the priority and benefit of U.S. provisional application No. 61/672,214 entitled "3D SEMICONDUCTOR CHIPS HAVING
INTEGRATED ULTRASONIC COMMUNICATION LINKS AND NODES," filed on July 16, 2012, the entire disclosure of which is incorporated herein by reference for all purposes.
STATEMENT OF GOVERNMENT SUPPORT
[0002] This invention was made with government support under Grant No. N66001-12-C- 2009, awarded by the Intelligence Advanced Research Projects Activity (IARPA) Trusted Integrated Chips (TIC) program. The government has certain rights in this invention.
TECHNICAL FIELD
[0003] This patent document relates to semiconductor technologies.
BACKGROUND
[0004] Semiconductor fabrication and nanotechnology provide techniques or processes for fabricating structures, devices, and systems with features at a micro or nano scale, e.g., structures in a range of one to hundreds of nanometers in some applications. Integrated circuits and microprocessors are examples of such structures, devices and systems.
SUMMARY
[0005] Techniques, systems, and devices are disclosed for implementing multidimensional semiconductor integrated circuits having integrated ultrasonic in-chip communication links and nodes.
[0006] In one aspect, a semiconductor integrated circuit device having wireless ultrasonic communication links includes a semiconductor substrate, layers formed over the
semiconductor substrate and patterned to form circuit elements including transistors, and an array of ultrasound transducers formed in the layers over the semiconductor substrate, each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements. Each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
[0007] Implementations of the device can optionally include one or more of the following features. For example, the semiconductor substrate can be formed of a substrate material that includes silicon, the ultrasound transducer elements within each ultrasound transducer can include a piezoelectric material layer that includes aluminum nitride (A1N) amongst other piezoelectric materials, and the layers formed over the semiconductor substrate and patterned to form circuit elements can be complementary metal-oxide- semiconductor (CMOS) layers. Also, for example, the ultrasound transducer elements within each ultrasound transducer includes a piezoelectric material layer that can include lead zirconate titanate (PZT). For example, the ultrasound transducers can be formed in one layer of the layers over the semiconductor substrate or on the side opposing the circuitry. In some implementations, for example, the device can further include a reflector layer formed over the semiconductor substrate to provide a boundary to reflect an ultrasound signal from one ultrasound transducer to another ultrasound transducer. For example, the ultrasound transducers can be formed in two or more different layers over the semiconductor substrate as a three-dimensional (3D) array. For example, the layers formed over the semiconductor substrate can include (1) front- end-of-line (FEOL) layers that are formed and patterned to include the circuit elements including transistors, and (2) back-end-of-line (BEOL) layers over the FEOL layers to include wired interconnects between the ultrasound transducers and respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers. In some implementations, for example, the device can further include transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer, in which each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements. For example, the layers formed over the
semiconductor substrate can include (1) front-end-of-line (FEOL) layers that are formed and patterned to include the circuit elements including transistors and the transducer driver circuits, and (2) back-end-of-line (BEOL) layers over the FEOL layers to include wired interconnects between the ultrasound transducers and respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers. For example, each transducer driver circuit can include a phase generation circuit to control phase delays of different ultrasound transducer elements within each ultrasound transducer. In some implementations, for example, the device can further include physical acoustic structures in the layers formed over the semiconductor substrate to facilitate guiding of ultrasound signals from ultrasound transducers. For example, the physical acoustic structures include metal reflectors for reflecting sound, e.g., in which one or more physical acoustic transducers can use surface acoustic waves to transmit information to one or more other physical acoustic transducers. For example, the circuit elements formed in the layers can include an field-programmable gate array (FPGA) having FPGA logic elements that are interconnected via ultrasonic communication links between the respective ultrasound transducers, wherein the FPGA is programmable by adjusting the ultrasonic communication links between the respective ultrasound transducers. In some implementations, for example, the device can further include transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer, in which each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements, and in which the transducer driver circuits are configured to control or adjust ultrasonic communication links between the respective ultrasound transducers to effectuate various interconnects between the circuit elements for different circuit functions, thus providing a programmable circuit device. In some implementations, for example, the device can further include a monitor circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a local condition that is reflected in a received ultrasound signal at the ultrasound transceiver, rendering the array of ultrasound transducers to function as an array of circuit sensors for monitoring the device operating conditions. For example, the monitor circuit can be configured to monitor a temperature at different locations within the device. For example, the monitor circuit can be configured to monitor conditions of physical contacts at different locations within the device. In some implementations, for example, the device can further include a circuit security verification circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a physical signature that is reflected in a received ultrasound signal at the ultrasound transceiver to provide an indication of whether a circuit layout of the device matches a predetermined circuit layout.
[0008] The subject matter described in this patent document can be implemented in specific ways that provide one or more of the following features. For example, the disclosed technology integrates piezoelectric and electrostatic actuator arrays into 3D IC chips to form sonar arrays that transmit from one location in chip to another. In 3D integrated chips, this allows for tunable sonic communication links between any two points. For example, the sonars can also be used to transmit signals from one chip to another through the common substrate, while making use of the frequency-selective nature of acoustic transducers and waveguides to communicate to multiple receivers over different frequency bands at the same time, e.g., via frequency division multiplexing. Frequency division multiplexing can be implemented to carry different channels at different acoustic frequencies. For example, the integrated sonars can also be used to interrogate defects in chip interconnects over time to measure chip parameters and interfaces to determine reliability.
[0009] The disclosed technology can provide ultrasonic communication links in integrated circuit devices that enables programmable interconnections between circuit elements of the devices, provides local sensing of structures and operating conditions of the devices for monitoring health of the device and for controlling distribution of processing within the integrated circuit device to prolong the device lifetime, and enhances the physical security of the integrated circuit device, e.g., by using ultrasonic transducers as imaging sensors to read physical patterns and determine acoustic signatures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1A shows an architectural diagram of a conventional integrated circuit chip design and an architectural diagram of an integrated circuit chip design of the disclosed technology.
[0011] FIG. IB shows a diagram of the disclosed acoustic in-chip communication signaling IC chip design. [0012] FIG. 1C shows a schematic illustration of an exemplary chip-scale wireless communications IC device.
[0013] FIG. ID shows an inset schematic from FIG. IC showing an exemplary CMOS- integrated piezoelectric transducer array of an exemplary sonar module.
[0014] FIG. IE shows an inset schematic from FIG. ID showing an exemplary CMOS- integrated piezoelectric transducer element.
[0015] FIG. IF shows an inset schematic from FIG. ID showing a cross-sectional view of the exemplary CMOS-integrated piezoelectric transducer element.
[0016] FIG. 2A shows a diagram of an exemplary one dimensional array of transducer elements spaced apart and used to focus on a single point. [0017] FIG. 2B shows data plots of exemplary acoustic responses from an acoustic radiator source.
[0018] FIG. 3A shows an exemplary simulation plot of phased array acoustic radiation pressure for zero degree phase shift between elements.
[0019] FIG. 3B shows an exemplary simulation plot of acoustic radiation pressure for 20 degrees phase shift between elements of a phased array. [0020] FIG. 3C shows a plot of the applied signal voltage for an exemplary simulation of the time domain response of an exemplary transducer element generating an acoustic pulse.
[0021] FIG. 3D shows an exemplary simulation plot of the acoustic radiation pressure for the initial pulse. [0022] FIG. 3E shows a data plot of the signal received by an exemplary transducer element in the array.
[0023] FIG. 3F shows an exemplary simulation plot of acoustic radiation pressure for the traveling and reflected pulse.
[0024] FIG. 4A shows a cross-sectional view of a schematic illustration of one exemplary piezoelectric transducer element produced using an exemplary fabrication process.
[0025] FIG. 4B shows a top view of a CAD layout diagram and an image of an exemplary acoustic in-chip communication device produced using an exemplary fabrication process.
[0026] FIGS. 5A and 5B show an image and schematic illustration depicting an exemplary acoustic in-chip communication device in an exemplary implementation setup configuration. [0027] FIG. 6A shows a data plot showing exemplary results of reflection scattering parameters for the two transducer elements in an exemplary sonar array in-chip
communication device.
[0028] FIG. 6B shows a data plot showing exemplary results of a transmission scattering parameter for the two exemplary transducer elements in the array. [0029] FIG. 7A shows a schematic illustration of an exemplary 3D chip-scale wireless communications IC device.
[0030] FIG. 7B shows an inset schematic from FIG. 7A showing an exemplary configuration of the acoustic propagation medium sub-layer.
[0031] FIG. 8 shows a diagram of an exemplary PZT transfer process to an exemplary CMOS based IC chip.
[0032] FIG. 9 shows a diagram of an exemplary BEOL stack including metal reflectors to optimize wave coupling to the exemplary semiconductor substrate. [0033] FIG. 10 shows a process diagram of an exemplary fabrication technique to produce wireless in-chip communication devices of the disclosed technology.
[0034] FIG. 11A shows diagrams of exemplary delay lines including one or more inverter delay elements. [0035] FIG. 11B shows a diagram of an exemplary 4-bit current splitting D/A converter.
[0036] FIG. llC shows a diagram of an exemplary delay line circuit followed by inverter chain buffer.
[0037] FIG. 11D shows a diagram of an exemplary quadrature mixing circuit for amplitude and phase shift control with two analog weights. [0038] FIG. HE shows a diagram of an exemplary unit cell of an analog memory.
[0039] FIG. 11F shows a diagram of an exemplary analog memory for multiple phase generation.
DETAILED DESCRIPTION
[0040] Silicon-based and other semiconductor integrated circuit (IC) chips typically use conductive wires for in-chip communication links, which create several limitations in IC chip designs including spot heating, thermal cycling degradation of components, signal interference, among others. Some chip-scale communications approaches to mitigating such problems associated with conductive wires include optical and/or wireless in-chip communications which have been explored in several physical domains, but complement and/or add to the traditional metal interconnects.
[0041] In one example, photonic interconnects have been proposed as a way to transmit digital and analog information on optical waveguides integrated into a complementary metal- oxide-semiconductor (CMOS) stack. For example, optical waveguide interconnects can provide very high bandwidth and low power consumption information transmission within chips. However, due to the internal losses of optical signals in CMOS compatible optical waveguides, and the resulting high power for optical links, much work is still needed for use of optical interconnects. Also, one of the drawbacks of the photonic links is that the links are defined by lithography in the front end of line (FEOL) or back end of line (BEOL) IC fabrication processes, which can enable adversarial interests in the IC design to physically detect function, e.g., by detecting scattered light, or tracing the optical paths.
[0042] In another example, radio-on-chip networks have been proposed for ad-hoc wireless networks on chip. For example, such radio-on-chip networks can transmit over the chip using RF radio. Due to the large signal wavelengths corresponding to common RF frequencies, such RF transmitters are point emitters operating in the near field configurations that tend to use coded signals to reduce EM interference and thus require significant power consumption.
[0043] Additionally, there has been some effort in protecting IC designs that are mapped to field programmable gate arrays (FPGAs). For example, the key to determining the functionality of an FPGA is determining its bit-stream patterns with various parts of FPGAs. Bit-streams can be encrypted in high-end FPGAs to protect the contents of the configuration memory. The encryption key (e.g., a key based on the advanced encryption standard (AES)) is stored in volatile memory, and powered by a battery in an effort to defeat unsophisticated tampering. Obfuscation is also a commonly used software technique, and can also be applied to the hardware description language used to create the design mapped to the FPGA. These techniques can be combined with the notion of a physically unclonable function (e.g., logic whose behavior is a function of chip-specific process variations) to protect a design.
However, these approaches do not protect against EM-based attacks or differential power analysis. In addition, an adversary may have access to the FEOL processing or the entire IC processing during the fabrication and production at a semiconductor foundry that is operated by another party.
[0044] In the past, microelectronic devices were manufactured by companies that both designed and produced the devices. At that time, manufacturing involved fine-tuning device and manufacturing process parameters, which often warranted a need for redesign involving both the research and development (R&D of the microcircuit design and the manufacturing processes. Currently, manufacturing processes are highly advanced and standardized such that multiple microelectronic device designs can be fabricated by a single, large-scale manufacturing entity. For example, separation of manufacturing and design has created a new model for microelectronic device fabrication: the foundry model. The foundry model refers to the separation of a semiconductor fabrication plant operation (foundry) from an integrated circuit design operation, e.g., enabling a "fabless" semiconductor company to operate without any semiconductor manufacturing capability but rather contract production from a separate manufacturer entity (merchant foundry). While the foundry model is economically efficient for rapid development of integrated circuit devices, it is subject to device security concerns including theft of device designs and unauthorized alterations or modifications during production by the merchant foundry or other adversarial actors.
[0045] Moreover, as the need for computational power increases, high density integration of transistors and other circuit elements, such as 2D integration and 3D integration of multiple processor layers, are becoming increasingly necessary for many IC applications to increase the IC processing power. One of the problems in highly integrated IC chips, e.g., vertically stacked 3D ICs, is the difficulty to provide complex and a large number of interconnects between different circuit elements. In a 3D stacked chip, for example, the number of communication channels between wafers tends to be limited because of the relatively large size of through- wafer vias (TWV) to ensure bonding reliability.
[0046] The technology disclosed in this patent document uses ultrasound transducers as communication transceivers for providing wireless ultrasonic communication interconnects between different circuit elements without hardwiring between circuit elements and as built- in circuit sensors for sensing circuit conditions. Such ultrasonic communication
interconnects can significantly reduce the metal interconnects between circuit elements. The disclosed technology can be used to provide programmable or reconfigurable interconnects to enable fixed circuit elements to form various functionally different circuit devices and to conceal the final circuit functions and designs from an unauthorized party and from the physical fabrication or manufacturing of the circuits. The disclosed technology can also be implemented to address the above aforementioned technical problems and limitations.
[0047] Techniques, systems, and devices are described to provide 2D and 3D integrated circuit chip designs having integrated ultrasonic or acoustic in-chip communication links and nodes.
[0048] The disclosed technology integrates ultrasound actuator arrays into 2D or 3D IC chips to form sonar arrays that transmit a directional sonic pulse from one functional unit or module in the chip to another, providing tunable sonic intra-chip communication links between any two points by adjusting the delays/phases and/or amplitudes of the sonic communication signals on transmit. In some implementations, for example, the ultrasound actuators can be based on piezoelectric materials or elements. In addition, the ultrasound actuators can be configured using electrostatic transducers, e.g., including
capacitive/electrostatic materials or elements (e.g., including capacitive micro-machined ultrasonic transducers (CMUT)), which can be implemented, for example, in addition to or instead of the piezoelectric-based actuators (e.g., the piezoelectric A1N transducer elements). Examples of CMUT transducer elements are described in Wygant, I., "A comparison of CMUTs and piezoelectric transducer elements for 2D medical imaging based on conventional simulation models", Ultrasonics Symposium (IUS), 2011 IEEE International, Vol. 100, No. 18-21, Oct. 2011, which is incorporated by reference as part of this patent document. More generally, the disclosed technology can implement the ultrasound in-chip wireless communication links using any of piezoelectric, electrostatic, magnetic, thermal,
electrostrictive actuation/sensing elements acoustic communication signaling. In some implementations, such sonar modules can be used to transmit signals from one chip to another chip through a common substrate, while making use of the frequency- selective nature of acoustic transducers and waveguides to communicate to multiple receivers over different frequency bands at the same time, e.g., via frequency division multiplexing. Frequency division multiplexing can be implemented to carry different channels at different acoustic frequencies. For example, the integrated sonars can also be used to interrogate defects in chip interconnects over time to measure chip reliability. [0049] FIG. 1A shows an architectural diagram of a conventional integrated circuit chip design 10 based on the complementary metal-oxide-semiconductor (CMOS) technology and an architectural diagram of an example of an integrated circuit chip design 20 for
implementing the disclosed technology. The conventional CMOS IC chip design 10 includes a bulk semiconductor portion, e.g., bulk silicon die or substrate, upon which an front-end-of- line (FEOL) portion is structured to include individual and discrete circuit elements, e.g., transistors, capacitors, resistors, etc., patterned in layers within the FEOL portion formed over the semiconductor substrate. In some configurations, the FEOL portion of the conventional IC chip design 10 can include CMOS circuit elements for one or more digital logic circuits. The conventional IC chip design 10 includes a back-end-of-line (BEOL) portion to provide the hardwiring connects within each circuit element and hardwiring interconnects between the discrete circuit elements in the FEOL portion, such as metal contacts or lines. For example, the BEOL includes conductive contacts such as metal lines, metal contacts or metal vias, insulating layers or materials (e.g., dielectrics), and bonding sites for chip-to-package connections. The interconnects in the BEOL in the IC chip design 10 link the discrete circuit elements in FEOL to form functional circuit blocks.
[0050] The architectural diagram of the IC chip design 20 of the disclosed technology shown in FIG. 1A is based on a different interconnect configuration using ultrasound communication links. The IC chip design 20 includes a bulk semiconductor portion, a front- end-of-line (FEOL) portion that includes discrete circuit elements, a back-end-of-line (BEOL) portion and ultrasound transducer modules (e.g., piezoelectric transducer modules). Different from the IC chip design 10 where the interconnects in the BEOL link the discrete circuit elements in the FEOL portion to form functional circuit blocks, the IC chip design 20 uses the ultrasound transducer modules as communication nodes to provide a significant portion of or all of inter-element communication interconnects between different circuit elements in the FEOL portion by using wireless ultrasound signaling as interconnects. The BEOL portion of the IC chip design 20 provides conductive connections between the ultrasound transducer modules and circuit elements in the FEOL portion and may also include, in some implementations, certain interconnects for the circuit elements in the FEOL portion. When the ultrasound transducer modules are not activated or functional, the circuit elements in the FEOL portion are largely discrete or isolated circuit elements or circuit element blocks or clusters of two or more interconnected circuit elements. When the ultrasound transducer modules are activated to provide desired interconnects between the circuit elements in the FEOL portion, the circuit elements in the FEOL portion form a functional IC device under the IC chip design 20 and become functional. Therefore, the ultrasound transducer modules provide ultrasonic or acoustic communication signaling capabilities of the discrete circuit elements (e.g., CMOS digital logic circuits) to
communicate wirelessly between such elements, thereby reducing some or all of the hardwired interconnections in a conventional IC chip design. In some examples, the IC chip design 20 includes control circuits including driver, read, and logic circuits as part of the FEOL portion that electrically communicate with the piezoelectric transducer modules via electrical connections of the BEOL portion. The BEOL portion can also include metal reflectors or other components that aid in the acoustic signal propagation. In FIG. 1A, the IC chip design 20 is shown to have a particular structure where the FEOL portion, the BEOL portion, and the layers for the ultrasound transducer modules are formed in the shown sequential order over the substrate. This configuration of the IC chip design 20 is an example only and other configurations or structural sequences may be implemented depending the specific needs of IC designs and circuit applications.
[0051] An ultrasound signal tends to have a footprint and spatial extent determined by the acoustic frequency of the signal and the physical conditions of the signal path that may cause diffraction, scattering and spreading of the ultrasound signal. The smallest beam spot size is dictated by the diffraction limit on the order of one half of the ultrasound signal wavelength. Accordingly, a metal interconnect may be configured to have a smaller footprint than that of an ultrasound signal interconnect. In implementing the wireless ultrasound signaling as interconnects for different circuit elements in the IC chip design 20 in FIG. 1A, it may be advantageous in some applications to use ultrasound signaling for all interconnects of the different circuit elements and, in other applications, it may be more beneficial to use ultrasound signaling for part of the interconnects and use metal lines or contacts for the remaining interconnects. Such metal lines or contacts for interconnects between different circuit elements are can be in the BEOL portion. [0052] FIG. IB shows a functional diagram 30 of the IC chip design 20 of the disclosed technology illustrating wireless intra-communication in a semiconductor medium between circuit modules of the IC chip. The diagram 30 shows an exemplary embodiment of the IC chip design 20 in which an array of 1, 2, ... N piezoelectric transducer modules are operable to transmit and receive directional acoustic signals carrying information to communicate between the transducer modules. For example, the wavelength of the sonic signals depends on the frequency and propagation speed of the signal, and the propagation speed depends on the medium through which the signal propagates. The speed of sonic transmission in a semiconductor medium (e.g., ~9xl03 m/s in a dielectric medium such as silicon) is five orders of magnitude lower that the speed of electromagnetic transmission (e.g., 2.997xl08 m/s). Thus, sonic signals can be transmitted at wavelengths in the microns for desired frequencies in the GHz range, e.g., protecting the acoustic communication signal from RF and other noise within the IC circuit. The array of piezoelectric transducer modules are communicatively coupled to individual control circuit elements or blocks (e.g., of two or more circuit elements), e.g., which can be formed in the FEOL portion over the
semiconductor substrate. The individual control circuits can include a driver circuit to generate an electric signal to the corresponding transducer module that determines the magnitude, frequency, and/or phase of the acoustic communication signal. The individual control circuits can include a read circuit to receive a transduced electric signal from the corresponding transducer module that receives the transmitted acoustic communication signal. For example, the driver circuits and/or read circuits can include analog and digital circuit components (e.g., inverter delay elements, analog-to-digital converters (ADC) and digital-to-analog converters (DAC), amplifiers, etc.). The individual control circuits can include a logic circuit, e.g., of digital and/or analogic logic circuit components, to provide and receive electric signals as digital waveform carrying the information to and from the driver and read circuits, respectively, which can be processed by other circuits of the IC chip. For example, the digital waveform can be a phase-coded and/or frequency-coded waveform or waveforms included in a composite waveform. In some examples, the logic circuits can be configured of one or more CMOS layers.
[0053] Each of the ultrasound transducer modules of FIGS. 1A and IC is configured to generate a steerable acoustic ultrasound signal to target one or more desired ultrasound transducer modules to provide desired ultrasound interconnects for the circuit elements associated with the transmitting and receiving ultrasound transducer modules. As illustrated in FIG. IC and described in greater detail below, each ultrasound transducer module includes multiple ultrasound transducer elements, e.g., in a 2-D array, and operates to control the relative amplitude and phase values of ultrasound signals generated by multiple ultrasound transducer elements so that the ultrasound signals are added up to form a final composite ultrasound signal that is directed to a particular location or region in the circuit where one or more targeted receiving ultrasound transducer modules are located. Each ultrasound transducer module can be operated as a transmitter and a receiver and thus is a ultrasound transducer transceiver element. The driver/read and logic circuits for the ultrasound transducer modules are shown to be part of the FEOL portion in FIG. IB, but may also be in the BEOL portion or other layers. The use of multiple ultrasound transducer elements for an ultrasound transducer module as a transceiver device for transmitting steerable output ultrasound signals and for receiving/detecting ultrasound signals can be implemented in various configurations, including some examples described in "Two-Port Electromechanical Model for Bulk-Piezoelectric Excitation of Surface Micromachines Beam Resonators" by Ardanuc and Lai in Journal of Microelectromechanical Systems, pp. 626-640 in Vol. 18, No. 3, June 2009, and "Beam Steering with Pulsed Two-Dimensional Transducer Arrays" by Turnbull and Foster in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, pp. 320-333, Vol. 28, No. 4, July 1991, which are part of the U.S. provisional application No. 61/672,214 and are incorporated by reference as part of this patent document.
[0054] The disclosed acoustic in-chip communication technology can be implemented to provide many advantages. For example, the disclosed acoustic in-chip communication can use linear and two-dimensional arrays of piezoelectric transducers to generate directional ultrasonic pulses in three dimensions for CMOS information processing and trusted integrated circuit (TIC) operation. For example, exemplary phased array sonic transducers can be operated at GHz frequencies alongside and/or integrated with other analog or digital chip logic on a single IC chip. For example, the disclosed technology can be implemented in a variety of applications including medical (ultrasound) imaging, non-destructive evaluation (NDE) of IC chip components, and sonar communications. Historically, for example, these arrays have operated in the frequency range of l-30MHz for medical imaging, 100 kHz to 10 MHz for NDE, and 1-100 kHz for sonar communications. By operating at high frequencies of 1-10 GHz, the wavelength in silicon can be in an exemplary range of 9 to 0.9 μιη. Since the elements of a sonar array are spaced by fractions of the sonic wavelength (e.g., λ/2), chip devices employing the disclosed technology can be configured with hundreds to thousands of sonar arrays, e.g., for a millimeter to centimeter sized IC chip.
[0055] For example, the disclosed acoustic in-chip communication technology can provide a sonic 2D or 3D programmable interconnect framework for massively parallel computation in IC chip devices. The sonic 2D or 3D IC interconnects can enable
communications in one chip, or through IC stacks, forming a user defined communications layer for 3D ICs. In some implementations, encrypted pulse sequences can be used to form secure communication channels that are ad-hoc in nature, e.g., providing programmable wireless interconnections between discrete IC elements (e.g., of the FEOL portion). The added interconnect capability can allow the programmers to use ultra-high fan-out and fan-in capabilities, e.g., which is often needed to implement algorithms in associative pattern recognition algorithms, such as in applications including face or feature recognition in image processing. Furthermore, the added acoustic programmable wireless link can relieve the communications bottleneck encountered in multi-core digital systems. [0056] For example, the disclosed acoustic in-chip communication technology can provide sonar based chip-interrogation. For example, the disclosed integrated piezoelectric transducer arrays can be used to interrogate the chip or a multi-chip package to realize an integrated non-destructive evaluation (NDE) capability. Such interrogations can be employed for chip-scale NDE of wire-bonds, chip-to-chip interconnects, vias, etc. Also, for example, for security, an adversary initiated chip manipulation could be detected at a very early stage (e.g., such as by a merchant foundry for manufacturing of an IC chip design). Moreover, early detection of chip tampering could lead to immediate removal of memory or self-destruction for trusted use of integrated circuits.
[0057] Furthermore, most existing IC devices generate substantial amounts of heat that can (1) lead to degradation of portions or the entire IC device and (2) lower performance (e.g., speed) of the device during operation, e.g., particularly during extensive periods of use. IC devices can undergo various spot heating, in which particular locations or regions (e.g., circuit blocks) of the IC generate high heat. For example, the disclosed integrated piezoelectric transducer arrays can be used to monitor spot heating within the IC device to which the disclosed transducer arrays are employed. Knowledge of spot heating during operation of IC devices is of great interest, as such monitoring could be used to reroute process implementations to other IC device resources in areas outside of the spot heating, thereby allowing for the spot heat to dissipate faster and avoid reduced device performance or degradation.
[0058] Moreover, for example, the disclosed integrated piezoelectric transducer arrays can be used to image and thereby monitor structural defects and fractures of in-chip elements and chip-to-chip interconnection structures that can lead to device failure. For example, thermal cycling of ICs in various microchip-based devices like computers, mobile communication (smart phone devices), etc. can also cause degradation at the grease interface between IC chips and their coupled heat syncs. Additionally, delamination of solder balls at wire bonding interfaces is a common problems that result in premature failure of such chip-based devices. Thus, using the disclosed technology, sonar based chip-interrogation can be implemented to prolong the lifetime of such chip-based devices.
[0059] For example, the disclosed acoustic in-chip communication technology can provide sonar based lock-key operations. For example, for safe operation of some proprietary chip-sets, a lock/key system is employed to ensure activation by a known entity, and deem the chip inoperable by an adversary. Current methods include MEMS gears and beams for enabling a lock, which although effective can be not as reliable due to stiction. For example, the disclosed integrated piezoelectric transducer arrays can be used to provide sonar links to read surfaces preprogrammed to reflect ultrasonic pulses through a set of programmable reflectors, triggering a device if the pulse makes it to a target receiver on chip.
[0060] In one aspect, an integrated circuit chip device with wireless on-chip
communications capabilities includes a semiconductor substrate capable of propagating acoustic energy signals and an array of acoustic signaling modules formed on the substrate and structured to include a sub-array of acoustic transducer elements capable of transmitting and receiving the acoustic energy signals, in which each acoustic transducer element is operable to generate an acoustic communications signal to propagate through the substrate based on an electronic control signal and to receive the acoustic communications signal an acoustic signaling module to communicate with one or more other acoustic signaling modules. For example, the device can further include a control circuit layer formed on the semiconductor substrate and under the array of acoustic signaling modules to receive an external electronic signal and produce the electronic control signal to one or more acoustic transducer elements. For example, the acoustic communications signal can be modulated by the device using one or more of amplitude modulation, frequency modulation, or phase modulation.
[0061] In another aspect, a semiconductor integrated circuit device having wireless ultrasonic communication links includes a semiconductor substrate, layers formed over the semiconductor substrate and patterned to form circuit elements including transistors, and an array of ultrasound transducers formed in the layers over the semiconductor substrate, each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements. Each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
[0062] FIG. 1C shows a schematic illustration of an exemplary chip-scale wireless communications IC device 100 including an array of acoustic transceiver (sonar) modules 110 capable of transmitting and receiving acoustic communications signals. The device 100 is structured to include a substrate 120 to provide a base for the array of sonar modules 110 and formed of a solid state semiconductor material capable of propagating acoustic energy (e.g., ultrasound signal) within the device 100, e.g., including between sonar modules 110 of the array. In some examples, the sonar modules 110 can be configured as thin films of aluminum nitride (A1N) and/or lead zirconium titanate (PZT) on top of a metallization layer. In some examples, the acoustic propagation medium 120 can include silicon, e.g., such as the silicon material of a silicon die. Each or any of the sonar modules 110 can be structured to include a sub-array of individual piezoelectric transducer elements 130 (shown in FIG. ID), e.g., sometimes referred to herein as pixel elements or pixels. The sub-array of individual piezoelectric transducer elements 130 can be communicatively linked to underlying electronic control circuits (shown in FIG. ID as control circuit layer 132). The electronic control circuits can include driving circuits for providing the driving signals that the transducer elements 130 transduce to produce the acoustic communication signals and logic circuits to process received acoustic communication signals transduced by the transducer elements 130.
[0063] In some implementations, for example, the device 100 can further include an acoustic reflector / mismatching layer 125 capable of reflecting or refracting the exemplary intra-device ultrasound signal, e.g., which can be used to steer the ultrasound communication signal from one or more sonar modules 110 to another one or more sonar modules 110. For example, the acoustic reflector layer 125 can be configured under the acoustic propagation medium substrate 120, as shown in FIG. IC, and/or be configured along one or more sides of the substrate 120. In some implementations, for example, the device 100 can further include an acoustic absorber layer 126 to absorb the exemplary intra-device ultrasound signal, e.g., preventing the ultrasound communication signal from transmission beyond the device 100. In the example shown in FIG. IC, the acoustic absorber layer 126 is configured along the sides of the acoustic propagation medium substrate 120. In some implementations, for example, the device 100 can be included in an array of devices 100 for both intra- and inter- device in-chip wireless communication signaling. In some implementations, for example, the device 100 can be included on a conventional integrated circuit chip, as described later in this patent document.
[0064] As shown in FIG. ID, the piezoelectric transducer elements 130 of the sonar modules 110 can be configured with uniform or periodic spacing in the pixel array, e.g., including λ/2 spacing. For example, since each piezoelectric transducer element 130 of the sub-array (of a sonar module 110) is a fraction of a wavelength in lateral dimensions, relatively small phased arrays for sonar transmit and receive blocks can be implemented. In some embodiments of the device 100, for example, each sonar module 110 can include 10-20 pixels which are placed approximately one-half of an acoustic wave wavelength apart. In one example, each pixel can be configured to a size in a range of 3-10 μιη, such that each sonar module 110 includes a planar size of -100 x 100 μιη, e.g., which is about the size of a contact pad on a CMOS chip. Also for example, the acoustic propagation medium substrate 120 can be configured to a height of 750 μιη (or 84λ in this example). [0065] FIGS. IE and IF show inset schematics from FIG. ID showing the piezoelectric transducer element 130 of the device 100 in a three-dimensional view and a cross-sectional view, respectively, over a control circuit layer 132 and the substrate 120. For example, the acoustic propagation medium material of the substrate 120 can include bulk Silicon material 131. In some examples, the control circuit layer 132 can be structured to include one or more CMOS active layers 132 structured to include individual control circuit blocks corresponding to the individual piezoelectric transducer elements 130 of the sub-array, e.g. in which the control circuits can include one or more driving circuits, read circuits, and logic circuits including digital logic, analog logic and/or amplifiers, which are formed on the exemplary bulk Silicon layer 131. A first metal layer 133 can be formed over the one or more CMOS active layers 132. For example, the bulk Silicon substrate 131, the CMOS active layers 132, and the first metal layer 133 form a FEOL region of the device 100. The transducer element 130 can be structured to include more metal layers, e.g., including a second, a third, and a fourth metal layers 134a, 134b, and 134c, respectively, as shown in FIGS. IE and IF. The transducer element 130 can be structured to include an electrode structure layer 136b, upon which, a piezoelectric material (e.g., A1N) layer 136a is formed. The transducer element 130 can be structured to include an intermetal dielectric material 135 that is formed between the metal layers 134a, 134b, and 134c, and over the FEOL region. For example, the metal layers 134a, 134b, and 134c, the electrode structure layer 136b, the intermetal dielectric material 135, and the piezoelectric material layer 136a form a BEOL region of the device 100.
[0066] For example, the metal layer structures 133, 134a, 134b, and/or 134c function both as interconnect layer(s) for electronics, and can also function as part of the disclosed technology as custom designed acoustic wave guiding, channeling, or scattering structures. In some examples, is also possible to clear the underlying regions of certain pixels of metals and route them around the pixels to allow propagation of ultrasonic signals without any obstruction.
[0067] The sonar modules 110 are operable to receive and convert an electrical control signal to generate an acoustic energy wave or pulse carrying a communication signal to communicate with one or more other sonar modules of the array, which can receive the acoustic communication signal and transduce it to an electrical signal. For example, the array of sonar modules 110 can operate as acoustic transmitter and receiver (transceiver) modules, which can communicate with each other by proper phasing of sonar pulses sent at desired angles, frequency division modulation, or other techniques. As shown in FIG. 1C, a sonar transceiver module 110 A transduces an electrical control signal that it receives to an ultrasound signal 111 that propagates through the acoustic propagation medium 120. For example, the ultrasound signal 111 can reflect off a device boundary (e.g., such as acoustical reflector layer 125) and be incident on another sonar transceiver module 110b, as shown by the signal propagation path 111a. Additionally or alternatively, for example, surface acoustic waves (SAW) can be used to communicate laterally, as shown by the SAW propagation path 111b.
[0068] In some implementations, the generated ultrasound signal 111 can be a continuous or pulsed ultrasound (sonic) wave. For example, the sonic waves can be generated at frequencies from the hundreds of MHz to GHz in a silicon-based propagation medium, with the corresponding wavelengths in a range from the tens to single microns, e.g., including 90 to 9 μιη wavelength sonic waves at 100 MHz to 1 GHz frequencies, respectively, in a silicon medium. The relatively small acoustic wavelength, e.g., as compared to the thickness of the silicon medium or substrate, enables the use of the propagation medium 120 to transmit the ultrasound signals from one place to another. [0069] For example, the ultrasound beam 111 can be launched into the propagation medium 120 at a wide range of solid angles and targeted to a specific receiver sonar module 110b, e.g. any of the sonar modules in the array, by adjusting the delays/phases and amplitudes of the ultrasound pulses to each of the piezoelectric transducer elements 130. [0070] In some implementations of the disclosed acoustic in-chip communication technology, for example, further accuracy in targeting can be achieved by recombining the electronic signals from the receiving transducer array with appropriate delays for the desired channel. This sonic programmable communications channel can be used as a reconfigurable interconnect network that a non-desired party (adversarial interests) cannot determine with any physical scheme. The sonic interconnects can be software defined, and hence protectable using many methods of software encoding.
[0071] The exemplary acoustic in-chip communication devices can be configured to prevent the acoustic signals from propagating out of the device, or leaking. For example, because sound waves decay very fast and they cannot propagate out of the device, it can be very hard for a non-desired user (or adversary) to listen to the acoustic channels. For example, since optimal communication uses both the configuration of the transmitter and receiver arrays, the actual acoustic signals can be obfuscated with deliberate transmitter spurious signals that match nulls in the receivers but are otherwise indistinguishable from the real signals. [0072] For example, a different modality of ultrasonic chip-scale/board-level
communication is possible under acoustically mismatched or highly reflective boundary conditions instead of absorbing boundary conditions. In this exemplary mode, individual ultrasonic transducers on the transmitting array can be used to control standing wave patterns at the transducers of the receiving array. As such, the disclosed acoustic in-chip
communication devices can be regarded as a large acoustic resonator, to which different transducers located at different locations couple to with varying coupling coefficients that are a function of frequency of excitation. A matrix approach based on linear superposition is useful to model the linear regime of this modality.
[0073] Linear phased arrays can be used to focus a beam and aim it in the desired direction with characteristic radiation profiles. In ultrasound imaging, the beam can be scanned over the target field, and the returned signal is used to form the image based on acoustic reflection/transmission characteristics or time-of-flight information. In the disclosed technology, scanning a beam and focusing it in a single direction allows for the choice of where to communicate data. The principles of beam steering and focusing, e.g., using a linear phased array, is described, which is important for the understanding of the disclosed techniques of SONAR (SOund NAvigation & Ranging) operation. Examples of beam steering and focusing of the disclosed transducer arrays based devices for ultrasound imaging applications, for example, are described in: "An Integrated Circuit with Transmit
Beamforming and Parallel Receive Channels for Real-Time Three-Dimensional Ultrasound Imaging" by Wygant et al., 2006 IEEE Ultrasonics Symposium (IUS), pp. 2186-89; "Circuit Design and Simulation of a Transmit Beamforming ASIC for High-Frequency Ultrasonic Imaging Systems" by Athanasopoulos et al., 2011 IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 58, No. 7, pp. 1320-31; and "Medical Imaging: Principles, Detectors, and Electronics - Chapter 7: Electronics for Diagnostic Ultrasound" by Wodnicki et al., Krzysztof Iniewski (ed), John Wiley & Sons 2009, in which the
aforementioned documents are incorporated by reference as part of this patent document.
[0074] FIG. 2A shows a diagram of an exemplary one dimensional array of N elements spaced d apart, used to focus on a single point T. The distance from the center of the array to the target is denoted as R, and the distance from element n to the target is denoted as Rn. Each element is represented as an isotropic emitter. As such the wave radiating from each would be represented as in Equation (1):
(1)
[0075] In Equation (1), A is the amplitude of the signal, k is the wavenumber, r is the spherical radius from the source, ω is the frequency, t is time, and β is the time phase delay of the source. If the target point T is far enough away such that R is much greater than the inter- element spacing d, than the angle Θ (with respect to the positive z direction) for all the elements can be approximated as the same. This means that effectively all of the paths to the target from the elements are parallel, and the difference in path length, n n , can be found from a simple trigonometric identity. ^K Rn ^ i ^ cos(S)
(2) [0076] This leads to the pattern radiating from the n element in the array to have the following form in Equation (3): n
(3)
[0077] If the actuation pattern of the array is chosen so that all elements are operated with the same amplitude and frequency but different phases, then the corresponding acoustic phasor at the target point T, cot , is the sum of all the wave contributions w„ of the individual elements as given by Equation (4): —«-o
(4)
[0078] From this equation, it can be seen that a maximum will occur when the following k■ ^-**1 · d■ cos(0) + β„ = 0
equality is met: 2
(5)
[0079] By selecting a value for Θ, the phase delay needed at each element can be calculated. From Equation (5), it can be seen that the phase is linear between elements. However, for example, due to the cyclic nature of both Equations (4) and (5), in addition to the designed main lobe of the beam, undesirable side-lobes may appear as well. Careful design of element spacing and number of elements is implemented to treat such results. In addition to this, there can be a trade-off in terms of space and power, which is taken into account.
[0080] For example, using a single isotropic acoustic radiator as in FIG. 2B(a) shows a uniform response at all angles from the source. For example, using four isotropic acoustic radiators separated by d = λ/2 and actuated with the same phase, a pattern as shown in FIG. 2B(b) can be produced. In this case, the amplitude is 4 times as large at the 90 degree and reduced for other angles. The plots shown in FIGS. 2B(c) and 2B(d) represent patterns obtained from phase delays of 20 degree and 45 degree, respectively. [0081] Exemplary simulations of the disclosed acoustic in-chip communication devices were performed. For example, the exemplary simulations utilized Finite Element Modeling (FEM) software, which can provide a tool to aid in the phased-array design, especially in the presence of complex boundary conditions. Also, for example, PZFlex was used to calculate time domain responses of materials to phased acoustic excitations of piezoelectric elements on a silicon substrate. In the exemplary simulations, each element is pulsed with wavelet pulses of either in-phase or a linearly changing phase difference between elements. The exemplary resulting acoustic pressure field is plotted in FIGS. 3 A and 3B for in-phase and linearly changing phase difference (e.g., steps of 20° between neighboring elements) excitations, respectively.
[0082] FIG. 3A shows an exemplary simulation plot of phased array acoustic radiation pressure for zero degree phase shift between elements. The inset diagram in FIG. 3A shows a zoomed view of an exemplary A1N transducer array. In this example, the input excitation was 1 V at 100 MHz, yielding an ultrasonic wave with a maximum pressure of 20 kPa. FIG. 3B shows an exemplary simulation plot of acoustic radiation pressure for 20 degrees phase shift between elements of the phased array. In this example, the maximum amplitude of the pressure wave is 20 kPa.
[0083] PZFlex was also used to calculate the time domain response of a single element pulsed as well as the received signals on the neighboring pixels. For example, a voltage signal on the first pixel creates an acoustic wave, which travels through the silicon substrate and reflects off of the back surface and returns to the top surface. As it travels beam spreads out and the neighboring pixel will generate a voltage in response to the acoustic pulse.
[0084] FIG. 3C shows a plot of the applied signal voltage, e.g., 1 Vp-p 5 cycles of 500 MHz Sine wave, for the exemplary simulation of the time domain response of an exemplary single transducer element generating an acoustic pulse wave. FIG. 3D shows an exemplary simulation plot of the acoustic radiation pressure for the initial pulse leaves from the left-most pixel of the exemplary array. FIG. 3E shows a plot of the receive signal at the adjacent pixel, e.g., including a delay is 160 ns, which corresponds to the speed of acoustic waves in silicon. FIG. 3F shows an exemplary simulation plot of acoustic radiation pressure for the pulse after travelling to a reflecting surface (e.g., at the bottom) and reflecting back. As shown in FIG. 3F, the beam width has widened and some of the energy is picked up by the immediately adjacent pixel.
[0085] Exemplary implementations of the disclosed acoustic in-chip communication technology were performed. In one implementation, for example, exemplary acoustic in-chip communication devices were fabricated using an RF MEMS process. Starting with a silicon substrate, the RF MEMS process involved deposition of silicon dioxide of 3.5 μιη. Trenches were etched into the silicon dioxide and filled with tungsten, which was then planarized using chemical mechanical polishing. The tungsten can act as an etch stop for the aluminum nitride in subsequent steps. Next, a bottom electrode was deposited and patterned for the back side electrical contact. This was followed by the deposition of the piezoelectric aluminum nitride layer. After a photolithography step, the piezoelectric aluminum nitride layer was etched until reaching the tungsten layer. Finally, a top layer metal was deposited and patterned for the exemplary devices. In one exemplary embodiment of the devices for a SONAR system, a four by four piezoelectric transducer element array was laid out in this process. The exemplary transducer elements were configured to be 100 μιη x 100 μιη squares separated by 200 μιη.
[0086] FIG. 4A shows a cross-sectional view of a schematic illustration of one exemplary piezoelectric transducer element fabricated using the exemplary RF MEMS process. FIG. 4B shows a top view of a CAD layout diagram as well as an image of the exemplary acoustic in- chip communication device fabricated using the exemplary RF MEMS process. As shown in FIGS. 4A and 4B, the exemplary acoustic in-chip wireless communication device includes a 4 x 4 array of the piezoelectric transducer elements each electrically coupled to an electrical bonding pad via corresponding electrical interconnections. The exemplary device includes contact pads that are electrically coupled to the ground electrode of the device.
[0087] The exemplary fabricated silicon die with the aluminum nitride arrays was mounted to a printed circuit board (PCB) to perform tests using an HP8753ES RF network analyzer, as shown by the image in FIG. 5A. The PCB houses SMA ports to interface with RF equipment. The die was mounted on the PCB on top of spacers. For example, this allows the bottom of the silicon to be exposed to air creating a large contrast in acoustic impedances resulting in a strong reflection at the bottom surface. For example, if the exemplary chip device were secured to the PCB underneath, part of the sound waves would may propagate into the PCB due to its material, e.g., FR4, having a much closer acoustic impedance to silicon compared to air. This exemplary configuration prevents a large loss in signal power transmitted to the target. Wire-bonding pads on the chip, which are used for electrical connections to the PCB, were placed away from the sites of the active piezoelectric elements, e.g., so as to reduce sonic coupling into the wires. FIG. 5B shows a cross-sectional view of a schematic illustration of this exemplary setup. [0088] In one exemplary implementation, two pixels in the array of the exemplary device shown in FIGS. 4A-5B, which are 400 μιη apart, were wire bonded to the SMA connectors for measurement of the scattering parameters using the network analyzer. For example, reflection scattering parameters Sn and S22 correspond to the reflection of energy back into the port under the implementation, as shown in FIG. 6A. Exemplary results of the implementation showed that there are peaks at 1.34GHz and 1.66 GHz, which are the fundamental resonant modes of the exemplary device. These are the modes at which ultrasonic energy is most easily injected into the silicon substrate. FIG. 6B shows a data plot showing exemplary results of a transmission scattering parameter, S21, for the two exemplary transducer elements in the array. The S21 parameter shows that from 1.06 GHz to 1.67 GHz there is a loss of only 5 dB. This exemplary implementation demonstrates exemplary bandwidth of communication between these two elements.
[0089] As shown in these exemplary implementations, exemplary ultrasonic phased arrays in-chip communication devices can be integrated on chip to enable pulses to be transmitted from any location to another by beam steering for reconfigurable communication links. Exemplary results showed acoustic coupling between the transducer elements in the array, e.g., by measuring the reflection scattering parameters of the two exemplary microfabricated, 100 μιη x 100 μιη A1N transducer elements, which are spaced 400 μιη away within the same 4 x 4 array. [0090] In some aspects, the disclosed array of CMOS-integrated piezoelectric transducer (sonar) modules can be integrated into a 3D chip-stack to enable pulses to be transmitted from any location to another by beam steering. An array of sonar elements can transmit sound pulses through stacks with mechanical connections.
[0091] FIG. 7A shows a schematic illustration of an exemplary 3D chip-scale wireless communications IC device 700 including a plurality of layers 701 of arrays of the acoustic transceiver (sonar) modules 110 capable of transmitting and receiving directional acoustic communications signals 702 in a single layer and between multiple layers. Each of the layers 701 are structured to include dielectric sub-layer 720 to provide an acoustic propagation medium for the acoustic communication signal 702 (e.g., ultrasound wave) to propagate within the device 700, e.g., including between sonar modules 110 of the arrays. The device 700 can include an underfill region 715 between dies and around bumps to provide continuous propagation medium transitions between the layers 701. As previously described and shown in FIGS. 1C-1F, each or any of the sonar modules 110 of the device 700 can be structured to include a sub-array of individual piezoelectric transducer elements 130 (shown in FIG. ID). The sub-array of individual piezoelectric transducer elements 130 can be communicatively linked to underlying electronic control circuits including driving/read circuits and logic circuits. The device 700 can include a plurality of through-layer vias
(TLVs) 705, e.g., in this example represented as through-Silicon vias, which can be used for electronic control signal routing, e.g. including power and clock signal routing. The device 700 can include communication layer interconnections that connect the electronic control circuits in each layer to the TLVs 705. [0092] FIG. 7B shows an inset schematic from FIG. 7A showing an exemplary configuration of the acoustic propagation medium sub-layer 720 including artificial structures as acoustic metamaterials to guide the sonic signals, e.g., effectuating the directional acoustic communication signal 702. In implementations, the acoustic metamaterial can function as an acoustic waveguide to promote more efficient transmission of acoustic waves from one point to another. It can also include frequency filtering functionality to transmit only ultrasonic waves of certain frequency (wavelength) or mode (shear or longitudinal waves) while attenuating or obstructing the passage of undesired frequencies or modes.
[0093] In some aspects, the disclosed technology includes fabrication methods to produce 2D and 3D in-chip wireless communication signaling devices. [0094] In one exemplary embodiment, a method to fabricate exemplary chip-scale wireless communications IC devices, e.g., including the devices 100 and 700, can include A1N deposition techniques to form the piezoelectric transducer arrays. In some examples, sputter deposition of A1N is implemented at low temperatures (range), e.g., to be compatible with CMOS, but may utilize optimum metals like Tantalum for best films. The deposition of A1N at low temperatures also enables the placement of A1N embedded in the metallization stack. In some implementations, PZT thin films can be deposited though the sol-gel process, and require an anneal step which is typically at 700-800 °C. This high temperature implies that the process flow for the PZT is to be implemented after CMOS fabrication. For example, PZT films can be transferred onto CMOS-based chips using oxide-oxide bonding, oxide- metal bonding, or metal-metal bonding. [0095] FIG. 8 shows a diagram of an exemplary PZT transfer process to a CMOS based IC chip, in which a PZT stack is bonded to BEOL oxide-oxide oxide bonding that can be done at low temperatures with follow on processing to enable interconnects to top conductors of the exemplary PZT stack. [0096] In some implementations for example, the exemplary A1N stack with TEOS oxide layers can form a 1-D waveguide to launch pressure (P) waves, also referred to as longitudinal waves, with the motion transduced into the thickness of the wafer. For such exemplary implementations, the exemplary devices can be designed and fabricated to effectuate the longitudinal wave impedance of the silicon wafer and possible reflections and transmissions through metal layers, e.g., which can be intentionally placed in the IC design to tune the impedance of the transducer. FIG. 9 shows a diagram of an exemplary BEOL stack including metal reflectors to optimize wave coupling to the semiconductor substrate. For example, longitudinal waves can be guided to prevent lateral diffraction based on the metal reflector structures positioned in the BEOL stack, e.g., such that the impedance of an exemplary copper-laden segment can have higher impedance than a TEOS-only segment. For example, the transducer electrical impedance can be calculated using an exemplary ID model, e.g., including resonances and anti-resonances, and the absolute values of the impedances can lead to calculations of Q (quality factor) and K2 (electromechanical coupling) of the transducers. For example, the value of QK2 can determine the power efficiency of transducer efficiency.
[0097] For example, the design and fabrication of the exemplary wireless in-chip communication devices can be implemented to mitigate the effects of shear and SAW waves. For example, in addition to the longitudinal waves, the transducers can couple energy into shear and surface acoustic waves. For a pulse transduction, 67% of the energy is emitted as a surface wave if a surface transducer is used. In some examples, the exemplary techniques can determine the transducers design spacing by spacing the array elements in the stop-band of SAW waves. Longitudinal and shear waves can thus be used for the communication links, e.g., to minimize the coupling of energy into shear and SAW modes, as the wave motion corresponding to these modes will travel at different speeds and different directions, leading to unwanted cross-talk. Similarly, for example, shear waves can be minimized by configuring electrodes in symmetrical geometries to cancel out shear motion. [0098] FIG. 10 shows a process diagram of an exemplary fabrication technique to produce wireless in-chip communication devices of the disclosed technology including piezoelectric transducer elements formed on a cantilever beam or any other structure to act as a resonator. For example, this resonator characteristic can provide frequency selectivity during both transmission and detection as the ultrasonic transducer can generate (launch) or receive acoustic waves from its anchor, allowing resonant sensing and actuation. The exemplary fabrication technique can include a process 1010 to form the initial layers of materials of the piezoelectric resonator transducer. In the example shown in the process 1010, AIN is formed over a silicon oxide layer over a silicon substrate, in which a Al or Ti/TiN/Al layer is formed between the silicon oxide and AIN layers, and in which tungsten is formed in a cavity of the silicon substrate and/or silicon oxide layers to form an etch stop. The fabrication technique can include a process 1020 to etch into the layers of the materials and deposit an Al layer. In the example shown in the process 1020, a well is etched into the AIN layer above the W etch stop and an Al layer is subsequently patterned over the portions of the AIN layer including the etched well above the W etch stop. The fabrication technique can include a process 1030 to form the cantilever structure. The process 1030 includes etching away a sacrificial layer to have cavities or unconstrained boundaries around the acoustic transducer element. For example, one advantage of resonant sensing is that it can perform better to detect low amplitude acoustic signals on the receiver side. In the example shown in the process 1030, a portion of the AIN, silicon oxide, and silicon substrate are etched to isolate a cantilever structure underneath a portion of the silicon oxide layer and Al or Ti/TiN/Al layer below the AIN layer covered by the Al layer. The materials and process steps shown in FIG. 10 are examples, and other material and/or structural designs can be implemented to fabricate the exemplary piezoelectric resonator transducer structures for the disclosed wireless in-chip communication devices. FIG. 10 includes a diagram 1040 showing a cross-sectional view of an exemplary piezoelectric resonator transducer including an undoped polysilicon layer within the silicon oxide layer.
[0099] In some aspects, the disclosed technology includes devices and techniques for direct CMOS integration with the disclosed ultrasonic transducers, e.g., including the piezoelectric transducer elements configured in a layer adjacent to a layer of CMOS transmit and receive electronics on the same wafer. For example, such integration reduces load capacitance and inductance by minimizing interconnect and routing area and by eliminating wire bonds. The reduction of the load capacitance presented by the interconnects between the electronics and the piezoelectric transducer elements can lower transmit amplitudes such that higher receive amplitudes can be obtained. Also, a reduction in area allows more transducers and electronics to be integrated in the IC device. Furthermore, parasitic capacitances and inductances from the interconnects and routing between control circuits and transducer elements can be kept to minimum in the disclosed IC designs, such that their effect on the frequency response of the transmit and receive circuitry is negligible. Also for example, in some implementations, the transmit and receive electronics corresponding to a sonar pixel can be configured directly beneath the transducer element such that the problem of signal crosstalk between wiring carrying signals from different pixels is minimized. [0100] The disclosed technology can include a variety of circuits for controlling the phase or delay of pixel excitation waveforms. Described are two exemplary circuit topologies that can be implemented in the exemplary control electronics for controlling the phase or delay of the acoustic waveforms: delay generation through inverter based delay lines and the generation of phase shifts through quadrature mixing. [0101] In one example, digital delay lines can be used to obtain the necessary delays.
These exemplary delay lines can include one or more inverter delay elements, such as those shown in FIG. 11 A, in series. For example, such delay elements are essentially inverters whose propagation delay is adjusted by varying the supply current, the load capacitance or the supply voltage. Thus the amount of time that each delay line can delay the input signal can be adjusted by varying one or more control voltages and by the number of delay elements that are in cascade. Instead of using just the output from the end of a delay line, tapped delay lines where the output after each delay element is accessible may be used for finer delay resolution.
[0102] For example, the delay control voltages or current sources, as in the case of the current starving topology in FIG. llA(a), can be generated by storing digital values on-chip in digital memory such as SRAM and using a digital-to-analog (D/A) converter to obtain the analog voltages or currents. For example, per pixel, D/A converters are relatively large components that can affect the size of the electronic area consumed by the pixel. An example of one of the smallest D/A converter topologies includes current splitting or current steering D/A converters, which includes a current mirror comprising N+l transistors of unit size W/L and N-l transistors of 2W/L. N switches of at least 2 transistors each are used to set the D/A converter output current by switching between the output node or a dump node. FIG. 11B shows a diagram of an exemplary 4-bit current splitting D/A converter. For example, to reduce the size and/or power consumption requirements that having one or more D/A converters per pixel would impose, an appropriate analog memory topology can be used as described further below. [0103] FIG. l lC shows a diagram of an exemplary delay line circuit followed by inverter chain buffer. For example, while minimum size inverters can be used for fine delay resolution and to minimize circuit area in each pixel, the output inverter used to drive the sonar should be large enough to drive the capacitive load that the piezoelectric elements present. For example, as large inverters also can present a large capacitive load at their inputs, instead of using a single inverter as the output buffer, an inverter chain with progressively increasing inverter sizing can be used to minimize the loading effect at the buffer input, as shown in FIG. 11C.
[0104] In another example, phase shifting a sinusoidal waveform can be implemented to generate the necessary delays. For example, the phase shifting is implemented through a quadrature mixing scheme, e.g., including two analog weights A and B that are multiplied with waveforms sin(tot) and cos(i t), respectively, and then added for an output waveform of A - R cosCiiih . For example, this is equivalent to an output of sin{is*i 4- ), where C is A2 -f B∑ and <p is tan-1 ίβ/Α). Constant amplitude phase shifting can be obtained by selecting the analog weights A and B to be C cos ip and sin -p, respectively, where C is the desired output amplitude and φ is the desired output phase.
[0105] FIG. 11D shows a diagram of the exemplary sinusoidal phase shifting that can be implemented by a typical quadrature modulation circuit, and analog voltages that are applied to the mixer inputs. As in the exemplary inverter delay line topology, they can be generated by on-chip storage of digital weights that are subsequently converted to analog voltages through D/A converters. For example, the mixers can be implemented with generic Gilbert cell mixers with output nodes connected such that the summing occurs through current addition. For example, the sinusoidal voltages stn(<s>t) and cos «it} can be generated by applying a signal with frequency 2ω into a frequency divider circuit, which will output two signals at frequency ω that are 90 degrees in phase apart. The output of this quadrature phase shifting circuit can be pulsed through the use of appropriately placed switch transistors. [0106] For example, to implement a large number of sonar pixels, it is desired to keep the power and area consumed by the supporting electronics as low as possible. As an exemplary alternative to implementing multiple DACs per pixel, an analog memory for analog weight storage can be used instead. For example, each D/A converter can be replaced by a cell comprising of a single capacitor CI and a switch SI used to selectively write to the capacitor. FIG. 1 IE shows a diagram of an exemplary unit cell of an analog memory. For example, in some implementations of the disclosed devices, metal-insulator-metal (MIM) capacitors may occupy layers in the metal stack above the transistor layers and below the sonar transducer layer. For such implementations, for example, the use of such capacitors can effectively reduce the area required for pixel electronics, despite the relatively large size. In the exemplary unit cell of an analog memory, the capacitor stores the analog voltages required for the sonar circuitry, e.g., either the control voltages for delay lines or the analog weights for phase control. A single or a few global D/A converters can be used to generate these analog voltages for all of the pixels. For example, to set the analog weight on a pixel, the DAC is first set to the desired value and then the access switch for the appropriate capacitor is turned on. Once the capacitor charges to the desired voltage, the switch is turned off and the next capacitor can then be charged. Due to leakage effects, the capacitor voltage must be periodically refreshed. While a single transistor or a transmission gate can be used for the switch, various low leakage switch topologies can also be used. [0107] Several modifications can be made to this exemplary analog memory architecture to increase leakage tolerance. For example, by switching to a differential input mixer topology and using two of the capacitor based analog memory cells instead of a single one, the voltage difference of the two cells is used as the input and thus the effect of leakage can be greatly reduced. Alternatively, active analog memories which employ some form of leak compensation can be used. For even longer term storage, instead of using a capacitor, nonvolatile storage elements such as floating gate transistors can be used instead.
[0108] FIG. 11F shows a diagram of an exemplary analog memory for multiple phase generation, which can be integrated into the electronics for each sonar pixel.
[0109] Other methods of delay generation derived from ultrasonic imaging systems may also be implemented. In some examples, the transmit path of an ultrasonic imaging system typically includes the transmit beamforming electronics followed by a high voltage pulser. Multilevel pulsers can be used to send signals of different output voltages, which can be used in beamforming. As sufficient receive amplitudes can be obtained while driving the sonar transducer at amplitudes below the nominal supply voltages for transistors on advanced process nodes, a high voltage driver is not necessary.
[0110] As the transmit beamformer for ultrasonic imaging applications is typically digital in nature, shift registers or timer/counter circuits may be used to implement the transmit delays. For example, for the case of a counter, instead of applying an input waveform and delaying it, a comparator can be used at the counter outputs to generate a trigger signal once the counter reaches a certain value. This exemplary trigger signal then activates a pulser circuit which outputs a single or multiple pulses at the desired voltage, pulse width, and frequency. For example, delay resolution can be improved by employing clock division with delay locked loop based circuits.
[0111] Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine -readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
[0112] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
[0113] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
[0114] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
[0115] While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
[0116] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
[0117] Only a few implementations and examples are described and other
implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

What is claimed is: 1. A semiconductor integrated circuit device having wireless ultrasonic communication links, comprising:
a semiconductor substrate;
layers formed over the semiconductor substrate and patterned to form circuit elements including transistors; and
an array of ultrasound transducers formed in the layers over the semiconductor substrate, each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being
communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements,
wherein each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic
communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
2. The device as in claim 1, wherein:
the ultrasound transducers are formed in one layer of the layers over the
semiconductor substrate.
3. The device as in claim 2, further comprising:
a reflector layer formed over the semiconductor substrate to provide a boundary to reflect an ultrasound signal from one ultrasound transducer to another ultrasound transducer.
4. The device as in claim 1, wherein:
the ultrasound transducers are formed in two or more different layers over the semiconductor substrate as a three-dimensional array.
5. The device as in claim 4, further comprising:
an acoustic waveguide in at least one of the semiconductor substrate or the layers over the semiconductor substrate having the array of ultrasound transducers to effectuate transmission of the ultrasound signal from one ultrasound transducer to another ultrasound transducer.
6. The device as in claim 5, wherein the acoustic waveguide provides frequency filtering to transmit only ultrasonic waves of certain frequency or mode while attenuating or obstructing the passage of undesired frequencies.
7. The device as in claim 1, wherein:
the layers formed over the semiconductor substrate include (1) front-end-of-line (FEOL) layers that are formed and patterned to include the circuit elements including transistors, and (2) back-end-of-line (BEOL) layers over the FEOL layers to include wired interconnects between the ultrasound transducers and respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers.
8. The device as in claim 1, further comprising:
transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer,
wherein each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements.
9. The device as in claim 8, wherein:
the layers formed over the semiconductor substrate include (1) front-end-of-line
(FEOL) layers that are formed and patterned to include the circuit elements including transistors and the transducer driver circuits, and (2) back-end-of-line (BEOL) layers over the FEOL layers to include wired interconnects between the ultrasound transducers and respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers.
10. The device as in claim 8, wherein:
each transducer driver circuit includes a phase generation circuit to control phase delays of different ultrasound transducer elements within each ultrasound transducer.
11. The device as in claim 1, further comprising:
physical acoustic structures in the layers formed over the semiconductor substrate to facilitate guiding of ultrasound signals from ultrasound transducers.
12. The device as in claim 11, wherein:
the physical acoustic structures include metal reflectors for reflecting sound.
13. The device as in claim 1, wherein:
the circuit elements formed in the layers include an field-programmable gate array (FPGA) having FPGA logic elements that are interconnected via ultrasonic communication links between the respective ultrasound transducers, wherein the FPGA is programmable by adjusting the ultrasonic communication links between the respective ultrasound transducers.
14. The device as in claim 1, further comprising:
transducer driver circuits coupled to the array of ultrasound transducers, respectively, where each transducer driver circuit is configured to drive ultrasound transducer elements within a corresponding ultrasound transducer with different ultrasound transducer element control signals having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer,
wherein each transducer driver circuit is coupled between a corresponding ultrasound transducer and a corresponding individual circuit element or a corresponding block of two or more circuit elements, and
wherein the transducer driver circuits are configured to control or adjust ultrasonic communication links between the respective ultrasound transducers to effectuate various interconnects between the circuit elements for different circuit functions, thus providing a programmable circuit device.
15. The device as in claim 1, further comprising:
a monitor circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a local condition that is reflected in a received ultrasound signal at the ultrasound transceiver, rendering the array of ultrasound transducers to function as an array of circuit sensors for monitoring the device operating conditions.
16. The device as in claim 15, wherein:
the monitor circuit is configured to monitor a temperature at different locations within the device.
17. The device as in claim 15, wherein:
the monitor circuit is configured to monitor conditions of physical contacts at different locations within the device.
18. The device as in claim 1, further comprising:
a circuit security verification circuit coupled to the array of ultrasound transducers to read out output signals from the ultrasound transducers and to process an output signal from an ultrasound transceiver to extract a physical signature that is reflected in a received ultrasound signal at the ultrasound transceiver to provide an indication of whether a circuit layout of the device matches a predetermined circuit layout.
19. The device as in claim 1, wherein:
the semiconductor substrate is formed of a substrate material that includes silicon; an ultrasound transducer element within each ultrasound transducer includes a piezoelectric material layer that includes aluminum nitride (A1N), and
the layers formed over the semiconductor substrate and patterned to form circuit elements are complementary metal-oxide-semiconductor (CMOS) layers.
20. The device as in claim 1, wherein:
an ultrasound transducer element within each ultrasound transducer includes a piezoelectric material layer that includes lead zirconate titanate.
21. A semiconductor integrated circuit device, comprising:
a semiconductor substrate capable of propagating acoustic energy signals; and an array of acoustic signaling modules formed on the substrate and structured to include a sub-array of acoustic transducer elements capable of transmitting and receiving the acoustic energy signals, wherein each acoustic transducer element is operable to generate an acoustic communications signal to propagate through the substrate based on an electronic control signal and to receive the acoustic communications signal an acoustic signaling module to communicate with one or more other acoustic signaling modules.
22. The device as in claim 21, further comprising:
a control circuit layer formed on the semiconductor substrate and under the array of acoustic signaling modules to receive an external electronic signal and produce the electronic control signal to one or more acoustic transducer elements.
23. The device as in claim 21, further comprising a reflector layer formed over the substrate to provide a boundary to reflect the acoustic energy signals.
24. The device as in claim 21, wherein the acoustic communications signal is modulated by one or more of amplitude modulation, frequency modulation, or phase modulation.
25. The device as in claim 21, wherein the acoustic communications signal includes one or more frequencies in a range of 0.1 to 10 GHz.
26. The device as in claim 21, wherein the acoustic transducer elements include piezoelectric materials including at least one of aluminum nitride (A1N) or lead zirconate titanate (PZT) configured as thin films.
27. The device as in claim 21, wherein the array of acoustic transducer element is arranged two dimensionally and spaced at a distance in a range of 45 to 4.5 μιη.
28. The device as in claim 21, wherein the semiconductor substrate includes silicon.
29. The device as in claim 21, further comprising an absorber layer coupled to one or more vertical sides of the semiconductor substrate to absorb the ultrasonic waveforms.
30. A method for wireless communication between circuit elements in an integrated circuit (IC) device, the method comprising: transducing an electrical signal to an ultrasound signal at one or more ultrasound transducers, the ultrasound signal carrying information from the electrical signal that is provided by a first circuit element or group of two or more circuit elements;
transmitting the ultrasound signal from the one or more ultrasound transducers to one or more other ultrasound transducers that receive the ultrasound signal; wherein the transmitted ultrasound signal propagates in a semiconductor medium of the IC device; and transducing the received ultrasound signal at one or more other ultrasound transducers into a received electrical signal provided to a second circuit element or group of two or more circuit elements of the IC device,
wherein the information is transferred between the circuit elements using the ultrasound signal as a wireless interconnection.
31. The method as in claim 30, further comprising:
guiding the ultrasound signal using a reflector layer formed adjacent to the semiconductor medium to provide a boundary to reflect the ultrasound signal from one ultrasound transducer to another ultrasound transducer.
32. The method as in claim 30, further comprising:
guiding the ultrasound signal using a reflector layer formed adjacent to the semiconductor medium to provide a boundary to reflect the ultrasound signal from one ultrasound transducer to another ultrasound transducer.
33. The method as in claim 30, wherein:
the ultrasound transducers and corresponding circuit elements and semiconductor medium are formed in two or more different layers as a three-dimensional stack of IC device layers.
34. The method as in claim 33, further comprising:
guiding the ultrasound signal using an acoustic waveguide in at least one of the semiconductor mediums of the two or more different layers to effectuate transmission of the ultrasound signal from one ultrasound transducer to another ultrasound transducer.
35. The method as in claim 33, wherein:
the acoustic waveguide provides frequency filtering to transmit only ultrasonic waves of certain frequency or mode while attenuating or obstructing the passage of undesired frequencies.
36. The method as in claim 30, further comprising:
steering the transmitted ultrasound signal based on control parameters of the electrical signal having respective control signal phase delays to collectively form a respective ultrasound signal and steer the respective ultrasound signal to a targeted ultrasound transducer.
37. The method as in claim 30, further comprising:
transmitting ultrasound probe signal toward one or more target structures in the IC device;
receiving a return ultrasound signal carrying information of the one or more target structures based on a change in the ultrasound probe signal affected by acoustic impedances of the one or more target structures; and
processing the received return ultrasound signal to extract the information on a local condition of the one or more target structures for monitoring the IC device operating conditions.
38. The method as in claim 37, wherein:
the local condition includes one or more of temperature, structural integrity, or structural identity of the one or more target structures.
PCT/US2013/050772 2012-07-16 2013-07-16 Integrated circuits having integrated acoustic communication links WO2014014968A1 (en)

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