WO2013131804A1

WO2013131804A1 - Semiconductor element with an oriented layer and method for the production thereof

Info

Publication number: WO2013131804A1
Application number: PCT/EP2013/054056
Authority: WO
Inventors: Lutz Kirste; Volker Cimalla; Rolf Aidam
Original assignee: Fraunhofer Gesellschaft Zur Förderung Der Angew. Forschung E.V.
Priority date: 2012-03-05
Filing date: 2013-02-28
Publication date: 2013-09-12
Also published as: DE112013001279A5; DE102012203421A1; DE112013001279B4

Abstract

The invention relates to a method (50) for producing an oriented layer (12) on a substrate (10), the layer (12) containing or consisting of at least one connecting semiconductor with a wurtzite structure, a nucleation layer (11) being deposited on the substrate (10) during a first method step (52) by means of MBE and/or MOCVD and/or MOVPE and the oriented layer (12) being deposited in a subsequent second method step (55) by means of a PVD process. The invention further relates to a semiconductor element comprising a substrate (10) and an oriented layer (12) that contains or consists of at least one connecting semiconductor with a wurtzite structure, a nucleation layer (11) being arranged between the substrate (10) and the oriented layer (12) and being approximately 5nm to 20nm thick.

Description

Semiconductor device having an oriented layer and method of making the same

The invention relates to a method for producing an oriented layer on a substrate, wherein the layer contains or consists of at least one compound semiconductor with wurtzite structure. Layers of the entrance

mentioned type can be used as part of a semiconducting device structure.

It is known from practice to produce semiconducting electronic component structures from binary, ternary and / or quaternary compounds which crystallize in wurtzite structure. These compounds are collectively referred to below as compound semiconductor with wurtzite structure. Such semiconductive devices require at least during some manufacturing steps an underlying substrate, which ensures the mechanical stability of the semiconductive component structure.

For example, sapphire, silicon or silicon carbide may be used as the substrate. In particular, the use of silicon is advantageous since this large area

inexpensive and widely available. Furthermore, such a silicon substrate in turn may again contain semiconducting component structures, for example in the form of CMOS devices. In this way, a monolithic integrated circuit may include both silicon-based devices and wurtzite-based compound semiconductor devices.

To compensate for the different lattice constants of the substrate on the one hand and the compound semiconductor with wurtzite structure on the other hand, it is known that a buffer layer of aluminum nitride or gallium nitride on the

Deposit substrate and arrange the semiconducting device structures on this buffer layer. However, the substrate and the buffer layer have different

thermal expansion coefficients, so that a heteroepitactically deposited layer of a compound semiconductor with wurtzite structure on a substrate leads to high mechanical stresses. These can be used for

Formation of cracks and defects or lead to a temperature-dependent curvature of the substrate, so that the

Substrate has no flat surface. As a result, the subsequent processing and / or the function of the semiconducting components can be hindered or prevented.

To solve this problem, US 6,692,568 B2 proposes to deposit a buffer layer of a group III nitride by means of reactive ion sputtering at a substrate temperature up to 1200 ° C.

However, the method known from the prior art has the disadvantage that the crystal quality of such layers is lower than the quality-oriented layers, which can be achieved by metalorganic vapor phase epitaxy, molecular beam epitaxy or organometallic chemical vapor deposition at higher substrate temperature.

The invention is therefore based on the object of specifying a method for producing an oriented layer, which contains at least one compound semiconductor with wurtzite structure and which has a good crystal quality. Furthermore, the method is intended to provide a planar substrate with the layer deposited thereon.

The object is achieved by a method according to claim 1 and a component according to claim 14.

According to the invention, it is proposed to use a substrate containing sapphire, silicon carbide or silicon. In addition, the substrates mentioned may have dopants to a predetermined electrical conductivity or

Have lattice constant. In some embodiments of the invention, the substrates may additionally have unavoidable impurities, for example, hydrogen, carbon or oxygen. A substrate which contains or consists of silicon may moreover have a lateral structuring and / or a deep structuring, so that electronic components are realized on the substrate at least on a partial surface. These components may, for example, bipolar transistors, field effect transistors, resistors, capacitors or

Have printed conductors or more complex electronic circuits composed thereof. The structuring of the substrate can be achieved by metallizations and / or doped spatial regions or surface regions, which are obtainable in a manner known per se by masking, etching and processing of the substrate, for example in a CMOS process.

In some embodiments of the invention, the substrate may be a monocrystalline substrate, ie the substrate has at least one, but usually a plurality of monocrystalline domains or regions which are separated from one another by grain boundaries. Individual domains or regions may be oriented to each other. The layer to be deposited contains at least one compound semiconductor with wurtzite structure. The compound semiconductor with wurtzite structure may belong to the crystal class dihexagonal-pyramidal and have a hexagonal crystal system. The layer to be deposited should have an orientation with respect to the substrate surface, ie the crystal direction of the substrate and the essential crystal direction of the oriented layer have a fixed angular relationship to one another. The layer may serve as a raw material for fabricating electronic devices by patterning the layer. In other embodiments of the invention, the layer may be a buffer layer, which serves for adaptation of the lattice constants and / or for electrical insulation between the substrate and the electronic components.

In some embodiments of the invention, the compound semiconductor may include or consist of a compound of at least one element of the first main group of the periodic table and at least one element of the seventh main group of the periodic table. In some embodiments of the invention, the compound semiconductor may include or consist of AgI. In some embodiments of the invention, the compound semiconductor may be a compound of at least one element of the second main group of

Periodic table and at least one element of the sixth main group of the periodic table or consist thereof. In some embodiments of the invention, the compound semiconductor may include or consist of ZnO and / or CdSe and / or CdS. In some embodiments of the invention, the compound semiconductor may contain or consist of a compound of at least one element of the third main group of the periodic table and at least one element of the fifth main group of the periodic table. In some embodiments of the invention, the compound semiconductor may comprise at least one element of III. Main group of the periodic table and contain nitrogen. Thus, the layer to be deposited may be a binary, ternary or quaternary nitride compound. In some embodiments of the invention, the layer may contain or consist of aluminum nitride, gallium nitride or aluminum gallium nitride. The oriented layer can in

Be substantially closed, i. they are not individual islands, columns or domains, but low-defect semiconductor material which is suitable for the production of electronic components.

In some embodiments of the invention, the

oriented layer monocrystalline domains or areas which are separated by grain boundaries. From an orientation within the meaning of the present

Invention should also be assumed if the

Angular relationship of the crystal directions is not constant over the entire surface of the substrate, but deviates by a predetermined amount. For example, the

Crystal directions vary by a value of +/- 2 °, +/- 1 ° or +/- 0.5 °.

Furthermore, the substrate produced according to the invention should be substantially planar. For the purposes of the invention

this means that the curvature is less than 20 km ^"1 , less than 30 km ^{" 1} or less than 50 km ^"1 , which makes further processing easier or only possible.

In some embodiments of the invention, the oriented layer produced according to the invention may have a thickness of more than 1 μπι, more than 2 μπι or more than 5 μπι.

According to the invention, it is now proposed for the deposition of the oriented layer, which as starting material for the production of electronic components based on Group III nitrides or serve as a buffer layer, first deposited in a first process step, a nucleation layer using MBE and / or MOCVD and / or MOVPE. In a subsequent second method step, the oriented layer can then be deposited on the nucleation layer by means of a PVD method. The proposed method combines the advantages of PVD processes, namely low growth temperatures, rapid layer growth and simple process control without ultra-high vacuum system with the advantages of the epitaxial processes, which a high-quality, epitaxial

can provide heteroepitaxial layer.

The proposed nucleation layer may be in some

Embodiments have a thickness of about 3 nm to about 50 nm or a thickness of about 5 nm to about 20 nm. The nucleation layer is produced in a manner known per se by means of molecular beam epitaxy, organometallic chemical vapor deposition or organometallic vapor phase epitaxy. When the substrate is cooled from the growth temperature of the nucleation layer to room temperature, however, no or only low mechanical stresses are induced in the substrate, since the nucleation layer has only a small thickness. In some embodiments of the invention, the nucleation layer need not be fully applied, but may adhere to the substrate surface in the form of discrete islands. The said epitaxy methods make it possible to provide a nucleation layer whose crystal structure is based on the crystal structure of the underlying substrate. This will be a fixed

Angular relationship between the crystal direction of the monocrystalline substrate and the crystal direction of the hetero-epitaxial layer allows.

According to the invention has now been recognized that this once

achieved orientation of the nucleation layer also in

Depositing the oriented layer of nominally the same chemical composition by a PVD process preserved. Although a PVD process proceeds at a lower temperature, which results in less mobility of the deposited atoms on the surface and the kinetic energy of the ions or atoms impinging on the surface is considerably larger, a PVD process proposed according to the invention does not result in complete surprise to a mixing of the material of the oriented layer with the substrate material and also not to a destruction of the nucleation layer. Rather, it was first recognized that the epitaxial nucleation layer can serve as a seed for an oriented growth of a PVD layer.

In some embodiments of the invention, the

PVD methods may be selected from reactive magnetron sputtering and / or laser deposition and / or thermal

Evaporate. When magnetron sputtering can at least one

Element of the III. Main group are provided as a solid, which is atomized by impinging inert and / or active gas ions. Nitrogen can be supplied in this case from the gas phase, so that the desired

Layer of at least one element of III. Main group of the Periodic Table of nitrogen.

For laser deposition, a target material can be vaporized by high-energy, usually pulsed laser radiation. In other embodiments of the invention, a metal or alloy may be heated by resistance heating or electron impact heating to the extent that the material evaporates. In any case, the substrate with the nucleation layer arranged thereon is arranged so that the evaporating atoms, ions or clusters are deposited on the surface of the substrate and provide there the desired layer. The PVD methods mentioned here have the advantage that the substrate temperature can be chosen considerably lower than in the case of the epitaxial method used in the first method step. Furthermore, the growth rate can be increased, so that the oriented layer can be deposited in a shorter time. Due to the lower temperature induced by different thermal expansion coefficients mechanical stresses are reduced, so that a curvature of the substrate can be reduced.

In some embodiments of the invention, the

Temperature of the substrate in the second process step be less than 400 ° C, less than 300 ° C, less than 100 ° C or less than 50 ° C. In the stated temperature range, on the one hand, the growth of an oriented layer with good crystal quality is possible. On the other hand, the temperature is chosen so low that mechanical stresses on cooling of the substrate at the end of the growth step are largely avoided or remain controllable.

In some embodiments of the invention, the temperature of the substrate in the first process step may be greater than 600 ° C, greater than 800 ° C, or greater than 900 ° C. In the temperature range mentioned, the mobility of the atoms adsorbed on the surface of the substrate is sufficiently high that they condense by hopping processes in the desired crystal structure. For example, this may be a hexagonal crystal structure.

In some embodiments, the oriented layer may have a thickness of about 100 nm to about 10 μπι or from about 300 nm to about 5 μπι. Oriented layers of this thickness on the one hand have good electrical insulation values in order to ensure a decoupling of the electronic components from the substrate. Furthermore, in some

Embodiments of the invention after the preparation of the oriented layer the substrate are removed,

for example by etching. Furthermore, in these

Layer thicknesses are avoided a negative influence of the crystal structure of the substrate on the structure of a deposited on the oriented layer device structure.

In some embodiments of the invention, the method has the additional step of placing the substrate in one to temper the oxidizing atmosphere. In some embodiments of the invention, the temperature may be more than 500 ° C or more than 700 ° C. In this way, a deposited Group III nitride can be oxidized to an oxynitride. Such an oxynitride may have improved electrical or electronic properties, have a different crystal structure or allow for improved isolation or dielectric numbers.

In some embodiments of the invention, the first method step may be performed in a first vacuum chamber and the second method step in a second vacuum chamber. Such a procedure advantageously allows the use of per se known and usually existing devices for gas phase epitaxy or for

PVD coating. Thus, the proposed method in a particularly simple manner with existing equipment

be implemented without the need to procure new and expensive equipment.

In some embodiments of the invention, the transfer of the substrate from the first vacuum chamber to the second vacuum chamber may be in air. According to the invention, it has been recognized that the surfaces are not impaired by this or existing impairments can be removed again by a simple cleaning step in the second vacuum chamber. This further simplifies the proposed method.

The invention is based on figures without

Restriction of the general inventive concept will be explained in more detail. Showing:

1 shows a section through a substrate according to the invention with the oriented layer arranged thereon.

FIG. 2 shows a flowchart of the invention

proposed method. FIG. 3 shows data from an X-ray structural analysis of an oriented material produced according to the invention

Shift.

FIG. 4 shows a pole figure of the nucleation layer. FIG. 5 shows a pole piece of the oriented layer.

FIG. 6 shows a measuring device with which the data according to FIGS. 3 to 5 can be obtained.

FIG. 1 shows a section through a substrate 10 with an oriented layer 12 arranged thereon. The substrate may, for example, contain or consist of silicon. In addition, the substrate 10 may contain a dopant to adjust a predetermined electrical conductivity. The substrate 10 may be a single crystal, for example, a conventional wafer used in microelectronics. The substrate 10 may have a thickness of 50 μπι to 1 mm. The diameter of the substrate may be about 10 cm to about 30 cm.

On the surface 101 of the substrate 10, a nucleation layer 11 is first deposited. The nucleation layer 11 may have a thickness of from about 3 nm to about 50 nm, or from about 5 nm to about 20 nm. The nucleation layer 11 may contain or form a group III nitride

consist. In some embodiments of the invention, the nucleation layer 11 may include aluminum nitride, gallium nitride, or aluminum gallium nitride. The nucleation layer 11 may, as shown in Figure 1, be applied over the entire surface or in the form of individual islands with

intervening interruptions may be formed on the surface 101.

The nucleation layer 11 is obtained by a per se known epitaxial process, for example MBE, MOVPE or MOCVD. The nucleation layer may be deposited at a temperature greater than 800 ° C or greater than 900 ° C.

On the nucleation layer 11 is the oriented layer 12 by means of physical vapor deposition (PVD)

deposited. For example, the oriented layer 12 may be deposited by sputtering, thermal evaporation or laser deposition. The oriented layer 12 usually contains the same material as the nucleation layer 11. In some embodiments of the invention, however, a different material system may be used.

According to the invention, it was recognized that the orientation of the nucleation layer 11, which due to the used

Epitaxieverfahrens oriented on the surface 101 of the substrate 10 grows, even when deposited by means of a PVD process is maintained. In this way, an oriented layer can be higher with a sputtering technique

Crystal quality are deposited, although such

Techniques are usually used only for applications that do not place great demands on the

Crystal quality. By way of example, the coating of architectural glass with a thermal barrier coating is mentioned.

Such layers are typically unoriented, i. the layer is either polycrystalline or has monocrystalline regions which, however, are tilted relative to adjacent regions and relative to the substrate. These layers are therefore not useful for microelectronic applications. more

It is more surprising that the orientation predetermined by the nucleation layer is also retained during the deposition of a group III nitride layer by means of a PVD process.

With reference to Figure 2, the proposed method according to the invention will be explained again. In the first method step 51, the substrate 10 is inserted into the vacuum of an epitaxy system. funneled. Previously, the surface can be roughly cleaned, for example, in an ultrasonic bath and / or by rinsing with various solvents and / or deionized water. Within the vacuum of the epitaxial system, the substrate 10 may be subjected to further purification,

for example by ion etching or sputtering.

This is followed by the first method step 52. In method step 52, MBE and / or MOCVD

and / or MOVPE or another known per se

Epitaxy a nucleation layer deposited on the surface 101. The nucleation layer may be monocrystalline. At least the nucleation layer is oriented deposited on the surface 101 such that the crystal direction of the nucleation layer is in a fixed angular relationship to the crystal orientation of the substrate 10.

The nucleation layer may have a thickness of about 3 nm to about 50 nm. Typically, the nucleation layer is deposited at a temperature greater than 600 ° C, greater than 800 ° C, or greater than 900 ° C. In one embodiment, the nucleation layer contains AlN and is deposited from two molecular beams containing or consisting of aluminum and nitrogen.

In method step 53, substrate 10 is cooled to room temperature and removed from the ultrahigh vacuum of the epitaxy system. Now a transfer to a sputtering system takes place in which the PVD coating is carried out. The transfer can be carried out under protective gas or in a vacuum. In some embodiments of the invention, the transfer may also be performed without special precautions.

In method step 54, the substrate is introduced into the vacuum of a sputtering system. Thereafter, the substrate can be cleaned by thermal desorption or plasma cleaning of adherent adsorbates to remove adhering contaminants from the previous process step.

This is followed by the second method step 55. In method step 55, the oriented layer is deposited in an active gas sputtering process. For the measurements shown in FIGS. 3 to 5, an oriented layer was used, which was deposited with the following parameters:

Working pressure: 4.5 x 10 ^"4 Torr

Target: AI, 99.999%

High frequency power: 1340 watts

Argon purity: 99.999%

Argon flow: 70 sccm

Nitrogen purity: 99.999%

Nitrogen flow: 40 sccm

Distance substrate target: 90 mm

Substrate bias voltage: -100 volts

In this way, at low temperature a

Aluminum nitride are deposited, which the

Has maintained orientation of the underlying nucleation layer. The oriented aluminum nitride layer can directly as a substantially closed layer

are deposited, i. they are not individual islands, columns or domains, but low-defect

Semiconductor material which is suitable for the production of electronic components. In some

Embodiments of the invention may produce the oriented layer 12 with a defect density of less than 10 ⁹ cm ^-3 .

In some embodiments of the invention, the

Nucleation layer immediately on the surface of the

Substrate can be arranged and the oriented layer or the aluminum nitride layer can directly on the

Nucleation layer can be arranged. By the low Temperature in the production of the oriented layer, the substrate with the layer is largely stress-free.

Further intermediate layers to compensate for lattice mismatch need not be provided.

The layer properties are explained in more detail below with reference to FIGS. 3 to 5. The measurements were carried out by means of an X-ray diffraction system, which is shown schematically in FIG. As can be seen from FIG. 6, the measuring device comprises an X-ray source 60. The

X-ray source 60 generates characteristic X-ray radiation and X-ray Bremsstrahlung by braking an electron beam on a copper target. The X-ray beam 61 emerging from the X-ray source 60 is monochromatized by means of an optional monochromator 62. In the present embodiment, the CuK _a line of the characteristic X-ray was used for analysis.

The monochromatized X-radiation strikes the sample 65, in the present example the substrate 10 with the nucleation layer 11 and / or the oriented layer 12 arranged thereon.

The sample 65 can be goniometered about three axes

be panned. Perpendicular to the plane of the drawing is the axis of rotation of the angle CO. In the drawing plane are the rotation angles φ and χ. The X-ray radiation reflected by the sample 65 is detected in the detector 62. As a detector, a semiconductor counter,

For example, a germanium detector, or a counter tube can be used.

FIG. 3 shows the measured intensity of the X-radiation in the detector 62 on the ordinate and the angle 2Θ (the axis of rotation CO) on the abscissa. The measurements were carried out at constant angles φ and χ. As FIG. 3 shows, three scattering angles of the silicon substrate with [111] orientation can be detected.

Furthermore, FIG. 3 shows three measuring signals, which are three of the six orientations of the hexagonal crystallizing

Aluminum nitrides can be assigned.

FIG. 4 shows a pole figure of the nucleation layer. This means that the sample 65 contains only the substrate 10 and the nucleation layer 11 deposited thereon. The pole figure is produced by varying the angles φ and χ. The angle φ varies from 0 to 90 °, with different angles χ being plotted as concentric circles. The intensity of the X-ray radiation detected in the detector 62 is coded in the form of different gray levels. Clearly recognizable is the hexagonal structure of the epitaxially deposited

Nucleation layer of aluminum nitride, which leads to six distinct signals at different angles φ and constant χ in the pole figure.

Finally, FIG. 5 shows the same measurement as FIG. 4, wherein the sample 65 proposed according to the invention

Layer system comprises, namely the substrate 10 with the

Nucleation layer 11 and the sputtered oriented layer 12. It has been found, quite surprisingly, that the hexagonal structure of the nucleation layer 11 is also retained in the sputtered layer 12. Had the

sputtered layer 12 the known per se, polycrystalline or fibrous structure, so would in the pole figure according to

Figure 5 instead of the six discrete maxima an annular signal with continuous distribution of the angle φ be recognizable. Obviously, however, it is possible with the method according to the invention to deposit layers of high quality, which is suitable as a base material for microelectronic building elements.

Of course, the invention is not limited to the embodiments shown in the figures. The The above description is therefore not to be considered as limiting, but as illustrative. The following claims are to be understood as meaning that a named feature is present in at least one embodiment of the invention. This does not exclude the presence of further features.

Claims

claims

A method (50) for producing an oriented

Layer (12) on a substrate (10), wherein the layer (12) contains or consists of at least one compound semiconductor with wurtzite structure,

characterized in that

a nucleation layer (11) is deposited on the substrate (10) in a first method step (52) by means of MBE and / or MOCVD and / or MOVPE and in a subsequent second method step (55) the oriented layer (12) by means of a PVD method is deposited.

2. The method according to claim 1, characterized in that the PVD method is selected from reactive magnetron sputtering and / or laser deposition and / or thermal evaporation.

3. The method according to any one of claims 1 or 2, characterized in that the layer (12) at least one

Element of the III. Main group of the Periodic Table and contains nitrogen.

4. The method according to any one of claims 1 to 3, characterized in that the nucleation layer (11) has a thickness of about 3 nm to about 50 nm or from about 5 nm to about

20 nm.

5. The method according to any one of claims 1 to 4, characterized in that the temperature of the substrate (10) in the second process step is less than 400 ° C, less than 300 ° C, less than 100 ° C or less than 50 ° C.

6. The method according to any one of claims 1 to 5, characterized in that the temperature of the substrate (10) in first process step (52) is greater than 600 ° C, greater than 800 ° C or greater than 900 ° C.

7. The method according to any one of claims 1 to 6, characterized in that the oriented layer (12) has a thickness of about 100 nm to about 10 μπι or from about 300 nm to about 5 μπι.

A method according to any one of claims 1 to 7, further comprising the step of: annealing the substrate (10) in an oxidizing atmosphere.

9. The method according to claim 8, characterized in that the temperature is more than 500 ° C or more than 700 ° C.

10. The method according to any one of claims 1 to 9, characterized

in that the first method step (52) is carried out in a first vacuum chamber and the second method step in a second vacuum chamber.

11. The method according to any one of claims 1 to 10, characterized in that the substrate with the oriented layer at room temperature has a curvature of less than 20 km ^"1 , less than 30 km ^{" 1} or less than 50 km ^"1 .

12. The method according to any one of claims 1 to 11, characterized in that the oriented layer (12)

closed on the substrate is deposited.

13. The method according to any one of claims 1 to 12, characterized in that the oriented layer (12) is produced with a defect density of less than 10 ⁹ cm ^"3 .

14. A semiconductor device comprising a substrate (10) and an oriented layer (12) which contains or consists of at least one compound semiconductor with wurtzite structure, wherein between the substrate (10) and the

oriented layer (12) a nucleation layer (11) is arranged, characterized in that the Nucleation layer (11) has a thickness of about 5 nm to about 20 nm and the oriented layer (12)

is deposited over the entire surface of the substrate.

15. Semiconductor component (1) according to claim 14, characterized

in that the nucleation layer (11) is obtainable by MBE and / or the oriented layer (12) is obtainable by a PVD process.

16. Semiconductor component (1) according to claim 14 or 15,

characterized in that the substrate has a curvature of less than 20 km ^-1, less than 30 or less than 50 KRRT ¹ knf ¹ has.

17. Semiconductor component (1) according to one of claims 14 to 16, characterized in that the oriented

Layer (12) has a defect density of less than 10 ⁹ cm ^"3 .

18. Semiconductor component (1) according to one of claims 14 to 17, characterized in that the oriented

Layer (12) is deposited closed on the substrate.