WO2013114398A2

WO2013114398A2 - Fpga system for usb bridge implementation

Info

Publication number: WO2013114398A2
Application number: PCT/IN2013/000031
Authority: WO
Inventors: Raghukul Dikshit; Akanksha Jain
Original assignee: The Tata Power Company Ltd.
Priority date: 2012-01-30
Filing date: 2013-01-17
Publication date: 2013-08-08
Also published as: WO2013114398A3

Abstract

A Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device overcomes drawbacks known in the art including lack of security due to software based encryption implementation and driver and OS dependency. The USB bridge comprises a Host PHY operating in a Device mode and a Device PHY operating in a Host mode, connected to the USB Host and the USB mass storage device respectively via a bidirectional USB link. The FPGA is connected to each of the Host PHY and the Device PHY via a bidirectional ULPI link respectively. Data from the USB Host is written into the FPGA of the USB bridge through the Host PHY. This data in parallel form is then stored internally and subsequently communicated to the USB mass storage device through the Device PHY over the Device ULPI Interface.

Description

FPGA SYSTEM FOR USB BRIDGE IMPLEMENTATION

FIELD OF THE DISCLOSURE

The present disclosure relates to the field of computing.

Particularly, this disclosure relates to a system for interfacing devices over a computer bus. Still particularly, this disclosure relates to a system for processing data flow through a Universal Serial Bus (USB) using Field-programmable gate array (FPGA).

BACKGROUND

Universal Serial Bus (USB) is a specification developed by Compaq, Intel, Microsoft and NEC, and further developed by Hewlett Packard, Lucent and Phillips. The USB was developed as a means to connect a large number of devices to a Personal Computer (PC), with hot pluggable feature. A USB 2.0 specification defines three data rates pertaining to clocking rates of a system, namely High Speed (480 Mbps), full Speed (12 Mbps) and Low Speed (1.5 Mbps).

Each USB bus connects a USB Host like a desktop, a laptop, and the like to a USB Device like a mass storage device, a CD-ROM drive, and the like. USB is based on a tiered star topology supporting up to 127 devices attached to a Host at a time using a 7 bit unique address. Each USB packet is identified by its dedicated packet identifier field, henceforth referred to as PID, thereby distinguishing the USB commands from the USB data packets. USB uses a differential transmission pair for data. This is encoded using Non Return to Zero Inverted (NRZI) encoding format and is overfed to ensure adequate transitions in the data stream. On Low and full Speed devices, a differential T is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V. A differential Ό' on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors. The USB specification supports four types of data transfers depending on the application involved. These are control, bulk, and isochronous and interrupt transfers. This disclosure deals with USB 2.0 High Speed devices and their communication with a Host. For a USB 2.0 device to be recognized, it has to go through a High Speed signaling process with a chirp sequence handshaking between the Host and the Device. Any High Speed Device is initially recognized as a full Speed Device. Post the chirp sequence, it is ready to operate in a High Speed mode. Full and High Speed devices both have a 1.5ΚΩ pull up on the D+ line. When the Device is connected, power is applied to the cable, the Device, and the pull-up on D+ line. This causes the voltage to rise above Vm at the Host, where V_IH is the threshold voltage minimum of two volts for full Speed detection. The USB Host then polls the Device and detects full-Speed Device attachment. After the Host detects that a full-Speed Device is connected, it issues reset to the Device. If the Device is High Speed capable, it initiates the chirp sequence with a chirp K .In response to the chirp K detected by the Host from the Device, the Host sends alternate sequence of Ks and Js to the Device. Upon successful detection of at least 3 such KJ pairs, the Device is transitioned to operate in the High Speed mode. Once the Device is ready to communicate with the Host in High Speed mode, the Device enumeration process begins. For any data transfer between the Host and the Device, the communication has to be necessarily initiated by the Host. Control transfers are typically used for command and status operations. Each control transfer comprises three communication stages namely a setup stage, a data stage and a status stage. The setup stage is where the request is sent. This consists of three phases. The setup token is sent first in the setup phase, which contains an address and an endpoint number. Followed by this, a data packet is sent and always includes a PID type of data and includes a setup packet which details the type of request. If the Device successfully receives the setup data without any CRC (cyclic redundancy check) or PID (packet identifier) error, it responds with an ACK (acknowledge) handshake. If the packet is corrupted, the Device ignores the data and does not send an ACK handshake packet. Following the setup stage, is the optional data stage which involves data transfer between the Host and the Device. For Bulk write transfers i.e. if data transfer is directed from the Host to the Device, an OUT token is initiated by the Host. After this, the Host sends the data to the Device. On successful reception, the Device issues an acknowledgement to the Host. If the Device cannot accept data due to some reason, it issues a NAK (negative acknowledge) till the Device becomes ready again to receive data from the Host. For functional errors, a Stall packet is sent by the Device. For Bulk read transfers, an IN token is initiated by the Host. In response to this, if the Device is ready, it sends data to the Host. The Host then acknowledges the data with an ACK packet. Finally to indicate successful data transfer is the status stage which is always directed opposite to the data stage. Thus, a successful data transfer is established between the Host and the Device. In order to prevent the USB bus from slipping into inactive mode, a start of frame is sent by the Host at every 125 micro second intervals for High Speed USB transfers.

USB mass storage devices responsible for storage of Bulk data, typically USB flash drives, hard drives, pen drives and the like are portable and hence data security in this media is always a concern. Various techniques have been implemented to incorporate encryption at application software or OS (Operating System) level on the USB Host system. However, Host software based implementations are plagued with disadvantages including:

• requirement of operating system specific drivers or services which can be installed only after loading the operating system; • requirement of additional CPU cycles to perform on the fly encryption leading to increased latency; and

• vulnerability to security breach since the encryption function implementation is implemented in the Host software and the encryption services can be bypassed.

The present disclosure envisages a system that overcomes drawbacks of the prior art by specifically aiming towards:

• implementing the mass storage drive encryption feature at hardware level;

• ensuring that the implementation residing in the system is driver free and operating system independent, thus making it suitable for bootable devices as well;

• emulating both USB 2.0 Host , USB 2.0 device and the encryption logic on a single FPGA chip;

• making the design compatible for any standard USB 2.0 High Speed compliant mass storage devices available in the market;

• providing a more efficient implementation in which the cipher keys can be given directly to the FPGA rather than routing through a PC, thereby enhancing the security; and

• providing an implementation which is compatible with any cryptographic algorithm generally used for securing data.

OBJECTS

Some of the objects of the present disclosure aimed to ameliorate one or more problems of the prior art or to at least provide a useful alternative are described herein below: An object of the disclosure is to provide a low cost single chip implementation of a USB 2.0 bridge comprising a USB Host and a Device on a Field Programmable Gate Array (FPGA).

Another object of the disclosure is to provide a framework for encrypting data over USB on-the-fly for enhancing security at the hardware level.

Yet another object of the disclosure is to implement USB 2.0 Host and Device core and encryption logic in a single FPGA, thereby providing a power efficient and extremely compact solution.

Still another object of the disclosure is to capture real time USB data transfer between a USB 2.0 Host and a Device, without any interference in communication and in strict compliance with the USB 2.0 specifications.

Another object of the disclosure is to provide a method for capture and storage of data between a USB 2.0 Host and a Device which could be used for recording purposes.

Still another object of the disclosure is to provide a method for capture of USB data for analysis or display, thereby enabling the system to be used as an emulator or for debugging purposes.

Other objects and advantages of the present disclosure will be more apparent from the following description when read in conjunction with the accompanying figures, which are not intended to limit the scope of the present disclosure. SUMMARY

In accordance with one aspect of the present disclosure, there is provided a Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device, the USB bridge comprising:

• a Host PHY connected to the USB Host via a bidirectional USB link, the Host PHY adapted to operate in a Device mode;

• a Device PHY connected to the USB mass storage device via a bidirectional USB link, the Device PHY adapted to operate in a Host mode; and

• an FPGA connected to each of the Host PHY and the Device PHY via a bidirectional ULPI link respectively,

the FPGA comprising:

an initialization module configured to perform initialization of the USB mass storage device and enable handshaking process between the USB Host and the USB mass storage device;

a Host ULPI Device wrapper (UDW) module adapted to communicate with the Host PHY;

a Device ULPI Device wrapper (UDW) module adapted to communicate with the Device PHY;

a Host Interface Engine adapted to transmit and receive data from the Host UDW module;

a Device Interface adapted to transmit and receive data from the Device UDW module; a Data Identification and Separation module adapted to receive data from the Host Interface Engine and the Device Interface Engine;

a Custom Encode Logic module adapted to receive data from the Data Identification and Separation module and further adapted to encrypt the data received from the Host PHY to generate modified write data;

a Custom Decode Logic module adapted to receive data from the Identification and Separation module and further adapted to recover original unmodified data received from the Device PHY to generate decrypted read data;

a Host Data Combiner module adapted to combine commands from the Data Identification and Separation module and the modified write data into a single stream of Host data, the Host Data Combiner module further adapted to process the Host data and transfer the processed Host data to the Device Interface Engine for further transmission to the USB mass storage device; and

a Device Data Combiner module adapted to combine commands from the Data Identification and Separation module and the decrypted read data into a single stream of Device data, the Device Data Combiner module further adapted to process the Device data and transfer the processed Device data to the Host Interface Engine for further transmission to the USB Host.

Typically, the Host PHY and the Device PHY is a Hi-Speed USB physical layer transceiver. In accordance with the present disclosure, the ULPI link is adapted to communicate 8 bit data between the FPGA and each of the Host PHY and the Device PHY.

Typically, the initialization module referred herein above comprises:

• a Device initialization sub module adapted to perform the initialization and handshaking process for the USB mass storage device, the Device initialization sub module further comprising a Device disconnect sub module adapted to detect ejection of the USB mass storage device;

• a power on reset sub module adapted to selectively generate a reset signal for all modules of the FPGA ; and

• a clock module that provides Host and Device clocks to the respective sub modules constituting the FPGA.

Typically, each of the Host UDW and the Device UDW comprise a receive module and a transmit module, the receive module being adapted to eliminate the CRC (cyclic redundancy check) from the data to generate pure data packets, the transmit module being adapted to receive the pure data packets and further adapted to recalculate the CRC for the pure data packets and transmit the checked data packets to the USB mass storage device via the Device PHY and the USB Host via the Host PHY respectively.

Typically, the Host Interface Engine comprises:

• a Host Protocol Handler comprising a first receive engine and a first transmit engine, the first receive engine adapted to receive data from the Host UDW, the first transmit engine adapted to transmit data to the Host UDW for further transmission to the Host PHY;

• a Host receive FIFO adapted to receive data from the first receive engine; and • a Host transmit FIFO adapted to send data to the first transmit engine. Typically, the Device Interface Engine comprises:

• a Device Protocol Handler comprising a second receive engine and a second transmit engine, the second receive engine adapted to receive data from the Device UDW, the second transmit engine adapted to transmit data to the Device UDW for further transmission to the Device PHY;

• a Device receive FIFO adapted to receive data from the second receive engine; and

• a Device transmit FIFO adapted to send data to the second transmit engine.

Typically, the Data Identification and Separation module is adapted to receive data from either a Host receive FIFO or a Device receive FIFO constituting the Host Interface Engine and the Device Interface Engine respectively, the Data Identification module being further adapted to separate the data into non Bulk data for transmission to either of the Host Data Combiner module or the Device Data Combiner module and Bulk data for transmission to either of the Custom Encode Logic module or the Custom Decode Logic module.

In accordance with another aspect of the present disclosure, there is provided a method of implementing a USB bridge between a USB Host and a USB mass storage device using a Field Programmable Gate Array (FPGA), the method comprising the following steps:

• connecting a Host PHY to the USB Host via a bidirectional USB link;

• connecting a Device PHY to the USB mass storage device via a bidirectional USB link; • connecting a Host ULPI Device wrapper (UDW) module to the Host PHY;

• connecting a Device ULPI Device wrapper (UDW) module to the Device PHY;

• initiating the initializing and handshaking process for the USB mass storage Device;

• receiving data and eliminating CRC (cyclic redundancy check) from the data to generate pure data packets at a receive module of either the Host UDW or the Device UDW;

• recalculating CRC for the pure data packets at a transmit module of either the Host UDW or the Device UDW;

• separating the checked data packets into non Bulk data containing commands and Bulk data including Bulk read data and Bulk write data for Bulk transmission;

• encrypting the Bulk data to generate modified write data or decrypting the Bulk data to read data;

• combining the commands and the modified write data to generate a single stream of Host data or combining the commands and the read data to generate a single stream of Device data; and

• processing the Host data and transferring the processed Host data to the USB mass storage device or processing the Device data and transferring the processed Device data to the USB Host.

The method of implementing a USB bridge as described herein above, typically comprises the following additional steps:

• detecting ejection of the USB mass storage device; and

• signaling reset of the bridge. BRIEF DESCRIPTION

The Field Programmable Gate Array (FPGA) based USB bridge, of the present disclosure, will now be described in relation to the accompanying drawings, in which:

FIGURE 1 illustrates a general representation of an FPGA system for USB bridge implementation in accordance with the present disclosure;

FIGURE 2 illustrates an overall schematic layout of the components of the Field Programmable Gate Array (FPGA) system for USB Bridge implementation of FIGURE 1;

FIGURE 3 illustrates a schematic flow diagram of an FPGA sub-module, exhibiting the FPGA to PHY connectivity;

FIGURE 4 illustrates a schematic flow diagram of a Host Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Host side; and

FIGURE 5 illustrates a schematic flow diagram of a Device Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Device side.

DETAILED DESCRIPTION

A preferred embodiment will now be described in detail with reference to the accompanying drawings. The preferred embodiment does not limit the scope and ambit of the disclosure. The description provided is purely by way of example and illustration. The embodiments herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiments in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

The present disclosure envisages a Field Programmable Gate Array (FPGA) based Universal Serial Bus (USB) bridge implementation for communication of data between a USB Host and a USB mass storage device. The single FPGA based implementation emulates both, a USB 2.0 High Speed Host and a USB 2.0 High Speed Device. Any write or read operation on the Device, initiated by the Host, happens through the USB bridge as envisaged. Along with the basic USB 2.0 High Speed bridge implementation, the disclosure further focuses on data encryption feature at the hardware level for USB mass storage device class in particular.

The Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host, and a USB mass storage device in accordance with the present disclosure will now be explained with reference to FIGURE 1 through FIGURE 5 with the key components being generally referenced by numerals as illustrated.

The present disclosure envisages an FPGA 10 for implementation of the USB bridge 60. The FPGA 10 is configured for receiving and converting USB data from a USB Source (USB Host 40 or USB mass storage device 50) into a format compatible for storage and its subsequent transmission to a recipient side (USB mass storage device 50 or USB Host 40) of a communication bus, maintaining compliance with USB 2.0 specifications.

In accordance with the present disclosure, the USB system 100 as illustrated in FIGURE 1 reads input data from the USB Source, typically, USB transceivers, in a parallel form, compatible for storage in the FPGA internal buffers and subsequent communication to the intended recipient side (USB mass storage device 50 or Host 40). For instance, the data from the USB Host 40 is written into the FPGA 10 of the USB Bridge 60 through the Host PHY 30. This data, in parallel form, is then stored internally and subsequently communicated to the USB mass storage device 50 through the Device PHY 20 over a Device ULPI (UTMI + Lowe Pin Interface) Interface.

FIGURE 2 illustrates an overall schematic layout of the components of the Field Programmable Gate Array (FPGA) system for USB Bridge implementation of FIGURE 1.

The main components of the USB bridge 60 as illustrated in FIGURE 2 are referenced generally with numerals as indicated below:

Host ULPI Device wrapper (UDW) 34;

Device ULPI Device wrapper (UDW) 36;

Host PHY 30;

Device PHY 20;

initialization module 8;

Host Interface Engine 12;

Device Interface Engine 14;

Custom Encode Logic module 16;

Custom Decode Logic module 22;

Host Data Combiner module 24; Device Data Combiner module 26; and

Data Identifier and Separation module 32.

The USB bridge, in accordance with the present disclosure, is implemented using the FPGA 10. The bridge comprises the FPGA 10 as the heart of the system along with two USB PHY (20, 30), one emulating the Host while the other emulating the Device.

The Host PHY 30, operating in a Device mode, interacts with the USB Host 40 through a USB Interface. The Device PHY 20, operating in a Host mode, interacts with the USB mass storage device 50 through its USB Interface. The PHY (30, 20) interacts with the FPGA 10, commonly referred to as link through its ULPI Interface. The Host ULPI Device wrapper (UDW) 34 and the Device ULPI Device wrapper (UDW) 36 communicate directly with the Host PHY 30 and the Device PHY 20 respectively over their corresponding ULPI Interfaces.

The initialization module 8 comprises the Device initialization sub module 18 and the power on reset sub module 28. The Device initialization sub-module 18 performs the initialization and the handshaking process for the USB mass storage device 50. It further embodies the Device disconnect module 38. The Device disconnect module 38 supports the plug and play functionality of the USB mass storage device 50 by detecting the mass storage device ejection from the USB system and consequently signaling the power on reset sub module 28 to reset the entire system. A clock module (not shown) provides the respective clocks to the Host and the Device modules of the USB bridge 60.

The USB link is a bidirectional link that transmits and receives data over a single differential pair of wire (D+ and D-). The PHYs used, Interface the serial USB link with the parallel input Interface of the FPGA 10. The ULPI Device wrapper (UDW) Modules (34, 36) connect to the PHY (20, 30) over the ULPI Interface. This module separates the bidirectional data into individual receive and transmit streams. For example, if the Host sends some data to the Device then the receive engine of the Host UDW 34 strips off the incoming cyclic redundancy check (CRC) and passes pure data packets through the receive stream to the Host Interface Engine 12. The transmit engine of the Device UDW 36 receives this data from the Host UDW 34 after processing through the further sub-modules. The CRC is re-calculated for the data packets in the Device UDW 36 transmit engine and passed on to the Device PHY 30 from where it is subsequently transmitted to the USB mass storage device 50. The separated data receive and transmit data streams are thus passed on to the respective Interface modules for subsequent processing of data till it reaches the other end of the USB bus.

The Host Interface Engine 12 processes the incoming Host data from the Host UDW 34 and passes it to the subsequent Data Identification and Separator 32 module. It also reads the response from the Device side and passes it to the Host UDW 34. For data buffering on both the paths, it comprises individual receive and transmit First In First Out storage buffers (henceforth referred to as FIFOs). The receive stream passes the entire set of commands and the unmodified write data to the Data Identification and Separation module 32. The transmit stream receives the Device response from the Device Data Combiner module 26 and passes it to the Host PHY 30 from where it is subsequently passed on to the USB Host 40.

The Device Interface Engine 14 processes the incoming Device data from the Device UDW 36 and passes it to the subsequent Data Identification and Separator 32 module. It also reads the data (commands as well as modified write data) from the Host Data Combiner module 24 and passes it to the Device UDW 36. For data storage on both the paths, it comprises individual receive and transmit FIFOs. The receive stream passes the entire set of commands and the modified read data to the data modification module. The transmit stream receives the Host data from the Host Data Combiner module 24 and passes it to the Device PHY 20 from where it is subsequently passed on to the USB mass storage device 50. The USB mass storage device 50 is used to store Bulk data during USB 2.0 Bulk transfers. Henceforth, any data being written by the USB Host 40 to the USB mass storage device 50 is referred to as Bulk write data while any data being read from the USB mass storage device 50 is referred to as Bulk read data.

The Data Identifier and Separation module 32 further contains a Data Identification sub module and a Separator sub module. This module receives the data from the receive FIFO of the Host Interface or the Device Interface Engines. Any Bulk operation (whether Bulk read or Bulk write) is always initiated by the USB Host 40, by sending the respective commands to the mass storage device 20.The Data Identification sub module identifies these incoming commands from the Host. Based on the identification, it is ascertained whether the data following the command, needs to be encrypted or decrypted (depending on whether it is a data initiated by the Host or the Device respectively). Once the internal logic processes this data, it is bifurcated into two separate paths namely non-Bulk and Bulk path. The non-Bulk path contains the commands which would be passed blindly through the Data Combiner to the recipient. The Bulk path contains the data which needs to be passed through the Custom Logic module for encryption. If the Bulk data is initiated by the Host to be written into the mass storage device, it is passed to the Custom Encode Logic module 16 for data encryption. On the other hand, if the data is being read from the mass storage device, it is passed to the Custom Decode Logic module 22 for recovering the original unmodified data before passing it to the Host side. Before passing it through the Custom Logic module, this Bulk data is packetized into blocks of 512 bytes and stored in an internal Bulk memory buffer.

The Host Data Combiner module 24 sub-module combines the commands coming from the Data Identification and Separation module 32 and modified write data from the Custom Encode Logic module 16 into a single stream of Host data. The combined data is then processed typically into byte data format before passing it to the Device Interface Engine 14.

The Device Data Combiner module 26 combines the command coming from the Data Identification and Separation module 32 and decrypted read data from the Custom Decode Logic module 22 into a single stream of data. This combined data is then processed typically into byte data format before passing it to the Host Interface Engine 12.

This Custom Encode Logic module 16, is typically, any user defined cryptographic implementation used for securing the data content on the USB mass storage device 50. This module modifies the incoming Bulk write data from the Data Identification and Separation module 32. The write data is then encrypted before finally being written into the USB mass storage device 50 through the Host Data Combiner module 24. Similarly the Custom Decode Logic module 22 extracts the original Bulk data from the encrypted read data, during a Bulk read operation. This decoded read data is then passed on to the Device Data Combiner module 26 from where it is subsequently passed on to the USB Host 40. The Decode Logic performs an exactly reverse operation, of the Encode Logic, on the incoming modified data in order to extract the original data from it. FIGURE 3 illustrates a schematic flow diagram exhibiting the FPGA 10 to PHY connectivity. A USB Host 40 or Device communicates with a corresponding ULPI Device wrapper via a respective PHY. On the USB Interface, the information is carried as a string of 0s and Is on differential lines. The ULPI Interface comprises 12 signals to communicate with the FPGA 10, commonly referred to as the link. Each ULPI Device wrapper (UDW) consists of two engines referred to as a receive module and a transmit module. The received information from the USB Host 40 or Device is processed by the receive module and subsequently signaled to the corresponding Interface Engine. The transmit module receives information from a Transmit FIFO and eventually passes it to the intended recipient. At a time an 8 bit ULPI data bus can either transmit data to the link or receive data from the link.

The PHY sends data to the FPGA 10 on assertion of the DIR signal. Only when the DIR signal is de-asserted, the link can initiate data transmission to the PHY. Each data byte is acknowledged by the PHY with the assertion of the NXT signal.

The components involved in the FPGA to PHY connectivity flow are explained herein below with reference to FIGURE 3.

USB PHY

The USB PHY is a Hi-Speed USB Physical Layer Transceiver (PHY). ULPI Interface allows the USB PHY to operate as a Device, Host, or an On-The-Go (OTG) Device. This PHY is designed from the start with a ULPI Interface. This provides the PHY with a low latency transmit and receive time. The simple and efficient ULPI Interface supported by the USB PHY makes it aptly suitable for FPGA 10 interfacing purpose.

Receive Module The receive module of the ULPI Device wrapper module (UDW) receives the information from the USB (Host/Device) through the PHY over the ULPI Interface and bifurcates the electrical level signaling data from the USB packets. The processed information is then passed to the corresponding Interface Engine module wherein it is subsequently written into the corresponding receive FIFO. This stored data is then processed before it is being finally read at the recipient side.

Transmit Module

The transmit module of the ULPI Device wrapper (UDW) module receives the information from the link and transmits it to the PHY over the ULPI Interface. This module retrieves the data from a transmit FIFO and makes it compatible to be transmitted to the USB PHY. The information is transmitted to the PHY on the de-assertion of the direction (DIR) signal. The transmission is commissioned with assertion of the stop (STP) signal indicating the last data bit being sent, in full compliance with the ULPI specifications.

FIGURE 4 illustrates a schematic flow diagram of a Host Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Host side. The Host Interface Engine 12 comprises the Host Protocol Handler, the Host receive FIFO and the Host transmit FIFO. The Host Protocol Handler in turn comprises a receive engine, and a transmit engine. The receive engine receives the data from the Host UDW 34 and finally writes it into the Host receive FIFO. On the other hand, the Tx engine reads off the data from the Host transmit FIFO and finally gives it to the UDW. The UDW in turn transmits it to the Host-PHY. The Host receive FIFO consists of either the command or the unmodified Bulk write data which needs to be encrypted before finally sending to the Device. Similarly the Host transmit FIFO either contains the handshakes from the Device or the decrypted Bulk read data.

The Host Protocol Handler is responsible for handling the USB data traffic on the Host side. It receives the data to be passed on to the USB mass storage device 50 and stores it in the Host receive FIFO. Internal logic within this module ensures full compliance with the ULPI timing specifications. The internal logic within this module keeps the Host engaged in the response activity till the Device response reaches the Host. This prevents the USB bus from slipping into suspend state.

The Host receive FIFO contains the data from the Host to be eventually sent to the Device. It has independent clock domains for write and read operation. The information stored is either the commands or the Bulk write data preceding the encryption stage. The data is written on the Host clock while read off on the Device clock.

The Host transmit FIFO contains the data from the Device to be eventually sent to the Host. It has independent clock domains for write and read operations. The information stored is either the commands or the Bulk read data following the decryption stage. The data is written on the Device clock while read off on the Host clock.

FIGURE 5 illustrates a schematic flow diagram of a Device Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Device side. The Device Interface module comprises the Device Protocol Handler, the Device receive FIFO and the Device transmit FIFO. The Device Protocol Handler in turn comprises a Receive Engine, and a Transmit Engine. The receive engine receives the data from the Device UDW 36 and writes it into the Device receive FIFO. On the other hand, the Tx engine reads the data from the Device transmit FIFO and finally gives it to the Device UDW 36. This UDW in turn transmits it to the Device PHY. The Device receive FIFO consists of either the command or the encrypted read data which needs to be decrypted before finally sending to the Host 40. Similarly the Device transmit FIFO either contains the commands or the encrypted Bulk write data (after passing to the Custom Encode Logic 16 module) to be written to the mass storage device.

The Device Protocol Handler is responsible for handling the USB data traffic on the Device side. It receives the data to be passed on to the USB Host 40 and stores it in the Device receive FIFO. Internal logic within this module ensures full compliance with the ULPI timing specifications.

On similar lines of the Host Interface Engine 12, the Device Interface Engine 14 too comprises separate receive and transmit buffers. The Device receive FIFO is used to buffer the incoming unprocessed data from the USB mass storage device 50 before passing it to the Data Identifier and Separator module for subsequent processing. The Device transmit FIFO on the other hand receives the input from the Host Data Combiner module 24 and subsequently passes it to the USB mass storage device 50 through the Device UDW 36.

The present disclosure thus provides a USB bridge implementation using an FPGA to overcome the drawbacks of the prior art.

TECHNICAL ADVANCEMENTS

The technical advancements offered by the Field Programmable Gate Array (FPGA) based USB bridge of the present disclosure includes the realization of: • a low cost single chip implementation of a USB 2.0 bridge comprising a USB Host and a Device on a Field Programmable Gate Array (FPGA);

• a framework for encrypting data over USB on-the-fly for enhancing security at the hardware level;

• a USB 2.0 Host and Device core and encryption logic implemented in a single FPGA, thereby providing a power efficient and extremely compact solution;

• a USB bridge to capture real time USB data transfer between a USB 2.0 Host and a Device, without any interference in communication and in strict compliance with the USB 2.0 specifications;

• a method for capture and storage of data between a USB 2.0 Host and a Device which could be used for recording purposes; and

• a method for capture of USB data for analysis or display, thereby enabling the system to be used as an emulator or for debugging purposes.

Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps. The numerical values mentioned for the various physical parameters, dimensions or quantities are only approximations and it is envisaged that the values higher/lower than the numerical values assigned to the parameters, dimensions or quantities fall within the scope of the disclosure, unless there is a statement in the specification specific to the contrary.

The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.

Claims

CLAIMS:

1. A Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device,

said USB bridge comprising:

• a Host PHY connected to the USB Host via a bidirectional USB link, said Host PHY adapted to operate in a Device mode;

• a Device PHY connected to the USB mass storage device via a bidirectional USB link, said Device PHY adapted to operate in a Host mode; and

• an FPGA connected to each of said Host PHY and said Device PHY via a bidirectional ULPI link respectively,

said FPGA comprising:

a Host ULPI Device wrapper (UDW) module adapted to communicate with said Host PHY;

a Device ULPI Device wrapper (UDW) module adapted to communicate with said Device PHY;

a Host Interface Engine adapted to transmit and receive data from said Host UDW module;

a Device Interface adapted to transmit and receive data from said Device UDW module; a Data Identification and Separation module adapted to receive data from said Host Interface Engine and said Device Interface Engine;

a Custom Encode Logic module adapted to receive data from said Data Identification and Separation module and further adapted to encrypt said data received from said Host PHY to generate modified write data;

a Custom Decode Logic module adapted to receive data from said Identification and Separation module and further adapted to recover original unmodified data received from said Device PHY to generate decrypted read data;

a Host Data Combiner module adapted to combine commands from said Data Identification and Separation module and said modified write data into a single stream of Host data, said Host Data Combiner module further adapted to process said Host data and transfer the processed Host data to said Device Interface Engine for further transmission to the USB mass storage device; and

a Device Data Combiner module adapted to combine commands from said Data Identification and Separation module and said decrypted read data into a single stream of Device data, said Device Data Combiner module further adapted to process said Device data and transfer the processed Device data to said Host Interface Engine for further transmission to the USB Host.

2. The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1, wherein each of said Host PHY and said Device PHY is a Hi-Speed USB physical layer transceiver.

3. The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1, wherein said ULPI link is adapted to communicate 8 bit data between said FPGA and each of said Host PHY and said Device PHY.

4. The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1 , wherein said initialization module comprises:

• a Device initialization sub module adapted to perform said initialization and handshaking process for the USB mass storage Device, said Device initialization sub module further comprising a Device disconnect sub module adapted to detect ejection of the USB mass storage device;

• a power on reset sub module adapted to selectively generate a reset signal for all modules of said FPGA; and

• a clock module that provides Host and Device clocks to the respective sub modules constituting said FPGA.

5. The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1 , wherein each of said Host UDW and said Device UDW comprise a receive module and a transmit module, said receive module being adapted to eliminate the CRC (cyclic redundancy check) from the data to generate pure data packets, said transmit module being adapted to receive said pure data packets and further adapted to recalculate the CRC for said pure data packets and transmit the checked data packets to the USB mass storage Device via said Device PHY and the USB Host via said Host PHY respectively. The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1 , wherein said Host Interface Engine comprises:

• a Host Protocol Handler comprising a first receive engine and a first transmit engine, said first receive engine adapted to receive data from said Host UDW, said first transmit engine adapted to transmit data to said Host UDW for further transmission to said Host PHY;

• a Host receive FIFO adapted to receive data from said first receive engine; and

• a Host transmit FIFO adapted to send data to said first transmit engine.

The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1, wherein said Device Interface Engine comprises:

• a Device Protocol Handler comprising a second receive engine and a second transmit engine, said second receive engine adapted to receive data from said Device UDW, said second transmit engine adapted to transmit data to said Device UDW for further transmission to said Device PHY;

• a Device receive FIFO adapted to receive data from said second receive engine; and

• a Device transmit FIFO adapted to send data to said second transmit engine.

The Field Programmable Gate Array (FPGA) based USB bridge as claimed in claim 1, wherein said Data Identification and Separation module is adapted to receive data from either a Host receive FIFO or a Device receive FIFO constituting said Host Interface Engine and said Device Interface Engine respectively, said Data Identification module being further adapted to separate said data into non Bulk data for transmission to either of said Host Data Combiner module or said Device Data Combiner module and Bulk data for transmission to either of said Custom Encode Logic module or said Custom Decode Logic module.

9. A method of implementing a USB bridge between a USB Host and a USB mass storage device using a Field Programmable Gate Array (FPGA), said method comprising the following steps:

• connecting a Host PHY to the USB Host via a bidirectional USB link;

• connecting a Device PHY to the USB mass storage device via a bidirectional USB link;

• connecting a Host ULPI Device wrapper (UDW) module to said Host PHY;

• connecting a Device ULPI Device wrapper (UDW) module to said Device PHY;

• receiving data and eliminating CRC (cyclic redundancy check) from said data to generate pure data packets at a receive module of either the Host UDW or the Device UDW;

• recalculating CRC for said pure data packets at a transmit module of either the Host UDW or the Device UDW;

• separating the checked data packets into non Bulk data containing commands and Bulk data including Bulk read data and Bulk write data for Bulk transmission; • encrypting said Bulk data to generate modified write data or decrypting said Bulk data to read data;

• combining said commands and said modified write data to generate a single stream of Host data or combining said commands and said read data to generate a single stream of Device data; and

• processing said Host data and transferring the processed Host data to the USB mass storage device or processing said Device data and transferring the processed Device data to the USB Host.

10. The method of implementing a USB bridge as claimed in claim 9, further comprising the following steps:

• detecting ejection of the USB mass storage device; and

• signaling reset of said bridge.