WO2013101849A1

WO2013101849A1 - Embedded through-silicon-via

Info

Publication number: WO2013101849A1
Application number: PCT/US2012/071681
Authority: WO
Inventors: Choong Kooi Chee
Original assignee: Intel Corporation
Priority date: 2011-12-27
Filing date: 2012-12-26
Publication date: 2013-07-04
Also published as: MY165677A; TWI506745B; TW201342550A

Abstract

Electronic assemblies and their manufacture are described. One embodiment relates to a device including a multilayer substrate comprising a plurality of dielectric layers and metal layers, the multilayer substrate including a first side and a second side. A semiconductor die is embedded in the substrate, the die including a plurality of through-semiconductor-vias extending from a first end to a second end of the die. The through-semiconductor-vias are electrically coupled to electrically conducting pathways defined by the metal layers, including pathways extending from the first end of the die to pads on the first side of the substrate, and pathways extending from the second end of the die to pads on the second side of the substrate. The through-semiconductor-vias in the die have a pitch that is smaller than that of the pads on the first side of the substrate. The through-semiconductor-vias in the die have a pitch that also is smaller than that of the pads on the second side of the substrate.

Description

EMBEDDED THROUGH-SILICON-VIA

BACKGROUND TO THE INVENTION Three dimensional (3D) integrated circuits having through-silicon-via (TSV) interconnection structures have been developed. TSV die structures include generally vertical vias (depending on the manufacturing process the sidewalls defining the via may not be vertical) in the silicon that contain an electrically conductive material therein and are used to make interconnections. The use of through-silicon-vias (TSVs) extending through the silicon may result in shortened interconnect length when compared with other routing methods, improved electrical performance, and reduced power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale.

Figure 1 illustrates a view of a TSV die embedded in a substrate, in accordance with certain embodiments.

Figure 2 illustrates a view during a coreiess substrate formation process for forming substrates containing an embedded TSV die, in accordance with certain embodiments.

Figure 3 illustrates a view of a TSV die embedded in a substrate, including a blown- up portion illustrating an interface between the die and a dielectric layer of the substrate that the die is positioned within, in accordance with certain embodiments. Figure 4 illustrates a view of a TSV die positioned on a core and embedded in a substrate, In accordance with certain embodiments.

Figure 5 illustrates a view of a TSV die embedded in a core in a substrate, In accordance with certain embodiments. Figure 6 illustrates a view of a first TSV die and a second TSV die that are each embedded within a substrate, in accordance with certain embodiments.

Figure 7 illustrates a flowchart of operations for forming electronic assemblies including an embedded TSV die, in accordance with certain embodiments.

Figure 8 Illustrates an example of an assembly including a substrate having an embedded TSV die and memory positioned on the substrate, In accordance with certain embodiments.

Figure 9 illustrates an electronic system arrangement in which embodiments may find application.

DETAILED DESCRIPTION OF THE INVENTION

Reference below will be made to the drawings wherein like structures may be provided with like reference designations. In order to show the structures of various embodiments most clearly, the drawings included herein include diagrammatic representations of electronic devices. Thus, the actual appearance of the fabricated structures may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may show only the structures necessary to understand the illustrated embodiments. Additional structures known in the art have not been included to maintain the clarity of the drawings. Certain embodiments relate to an assembly structure including a die including through-siiicon-vias (also referred to herein as a TSV die) that is embedded in a substrate and electrical pathways extending from the vias to pads on a surface of the substrate having a pitch that Is greater than that of the through-eilicon-vias in the die.

Figure 1 illustrates a schematic view of interconnection details of an assembly including a substrate 2 Including an embedded die 4 having through-siiicon-vias (TSVs) 6, in accordance with certain embodiments. The substrate 2 includes a plurality of dielectric layers 8, 10, 12, 14, 16. A different number of layers (more or less) is also possible. As illustrated in Figure 1, the substrate 2 includes a first surface 18 on the top dielectric layer 8 and a second surface 20 on the bottom dielectric layer 16. In the embodiment illustrated in Figure 1, the TSV die 4 is located within the central dielectric layer 12 in the stack. In other embodiments, the TSV die may be located at a different vertical position In the layer stack than that illustrated in Figure 1. T e TSVs 6 include an electrically conductive material therein. Any suitable electrically conductive material may be used, including, for example, a metal. As used herein, the term metal includes pure metals and alloys. The substrate 2 also includes electrically conductive paths extending from the TSVs 6 to bonding pads 22 on the first surface 18 and to bonding pads 24 on the second surface 20. The electrically conductive paths may travel through vias and along wiring layers within the dielectric layers. Signals may travel back and forth through the assembly, including, for example, from bonding pads 24 through the vias 26 and wiring layer 28 in dielectric layer 16, through the vias 30 and wiring layer 32 in dielectric layer 14, through the TSVs 6 in the die 4 in the dielectric layer 12, through the wiring layer 34 and vias 36 In the dielectric layer 10, and through the wiring layer 38 and vias 40 in dielectric layer 8, in order to reach the bonding pads 22.

As illustrated in Figure 1, the TSVs in the silicon die 4 have a pitch (spacing therebetween) that is smaller than the pitch of the bonding pads 22 on the first surface 18 and smaller than the pitch of the bonding pads 24 on the second surface 20. Such a structure enables the embedded die 4 with TSVs 6 to be more easily connected to other structures such as the component 48 coupled to the substrate 2 through bumps 42. In certain embodiments, the component 48 may be selected from the group consisting of a processor and memory. The substrate 2 as ii/ustrated Jn Figure 1 is also coupled to structure 50 through bumps 44. In certain embodiments, the structure 50 may be a motherboard. The pitch of the pads 22 on the first surface 18 of the substrate 2 need not be the same as the pitch of the pads 24 on the second surface 20 of the substrate 2. As illustrated in Figure 1 , the pitch of the pads 22 on the first surface 18 of the substrate 2 is smaller than that of the pads 24 on the second surface 20.

Certain embodiments relate to methods for manufacturing a substrate including an embedded TSV die. Embodiments may relate to the formation of both substrates having a core and coreless substrates. Such substrates may be manufactured using a variety of suitable methods. A TSV die, either alone, or one that is positioned within a dielectric layer, may In certain embodiments act as an initial layer on which additional layers are formed. In other embodiments, an underlying layer may act as an Initial layer and the TSV die positioned thereon.

Figure 2 Illustrates an operation in a coreless substrate processing embodiment in which a temporary core material 52 comprising, for example, a metal such as Cu, Is used. In the coreless substrate manufacture embodiment illustrated In Figure 2, dielectric and metal layers may be built up on opposite sides of the temporary core 52 and the temporary core is later removed to yield two substrate structures. As Illustrated In Figure 2, a substrate structure having the Identical layer structures as the substrate 2 in Figure 1 may be formed on opposite sides of the temporary core 52. Upon removal of the temporary core 52, two substrate structures each including an embedded TSV die 4 will result.

Figure 3 Illustrates a view of the substrate 2 of Figure 1, Including the dielectric layer 12 in which the TSV die 4 Including the TSVs 6 is positioned. The TSV die 4 Is positioned within a central opening In the dielectric layer 12. In certain embodiments, the combined dielectric layer 12 and TSV die 4 may be used as an initial layer on which other layers are formed in order to fabricate the multilayer substrate. The blown-up portion of Figure 3 illustrates the interface between the dielectric layer 12 and the TSV die 4, and shows the presence of an adhesive 35 positioned therebetween. In certain embodiments, depending on features such as the materials used and the method of forming the dielectric layer 12, the adhesive 35 may not be necessary in order to form an adequate bond between the dielectric layer 12 and the TSV die 4. The TSV die 4 with Its periphery surrounded by the dielectric layer 12 as illustrated in Figure 3 may be formed using any suitable method (including, but not limited to, masking, etching, and deposition processes). For example, a dielectric layer may be formed, then an opening formed in the dielectric layer, and the TSV die positioned within the opening. Alternatively, the TSV die may be provided, then a dielectric layer deposited around the die. Figures 1-3 Illustrate features Including a coreless substrate. Figure 4 Illustrates an embodiment including a substrate 102 having a core layer 127 on which other layers are formed. The core layer 127 may be formed from any suitable material, for example, a laminated multilayer structure including woven glass layers Impregnated with an epoxy resin material. The core layer 127 may include a plurality of electrical paths 129 extending therethrough. A TSV die 104 with TSVs 106 may be positioned on the core layer 127, with the electrically conductive material in the TSVs 106 being electrically coupled to the electrical paths 129 in the core layer 127. The TSV die 104 is positioned within dielectric layer 112. Dielectric layer 110 Is formed on the TSV die 104 and on the dielectric layer 112, and dielectric layer 108 is formed on dielectric layer 110. Dielectric layer 114 is positioned on the opposite side of the core layer 127 from the dielectric layer 112, and dielectric layer 116 is formed on the dielectric layer 114. As illustrated in Figure 4, the substrate Includes a first surface 118 on the top dielectric layer 108, including bonding pads 122 formed thereon, and a second surface 120 on the bottom dielectric layer 116, including bonding pads 124 formed thereon. Signals may travel back and forth through the assembly, Including, for example, from the bonding pads 124 through the vias 126 and the wiring layer 128 in dielectric layer 116, through the vias 130 and wiring layer 132 in dielectric layer 114, through the electrically conductive paths 129 in the core 127, through the TSVs 106 in the die 104 in the dielectric layer 112, through the metal wiring layer 134 and the vias 136 in the dielectric layer 110, and through the wiring layer 138 and vias 140 in dielectric layer 108 to reach the bonding pads 122.

Figure 5 illustrates an embodiment including a substrate having a core 227, in which the TSV die 204 is positioned in the core 227 instead of being positioned in a row next to the core as illustrated, for example, in Figure 4. The core 227 and TSV die 204 may be formed to have the same thickness, so that the TSV die 204 may be fit within an opening in the core 227, as Illustrated In Figure 5. The substrate In Figure 5 differs from the substrate Illustrated In Figure 1 because the layer 227 containing the TSV die 204 is a core layer that is different than the dielectric layers 208, 210, 214, and 216 of Figure 5, whereas the layer 12 containing the TSV die in Figure 1 !s a dielectric layer similar to or the same as dielectric layers 8, 10, 14, and 16. Signals may travel through the substrate, for example, from vlas 226 through wiring layer 228 in dielectric layer 216, through vlas 230 and wiring layer 232 In wiring layer 214, through TSVs 206 in core layer 227, through wiring layer 234 and vfas 236 in dielectric layer 210, through wiring layer 238 and vias 240 to pad 220.

Embodiments may also include more than one die embedded within a substrate. For example, Figure 6 illustrates an embodiment Including dielectric layers 308, 310, 312, 314, and 316, with more than one TSV die 304 having TSVs 306 positioned within the dielectric layer 314. Alternatively, each of the TSV die structures 304 could be positioned in a different dielectric layer of the substrate. While two TSV die structures 304 are illustrated in Figure 6, more could also be positioned within a substrate.

Embodiments may provide one or more advantages relating to size and manufacturing ease. First, by embedding the TSV die structure in the substrate, the thickness of the entire assembly may be decreased. Second, by embedding the TSV die structure in the substrate, the contacts to a device may be led out In the layers extending from embedded TSV die to the substrate upper and lower surfaces, so that the bonding pads at the surface have a pitch that is greater than the contacts at the surface of the embedded TSV die. In certain embodiments, the top end of the TSV die may have a contact pitch of 25 to 50 microns between contacts. To attach another device (for example, a memory device) to the tight contact pitch TSV die, a complex and costly attachment process known as thermal compression bonding (TCB) may be used. However, by embedding the TSV die in the substrate, layers between the TSV die and the surface of the substrate may be used to fan out the pitch of the contacts to an increased value that enables a less complex and less expensive attachment process to be used to attach a die or package to the substrate. Figure 7 illustrates a process flow arrangement in accordance with certain embodiments for forming an embedded TSV die substrate and assembly including the substrate. Box 401 is providing a TSV die. Box 403 is building up layers of dielectric and metal on the TSV die and fanning out the pitch of the TSVs so that the contacts at the surface of the substrate have a less dense pitch for easier attachment to other devices. Box 405 is coupling solder balls to the substrate for subsequent attachment to a board. Box 407 is attaching a component (including, but not limited to, a die structure such as a CPU or memory package) to the top surface of the substrate. Box 409 is attaching the substrate (including the component attached thereto) to a board using a solder ball connection.

Figure 8 illustrates an embodiment including a memory device in accordance with certain embodiments, in which a memory package Including multiple memory chips is coupled to an embedded TSV die substrate. The assembly includes a plurality of memory die structures 548 coupled to multilayer substrate 502 through solder bumps 542. Underfill 563 may also be present between the die structures 548 and between the lower die structure 548 and the substrate 502. The multilayer substrate 502 includes an embedded TSV die 504. The substrate 502 Is In turn coupled to board 550 through solder bumps 544.

It should be appreciated that many changes may be made within the scope of the embodiments described herein. For example, while the TSV die Is described as a silicon die structure, viae may also extend through other materials, for example, other semiconductors including, but not limited to, gallium arsenide. Such vias extending through semiconductors may be referred to as through-semlconductor- vlas. A through-silicon-via is an example of a through-semlconductor-via extending through silicon. As a result, embodiments as described herein may be applicable to die structures that are not formed from silicon. The term die as used herein refers to a workplace that is transformed by various process operations Into a desired electronic device. A die is usually slngulated from a wafer, and wafers may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting materials.

Assemblies including structures formed as described in embodiments above may find application in a variety of electronic components. Figure 9 schematically illustrates one example of an electronic system environment In which aspects of described embodiments may be embodied. Other embodiments need not include all of the features specified in Figure 9, and may include alternative features not specified In Figure 9. The system 600 of Figure 9 may Include at least one central processing unit (CPU) 683 (also known as a microprocessor} in a package substrate 685. in certain embodiments, the CPU 683 (referenced by a dotted line to indicate it is embedded in the substrate 685) may be an embedded TSV die such as described in embodiments above, which is coupled to a printed circuit board 887 (for example, a motherboard). Memory 689a may be positioned on the substrate 685 to form an assembly such as described above and Illustrated, for example, in Figure 6. A variety of other system components may also Include structures formed in accordance with embodiments such as described above. By locating various components (such as memory 689a on the substrate 685, the size of the entire system may be decreased.

The system 600 may further include additional memory 689b and one or more controllers 691a, 691b ... 691 n, which are also disposed on the motherboard 687. The motherboard 687 may be a single layer or multi-layered board which has a plurality of conductive lines that provide communication between the circuits in the package substrate 685 and other components mounted to the board 687. Alternatively, one or more of the various components may be disposed on other cards such as daughter cards or expansion cards. The components may also be seated in sockets or may be connected directly to a printed circuit board or all integrated in the same package. A display 695 may also be included.

Any suitable operating system and various applications execute on the CPU 683 and reside in the memory 689a, 689b. The content residing in memory 689a, 689b may be cached in accordance with known caching techniques. Programs and data in memory 689a, 689b may be swapped Into storage 693 as part of memory management operations. The system 600 may comprise any suitable computing device, Including, but not limited to, a mainframe, server, personal computer, workstation, laptop, handheld computer, netbook, tablet, book reader, handheld gaming device, handheld entertainment device (for example, MP3 (moving picture experts group layer-3 audio) player), PDA (personal digital assistant) telephony device (wireless or wired), network appliance, virtualization device, storage controller, network controller, router, etc. The controllers 691a, 691b ... 691 n may Include one or more of a system controller, peripheral controller, memory controller, hub controller, I/O (input/output) bus controller, video controller, network controller, storage controller, communications controller, etc. For example, a storage controller can control the reading of data from and the writing of data to the storage 693 in accordance with a storage protocol layer. The storage protocol of the layer may be any of a number of known storage protocols. Data being written to or read from the storage 693 may be cached In accordance with known caching techniques. A network controller can include one or more protocol layers to send and receive network packets to and from remote devices over a network 697. The network 697 may comprise a Local Area Network (LAN), the Internet, a Wide Area Network (WAN), Storage Area Network (SAN), etc. Embodiments may be configured to transmit and receive data over a wireless network or connection. In certain embodiments, the network controller and various protocol layers may employ the Ethernet protocol over unshielded twisted pair cable, token ring protocol, Fibre Channel protocol, etc., or any other suitable network communication protocol.

Terms such as "first", "second", and the like as used herein to not necessarily denote any particular order, quantity, or importance, but are used to distinguish one element from another. Terms such as "top", bottom", "upper", "lower", and the like are used for descriptive purposes only and are not to be construed as limiting. Embodiments may be manufactured, used, and contained in a variety of positions and orientations. In the foregoing Detailed Description, various features are grouped together for the purpose of streamlining the disclosure. This method of disclosure Is not to be Interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited In each claim. Rather, as the following claims reflect, inventive subject matter may lie in tess than ail features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment. While certain exemplary embodiments have been described above and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that embodiments are not restricted to the specific constructions and arrangements shown and described since modifications may occur to those having ordinary skill in the art

Claims

CLAIMS What is claimed:

1. A device comprising: a multilayer substrate comprising a plurality of dielectric layers and metal layers, the multilayer substrate including a first side and a second side; a semiconductor die embedded in the substrate, the die including a plurality of through-semiconductor-vias extending from a first end to a second end of the die; the through-semiconductor-vias being electrically coupled to electrically conducting pathways defined by the metal layers, including pathways extending from the first end of the die to pads on the first side of the substrate, and pathways extending from the second end of the die to pads on the second side of the substrate; wherein the through-semiconductor-vias in the die have a pitch that is smaller than that of the pads on the first side of the substrate; and wherein the through-semiconductor-vias in the die have a pitch that is smaller than that of the pads on the second side of the substrate.

2. The device of claim 1 , wherein the die is positioned so that dielectric and metai layers are positioned between the die and the first side of the substrate.

3. The device of claim 1 , wherein the substrate comprises a coreiess substrate.

4. The device of claim 1 , wherein the die is positioned within a dielectric layer.

5. The device of claim 1 , wherein the die includes an outer edge surrounded by a dielectric layer.

6. The device of claim 5, further comprising an adhesive positioned between the outer edge of the die and the dielectric layer.

7. The device of claim 1, wherein the substrate includes a core, the core comprising a composition different than that of the dielectric and metal layers.

8. The device of claim 1, further comprising an additional die embedded in the substrate, the additional die including a plurality of through-semiconductor vias.

9. The device of claim 1 , wherein the pitch of the pads on the second surface of the substrate is greater than that of the pads on the first surface of the substrate.

10. The device of claim 1 , further comprising: an additional semiconductor die embedded in the substrate, the additional die including a plurality of through-semlconductor-vlas extending from a first end to a second end of the additional die; the through-semlconductor-vlas of the additional die being electrically coupled to additional electrically conducting pathways defined by the metal layers, including pathways extending from the first end of the additional die to additional pads on the first side of the substrate, and pathways extending from the second end of the additional die to additional pads on the second side of the substrate; wherein the through-semlconductor-vias In the additional die have a pitch that is smaller than that of the additional pads on the first side of the substrate; and wherein the through-semiconductor-vias in the additional semiconductor die have a pitch that is smaller than that of the additional pads on the second side of the substrate.

11. The device of claim 1 , wherein the semiconductor die comprises silicon.

12. A device comprising: a multilayer substrate comprising a plurality of dielectric layers and metal layers, the multilayer substrate Including a first side and a second side; a semiconductor die embedded in the substrate, the die including a plurality of through-semiconductor-vlas extending from a first end to a second end of the die; the through-semiconductor-vlas being electrically coupled to electrically conducting pathways defined by the metal layers, including pathways extending from the first end of the semiconductor die to pads on the first side of the substrate, and pathways extending from the second end of the semiconductor dfe to pads on the second side of the substrate; wherein the through-semiconductor-vlas in the semiconductor die have a pitch that is smaller than that of the pads on the first side of the substrate; a component coupled to the pads on the first side of the substrate, the component including a semiconductor die; and a board coupled to the pads on the second side of the substrate; wherein the substrate is positioned between the component and the board.

13. The electronic device of claim 12, wherein the component comprises a memory structure.

14. The electronic device of claim 12, wherein the component comprises a plurality of semiconductor die structures.

15. The device of claim 12, wherein the semiconductor die comprises silicon.

16. A method for manufacturing a device, comprising: embedding a semiconductor dfe including through-semlconductor-vias within a multilayer substrate, the through-semiconductor vias having a pitch; and forming wiring paths extending from the through-semlconductor-vlas to pads on first and second surfaces of the substrate, wherein the pads on the first surface of the substrate have a pitch that is formed to be greater than that of the through- semiconductor-vias, and wherein the pads on the second surface of the substrate have a pitch that is formed to be greater than that of the through-semiconductor- vias.

17. The method of claim 16, wherein the embedding the semiconductor die within the multilayer substrate includes positioning a dielectric layer to extend around a perimeter of the die.

18. The method of claim 17, further comprising positioning an adhesive between an outer edge of the semiconductor die and the dielectric layer.

19. The method of claim 16, further comprising coupling a component to the pads on the first surface of the multilayer substrate.

20. The method of claim 19, wherein the component comprises a memory component.