WO2013065895A1 - Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same - Google Patents

Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same Download PDF

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Publication number
WO2013065895A1
WO2013065895A1 PCT/KR2011/009049 KR2011009049W WO2013065895A1 WO 2013065895 A1 WO2013065895 A1 WO 2013065895A1 KR 2011009049 W KR2011009049 W KR 2011009049W WO 2013065895 A1 WO2013065895 A1 WO 2013065895A1
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Prior art keywords
lead frame
package
semiconductor chip
semiconductor
lead
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PCT/KR2011/009049
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French (fr)
Korean (ko)
Inventor
헤안 소흐세이
지엔 시에우유엔
권용태
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주식회사 네패스
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Publication of WO2013065895A1 publication Critical patent/WO2013065895A1/en

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Definitions

  • the present invention relates to a method for manufacturing a fan-out semiconductor package using a leadframe, and to a semiconductor package and a package-on-package according to the present invention, and more particularly to a circuit pattern or via for achieving fan-out of the leadframe. via)
  • Semiconductor devices have been continuously reduced in size by reducing line widths and simplifying the design of circuits included therein.
  • continuous research and development has been conducted to include more functional electronic circuits in one semiconductor device. Accordingly, the size of the semiconductor chip has been gradually reduced, and the size and spacing of the bond pad, which is an external connection terminal included in the semiconductor chip, have evolved to a more compact fine-pitch type.
  • a fan-out structure means that a redistribution pattern connected to a bond pad is extended and relocated wider than the size of the semiconductor chip.
  • a fan-in structure is a semiconductor chip. The bond pad is relocated within the size limit of.
  • Korean Patent Publication No. 2011-0077213 discloses a semiconductor package of a fan-out type. However, this technique has a disadvantage in that there is a limit in simplifying the manufacturing process.
  • the present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost.
  • Another object of the present invention is to provide a fan-out semiconductor package manufacturing method using a lead frame, which can further improve product performance.
  • the present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. It is another object of the present invention to provide a fan-out semiconductor package using a lead frame that can further improve product performance.
  • the present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost.
  • Another aim is to provide a package-on-package (POP) using leadframe to further improve product performance.
  • POP package-on-package
  • a lead frame in a strip state having an opening in which a semiconductor chip can be seated at a center thereof and having a plurality of signal leads in a periphery thereof, and attaching the lead frame to a first base and Mounting a semiconductor chip on the first base through an opening of the semiconductor chip; sealing the semiconductor chip and the lead frame on the first base with an encapsulant and removing the first base; Forming an insulating film thereon and patterning the lead of the encapsulant and the bond pads of the semiconductor chip; forming a redistribution metal pattern connecting the exposed signal leads and the bond pads; Forming a redistribution metal pad exposing a portion of the redistribution metal pattern, and conducting conductive lead to the exposed redistribution metal pad
  • a method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. .
  • the lead frame of the strip state is provided with an opening in which the semiconductor chip can be seated in the center and a plurality of signal leads in the periphery
  • the projection lead is provided with a protrusion by half etching Preparing a lead, attaching the lead frame to the first base, mounting the semiconductor chip on the first base through the opening of the lead frame, and only the protrusion of the lead frame and the bottom surface of the semiconductor chip.
  • exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside by performing a molding process of exposing the substrate, removing the first base, and forming an insulating layer pattern on the entire opposite surface on which the protrusion is formed.
  • a method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. do.
  • the present invention provides a step of preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in the center and a signal lead in the form of a protrusion by half etching; Attaching the lead frame to a first base, mounting a semiconductor chip on the first base through an opening of the lead frame, forming an encapsulant that completely seals the semiconductor chip and the lead frame; Polishing the half-etched portion of the encapsulant and the leadframe to separate and expose the signal leads, and to remove the first base; and to form an insulating film pattern on the entire surface of the resultant in which the first base is removed.
  • Exposing the signal leads and bond pads of the semiconductor chip Forming a lower metal pattern connecting the pads, forming an insulating layer pattern on the entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating layer pattern; And attaching a conductive connection terminal on the lower metal pad, and performing a singulation process of separating a unit semiconductor package from the leadframe strip and separating individual signal lines.
  • a method of manufacturing an out-of- semiconductor package is provided.
  • the present invention a semiconductor chip, an encapsulant surrounding the bottom and the outer surface of the semiconductor chip, a plurality of signal leads of a lead frame material located inside the encapsulant, and A lead frame including a redistribution metal pattern connecting a bond pad and a plurality of signal leads of the lead frame material, a redistribution metal pad connected to the redistribution metal pattern, and a conductive connection terminal attached to the redistribution metal pad It provides a fan-out semiconductor package using.
  • the present invention the encapsulation material surrounding the semiconductor chip, the outer edge of the semiconductor chip, having the same height as the semiconductor chip, and located inside the encapsulation material in the vertical direction
  • a plurality of signal leads made of a lead frame material having a penetrating shape, a redistribution metal pattern connecting the bond pads of the semiconductor chip and the signal leads, a redistribution metal pad connected to the redistribution metal pattern, and the redistribution metal
  • the present invention a semiconductor chip, encapsulating the outer edge of the semiconductor chip, the encapsulant having the same height as the semiconductor chip, included in the encapsulant and penetrating the encapsulant in the vertical direction
  • a first semiconductor package having a conductive connection terminal, a sealing material mounted on the first semiconductor package through a conductive connection terminal, surrounding the semiconductor chip and the outer edge of the semiconductor chip, and having the same height as the semiconductor chip, the encapsulation member
  • a second semiconductor package including a redistribution metal pattern connecting the signal lead, a redistribution
  • the signal lead of the leadframe can simplify a complicated circuit design or be used as a vertical connection terminal.
  • This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
  • FIGS. 2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention.
  • FIGS. 4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
  • FIG. 10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
  • 11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention.
  • 13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
  • 19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
  • 20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention.
  • 22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
  • 28 and 29 are cross-sectional views illustrating modified examples of FIGS. 22 and 23.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
  • a lead frame as shown in FIGS. 2 and 3, in which an opening in which a semiconductor chip is mounted is prepared (S100).
  • the leadframe may be an etched leadframe or a stamped leadframe.
  • the present invention is not limited thereto, and a general conductive plate (eg, a metal plate) having a conductive structure as the lead frame may be applied without limitation, and a method of manufacturing the lead frame may be variously selected.
  • the lead frame is attached on the first base (S102).
  • the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 4 (S104).
  • a molding process is performed to form an encapsulant that seals the lead frame and the semiconductor chip on the first base as shown in FIG. 5 (S106), and illustrates a first base used to form an encapsulant.
  • the resultant from which the first base has been removed is inverted and a second base (118 of FIG. 7) is optionally attached to the lower part of the resultant if necessary.
  • an insulating film is formed and patterned on the resultant to form an insulating film pattern to expose the bond pad of the semiconductor chip and the signal lead of the lead frame to the outside (S110).
  • the redistribution metal pattern is formed to connect the bond pad and the signal lead as shown in FIG. 8 (S112).
  • the insulating layer pattern is formed again to expose the redistribution metal pad exposing a part of the redistribution metal pattern (S114). Thereafter, a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 8 (S116).
  • the conductive connection terminal may be solder balls or solder bumps.
  • a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed as shown in FIG. 9 (S118) to manufacture a fan-out semiconductor package using the lead frame according to the first embodiment of the present invention.
  • S118 a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed as shown in FIG. 9 (S118) to manufacture a fan-out semiconductor package using the lead frame according to the first embodiment of the present invention.
  • C1 of FIG. 2 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.
  • FIG. 2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention.
  • Figure 3 indicates the cut surface of 3-3 'of FIG.
  • the lead frame 100 used in the first embodiment of the present invention is preferably in the form of a strip in which at least two or more lead frames are arranged in a long band shape as shown in FIG. 2.
  • the strip frame lead frame 100 may have a strip shape in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.
  • the lead frame 100 has a dam line 106 for supporting the respective signal leads 102 on the outside thereof, and a plurality of signal leads 102 connected to the dam line 106 are formed. have. Meanwhile, the shape of the signal lead 102 shown in FIG. 2 is an example for describing the present invention and may be modified in various shapes for effective connection with the semiconductor chip.
  • the lead frame 100 is characterized in that the opening 104, which is a space in which the semiconductor chip can be mounted inside the signal lead 102, is provided.
  • a typical lead frame has a chip mounting portion formed in the center thereof, and thus there is no opening.
  • the lead frame 100 according to the present invention is characterized by an opening having an empty place.
  • This structure is a semiconductor package having a fan-out structure. It can be confirmed through the subsequent process that it is useful in the process of making.
  • FIGS. 4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
  • the lead frame 100 of FIGS. 2 and 3 is attached onto the first base 112 by using an adhesive material.
  • the first base 112 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used.
  • the semiconductor chip 108 is mounted on the first base 112 using an adhesive material through the opening of the lead frame (104 in FIG. 3).
  • the semiconductor chip 108 is preferably mounted so that the active region A in which the circuit portion is formed is directed downward, and the bottom surface B in which the circuit portion is not formed is mounted upward. Therefore, the bond pad 110 provided in the active region A in which the circuit unit is formed is in contact with the first base 112.
  • a molding process is performed on the resultant product on which the semiconductor chip 108 is mounted.
  • the encapsulant 114 is sealed to sufficiently cover the semiconductor chip 108 and the signal lead 102 of the lead frame.
  • the encapsulant 114 may be a high molecular compound such as an epoxy mold compound.
  • the first base 112 used for fixing the semiconductor chip 108 and the signal lead 102 is removed and removed to form the panel 116.
  • the bond pad 110 and the signal lead 102 of the semiconductor chip 108 are exposed to the position where the first base 112 is removed from the panel 116.
  • the second base 118 is selectively attached to the direction in which the bottom surface of the semiconductor chip 108 is positioned by inverting the result of removing the first base, as shown in FIG. 7.
  • the second base 118 may also be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used.
  • an insulating film 124 is formed on the entire surface of the exposed bond pad 110 and the signal lead 102, and then patterned to form the bond pad 110 and the signal lead 102. Expose to the outside.
  • a redistribution metal pattern 122 connecting the bond pad 110 and the signal lead 102 is formed on the exposed insulating pad 110 and the insulating film 124 having the signal lead 102.
  • the redistribution metal pattern 122 extends the array of bond pads 110 formed in the semiconductor chip 108 together with the signal leads 102 to the signal leads 102 formed outside the semiconductor chip 108. It is a means for implementing the out semiconductor package.
  • an insulating film 124 is formed on the resultant product on which the redistribution metal pattern 122 is formed and patterned to form a redistribution metal pad exposing a part of the redistribution metal pattern 122.
  • the redistribution metal pad may be formed on the metal layer pattern of the single layer structure connected to the bond pad as shown in FIG. 8, or may be formed on the metal layer pattern formed on the two layer structure as illustrated in FIG. 9.
  • a conductive connection terminal 126 for example, a solder ball or a solder bump is attached to the exposed redistribution metal pad.
  • each leadframe is separated along the cutout 128 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the leadframe strip.
  • the singulation process removes all the outer portions including the damper line (106 in FIG. 2) of the lead frame and leaves only the signal leads 102 separated from each other as shown in C1 of FIG. 2.
  • This signal lead (102 in FIG. 2) functions to expand the circuit wiring planarly or vertically in the semiconductor package of the fan-out structure, thereby reducing the number of layers of the redistribution metal pattern and simplifying the design of the circuit wiring. It can be a means.
  • the singulation process may be performed using a punch instead of cutting using the blade, or may be performed using a laser (LASER).
  • a fan-out semiconductor package using a lead frame includes a semiconductor chip (108 in FIG. 7), an encapsulant (114 in FIG. 8) surrounding the underside and the outside of the semiconductor chip, and the semiconductor.
  • the signal lead (102 in FIG. 7) of the lead frame material is disposed horizontally or vertically in the encapsulant around the semiconductor chip, thereby minimizing the number of layers forming the redistribution metal pattern, and a complicated circuit. It simplifies the design and improves the electrical performance of the semiconductor package.
  • the present invention is not limited thereto, and three or more semiconductor chips 108 may be attached thereto. At this time, a matrix arrangement of the semiconductor chips 108 is possible in the horizontal-vertical direction.
  • FIG. 10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
  • a lead frame as shown in FIGS. 11 and 12 having an opening on which a semiconductor chip is mounted is prepared (S200).
  • the lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed.
  • the lead frame is attached on the first base (S202).
  • the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 13 (S204).
  • a molding process is performed to form an encapsulant sealing the lead frame and the semiconductor chip on the first base (S206), and the protrusion of the lead frame is polished with a polishing stopper.
  • the protrusion of the signal lead is exposed to the outside as shown in FIG.
  • An upper metal pad for example, a vertically connected metal pad is formed on the exposed signal of the lead frame as shown in FIG. 15 (S210).
  • the first base used for forming the encapsulant is removed (S212).
  • an insulating film pattern is formed on the entire opposite surface on which the protrusion is formed, thereby exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S214).
  • the signal lead of the lead frame and the bond pad of the semiconductor chip may be connected to each other using a lower metal pattern, for example, a redistribution metal pattern, and an insulating layer pattern may be formed on the entire surface of the resultant product on which the lower metal pattern is formed, and then connected to the lower metal pattern.
  • a lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 16 (S218).
  • a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 16 (S220).
  • the conductive connection terminal may be solder balls or solder bumps.
  • a singulation process is performed to separate the unit semiconductor package from the lead frame in a strip state (S222).
  • two semiconductor packages are vertically mounted using conductive connection terminals and an upper metal pad.
  • POP package on package
  • C2 of FIG. 11 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.
  • FIG. 11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention.
  • FIG. 12 refers to the cut plane of 12-12 'of FIG.
  • a damper line 206 for supporting each signal lead 202 is formed at an outer side thereof.
  • a plurality of signal leads 202 connected to the damper line 206 are configured.
  • the signal lead 202 includes a half-etched portion (203 in FIG. 12) and a protrusion (201 in FIG. 12) that is protruded because it is not half-etched by etching only a part of the lead frame.
  • the shape of the signal lead 202 shown in FIG. 11 is an example for describing the present invention, and may be modified in various shapes for connection with a semiconductor chip.
  • the lead frame 200 is characterized in that the opening 204 is provided, which is a space in which the semiconductor chip can be mounted inside the signal lead 202.
  • the structure of the opening 204 may be usefully applied in the process of making a fan-out semiconductor package through a subsequent process.
  • the strip frame leadframe 200 may be a strip in which a plurality of unit leadframes for forming one semiconductor package are arranged in a matrix form.
  • 13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
  • the leadframe 200 illustrated in FIGS. 11 and 12 is attached onto the first base 212 using an adhesive material.
  • the lead frame 200 is preferably attached so that the protrusion (201 of FIG. 12) is upward in the signal lead 202 of the lead frame.
  • the first base 212 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used.
  • the semiconductor chip 208 is mounted on the first base 212 using an adhesive material through the opening of the lead frame (204 of FIG. 12).
  • the semiconductor chip 208 is preferably mounted so that the active region in which the circuit portion is formed faces downward, and is mounted so that the bottom surface where the circuit portion is not formed faces upward. Therefore, the bond pad 210 formed in the active region where the circuit portion is formed is in contact with the first base 212.
  • the molding process is performed on the resultant product on which the semiconductor chip 208 is mounted.
  • the encapsulant 213 is used to completely seal the semiconductor chip 208 and the signal lead 202 of the lead frame as shown in FIG. 13.
  • the encapsulant 213 may be made of a polymer compound such as an epoxy mold compound.
  • the protrusion 201 of the lead frame is polished to an upper portion of the encapsulant 213 by using a polishing stopper to expose the protrusion 201 of the signal lead to the surface of the encapsulant 213. Be sure to
  • the insulating film 214 is coated as shown in FIG. 15, and then patterned to expose the protrusion 201 of the signal lead, and then a metal film is formed on the insulating film 214 in a blanket manner. Patterning to form the upper metal pad 216 is electrically connected to the protrusion 201 of the signal lead.
  • the upper metal pad 216 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to create a package on package (POP).
  • POP package on package
  • the first base 212 used for fixing the semiconductor chip 208 and the signal lead 202 is removed and removed.
  • a single or multiple layers of upper metal patterns may be further formed.
  • an insulating film 218 is formed on the entire surface of the bond pad 210 and the signal lead 202 exposed to the surface from which the first base 212 is removed, and then patterned to form the insulating pad 210. And signal lead 202 are exposed to the outside.
  • the lower metal pattern 220 connecting the bond pad 210 and the signal lead 202 to the insulating layer 218 including the exposed bond pad 210 and the signal lead 202 may be formed.
  • the lower metal pattern 220 is formed of a single layer, but the present invention is not limited thereto, and may be formed of a plurality of layers.
  • the redistribution metal pattern 220 extends the arrangement of the bond pads 210 formed on the semiconductor chip to the signal lead 202 formed on the outside of the semiconductor chip 208, thereby becoming a main means for making a fan-out semiconductor package.
  • an insulating film 218 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 220 is formed, and a lower metal pad 222 connected to the lower metal pattern 220 and exposed to the outside by the insulating film 218 pattern is formed. do.
  • the insulating layer 218 may be a thin film having a multilayer structure made of the same material or different materials.
  • a conductive connection terminal 226, for example, a solder ball or a solder bump is attached to the lower metal pad 222. If the conductive connection terminal 226 is solder ball or solder bump, an under bump metal (UBM) may be further formed between the conductive connection terminal 226 and the lower metal pad 222. In addition, UBM may be further formed on the upper metal pad 216.
  • UBM under bump metal
  • each lead frame is cut (224) using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip.
  • the singulation process all the outer portions including some of the damper lines (206 in FIG. 11) of the lead frame are removed, and only the signal leads 202 are separated from each other as shown in C2 of FIG. 11.
  • the signal lead 202 of FIG. 11 may reduce the number of layers of the redistribution metal pattern in the semiconductor package having a fan out structure, and may have a half-etched staircase structure to simplify the circuit design.
  • the singulation process may be performed using a punch (cut) instead of the blade, or may be performed using a laser (LASER).
  • FIG. 17 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention, which is manufactured by the singulation process.
  • a fan-out semiconductor package 230A using a lead frame may include a semiconductor chip 208 of FIG. 14 and an outer surface of the semiconductor chip.
  • the signal lead 202 serves to reduce the number of layers of a metal layer, for example, a redistribution metal pattern used to manufacture a fan-out semiconductor package, between the bond pad of the semiconductor chip and the conductive connection terminal, which is an external connection terminal. This has the advantage of simplifying the circuit design in its path.
  • the half-etched signal lead 202 is a vertical connection penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact inside the encapsulant 213A. Can be used as a terminal. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
  • POP package on package
  • a package on package is manufactured by stacking first and second semiconductor packages 230B and 230A using the lead frame shown in FIG. 17 up and down.
  • the upper metal pad 216 may not be formed on the signal lead of the first semiconductor package 230B as shown in part D of the drawing.
  • the second semiconductor package 230A and the first semiconductor package 230B are physically and electrically connected to each other by the conductive connection terminal 226A of the second semiconductor package 230A.
  • first semiconductor package 230B and the second semiconductor package 230A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.
  • a passive element 228 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.
  • 19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
  • a lead frame as shown in FIGS. 20 and 21, in which an opening and a half etching part on which a semiconductor chip is mounted, is prepared (S300).
  • the lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed.
  • the lead frame is attached on the first base (S302).
  • the protruding portion downward as shown in FIG. 22.
  • the semiconductor chip is attached together on the first base through the opening of the lead frame (S304). At this time, it is suitable to attach the bond pad of the semiconductor chip to face downward.
  • a molding process may be performed to form an encapsulant that completely seals the lead frame and the upper portion of the semiconductor chip on the first base (S306), and the upper encapsulant and the leadframe half etching part (FIG. 21). 303) is removed completely. Accordingly, the signal lead (302 of FIG. 21) consisting of the half-etching portion (303 in FIG. 21) and the protrusion is separated, and only the protrusion 302 is exposed to the outside of the encapsulant as shown in FIG. 23 (S308). An upper metal pad, for example, a vertically connected metal pad, is formed on the exposed lead frame signal lead as illustrated in FIG. 24 (S310). Thereafter, the first base used for forming the encapsulant is removed (S312).
  • an insulating film is formed on the entire opposite surface on which the upper metal pad is formed and patterned to expose the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S314).
  • the signal lead of the lead frame and the bond pad of the semiconductor chip are connected to a lower metal pattern, for example, a redistribution metal pattern (S316), an insulating film pattern is formed on the entire surface of the resultant product on which the lower metal pattern is formed, and connected to the lower metal pattern.
  • a lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 25 (S318).
  • the conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 26 (S320).
  • the conductive connection terminal may be solder balls or solder bumps.
  • a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed (S322), and two semiconductor packages are vertically mounted using conductive connection terminals as shown in FIG. 27.
  • a process of manufacturing a fan-out semiconductor package, for example, a package on package (POP) using the lead frame according to the third embodiment is completed (S324).
  • the protrusion 301 indicates a portion of the lead frame in which signal terminals separated from each other remain in the semiconductor package.
  • FIG. 20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention.
  • FIG. 21 illustrates a cut plane of 21-21 'of FIG. 20.
  • the lead frame 300 used in the third embodiment of the present invention does not include a damper line like the lead frames described above, and has a half-etched flat half-etched portion ( Only the protrusion 302 to be used as the signal lead in 303 is formed in a rectangle.
  • the shape of the signal lead, that is, the protrusion 302 may be modified in various shapes.
  • the lead frame 300 is characterized in that the opening 304, which is a space in which the semiconductor chip can be mounted, is provided in the center.
  • the structure of the opening 304 may be usefully applied in the process of making a semiconductor package having a fan-out structure through a subsequent process.
  • the strip frame lead frame 300 may be a strip in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.
  • 22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
  • the lead frame 300 illustrated in FIGS. 20 and 21 is attached onto the first base 312 by using an adhesive material. At this time, it is suitable to attach the lead frame 300 so that the protrusion 302 of FIG. 22 faces downward in the lead frame.
  • the first base 312 can be used as long as the material of the solid (rigid type) material, for example, may be a molded molding or a polyimide tape.
  • the semiconductor chip 308 is mounted on the first base 312 using an adhesive material through the opening of the lead frame (304 in FIG. 21).
  • the semiconductor chip 308 is suitable to be mounted so that the active region in which the circuit portion is formed to face downward, it is suitable to be mounted so that the bottom surface without the circuit portion is formed to face upward. Therefore, the bond pad 310 formed in the active region where the circuit portion is formed is in contact with the first base 312.
  • the molding process is performed on the resultant product on which the semiconductor chip 308 is mounted.
  • the encapsulant 314 is used to completely seal the upper portion of the semiconductor chip 308 and the upper portion of the lead frame 300 as shown in FIG. 22.
  • the encapsulant 314 may be made of a polymer compound such as an epoxy mold compound.
  • the upper portion of the encapsulant 314 and the half-etched portion 303 of FIG. 21 are completely polished as shown in FIG. 23 to separate the signal leads 302 in the form of protrusions from the lead frame 300, respectively.
  • the surface of the encapsulant 314 is exposed.
  • the bottom surface of the semiconductor chip 308 may also be polished while the half etching portion 303 is polished.
  • a method of attaching the semiconductor chip 308 in the polished state may be used.
  • separation of the protrusion may be performed as follows. Referring to FIG. 28, when polishing is performed while the thickness of the protrusion 302v of the lead frame 300 ′ is covered by the encapsulant 314 ′ in a state where the thickness of the protrusion 302v is greater than the thickness of the semiconductor chip 308, FIG. 29. As shown, the bottom surface of the semiconductor chip 308 is not polished. At this time, the semiconductor chip 308 is covered with the encapsulant 314A '.
  • the signal lead 302 is exposed, and then a metal film is formed on the insulating film 316 in a blanket manner.
  • Patterning forms an upper metal pad 320 electrically connected to the signal lead 302.
  • the upper metal pad 320 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to make a package on package (POP).
  • POP package on package
  • the first base 312 used for fixing the semiconductor chip 308 and the signal lead 302 is removed and removed.
  • a single or multiple layers of upper metal patterns may be further formed.
  • another bond layer 310 is formed on the entire surface of the bond pad 310 and the signal lead 302 exposed to the surface from which the first base 312 is removed, and then patterned to form the bond pad 310. ) And the signal lead 302 are exposed to the outside.
  • the lower metal pattern 324 connecting the bond pad 310 and the signal lead 302 to the insulating layer 322 including the exposed bond pad 310 and the signal lead 302 may be formed.
  • the lower metal pattern 324 is formed as a single layer, but the present invention is not limited thereto and may be formed as a plurality of layers.
  • the redistribution metal pattern 324 extends the arrangement of the bond pads 310 formed on the semiconductor chip to the signal lead 302 formed on the outside of the semiconductor chip 308, thereby becoming a main means for making a fan-out semiconductor package.
  • an insulating film 322 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 324 is formed, and the lower metal pad 326 connected to the lower metal pattern 324 in the vertical direction and exposed to the outside by the insulating film 322 pattern.
  • the insulating layer 322 may be a thin film having a multilayer structure made of the same material or different materials.
  • a conductive connector 328 for example, solder balls or solder bumps, is attached to the lower metal pad 326.
  • each lead frame is cut 330 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip. In the singulation process, cutting may be performed using a punch instead of a blade, or cutting may be performed using a laser.
  • the signal lead 302 of FIG. 21 penetrates up and down the semiconductor package without forming a separate via hole or via contact inside the encapsulant 314. It can be used as a vertical connector.
  • This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
  • FIG. 26 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention, which is manufactured by the singulation process of FIG. 25.
  • a fan-out semiconductor package 340 using a lead frame may include a semiconductor chip (308 of FIG. 23), an outer surface of the semiconductor chip, and a semiconductor chip; 23 (314A in FIG. 23) having the same height, a plurality of signal leads (302 in FIG. 23) of lead frame material included in the encapsulant and penetrating the encapsulant vertically, and the semiconductor chip.
  • the signal lead 302 may be used as a vertical connection terminal penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact in the encapsulant 314A. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
  • POP package on package
  • a package on package POP is manufactured by stacking first and second packages 340B and 340A up and down using the lead frame illustrated in FIG. 26.
  • the upper metal pad 320 may not be formed on the signal lead of the first semiconductor package 340B.
  • the second semiconductor package 340A and the second semiconductor package 340B are physically and electrically connected to each other by the conductive connection terminal 328 of the second semiconductor package 340A.
  • UBMs may be further formed on the upper metal pad 320 and the lower metal pad 326.
  • first semiconductor package 340B and the second semiconductor package 340A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.
  • a passive element 330 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.
  • a package on package (POP) can be manufactured as a simple manufacturing process.

Abstract

Disclosed are a method for manufacturing a fanout semiconductor package using a lead frame, and a semiconductor package and a package-on-package for same. To this end, in the method of the present invention, a lead frame is installed at the perimeter of a semiconductor chip in order to realize a fanout semiconductor package structure. Accordingly, a signal lead is used so as to use the lead frame two-dimensionally and three-dimensionally in order to simplify complicated circuit designs and reduce the number of metal layers which are formed. The lead frame can be used as a flat-type connecting terminal or a three-dimensional vertical-type connecting terminal inside the semiconductor package.

Description

리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지Method for manufacturing fan-out semiconductor package using leadframe, semiconductor package and package on package
본 발명은 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지에 관한 것으로, 더욱 상세하게는 리드프레임을 팬-아웃(fan-out) 달성을 위한 회로패턴 혹은 비아(via) 연결통로로 사용하는 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 상기 반도체 패키지를 상하로 적층된 구조인 패키지 온 패키지(POP; Package On Package. 이하 "POP"라 함)에 관한 것이다.The present invention relates to a method for manufacturing a fan-out semiconductor package using a leadframe, and to a semiconductor package and a package-on-package according to the present invention, and more particularly to a circuit pattern or via for achieving fan-out of the leadframe. via) A method for manufacturing a fan-out semiconductor package used as a connection path, a semiconductor package, and a package on package (POP), which is a structure in which the semiconductor package is stacked up and down. .
반도체 소자는 웨이퍼 제조단계부터 선 폭(line width)을 줄이고, 내부에 포함되는 회로의 설계 단순화를 통해 그 크기를 지속적으로 줄여왔다. 이와 함께 하나의 반도체 소자 내에 보다 많은 기능의 전자 회로를 포함시키기 위해 끊임없는 연구 개발이 진행되어 왔다. 이에 따라 반도체 칩의 크기는 점차 작아져 왔고, 반도체 칩 내부에 포함된 외부연결단자인 본드패드의 크기 및 간격은 더욱 조밀한 파인 피치형(pine-pitch type)으로 진화되어 왔다.Semiconductor devices have been continuously reduced in size by reducing line widths and simplifying the design of circuits included therein. In addition, continuous research and development has been conducted to include more functional electronic circuits in one semiconductor device. Accordingly, the size of the semiconductor chip has been gradually reduced, and the size and spacing of the bond pad, which is an external connection terminal included in the semiconductor chip, have evolved to a more compact fine-pitch type.
하지만, 반도체 칩을 사용한 반도체 패키지 제조공정에서는, 반도체 칩에 형성된 좁은 간격의 본드패드를 더욱 넓게 확장시켜야만 솔더볼(solder ball)이나 범프(bump) 등과 같은 큰 크기를 갖는 외부연결단자(external connection terminals)를 부착시킬 수 있다. 이러한 필요를 충족시키기 위해 반도체 칩에 포함된 본드패드의 배치를 효과적으로 확장시킬 수 있는 여러 형태의 팬-아웃 반도체 패키지가 소개되고 있다.However, in a semiconductor package manufacturing process using a semiconductor chip, a narrow spaced bond pad formed on the semiconductor chip needs to be expanded more widely to have external connection terminals having a large size such as solder balls or bumps. Can be attached. To meet these needs, various types of fan-out semiconductor packages have been introduced that can effectively expand the placement of bond pads included in semiconductor chips.
한편, 반도체 패키지에 있어서 팬 아웃(fan-out) 구조란, 본드패드와 연결된 재배선 패턴이 반도체 칩의 크기보다 넓게 확장되어 재배치되는 것을 말하며, 팬-인(fan-in) 구조란, 반도체 칩의 크기 한도 내에서 본드패드가 다시 재배치되는 것을 말한다. 한국공개특허 제2011-0077213호에 팬-아웃 타입의 반도체 패키지가 개시되어 있다. 하지만, 이러한 기술로는 제조공정 단순화에 한계가 있는 단점이 있다.In the semiconductor package, a fan-out structure means that a redistribution pattern connected to a bond pad is extended and relocated wider than the size of the semiconductor chip. A fan-in structure is a semiconductor chip. The bond pad is relocated within the size limit of. Korean Patent Publication No. 2011-0077213 discloses a semiconductor package of a fan-out type. However, this technique has a disadvantage in that there is a limit in simplifying the manufacturing process.
본 발명은, 리드프레임을 이용하여 재배선 금속패턴이 형성되는 층수를 줄이고, 리드프레임의 신호리드를 평면형 혹은 수직형 연결 통로로 사용함으로써, 반도체 패키지 제조공정의 공정을 단순화시키고, 제조 단가를 낮추고, 제품의 성능을 더욱 향상시킬 수 있는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 제공하는 것을 목적으로 한다.The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. Another object of the present invention is to provide a fan-out semiconductor package manufacturing method using a lead frame, which can further improve product performance.
본 발명은, 리드프레임을 이용하여 재배선 금속패턴이 형성되는 층수를 줄이고, 리드프레임의 신호리드를 평면형 혹은 수직형 연결 통로로 사용함으로써, 반도체 패키지 제조공정의 공정을 단순화시키고, 제조 단가를 낮추고, 제품의 성능을 더욱 향상시킬 수 있는 리드프레임을 이용한 팬-아웃 반도체 패키지를 제공하는 것을 다른 목적으로 한다.The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. It is another object of the present invention to provide a fan-out semiconductor package using a lead frame that can further improve product performance.
본 발명은, 리드프레임을 이용하여 재배선 금속패턴이 형성되는 층수를 줄이고, 리드프레임의 신호리드를 평면형 혹은 수직형 연결 통로로 사용함으로써, 반도체 패키지 제조공정의 공정을 단순화시키고, 제조 단가를 낮추고, 제품의 성능을 더욱 향상시킬 수 있는 리드프레임을 이용한 패키지 온 패키지(POP)를 제공하는 것을 또 다른 목적으로 한다.The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. Another aim is to provide a package-on-package (POP) using leadframe to further improve product performance.
본 발명은, 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 복수개의 신호리드를 갖는 스트립 상태의 리드프레임을 준비하는 단계와, 상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계와, 상기 제1 베이스 위의 상기 반도체 칩 및 리드프레임을 봉지재로 밀봉하고 제1 베이스를 제거하는 단계와, 상기 봉지재 및 반도체 칩 위에 절연막을 형성하고 상기 봉지재의 리드 및 반도체 칩의 본드패드를 노출하는 패터닝을 진행하는 단계와, 상기 노출된 신호리드와 본드패드를 연결하는 재배선 금속패턴을 형성하고 상부에 절연막 패턴을 형성하여 상기 재배선 금속패턴의 일부를 노출하는 재배선 금속패드 형성하는 단계와, 상기 노출된 재배선 금속패드에 도전성 연결 단자 부착하는 단계와, 상기 리드프레임 스트립에서 단위 반도체 패키지를 분리함과 동시에 개개의 신호라인을 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 제공한다.According to an embodiment of the present invention, there is provided a lead frame in a strip state having an opening in which a semiconductor chip can be seated at a center thereof and having a plurality of signal leads in a periphery thereof, and attaching the lead frame to a first base and Mounting a semiconductor chip on the first base through an opening of the semiconductor chip; sealing the semiconductor chip and the lead frame on the first base with an encapsulant and removing the first base; Forming an insulating film thereon and patterning the lead of the encapsulant and the bond pads of the semiconductor chip; forming a redistribution metal pattern connecting the exposed signal leads and the bond pads; Forming a redistribution metal pad exposing a portion of the redistribution metal pattern, and conducting conductive lead to the exposed redistribution metal pad A method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. .
본 발명의 다른 측면에 따르면, 본 발명은, 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 복수개의 신호리드를 포함하고 상기 신호리드에는 하프 에칭에 의한 돌출부가 마련된 스트립 상태의 리드프레임을 준비하는 단계와, 상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계와, 상기 리드프레임의 돌출부 및 상기 반도체 칩의 밑면만을 외부로 노출시키는 몰딩 공정을 진행하고, 상기 제1 베이스를 제거하는 단계와, 상기 결과물에서 돌출부가 형성된 반대면 전체에 절연막 패턴을 형성하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 외부로 노출하는 단계와, 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결하는 하부 금속패턴을 형성하는 단계와, 상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 형성하는 단계와, 상기 하부 금속패드 위에 도전성 연결단자를 부착하는 단계와, 상기 리드프레임 스트립에서 단위 반도체 패키지를 분리함과 동시에 개개의 신호라인을 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 제공한다.According to another aspect of the invention, the present invention, the lead frame of the strip state is provided with an opening in which the semiconductor chip can be seated in the center and a plurality of signal leads in the periphery, the projection lead is provided with a protrusion by half etching Preparing a lead, attaching the lead frame to the first base, mounting the semiconductor chip on the first base through the opening of the lead frame, and only the protrusion of the lead frame and the bottom surface of the semiconductor chip. And exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside by performing a molding process of exposing the substrate, removing the first base, and forming an insulating layer pattern on the entire opposite surface on which the protrusion is formed. And a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip. Forming an insulating film pattern on the entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern; and a conductive connection on the lower metal pad. A method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. do.
본 발명의 다른 측면에 따르면, 본 발명은, 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 신호리드가 하프 에칭에 의한 돌출부의 형태로 마련된 스트립 상태의 리드프레임을 준비하는 단계와, 상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계와, 상기 반도체 칩 및 리드프레임을 완전히 밀봉하는 봉지재를 형성하는 단계와, 상기 봉지재 및 리드프레임의 하프 에칭부를 연마하여 신호리드를 분리하여 노출시키고 상기 제1 베이스를 제거하는 단계와, 상기 결과물에서 상기 제1 베이스가 제거된 방향의 전면에 절연막 패턴을 형성하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드패드를 노출시키는 단계와, 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결하는 하부 금속패턴을 형성하는 단계와, 상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 형성하는 단계와, 상기 하부 금속패드 위에 도전성 연결단자를 부착하는 단계와, 상기 리드프레임 스트립에서 단위 반도체 패키지를 분리함과 동시에 개개의 신호라인을 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 제공한다.According to another aspect of the present invention, the present invention provides a step of preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in the center and a signal lead in the form of a protrusion by half etching; Attaching the lead frame to a first base, mounting a semiconductor chip on the first base through an opening of the lead frame, forming an encapsulant that completely seals the semiconductor chip and the lead frame; Polishing the half-etched portion of the encapsulant and the leadframe to separate and expose the signal leads, and to remove the first base; and to form an insulating film pattern on the entire surface of the resultant in which the first base is removed. Exposing the signal leads and bond pads of the semiconductor chip; Forming a lower metal pattern connecting the pads, forming an insulating layer pattern on the entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating layer pattern; And attaching a conductive connection terminal on the lower metal pad, and performing a singulation process of separating a unit semiconductor package from the leadframe strip and separating individual signal lines. A method of manufacturing an out-of- semiconductor package is provided.
본 발명의 또 다른 측면에 따르면, 본 발명은, 반도체 칩과, 상기 반도체 칩의 밑면 및 외곽을 감싸는 봉지재와, 상기 봉지재 내부에 위치한 리드프레임 재질의 복수개의 신호리드와, 상기 반도체 칩의 본드패드와 상기 리드프레임 재질의 복수개의 신호리드를 연결하는 재배선 금속패턴과, 상기 재배선 금속패턴과 연결된 재배선 금속패드와, 상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 리드프레임을 이용한 팬-아웃 반도체 패키지를 제공한다.According to another aspect of the invention, the present invention, a semiconductor chip, an encapsulant surrounding the bottom and the outer surface of the semiconductor chip, a plurality of signal leads of a lead frame material located inside the encapsulant, and A lead frame including a redistribution metal pattern connecting a bond pad and a plurality of signal leads of the lead frame material, a redistribution metal pad connected to the redistribution metal pattern, and a conductive connection terminal attached to the redistribution metal pad It provides a fan-out semiconductor package using.
본 발명의 또 다른 측면에 따르면, 본 발명은, 반도체 칩과, 상기 반도체 칩의 외곽을 감싸며, 상기 반도체 칩과 동일 높이를 갖는 봉지재와, 상기 봉지재 내부에 위치하며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드와, 상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴과, 상기 재배선 금속패턴과 연결된 재배선 금속패드와, 상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 리드프레임을 이용한 팬-아웃 반도체 패키지를 제공한다.According to another aspect of the invention, the present invention, the encapsulation material surrounding the semiconductor chip, the outer edge of the semiconductor chip, having the same height as the semiconductor chip, and located inside the encapsulation material in the vertical direction A plurality of signal leads made of a lead frame material having a penetrating shape, a redistribution metal pattern connecting the bond pads of the semiconductor chip and the signal leads, a redistribution metal pad connected to the redistribution metal pattern, and the redistribution metal Provided is a fan-out semiconductor package using a lead frame having a conductive connection terminal attached to a pad.
본 발명의 또 다른 측면에 따르면, 본 발명은, 반도체 칩, 상기 반도체 칩의 외곽을 감싸며, 상기 반도체 칩과 동일 높이를 갖는 봉지재, 상기 봉지재 내부에 포함되며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드, 상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴, 상기 재배선 금속패턴과 연결된 재배선 금속패드, 및 상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 제1 반도체 패키지와, 상기 제1 반도체 패키지 위에 도전성 연결단자를 통해 탑재되며, 반도체 칩, 상기 반도체 칩의 외곽을 감싸며, 상기 반도체 칩과 동일 높이를 갖는 봉지재, 상기 봉지재 내부에 포함되며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드, 상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴, 상기 재배선 금속패턴과 연결된 재배선 금속패드, 및 상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 제2 반도체 패키지를 포함하는 리드프레임을 이용한 패키지 온 패키지를 제공한다.According to another aspect of the invention, the present invention, a semiconductor chip, encapsulating the outer edge of the semiconductor chip, the encapsulant having the same height as the semiconductor chip, included in the encapsulant and penetrating the encapsulant in the vertical direction A plurality of signal leads of a lead frame material of a shape, a redistribution metal pattern connecting the bond pads of the semiconductor chip and the signal leads, a redistribution metal pad connected to the redistribution metal pattern, and a redistribution metal pad A first semiconductor package having a conductive connection terminal, a sealing material mounted on the first semiconductor package through a conductive connection terminal, surrounding the semiconductor chip and the outer edge of the semiconductor chip, and having the same height as the semiconductor chip, the encapsulation member A plurality of signal leads of a lead frame material included in the ash and penetrating the encapsulant in the vertical direction, and the bond pad of the semiconductor chip. And a second semiconductor package including a redistribution metal pattern connecting the signal lead, a redistribution metal pad connected to the redistribution metal pattern, and a conductive connection terminal attached to the redistribution metal pad. Provide a package on package.
본 발명에 의하면, 첫째 리드프레임에서 여러 개의 신호리드를 분리하여 사용함으로써, 팬-아웃 반도체 패키지를 제조하는데 사용되는 메탈층 형성 개수를 줄일 수 있다. 이때 리드프레임의 신호리드는 복잡한 회로 디자인을 단순화시키거나, 수직형 연결단자로 사용될 수 있다.According to the present invention, by using a plurality of signal leads separated from the first lead frame, the number of metal layers formed to manufacture the fan-out semiconductor package can be reduced. At this time, the signal lead of the leadframe can simplify a complicated circuit design or be used as a vertical connection terminal.
둘째, 리드프레임에서 하프 에칭(half etching)에 의한 돌출부를 이용하여 리드프레임의 신호리드로 사용함으로써, 별도의 비아 홀(via hole)이나 비아 콘택(via contact)을 형성하지 않고도 수직형 연결단자로 사용할 수 있다. 이러한 구조는 두 개의 반도체 패키지를 수직으로 쌓아 만드는 패키지 온 패키지(POP)에서 신호연결에 유리한 장점이 있다.Second, it is used as a signal lead of the lead frame by using a protrusion by half etching in the lead frame, so that it is a vertical connection terminal without forming a separate via hole or via contact. Can be used. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
도 1은 본 발명의 제1 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
도 2 및 도 3은 본 발명의 제1 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다.2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention.
도 4 내지 도 9는 본 발명의 제1 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
도 10은 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
도 11 및 도 12는 본 발명의 제2 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다.11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention.
도 13 내지 도 18은 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
도 19는 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
도 20 및 도 21은 본 발명의 제3 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다.20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention.
도 22 내지 도 27은 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
도 28 및 도 29는 도 22 및 도 23에 대한 변형예를 보여주는 단면도들이다.28 and 29 are cross-sectional views illustrating modified examples of FIGS. 22 and 23.
본 발명의 구성 및 효과를 충분히 이해하기 위하여, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예들을 설명한다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라, 여러가지 형태로 구현될 수 있고 다양한 변경을 가할 수 있다. 단지, 본 실시예들에 대한 설명은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술 분야의 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것이다. 첨부된 도면에서 구성 요소들은 설명의 편의를 위하여 그 크기가 실제보다 확대하여 도시한 것이며, 각 구성 요소의 비율은 과장되거나 축소될 수 있다. In order to fully understand the constitution and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms and various changes may be made. However, the description of the embodiments is provided only to make the disclosure of the present invention complete, and to fully inform the scope of the invention to those skilled in the art. In the accompanying drawings, for convenience of description, the size of the components is larger than the actual drawings, and the ratio of each component may be exaggerated or reduced.
본 발명의 실시예들에서 사용되는 용어들은 다르게 정의되지 않는 한, 해당 기술 분야에서 통상의 지식을 가진 자에게 통상적으로 알려진 의미로 해석될 수 있다.Unless otherwise defined, terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those of ordinary skill in the art.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
제1 실시예First embodiment
도 1은 본 발명의 제1 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
도 1을 참조하면, 먼저 반도체 칩이 안착될 수 있는 개구부가 마련된 도 2 및 도 3과 같은 리드프레임을 준비(S100)한다. 상기 리드프레임은 에치드 리드프레임(etched leadframe) 혹은 (stamped leadframe)일 수 있다. 하지만, 본 발명은 이에 한정되지 않고, 상기 리드프레임으로서 도전성 구조를 가지는 일반적인 도전성 플레이트(예, 금속 플레이트)가 제한 없이 적용 가능하며, 상기 리드프레임의 제조방법도 다양하게 선택될 수 있다. 그리고 상기 리드프레임을 제1 베이스 위에 부착(S102)한다. 이와 함께 반도체 칩을 상기 리드프레임의 개구부를 통해 제1 베이스 위에 도 4와 같이 함께 부착(S104)한다.Referring to FIG. 1, first, a lead frame as shown in FIGS. 2 and 3, in which an opening in which a semiconductor chip is mounted, is prepared (S100). The leadframe may be an etched leadframe or a stamped leadframe. However, the present invention is not limited thereto, and a general conductive plate (eg, a metal plate) having a conductive structure as the lead frame may be applied without limitation, and a method of manufacturing the lead frame may be variously selected. The lead frame is attached on the first base (S102). In addition, the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 4 (S104).
그리고 몰딩 공정(molding process)을 진행하여, 도 5와 같이 상기 제1 베이스 위에 상기 리드프레임과 반도체 칩을 밀봉하는 봉지재를 형성(S106)하고, 봉지재 형성을 위해 사용된 제1 베이스를 도 6과 같이 제거(S108)한다. 그 후, 상기 제1 베이스가 제거된 결과물을 뒤집어서 필요에 따라 제2 베이스(도7의 118)를 선택적으로 결과물 하부에 부착한다. 이어서 상기 결과물 위에 절연막을 형성하고 패터닝하여 절연막 패턴을 만들어 상기 반도체 칩의 본드패드와 상기 리드프레임의 신호리드를 외부로 노출(S110)시킨다. 그리고 재배선 금속패턴을 형성하여 상기 본드패드와 신호리드를 도 8과 같이 연결(S112)시킨다. 그리고 절연막 패턴을 다시 형성하여 상기 재배선 금속패턴의 일부를 노출시키는 재배선 금속패드를 노출(S114)시킨다. 그 후 상기 노출된 재배선 금속패드에 도전성 연결단자를 도 8과 같이 부착(S116)시킨다. 상기 도전성 연결단자는 솔더볼 혹은 솔더 범프일 수 있다. In addition, a molding process is performed to form an encapsulant that seals the lead frame and the semiconductor chip on the first base as shown in FIG. 5 (S106), and illustrates a first base used to form an encapsulant. Remove as S6 (S108). After that, the resultant from which the first base has been removed is inverted and a second base (118 of FIG. 7) is optionally attached to the lower part of the resultant if necessary. Subsequently, an insulating film is formed and patterned on the resultant to form an insulating film pattern to expose the bond pad of the semiconductor chip and the signal lead of the lead frame to the outside (S110). Then, the redistribution metal pattern is formed to connect the bond pad and the signal lead as shown in FIG. 8 (S112). The insulating layer pattern is formed again to expose the redistribution metal pad exposing a part of the redistribution metal pattern (S114). Thereafter, a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 8 (S116). The conductive connection terminal may be solder balls or solder bumps.
한편 상기 선택적으로 부착된 제2 베이스는 도전성 연결단자를 부착한 후, 제거하는 것이 바람직하다. 마지막으로 스트립 상태의 리드프레임에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정(singulation process)을 도 9와 같이 진행(S118)하여 본 발명의 제1 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조공정을 완료한다. 이때 상기 도2의 C1은 리드프레임 중에서 각각 분리된 신호단자가 반도체 패키지 내부에 남는 부분을 가리킨다.Meanwhile, the selectively attached second base may be removed after attaching the conductive connection terminal. Finally, a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed as shown in FIG. 9 (S118) to manufacture a fan-out semiconductor package using the lead frame according to the first embodiment of the present invention. Complete the process. In this case, C1 of FIG. 2 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.
도 2 및 도 3은 본 발명의 제1 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다. 이때 도 3은 도 2의 3-3'의 절단면을 가리킨다.2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention. In this case, Figure 3 indicates the cut surface of 3-3 'of FIG.
도 2 및 도 3을 참조하면, 본 발명의 제1 실시예에 사용되는 리드프레임(100)은, 도 2와 같이 적어도 두 이상의 리드프레임이 긴 띠 모양으로 배열된 스트립(strip) 형태인 것이 적합하다. 상기 스트립 형태의 리드프레임(100)은 하나의 반도체 패키지를 형성하기 위한 단위 리드프레임이 매트릭스 형태로 복수개가 배열된 스트립 형태일 수도 있다.2 and 3, the lead frame 100 used in the first embodiment of the present invention is preferably in the form of a strip in which at least two or more lead frames are arranged in a long band shape as shown in FIG. 2. Do. The strip frame lead frame 100 may have a strip shape in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.
상기 리드프레임(100)은 외곽에 각각의 신호리드(102)들을 지지하기 위한 댐버 라인(damber line, 106)이 형성되고, 상기 댐버 라인(106)과 연결된 복수개의 신호리드(102)가 구성되어 있다. 한편 도 2에 도시된 신호리드(102)의 형태는, 본 발명을 설명하기 위한 예시적인 것이며, 반도체 칩과의 효과적인 연결을 위해 다양한 모양으로 변형이 가능하다.The lead frame 100 has a dam line 106 for supporting the respective signal leads 102 on the outside thereof, and a plurality of signal leads 102 connected to the dam line 106 are formed. have. Meanwhile, the shape of the signal lead 102 shown in FIG. 2 is an example for describing the present invention and may be modified in various shapes for effective connection with the semiconductor chip.
이와 함께 본 발명의 바람직한 실시예에 의한 리드프레임(100)은, 신호리드(102) 안쪽으로 반도체 칩이 탑재될 수 있는 공간인, 개구부(104)가 마련된 특징이 있다. 통상적인 리드프레임은 중앙부에 칩 탑재부가 형성되어 개구부가 없는 형태이지만, 본 발명에 의한 리드프레임(100)은 이 곳이 비어 있는 개구부가 마련된 특징이 있으며, 이러한 구조는 팬-아웃 구조의 반도체 패키지를 만드는 과정에서 유용하게 적용됨을 후속 공정을 통해 확인할 수 있다.In addition, the lead frame 100 according to the preferred embodiment of the present invention is characterized in that the opening 104, which is a space in which the semiconductor chip can be mounted inside the signal lead 102, is provided. A typical lead frame has a chip mounting portion formed in the center thereof, and thus there is no opening. However, the lead frame 100 according to the present invention is characterized by an opening having an empty place. This structure is a semiconductor package having a fan-out structure. It can be confirmed through the subsequent process that it is useful in the process of making.
도 4 내지 도 9는 본 발명의 제1 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
도 4를 참조하면, 도2 및 도 3의 리드프레임(100)을 제1 베이스(112) 위에 접착성 소재를 사용하여 부착한다. 상기 제1 베이스(112)는 고형(rigid type) 재질의 소재이면 어느 것이나 사용이 가능하며 예컨대, 몰드 성형물 혹은 폴리이미드 테이프 등을 사용할 수 있다. 이어서 반도체 칩(108)을 상기 리드프레임의 개구부(도3의 104)를 통해 접착성 소재를 사용하여 상기 제1 베이스(112) 위에 탑재한다. 한편, 상기 반도체 칩(108)은 회로부가 형성된 활성영역(A)이 아래 방향을 향하도록 탑재되는 것이 적합하며, 회로부가 형성되지 않은 밑면(B)이 위쪽을 향하도록 탑재되는 것이 적합하다. 따라서 회로부가 형성된 활성영역(A)에 마련된 본드패드(110)는 상기 제1 베이스(112)와 맞닿는 형태가 된다.Referring to FIG. 4, the lead frame 100 of FIGS. 2 and 3 is attached onto the first base 112 by using an adhesive material. The first base 112 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used. Subsequently, the semiconductor chip 108 is mounted on the first base 112 using an adhesive material through the opening of the lead frame (104 in FIG. 3). On the other hand, the semiconductor chip 108 is preferably mounted so that the active region A in which the circuit portion is formed is directed downward, and the bottom surface B in which the circuit portion is not formed is mounted upward. Therefore, the bond pad 110 provided in the active region A in which the circuit unit is formed is in contact with the first base 112.
도 5 내지 도 7을 참조하면, 상기 반도체 칩(108)이 탑재된 결과물에 몰딩 공정을 진행한다. 상기 몰딩 공정에서 봉지재(114)를 사용하여 상기 반도체 칩(108) 및 리드프레임의 신호리드(102)를 충분히 덮도록 밀봉한다. 상기 봉지재(114)는 에폭시 몰드 컴파운드(Epoxy Mold Compound)와 같은 고분자 화합물이 사용될 수 있다. 5 to 7, a molding process is performed on the resultant product on which the semiconductor chip 108 is mounted. In the molding process, the encapsulant 114 is sealed to sufficiently cover the semiconductor chip 108 and the signal lead 102 of the lead frame. The encapsulant 114 may be a high molecular compound such as an epoxy mold compound.
그 후, 도 6과 같이 반도체 칩(108) 및 신호리드(102)의 고정을 위해 사용된 제1 베이스(112)를 떼어내어 제거하여 패널(116)을 만든다. 이에 따라 패널(116)에서 반도체 칩(108)의 본드패드(110) 및 신호리드(102)가 제1 베이스(112)를 떼어낸 자리에 노출된다. 상기 제1 베이스를 떼어낸 결과물을 다시 뒤집어서 반도체 칩(108)의 밑면이 위치하는 방향에 제2 베이스(118)를 도 7과 같이 선택적으로 부착한다. 상기 제2 베이스(118) 역시 고형(rigid type) 재질의 소재이면 어느 것이나 사용이 가능하며, 일 예로 몰드 성형물 혹은 폴리이미드 테이프 등을 사용할 수 있다.Thereafter, as shown in FIG. 6, the first base 112 used for fixing the semiconductor chip 108 and the signal lead 102 is removed and removed to form the panel 116. As a result, the bond pad 110 and the signal lead 102 of the semiconductor chip 108 are exposed to the position where the first base 112 is removed from the panel 116. The second base 118 is selectively attached to the direction in which the bottom surface of the semiconductor chip 108 is positioned by inverting the result of removing the first base, as shown in FIG. 7. The second base 118 may also be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used.
도 8 및 도 9를 참조하면, 먼저 노출된 본드패드(110)와 신호리드(102)가 있는 전면에 절연막(124)을 형성하고 이를 패터닝하여 상기 본드패드(110)와 신호리드(102)가 외부로 노출되게 한다. 그리고 상기 노출된 본드패드(110)와 신호리드(102)가 있는 절연막(124) 위에 상기 본드패드(110)와 신호리드(102)를 연결하는 재배선 금속패턴(122)을 형성한다. 상기 재배선 금속패턴(122)은, 신호리드(102)와 함께 반도체 칩(108) 내에 형성된 본드패드(110)의 배열을 반도체 칩(108) 외곽에 형성된 신호리드(102)까지 확장시켜 팬-아웃 반도체 패키지를 구현하는 수단이 된다. 8 and 9, first, an insulating film 124 is formed on the entire surface of the exposed bond pad 110 and the signal lead 102, and then patterned to form the bond pad 110 and the signal lead 102. Expose to the outside. A redistribution metal pattern 122 connecting the bond pad 110 and the signal lead 102 is formed on the exposed insulating pad 110 and the insulating film 124 having the signal lead 102. The redistribution metal pattern 122 extends the array of bond pads 110 formed in the semiconductor chip 108 together with the signal leads 102 to the signal leads 102 formed outside the semiconductor chip 108. It is a means for implementing the out semiconductor package.
이어서 상기 재배선 금속패턴(122)이 형성된 결과물에 다시 절연막(124)을 형성하고, 이를 패터닝하여 상기 재배선 금속패턴(122)의 일부를 노출시키는 재배선 금속패드를 형성한다. 한편, 상기 재배선 금속패드는 도 8과 같이 본드패드와 연결된 단층 구조의 금속층 패턴에 형성될 수도 있고, 필요에 따라 도 9와 같이 2층 구조에 형성된 금속층 패턴에 형성될 수도 있다. 그리고 상기 노출된 재배선 금속패드에 도전성 연결단자(126), 예컨대 솔더볼이나 솔더 범프(bump)를 부착한다. 이어서 다이아몬드 재질의 블레이드(blade) 등을 사용하여 각각의 리드프레임을 절단부(128)를 따라 분리하여 리드프레임 스트립에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정을 진행한다. Subsequently, an insulating film 124 is formed on the resultant product on which the redistribution metal pattern 122 is formed and patterned to form a redistribution metal pad exposing a part of the redistribution metal pattern 122. Meanwhile, the redistribution metal pad may be formed on the metal layer pattern of the single layer structure connected to the bond pad as shown in FIG. 8, or may be formed on the metal layer pattern formed on the two layer structure as illustrated in FIG. 9. A conductive connection terminal 126, for example, a solder ball or a solder bump is attached to the exposed redistribution metal pad. Subsequently, each leadframe is separated along the cutout 128 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the leadframe strip.
한편, 상기 싱귤레이션 공정은 리드프레임의 댐버 라인(도2의 106)을 포함하여 외곽부분은 모두 제거하고 도 2의 C1과 같이 신호리드(102)만 서로 분리된 상태로 남게 된다. 이러한 신호리드(도2의 102)는 팬 아웃 구조의 반도체 패키지에서 회로 배선을 평면적 혹은 수직적으로 확장시킬 수 있는 기능을 하기 때문에, 재배선 금속패턴의 층수를 낮추고, 회로 배선에 대한 디자인을 단순화시키는 수단이 될 수 있다. 또한, 상기 싱귤레이션 공정은 상기 블레이드를 사용한 절단 대신에 펀치(punch)를 사용한 절단을 진행하거나, 레이저(LASER)를 사용한 절단을 진행할 수도 있다.Meanwhile, the singulation process removes all the outer portions including the damper line (106 in FIG. 2) of the lead frame and leaves only the signal leads 102 separated from each other as shown in C1 of FIG. 2. This signal lead (102 in FIG. 2) functions to expand the circuit wiring planarly or vertically in the semiconductor package of the fan-out structure, thereby reducing the number of layers of the redistribution metal pattern and simplifying the design of the circuit wiring. It can be a means. In addition, the singulation process may be performed using a punch instead of cutting using the blade, or may be performed using a laser (LASER).
이어서 도 9를 사용하여 본 발명의 바람직한 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지의 구조에 관해 설명한다.Next, a structure of a fan-out semiconductor package using a lead frame according to a preferred embodiment of the present invention will be described with reference to FIG. 9.
본 발명의 일 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지는, 반도체 칩(도7의 108)과, 상기 반도체 칩의 밑면 및 외곽을 감싸는 봉지재(도8의 114)와, 상기 반도체 칩의 본드패드(도7의 110)와 상기 리드프레임의 재질의 복수개의 신호리드(도7의 102)를 연결하는 재배선 금속패턴(122), 상기 재배선 금속패턴과 연결된 재배선 금속패드 및 상기 재배선 금속패드에 부착된 도전성 연결단자(126)를 포함한다.A fan-out semiconductor package using a lead frame according to an embodiment of the present invention includes a semiconductor chip (108 in FIG. 7), an encapsulant (114 in FIG. 8) surrounding the underside and the outside of the semiconductor chip, and the semiconductor. A redistribution metal pattern 122 connecting the bond pad of the chip (110 of FIG. 7) and a plurality of signal leads (102 of FIG. 7) of the material of the lead frame, a redistribution metal pad connected to the redistribution metal pattern, and The conductive connection terminal 126 is attached to the redistribution metal pad.
이때 리드프레임 소재의 신호리드(도7의 102)는, 반도체 칩의 주변에 있는 봉지재 내부에 수평적 혹은 수직적으로 배치되어, 재배선 금속패턴을 형성하는 층수를 최소화시킬 수 있게 하며, 복잡한 회로 디자인을 단순화시키고, 반도체 패키지의 전기적 성능을 개선시킬 수 있는 역할을 수행한다.At this time, the signal lead (102 in FIG. 7) of the lead frame material is disposed horizontally or vertically in the encapsulant around the semiconductor chip, thereby minimizing the number of layers forming the redistribution metal pattern, and a complicated circuit. It simplifies the design and improves the electrical performance of the semiconductor package.
제1실시예에서는 2개의 반도체 칩(108)들이 도시되어 있지만, 본 발명은 이에 한정되지 않고, 3개 이상의 반도체 칩(108)들이 부착 가능하다. 이 때, 가로-세로 방향에 대하여 반도체 칩(108)들의 매트릭스 배열이 가능하다.Although two semiconductor chips 108 are shown in the first embodiment, the present invention is not limited thereto, and three or more semiconductor chips 108 may be attached thereto. At this time, a matrix arrangement of the semiconductor chips 108 is possible in the horizontal-vertical direction.
도 10은 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
도 10을 참조하면, 먼저 반도체 칩이 안착될 수 있는 개구부가 마련된 도 11 및 도 12와 같은 리드프레임을 준비(S200)한다. 상기 리드프레임은 하프 에칭(half etching)에 의한 돌출부가 형성된 에치드 리드프레임(etched leadframe)인 것이 적합하다. 이어서 상기 리드프레임을 제1 베이스 위에 부착(S202)한다. 이와 함께 반도체 칩을 상기 리드프레임의 개구부를 통해 제1 베이스 위에 도 13과 같이 함께 부착(S204)한다. 이때, 반도체 칩의 본드 패드가 아래쪽을 향하도록 부착하고, 리드프레임의 돌출부는 위쪽을 향하도록 부착하는 것이 적합하다.Referring to FIG. 10, first, a lead frame as shown in FIGS. 11 and 12 having an opening on which a semiconductor chip is mounted is prepared (S200). The lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed. Subsequently, the lead frame is attached on the first base (S202). At the same time, the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 13 (S204). At this time, it is preferable to attach the bond pad of the semiconductor chip to face downward, and attach the protrusion of the lead frame to face upward.
그리고 몰딩 공정(molding process)을 진행하여, 상기 제1 베이스 위에 상기 리드프레임과 반도체 칩을 밀봉하는 봉지재를 형성(S206)하고, 리드프레임의 돌출부를 연마저지층(polishing stopper)으로 연마를 진행하여 신호리드의 돌출부가 도 14와 같이 외부로 노출되게 한다. 그리고 노출된 리드프레임의 신호리드에 상부 금속패드, 예컨대 상하 연결형 금속패드를 도 15와 같이 형성(S210)한다. 그 후, 봉지재 형성을 위해 사용된 제1 베이스를 제거(S212)한다. In addition, a molding process is performed to form an encapsulant sealing the lead frame and the semiconductor chip on the first base (S206), and the protrusion of the lead frame is polished with a polishing stopper. Thus, the protrusion of the signal lead is exposed to the outside as shown in FIG. An upper metal pad, for example, a vertically connected metal pad is formed on the exposed signal of the lead frame as shown in FIG. 15 (S210). Thereafter, the first base used for forming the encapsulant is removed (S212).
이어서 상기 결과물에서 돌출부가 형성된 반대면 전체에 절연막 패턴을 형성하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 외부로 노출(S214)시킨다. 그리고 하부 금속패턴, 예컨대 재배선 금속패턴으로 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결(S216)시키고, 상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 도 16과 같이 형성(S218)한다. 그 후 상기 노출된 재배선 금속패드에 도전성 연결단자를 도 16과 같이 부착(S220)시킨다. 상기 도전성 연결단자는 솔더볼 혹은 솔더 범프일 수 있다. Subsequently, an insulating film pattern is formed on the entire opposite surface on which the protrusion is formed, thereby exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S214). In addition, the signal lead of the lead frame and the bond pad of the semiconductor chip may be connected to each other using a lower metal pattern, for example, a redistribution metal pattern, and an insulating layer pattern may be formed on the entire surface of the resultant product on which the lower metal pattern is formed, and then connected to the lower metal pattern. A lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 16 (S218). Thereafter, a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 16 (S220). The conductive connection terminal may be solder balls or solder bumps.
마지막으로 스트립 상태의 리드프레임에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정(singulation process)을 진행(S222)하고, 도 18과 같이 두 개의 반도체 패키지를 도전성 연결단자와 상부 금속패드를 이용하여 수직으로 탑재하여 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지, 예컨대 패키지 온 패키지(POP)의 제조공정을 완료한다. 이때 상기 도 11의 C2는 리드프레임 중에서 각각 분리된 신호단자가 반도체 패키지 내부에 남는 부분을 가리킨다.Finally, a singulation process is performed to separate the unit semiconductor package from the lead frame in a strip state (S222). As shown in FIG. 18, two semiconductor packages are vertically mounted using conductive connection terminals and an upper metal pad. This completes the manufacturing process of the fan-out semiconductor package, for example, the package on package (POP) using the lead frame according to the second embodiment of the present invention. In this case, C2 of FIG. 11 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.
도 11 및 도 12는 본 발명의 제2 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다. 여기서 도 12는 도 11의 12-12'의 절단면을 가리킨다.11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention. Here, FIG. 12 refers to the cut plane of 12-12 'of FIG.
도 11 및 도 12를 참조하면, 본 발명의 제2 실시예에 사용되는 리드프레임(200)은, 외곽에 각각의 신호리드(202)들을 지지하기 위한 댐버 라인(damber line, 206)이 형성되고, 상기 댐버 라인(206)과 연결된 복수개의 신호리드(202)가 구성되어 있다. 한편 상기 신호리드(202)는 리드프레임의 일부만 에칭(etching)되 하프 에칭부(도12의 203)와 하프에칭이 되지 않아 돌출된 형태인 돌출부(도12의 201)를 포함한다. 도 11에 도시된 신호리드(202)의 형태는, 본 발명을 설명하기 위한 예시적인 것이며, 반도체 칩과의 연결을 위해 다양한 모양으로 변형되어도 무방하다.11 and 12, in the lead frame 200 used in the second embodiment of the present invention, a damper line 206 for supporting each signal lead 202 is formed at an outer side thereof. A plurality of signal leads 202 connected to the damper line 206 are configured. On the other hand, the signal lead 202 includes a half-etched portion (203 in FIG. 12) and a protrusion (201 in FIG. 12) that is protruded because it is not half-etched by etching only a part of the lead frame. The shape of the signal lead 202 shown in FIG. 11 is an example for describing the present invention, and may be modified in various shapes for connection with a semiconductor chip.
이와 함께 본 발명의 바람직한 실시예에 의한 리드프레임(200)은, 신호리드(202) 안쪽으로 반도체 칩이 탑재될 수 있는 공간인, 개구부(204)가 마련된 특징이 있다. 이러한 개구부(204)의 구조는 팬-아웃 구조의 반도체 패키지를 만드는 과정에서 유용하게 적용됨을 후속 공정을 통해 확인할 수 있다.In addition, the lead frame 200 according to the preferred embodiment of the present invention is characterized in that the opening 204 is provided, which is a space in which the semiconductor chip can be mounted inside the signal lead 202. The structure of the opening 204 may be usefully applied in the process of making a fan-out semiconductor package through a subsequent process.
한편, 도 11에서는 하나의 반도체 패키지에 포함되는 리드프레임(200) 형태만을 도시하였으나, 이는 적어도 두 이상의 리드프레임이 긴 띠 모양으로 배열된 스트립(strip)인 것이 적합하다. 상기 스트립 형태의 리드프레임(200)은 하나의 반도체 패키지를 형성하기 위한 단위 리드프레임이 매트릭스 형태로 복수개가 배열된 스트립일 수도 있다.Meanwhile, although only the shape of the lead frame 200 included in one semiconductor package is illustrated in FIG. 11, at least two lead frames are preferably strips arranged in a long band shape. The strip frame leadframe 200 may be a strip in which a plurality of unit leadframes for forming one semiconductor package are arranged in a matrix form.
도 13 내지 도 18은 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
도 13 내지 도 15를 참조하면, 도 11 및 도 12에 도시된 리드프레임(200)을 제1 베이스(212) 위에 접착성 소재를 사용하여 부착한다. 이때, 리드프레임의 신호리드(202)에서 돌출부(도12의 201)가 위쪽을 향하도록 상기 리드프레임(200)을 부착하는 것이 적합하다. 상기 제1 베이스(212)는 고형(rigid type) 재질의 소재이면 어느 것이나 사용이 가능하며, 일 예로 몰드 성형물 혹은 폴리이미드 테이프 등을 사용할 수 있다. 이어서 반도체 칩(208)을 상기 리드프레임의 개구부(도 12의 204)를 통해 접착성 소재를 사용하여 상기 제1 베이스(212) 위에 탑재한다. 한편, 상기 반도체 칩(208)은 회로부가 형성된 활성영역이 아래 방향을 향하도록 탑재되는 것이 적합하며, 회로부가 형성되지 않은 밑면이 위쪽을 향하도록 탑재되는 것이 적합하다. 따라서 회로부가 형성된 활성영역에 형성된 본드패드(210)는 상기 제1 베이스(212)와 맞닿는 형태가 된다. 13 to 15, the leadframe 200 illustrated in FIGS. 11 and 12 is attached onto the first base 212 using an adhesive material. At this time, the lead frame 200 is preferably attached so that the protrusion (201 of FIG. 12) is upward in the signal lead 202 of the lead frame. The first base 212 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used. Subsequently, the semiconductor chip 208 is mounted on the first base 212 using an adhesive material through the opening of the lead frame (204 of FIG. 12). On the other hand, the semiconductor chip 208 is preferably mounted so that the active region in which the circuit portion is formed faces downward, and is mounted so that the bottom surface where the circuit portion is not formed faces upward. Therefore, the bond pad 210 formed in the active region where the circuit portion is formed is in contact with the first base 212.
상기 반도체 칩(208)이 탑재된 결과물에 몰딩 공정을 진행한다. 상기 몰딩 공정에서 봉지재(213)를 사용하여 상기 반도체 칩(208) 및 리드프레임의 신호리드(202)를 도 13과 같이 완전히 밀봉한다. 상기 봉지재(213)는 에폭시 몰드 컴파운드(Epoxy Mold Compound)와 같은 고분자 화합물이 재질로 사용될 수 있다. 그리고 도 14와 같이 상기 리드프레임의 돌출부(201)를 연마저지층(polishing stopper)으로 봉지재(213)의 상부를 연마하여 봉지재(213) 표면에 신호리드의 돌출부(201)가 외부로 노출되도록 한다. The molding process is performed on the resultant product on which the semiconductor chip 208 is mounted. In the molding process, the encapsulant 213 is used to completely seal the semiconductor chip 208 and the signal lead 202 of the lead frame as shown in FIG. 13. The encapsulant 213 may be made of a polymer compound such as an epoxy mold compound. As shown in FIG. 14, the protrusion 201 of the lead frame is polished to an upper portion of the encapsulant 213 by using a polishing stopper to expose the protrusion 201 of the signal lead to the surface of the encapsulant 213. Be sure to
이어서 도 15와 같이 절연막(214)을 도포한 후, 이를 패터닝하여 신호리드의 돌출부(201)가 노출되게 한 후, 상기 절연막(214) 상부에 금속막을 블랭킷(blanket) 방식으로 형성한 후, 이를 패턴닝하여 신호리드의 돌출부(201)와 전기적으로 연결된 상부 금속패드(216)를 형성한다. 상기 상부 금속패드(216)는 팬-아웃 반도체 패키지를 상하 방향으로 적층하여 패키지 온 패키지(POP)를 만드는 공정에서 수직 연결 통로의 역할을 수행할 수 있다. 그 후, 반도체 칩(208) 및 신호리드(202)의 고정을 위해 사용된 제1 베이스(212)를 떼어내어 제거한다. 다만, 상기 상부 금속패드(216)의 형성 전에, 단일 또는 복수 층의 상부 금속 패턴(미도시)을 더 형성할 수도 있다.Subsequently, the insulating film 214 is coated as shown in FIG. 15, and then patterned to expose the protrusion 201 of the signal lead, and then a metal film is formed on the insulating film 214 in a blanket manner. Patterning to form the upper metal pad 216 is electrically connected to the protrusion 201 of the signal lead. The upper metal pad 216 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to create a package on package (POP). Thereafter, the first base 212 used for fixing the semiconductor chip 208 and the signal lead 202 is removed and removed. However, before the upper metal pad 216 is formed, a single or multiple layers of upper metal patterns (not shown) may be further formed.
도 16을 참조하면, 상기 제1 베이스(212)를 제거한 면에 노출된 본드패드(210)와 신호리드(202)가 있는 전면에 절연막(218)을 형성하고 이를 패터닝하여 상기 본드패드(210)와 신호리드(202)가 외부로 노출되게 한다. 그리고 상기 노출된 본드패드(210)와 신호리드(202)가 있는 절연막(218) 위에 상기 본드패드(210)와 신호리드(202)를 연결하는 하부 금속패턴(220), 예컨대 재배선 금속패턴을 형성한다. 본 실시예에서는, 하부 금속패턴(220)이 단일층으로 형성되어 있지만, 본 발명은 이에 한정되지 않고, 복수 층으로 형성될 수도 있다. 상기 재배선 금속패턴(220)은 반도체 칩에 형성된 본드패드(210)의 배열을 반도체 칩(208) 외곽에 형성된 신호리드(202)까지 확장시켜 팬-아웃 반도체 패키지를 만드는 주요 수단이 된다.Referring to FIG. 16, an insulating film 218 is formed on the entire surface of the bond pad 210 and the signal lead 202 exposed to the surface from which the first base 212 is removed, and then patterned to form the insulating pad 210. And signal lead 202 are exposed to the outside. The lower metal pattern 220 connecting the bond pad 210 and the signal lead 202 to the insulating layer 218 including the exposed bond pad 210 and the signal lead 202 may be formed. Form. In the present embodiment, the lower metal pattern 220 is formed of a single layer, but the present invention is not limited thereto, and may be formed of a plurality of layers. The redistribution metal pattern 220 extends the arrangement of the bond pads 210 formed on the semiconductor chip to the signal lead 202 formed on the outside of the semiconductor chip 208, thereby becoming a main means for making a fan-out semiconductor package.
이어서 상기 하부 금속패턴(220)이 형성된 결과물 전면에 절연막(218) 패턴을 형성하고 상기 하부 금속패턴(220)과 연결되고 절연막(218) 패턴에 의해 외부로 노출된 하부 금속패드(222)를 형성한다. 상기 절연막(218)은 동일 재질 혹은 다른 재질로 만들어진 다층 구조의 박막일 수 있다. 그 후, 그리고 하부 금속패드(222)에 도전성 연결단자(226), 예컨대 솔더볼이나 솔더 범프(bump)를 부착한다. 만일, 상기 도전성 연결단자(226)가 솔더볼 또는 솔더 범프일 경우, 상기 도전성 연결단자(226)와 상기 하부 금속패드(222) 사이에 UBM(Under Bump Metal)이 더 형성될 수도 있다. 또한, 상부 금속패드(216)에도 UBM이 더 형성될 수도 있다.Subsequently, an insulating film 218 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 220 is formed, and a lower metal pad 222 connected to the lower metal pattern 220 and exposed to the outside by the insulating film 218 pattern is formed. do. The insulating layer 218 may be a thin film having a multilayer structure made of the same material or different materials. Thereafter, a conductive connection terminal 226, for example, a solder ball or a solder bump, is attached to the lower metal pad 222. If the conductive connection terminal 226 is solder ball or solder bump, an under bump metal (UBM) may be further formed between the conductive connection terminal 226 and the lower metal pad 222. In addition, UBM may be further formed on the upper metal pad 216.
그리고 다이아몬드 재질의 블레이드(blade) 등을 사용하여 각각의 리드프레임을 절단(224)하여 리드프레임 스트립에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정을 진행한다. Then, each lead frame is cut (224) using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip.
한편, 상기 싱귤레이션 공정에서 리드프레임의 일부 댐버 라인(도11의 206)을 포함하여 외곽부분은 모두 제거되고 도 11의 C2와 같이 신호리드(202)만 서로 분리된 상태로 남게 된다. 이러한 신호리드(도 11의 202)는, 팬 아웃 구조의 반도체 패키지에서 재배선 금속패턴의 층수를 줄이고, 하프 에칭된 계단 구조로 되어 있어 회로 디자인을 단순화시키는 수단이 될 수 있다. 또한, 상기 싱귤레이션 공정은 블레이드 대신에 펀치(punch)를 사용한 절단을 진행하거나, 레이저(LASER)를 사용한 절단을 진행할 수도 있다.On the other hand, in the singulation process, all the outer portions including some of the damper lines (206 in FIG. 11) of the lead frame are removed, and only the signal leads 202 are separated from each other as shown in C2 of FIG. 11. The signal lead 202 of FIG. 11 may reduce the number of layers of the redistribution metal pattern in the semiconductor package having a fan out structure, and may have a half-etched staircase structure to simplify the circuit design. In addition, the singulation process may be performed using a punch (cut) instead of the blade, or may be performed using a laser (LASER).
도 17은 상기 싱귤레이션 공정에 의해 제조가 완료된 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지의 단면이다.FIG. 17 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention, which is manufactured by the singulation process.
도 17을 참조하면, 본 발명의 제2 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지(230A)는, 반도체 칩(도 14의 208)과, 상기 반도체 칩의 외곽을 감싸며 상기 반도체 칩과 동일 높이를 갖는 봉지재(도14의 213A)와, 상기 봉지재 내부에 포함되며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드(도 14의 202)와, 상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴(220)과, 상기 재배선 금속패턴과 연결된 재배선 금속패드(222) 및 상기 재배선 금속패드(222)에 부착된 도전성 연결단자(226)를 포함하여 구성된다. Referring to FIG. 17, a fan-out semiconductor package 230A using a lead frame according to a second exemplary embodiment of the present invention may include a semiconductor chip 208 of FIG. 14 and an outer surface of the semiconductor chip. An encapsulant having the same height (213A in FIG. 14), a plurality of signal leads (202 in FIG. 14) of lead frame material included in the encapsulant and penetrating the encapsulant vertically, and the semiconductor chip A redistribution metal pattern 220 connecting the bond pad and the signal lead, a redistribution metal pad 222 connected to the redistribution metal pattern, and a conductive connection terminal 226 attached to the redistribution metal pad 222. It is configured to include).
여기서 상기 신호리드(202)는 팬-아웃 반도체 패키지를 제조하는데 사용되는 메탈층, 예컨대 재배선 금속패턴의 층 개수를 줄이는 역할을 수행하여 반도체 칩의 본드패드와 외부연결단자인 도전형 연결단자 사이의 경로에 있는 회로 디자인을 단순화시키는 장점이 있다. 이와 함께, 상기 하프 에칭된 신호리드(202)는, 봉지재(213A) 내부에 별도의 비아 홀(via hole)이나 비아 콘택(via contact)을 형성하지 않고도 반도체 패키지의 상하를 관통하는 수직형 연결단자로 사용할 수 있다. 이러한 구조는 두 개의 반도체 패키지를 수직으로 쌓아 만드는 패키지 온 패키지(POP)에서 신호연결에 유리한 장점이 있다.In this case, the signal lead 202 serves to reduce the number of layers of a metal layer, for example, a redistribution metal pattern used to manufacture a fan-out semiconductor package, between the bond pad of the semiconductor chip and the conductive connection terminal, which is an external connection terminal. This has the advantage of simplifying the circuit design in its path. In addition, the half-etched signal lead 202 is a vertical connection penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact inside the encapsulant 213A. Can be used as a terminal. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
도 18을 참조하면, 도 17에 도시된 리드프레임을 이용한 제1,2반도체 패키지(230B, 230A)를 상하로 적층하여 패키지 온 패키지(POP)를 제조한 단면이다. 이때, 도면의 D 부분처럼 제1 반도체 패키지(230B)의 신호리드 상부에 상부 금속패드(216)를 만들지 않을 수도 있다. 또한 제2 반도체 패키지(230A) 및 제1 반도체 패키지(230B)는 제2 반도체 패키지(230A)의 도전형 연결단자(226A)에 의해 서로 물리적 및 전기적으로 연결되어 있다.Referring to FIG. 18, a package on package (POP) is manufactured by stacking first and second semiconductor packages 230B and 230A using the lead frame shown in FIG. 17 up and down. In this case, the upper metal pad 216 may not be formed on the signal lead of the first semiconductor package 230B as shown in part D of the drawing. In addition, the second semiconductor package 230A and the first semiconductor package 230B are physically and electrically connected to each other by the conductive connection terminal 226A of the second semiconductor package 230A.
상기 제1 반도체 패키지(230B)와 상기 제2 반도체 패키지(230A)는 서로 실질적으로 동일한 구조를 가지지만, 본 발명은 이에 한정되지 않고, 서로 다른 크기 및 기능을 가질 수도 있다.Although the first semiconductor package 230B and the second semiconductor package 230A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.
한편, 제2 반도체 패키지(230A)에 상부 금속패드(216)가 형성된 경우, 저항, 커패시터 등과 같은 수동소자(228)를 추가로 부착하여 패키지 온 패키지의 기능을 개선할 수 있다.Meanwhile, when the upper metal pad 216 is formed on the second semiconductor package 230A, a passive element 228 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.
도 19는 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 플로차트이다.19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
도 19를 참조하면, 먼저 반도체 칩이 안착될 수 있는 개구부와 하프 에칭부가 마련된 도 20 및 도 21과 같은 리드프레임을 준비(S300)한다. 상기 리드프레임은 하프 에칭(half etching)에 의한 돌출부가 형성된 에치드 리드프레임(etched leadframe)인 것이 적합하다. 이어서 상기 리드프레임을 제1 베이스 위에 부착(S302)한다. 상기 리드프레임을 상기 제1 베이스에 부착하는 방식은 도 22와 같이 돌출부가 아래로 향하도록 부착하는 것이 적합하다. 이와 함께 반도체 칩을 상기 리드프레임의 개구부를 통해 제1 베이스 위에 함께 부착(S304)한다. 이때, 반도체 칩의 본드 패드가 아래쪽을 향하도록 부착하는 것이 적합하다.Referring to FIG. 19, first, a lead frame as shown in FIGS. 20 and 21, in which an opening and a half etching part on which a semiconductor chip is mounted, is prepared (S300). The lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed. Subsequently, the lead frame is attached on the first base (S302). In the method of attaching the lead frame to the first base, it is preferable to attach the protruding portion downward as shown in FIG. 22. In addition, the semiconductor chip is attached together on the first base through the opening of the lead frame (S304). At this time, it is suitable to attach the bond pad of the semiconductor chip to face downward.
그리고 몰딩 공정(molding process)을 진행하여, 상기 제1 베이스 위에 상기 리드프레임과 반도체 칩의 상부까지 완전히 밀봉하는 봉지재를 형성(S306)하고, 상부 봉지재 및 리드프레임 하프 에칭부(도 21의 303)를 완전히 제거한다. 이에 따라, 하프에칭부(도 21의 303)와 돌출부로 이루어진 신호리드(도 21의 302)는 각각 분리되면서 도 23과 같이 돌출부(302)만이 봉지재 외부로 노출(S308)되게 된다. 그리고 노출된 리드프레임의 신호리드에 상부 금속패드, 예컨대 상하 연결형 금속패드를 도 24와 같이 형성(S310)한다. 그 후, 봉지재 형성을 위해 사용된 제1 베이스를 제거(S312)한다. In addition, a molding process may be performed to form an encapsulant that completely seals the lead frame and the upper portion of the semiconductor chip on the first base (S306), and the upper encapsulant and the leadframe half etching part (FIG. 21). 303) is removed completely. Accordingly, the signal lead (302 of FIG. 21) consisting of the half-etching portion (303 in FIG. 21) and the protrusion is separated, and only the protrusion 302 is exposed to the outside of the encapsulant as shown in FIG. 23 (S308). An upper metal pad, for example, a vertically connected metal pad, is formed on the exposed lead frame signal lead as illustrated in FIG. 24 (S310). Thereafter, the first base used for forming the encapsulant is removed (S312).
이어서 상기 결과물에서 상부 금속패드가 형성된 반대면 전체에 절연막을 형성하고 이를 패터닝하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 외부로 노출(S314)시킨다. 그리고 하부 금속패턴, 예컨대 재배선 금속패턴으로 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결(S316)시키고, 상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 도 25와 같이 형성(S318)한다. 상기 노출된 재배선 금속패드에 도전성 연결단자를 도 26과 같이 부착(S320)시킨다. 상기 도전성 연결단자는 솔더볼 혹은 솔더 범프일 수 있다. Subsequently, an insulating film is formed on the entire opposite surface on which the upper metal pad is formed and patterned to expose the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S314). The signal lead of the lead frame and the bond pad of the semiconductor chip are connected to a lower metal pattern, for example, a redistribution metal pattern (S316), an insulating film pattern is formed on the entire surface of the resultant product on which the lower metal pattern is formed, and connected to the lower metal pattern. A lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 25 (S318). The conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 26 (S320). The conductive connection terminal may be solder balls or solder bumps.
마지막으로 스트립 상태의 리드프레임에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정(singulation process)을 진행(S322)하고, 도 27과 같이 두 개의 반도체 패키지를 도전성 연결단자를 이용하여 수직으로 탑재하여 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지, 예컨대 패키지 온 패키지(POP)의 제조공정을 완료(S324)한다. 이때 상기 도 20의 C3에서 돌출부(301)는 리드프레임 중에서 각각 분리된 신호단자가 반도체 패키지 내부에 남는 부분을 가리킨다.Finally, a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed (S322), and two semiconductor packages are vertically mounted using conductive connection terminals as shown in FIG. 27. A process of manufacturing a fan-out semiconductor package, for example, a package on package (POP) using the lead frame according to the third embodiment is completed (S324). At this time, in the C3 of FIG. 20, the protrusion 301 indicates a portion of the lead frame in which signal terminals separated from each other remain in the semiconductor package.
도 20 및 도 21은 본 발명의 제3 실시예에 사용되는 리드프레임을 설명하기 위한 평면도 및 단면도이다. 도 21은 도 20의 21-21'의 절단면을 가리킨다.20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention. FIG. 21 illustrates a cut plane of 21-21 'of FIG. 20.
도 20 및 도 21을 참조하면, 본 발명의 제3 실시예에 사용되는 리드프레임(300)은 앞서 설명된 리드프레임들과 같이 댐버 라인은 포함하지 않고, 하프 에칭된 평판형의 하프에칭부(303)에 오직 신호리드로 사용될 돌출부(302)만이 장방형으로 형성되어 있다. 상기 신호리드 즉 돌출부(302)의 형태는 다양한 모양으로 변형되어도 무방하다.20 and 21, the lead frame 300 used in the third embodiment of the present invention does not include a damper line like the lead frames described above, and has a half-etched flat half-etched portion ( Only the protrusion 302 to be used as the signal lead in 303 is formed in a rectangle. The shape of the signal lead, that is, the protrusion 302 may be modified in various shapes.
이와 함께 본 발명의 바람직한 실시예에 의한 리드프레임(300)은, 중앙부에 반도체 칩이 탑재될 수 있는 공간인, 개구부(304)가 마련된 특징이 있다. 이러한 개구부(304)의 구조는 팬-아웃 구조의 반도체 패키지를 만드는 과정에서 유용하게 적용됨을 후속 공정을 통해 확인할 수 있다.In addition, the lead frame 300 according to the preferred embodiment of the present invention is characterized in that the opening 304, which is a space in which the semiconductor chip can be mounted, is provided in the center. The structure of the opening 304 may be usefully applied in the process of making a semiconductor package having a fan-out structure through a subsequent process.
한편, 도 20 및 21에서는 하나의 반도체 패키지에 포함되는 리드프레임(300) 형태만을 도시하였으나, 이는 적어도 두 이상의 리드프레임이 긴 띠 모양으로 배열된 스트립(strip)인 것이 적합하다. 상기 스트립 형태의 리드프레임(300)은 하나의 반도체 패키지를 형성하기 위한 단위 리드프레임이 매트릭스 형태로 복수개가 배열된 스트립일 수도 있다.Meanwhile, although only the shape of a lead frame 300 included in one semiconductor package is illustrated in FIGS. 20 and 21, it is preferable that at least two lead frames are strips arranged in a long band shape. The strip frame lead frame 300 may be a strip in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.
도 22 내지 도 27은 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
도 22 내지 도 24를 참조하면, 도 20 및 도 21에 도시된 리드프레임(300)을 제1 베이스(312) 위에 접착성 소재를 사용하여 부착한다. 이때, 리드프레임에서 돌출부(도 22의 302)가 아래쪽을 향하도록 상기 리드프레임(300)을 부착하는 것이 적합하다. 상기 제1 베이스(312)는 고형(rigid type) 재질의 소재이면 어느 것이나 사용이 가능하며, 일 예로 몰드 성형물 혹은 폴리이미드 테이프 등을 사용할 수 있다. 이어서 반도체 칩(308)을 상기 리드프레임의 개구부(도 21의 304)를 통해 접착성 소재를 사용하여 상기 제1 베이스(312) 위에 탑재한다. 한편, 상기 반도체 칩(308)은 회로부가 형성된 활성영역이 아래 방향을 향하도록 탑재되는 것이 적합하며, 회로부가 형성되지 않은 밑면이 위쪽을 향하도록 탑재되는 것이 적합하다. 따라서 회로부가 형성된 활성영역에 형성된 본드패드(310)는 상기 제1 베이스(312)와 맞닿는 형태가 된다. 22 to 24, the lead frame 300 illustrated in FIGS. 20 and 21 is attached onto the first base 312 by using an adhesive material. At this time, it is suitable to attach the lead frame 300 so that the protrusion 302 of FIG. 22 faces downward in the lead frame. The first base 312 can be used as long as the material of the solid (rigid type) material, for example, may be a molded molding or a polyimide tape. Subsequently, the semiconductor chip 308 is mounted on the first base 312 using an adhesive material through the opening of the lead frame (304 in FIG. 21). On the other hand, the semiconductor chip 308 is suitable to be mounted so that the active region in which the circuit portion is formed to face downward, it is suitable to be mounted so that the bottom surface without the circuit portion is formed to face upward. Therefore, the bond pad 310 formed in the active region where the circuit portion is formed is in contact with the first base 312.
상기 반도체 칩(308)이 탑재된 결과물에 몰딩 공정을 진행한다. 상기 몰딩 공정에서 봉지재(314)를 사용하여 상기 반도체 칩(308) 상부 및 리드프레임(300)의 상부를 도 22와 같이 완전히 밀봉한다. 상기 봉지재(314)는 에폭시 몰드 컴파운드(Epoxy Mold Compound)와 같은 고분자 화합물이 재질로 사용될 수 있다. The molding process is performed on the resultant product on which the semiconductor chip 308 is mounted. In the molding process, the encapsulant 314 is used to completely seal the upper portion of the semiconductor chip 308 and the upper portion of the lead frame 300 as shown in FIG. 22. The encapsulant 314 may be made of a polymer compound such as an epoxy mold compound.
이어서 도 23과 같이 봉지재(314)의 상부 및 리드프레임(300)의 하프 에칭부(도 21의 303)를 완전히 연마하여 리드프레임(300)에서 돌출부 형태의 신호리드(302)가 각각 분리됨과 동시에 봉지재(314) 표면으로 노출되도록 한다. 이때, 하프 에칭부(303)를 연마하면서 상기 반도체 칩(308)의 밑면도 함께 연마될 수 있다. 변형예로, 반도체 칩(308)을 밑면이 연마되지 않도록 하기 위해서는, 미래 반도체 칩(308)을 연마된 상태로 부착하는 방식을 사용할 수도 있다. Subsequently, the upper portion of the encapsulant 314 and the half-etched portion 303 of FIG. 21 are completely polished as shown in FIG. 23 to separate the signal leads 302 in the form of protrusions from the lead frame 300, respectively. At the same time, the surface of the encapsulant 314 is exposed. In this case, the bottom surface of the semiconductor chip 308 may also be polished while the half etching portion 303 is polished. Alternatively, in order to prevent the bottom surface of the semiconductor chip 308 from being polished, a method of attaching the semiconductor chip 308 in the polished state may be used.
*또한, 상기 돌출부의 분리는 다음과 같이 수행될 수도 있다. 도 28을 참조하면, 리드프레임(300')의 돌출부(302v)의 두께가 상기 반도체 칩(308)의 두께보다 큰 상태에서 봉지재(314')에 덮여 있는 상태에서 연마가 수행되면, 도 29와 같이 상기 반도체 칩(308)의 밑면이 연마되지 않게 된다. 이 때, 상기 반도체 칩(308)은 봉지재(314A')에 의하여 덮인 상태이다.In addition, separation of the protrusion may be performed as follows. Referring to FIG. 28, when polishing is performed while the thickness of the protrusion 302v of the lead frame 300 ′ is covered by the encapsulant 314 ′ in a state where the thickness of the protrusion 302v is greater than the thickness of the semiconductor chip 308, FIG. 29. As shown, the bottom surface of the semiconductor chip 308 is not polished. At this time, the semiconductor chip 308 is covered with the encapsulant 314A '.
다시 도 24를 참조하면, 절연막(316)을 도포한 후, 이를 패터닝하여 신호리드(302)가 노출되게 한 후, 상기 절연막(316) 상부에 금속막을 블랭킷(blanket) 방식으로 형성한 후, 이를 패터닝하여 신호리드(302)와 전기적으로 연결된 상부 금속패드(320)를 형성한다. 상기 상부 금속패드(320)는 팬-아웃 반도체 패키지를 상하 방향으로 적층하여 패키지 온 패키지(POP)를 만드는 공정에서 수직 연결 통로의 역할을 수행할 수 있다. 그 후, 반도체 칩(308) 및 신호리드(302)의 고정을 위해 사용된 제1 베이스(312)를 떼어내어 제거한다. 다만, 상기 상부 금속패드(320)의 형성 전에, 단일 또는 복수 층의 상부 금속 패턴(미도시)을 더 형성할 수도 있다.Referring again to FIG. 24, after the insulating film 316 is coated and patterned, the signal lead 302 is exposed, and then a metal film is formed on the insulating film 316 in a blanket manner. Patterning forms an upper metal pad 320 electrically connected to the signal lead 302. The upper metal pad 320 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to make a package on package (POP). Thereafter, the first base 312 used for fixing the semiconductor chip 308 and the signal lead 302 is removed and removed. However, before the upper metal pad 320 is formed, a single or multiple layers of upper metal patterns (not shown) may be further formed.
도 25를 참조하면, 상기 제1 베이스(312)를 제거한 면에 노출된 본드패드(310)와 신호리드(302)가 있는 전면에 다른 절연막(322)을 형성하고 이를 패터닝하여 상기 본드패드(310)와 신호리드(302)가 외부로 노출되게 한다. 그리고 상기 노출된 본드패드(310)와 신호리드(302)가 있는 절연막(322) 위에 상기 본드패드(310)와 신호리드(302)를 연결하는 하부 금속패턴(324), 예컨대 재배선 금속패턴을 형성한다. 본 실시예에서는, 하부 금속패턴(324)이 단일층으로 형성되어 있지만, 본 발명은 이에 한정되지 않고, 복수 층으로 형성될 수도 있다. 상기 재배선 금속패턴(324)은 반도체 칩에 형성된 본드패드(310)의 배열을 반도체 칩(308) 외곽에 형성된 신호리드(302)까지 확장시켜 팬-아웃 반도체 패키지를 만드는 주요 수단이 된다.Referring to FIG. 25, another bond layer 310 is formed on the entire surface of the bond pad 310 and the signal lead 302 exposed to the surface from which the first base 312 is removed, and then patterned to form the bond pad 310. ) And the signal lead 302 are exposed to the outside. The lower metal pattern 324 connecting the bond pad 310 and the signal lead 302 to the insulating layer 322 including the exposed bond pad 310 and the signal lead 302 may be formed. Form. In the present embodiment, the lower metal pattern 324 is formed as a single layer, but the present invention is not limited thereto and may be formed as a plurality of layers. The redistribution metal pattern 324 extends the arrangement of the bond pads 310 formed on the semiconductor chip to the signal lead 302 formed on the outside of the semiconductor chip 308, thereby becoming a main means for making a fan-out semiconductor package.
이어서 상기 하부 금속패턴(324)이 형성된 결과물 전면에 절연막(322) 패턴을 형성하고 상기 하부 금속패턴(324)과 상하 방향으로 연결되고 절연막(322) 패턴에 의해 외부로 노출된 하부 금속패드(326)를 형성한다. 상기 절연막(322)은 동일 재질 혹은 다른 재질로 만들어진 다층 구조의 박막일 수 있다. 그 후, 그리고 하부 금속패드(326)에 도전성 연결단자(328), 예컨대 솔더볼이나 솔더 범프(bump)를 부착한다. 그리고 다이아몬드 재질의 블레이드(blade) 등을 사용하여 각각의 리드프레임을 절단(330)하여 리드프레임 스트립에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정을 진행한다. 상기 싱귤레이션 공정은 블레이드 대신에 펀치(punch)를 사용한 절단을 진행하거나, 레이저(LASER)를 사용한 절단을 진행할 수도 있다.Subsequently, an insulating film 322 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 324 is formed, and the lower metal pad 326 connected to the lower metal pattern 324 in the vertical direction and exposed to the outside by the insulating film 322 pattern. ). The insulating layer 322 may be a thin film having a multilayer structure made of the same material or different materials. Then, a conductive connector 328, for example, solder balls or solder bumps, is attached to the lower metal pad 326. Then, each lead frame is cut 330 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip. In the singulation process, cutting may be performed using a punch instead of a blade, or cutting may be performed using a laser.
한편, 본 실시예에 의한 신호리드(도 21의 302)는, 봉지재(314) 내부에 별도의 비아 홀(via hole)이나 비아 콘택(via contact)을 형성하지 않고도 반도체 패키지의 상하를 관통하는 수직형 연결단자로 사용할 수 있다. 이러한 구조는 두 개의 반도체 패키지를 수직으로 쌓아 만드는 패키지 온 패키지(POP)에서 신호 연결에 유리한 장점이 있다.Meanwhile, the signal lead 302 of FIG. 21 penetrates up and down the semiconductor package without forming a separate via hole or via contact inside the encapsulant 314. It can be used as a vertical connector. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
도 26은 도 25의 싱귤레이션 공정에 의해 제조가 완료된 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지의 단면도이다.FIG. 26 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention, which is manufactured by the singulation process of FIG. 25.
도 26을 참조하면, 본 발명의 제3 실시예에 의한 리드프레임을 이용한 팬-아웃 반도체 패키지(340)는, 반도체 칩(도 23의 308)과, 상기 반도체 칩의 외곽을 감싸며 상기 반도체 칩과 동일 높이를 갖는 봉지재(도 23의 314A)와, 상기 봉지재 내부에 포함되며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드(도 23의 302)와, 상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴(324)과, 상기 재배선 금속패턴과 연결된 재배선 금속패드(326) 및 상기 재배선 금속패드(326)에 부착된 도전성 연결단자(328)를 포함하여 구성된다. Referring to FIG. 26, a fan-out semiconductor package 340 using a lead frame according to a third embodiment of the present invention may include a semiconductor chip (308 of FIG. 23), an outer surface of the semiconductor chip, and a semiconductor chip; 23 (314A in FIG. 23) having the same height, a plurality of signal leads (302 in FIG. 23) of lead frame material included in the encapsulant and penetrating the encapsulant vertically, and the semiconductor chip. A redistribution metal pattern 324 connecting the bond pad and the signal lead, a redistribution metal pad 326 connected to the redistribution metal pattern, and a conductive connection terminal 328 attached to the redistribution metal pad 326. It is configured to include).
여기서 상기 신호리드(302)는 봉지재(314A) 내부에 별도의 비아 홀(via hole)이나 비아 콘택(via contact)을 형성하지 않고도 반도체 패키지의 상하를 관통하는 수직형 연결단자로 사용할 수 있다. 이러한 구조는 두 개의 반도체 패키지를 수직으로 쌓아 만드는 패키지 온 패키지(POP)에서 신호연결에 유리한 장점이 있다.The signal lead 302 may be used as a vertical connection terminal penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact in the encapsulant 314A. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.
도 27을 참조하면, 도 26에 도시된 리드프레임을 이용한 제1,2 패키지(340B, 340A)를 상하로 적층하여 패키지 온 패키지(POP)를 제조한 단면이다. 이때, 상기 제1 반도체 패키지(340B)의 신호리드 상부에 상부 금속패드(320)를 만들지 않을 수도 있다. 또한 상기 제2 반도체 패키지(340A) 및 상기 제2 반도체 패키지(340B)는 상기 제2 반도체 패키지(340A)의 도전성 연결단자(328)에 의해 서로 물리적 및 전기적으로 연결되어 있다. 상기 도전성 연결단자(328)가 솔더볼이나 솔더범프일 경우, 상부 금속패드(320) 및 하부 금속패드(326)에는 UBM이 더 형성될 수도 있다.Referring to FIG. 27, a package on package POP is manufactured by stacking first and second packages 340B and 340A up and down using the lead frame illustrated in FIG. 26. In this case, the upper metal pad 320 may not be formed on the signal lead of the first semiconductor package 340B. In addition, the second semiconductor package 340A and the second semiconductor package 340B are physically and electrically connected to each other by the conductive connection terminal 328 of the second semiconductor package 340A. When the conductive connection terminal 328 is solder balls or solder bumps, UBMs may be further formed on the upper metal pad 320 and the lower metal pad 326.
상기 제1 반도체 패키지(340B)와 상기 제2 반도체 패키지(340A)는 서로 실질적으로 동일한 구조를 가지지만, 본 발명은 이에 한정되지 않고, 서로 다른 크기 및 기능을 가질 수도 있다.Although the first semiconductor package 340B and the second semiconductor package 340A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.
한편, 상기 제2 반도체 패키지(340A)에 상부 금속패드가 형성된 경우, 저항, 커패시터 등과 같은 수동소자(330)를 추가로 부착하여 패키지 온 패키지의 기능을 개선할 수 있다.Meanwhile, when the upper metal pad is formed on the second semiconductor package 340A, a passive element 330 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.
본 발명을 이용하면, 단순한 제조 공정으로서 패키지 온 패키지(POP)를 제조할 수 있다.By using the present invention, a package on package (POP) can be manufactured as a simple manufacturing process.

Claims (21)

  1. 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 복수개의 신호리드를 갖는 스트립 상태의 리드프레임을 준비하는 단계;Preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in the center and having a plurality of signal leads in the periphery;
    상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계;Attaching the lead frame to a first base and mounting a semiconductor chip on the first base through an opening of the lead frame;
    상기 제1 베이스 위의 상기 반도체 칩 및 리드프레임을 봉지재로 밀봉하고 제1 베이스를 제거하는 단계;Sealing the semiconductor chip and the lead frame on the first base with an encapsulant and removing the first base;
    상기 봉지재 및 반도체 칩 위에 절연막을 형성하고 상기 봉지재의 리드 및 반도체 칩의 본드패드를 노출하는 패터닝을 진행하는 단계;Forming an insulating film on the encapsulant and the semiconductor chip and performing patterning to expose the lead of the encapsulant and the bond pad of the semiconductor chip;
    상기 노출된 신호리드와 본드패드를 연결하는 재배선 금속패턴을 형성하고 상부에 절연막 패턴을 형성하여 상기 재배선 금속패턴의 일부를 노출하는 재배선 금속패드 형성하는 단계: Forming a redistribution metal pad connecting the exposed signal leads and the bond pad and forming an insulating layer pattern thereon to expose a portion of the redistribution metal pattern;
    상기 노출된 재배선 금속패드에 도전성 연결 단자 부착하는 단계; 및Attaching a conductive connection terminal to the exposed redistribution metal pad; And
    상기 리드프레임 스트립에서 단위 반도체 패키지를 분리함과 동시에 개개의 신호라인을 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법. And a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines.
  2. 청구항 1에 있어서, The method according to claim 1,
    상기 반도체 칩을 상기 제1 베이스 위에 탑재하는 방법은,The method for mounting the semiconductor chip on the first base,
    상기 반도체 칩에서 회로부가 형성된 활성영역이 아래로 향하도록 탑재하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.The method of manufacturing a fan-out semiconductor package using a lead frame, characterized in that mounted in the semiconductor chip so that the active region in which the circuit portion is formed to face downward.
  3. 청구항 2에 있어서, The method according to claim 2,
    상기 제1 베이스를 제거하는 단계 후,After removing the first base,
    상기 봉지재 및 반도체 칩의 활성영역이 형성된 면의 반대면에 제2 베이스를 부착하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법. And attaching a second base to a surface opposite to a surface on which the encapsulant and the active region of the semiconductor chip are formed.
  4. 청구항 3에 있어서, The method according to claim 3,
    상기 도전성 연결단자를 부착하는 단계 후,After attaching the conductive connection terminal,
    상기 제2 베이스를 제거하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.Removing the second base further comprises the step of manufacturing a fan-out semiconductor package using a lead frame.
  5. 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 복수개의 신호리드를 포함하고 상기 신호리드에는 하프 에칭에 의한 돌출부가 마련된 스트립 상태의 리드프레임을 준비하는 단계;Preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in a center thereof, including a plurality of signal leads around the signal lead, and a protrusion formed by half etching;
    상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계;Attaching the lead frame to a first base and mounting a semiconductor chip on the first base through an opening of the lead frame;
    상기 리드프레임의 돌출부 및 상기 반도체 칩의 밑면만을 외부로 노출시키는 몰딩 공정을 진행하고, 상기 제1 베이스를 제거하는 단계; Performing a molding process of exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip to the outside, and removing the first base;
    상기 결과물에서 돌출부가 형성된 반대면 전체에 절연막 패턴을 형성하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 외부로 노출하는 단계;Exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside by forming an insulating film pattern on the entire opposite surface on which the protrusion is formed;
    상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결하는 하부 금속패턴을 형성하는 단계;Forming a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip;
    상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 형성하는 단계;Forming an insulating film pattern on an entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern;
    상기 하부 금속패드 위에 도전성 연결단자를 부착하는 단계; 및Attaching a conductive connection terminal to the lower metal pad; And
    상기 리드프레임 스트립에서 단위 반도체 패키지를 분리함과 동시에 개개의 신호라인을 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법. And a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines.
  6. 청구항 5에 있어서, The method according to claim 5,
    상기 리드프레임의 돌출부 및 상기 반도체 칩의 밑면만을 외부로 노출시키는 몰딩 공정을 진행하는 방법은,The method of performing a molding process of exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip to the outside,
    봉지재를 상기 리드프레임의 돌출부 및 반도체 칩의 밑면을 덮도록 몰딩하는 단계; 및Molding an encapsulant to cover the protrusion of the lead frame and the bottom surface of the semiconductor chip; And
    상기 리드프레임의 돌출부 및 반도체 칩의 밑면이 노출되도록 상기 봉지재를 연마하는 단계를 포함하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.And polishing the encapsulant such that the protrusion of the lead frame and the bottom surface of the semiconductor chip are exposed.
  7. 청구항 5에 있어서, The method according to claim 5,
    상기 리드프레임의 돌출부 및 상기 반도체 칩의 밑면만을 노출시키는 몰딩 공정 후, 상기 제1 베이스를 제거하기 전에, After the molding process exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip, before removing the first base,
    상기 노출된 리드프레임의 돌출부에 상부 금속패드를 형성하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of forming an upper metal pad on the exposed protrusion of the lead frame.
  8. 청구항 5 또는 청구항 7에 있어서The method according to claim 5 or 7
    상기 싱귤레이션 공정 후에,After the singulation process,
    상기 싱귤레이션이 진행된 두 개의 반도체 패키지를 상기 도전성 연결단자를 이용하여 상하로 탑재하여 패키지 온 패키지(POP)를 제조하는 단계를 더 진행하는 것을 특징으로 하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.Mounting the two semiconductor packages subjected to the singulation up and down using the conductive connection terminal to further manufacture a package on package (POP), characterized in that the fan-out using the lead frame Semiconductor package manufacturing method.
  9. 청구항 8에 있어서, The method according to claim 8,
    상기 패키지 온 패키지에서 상부 반도체 패키지의 상부 금속패드 위에 수동소자를 탑재하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of mounting the passive element on the upper metal pad of the upper semiconductor package in the package on package.
  10. 중앙에 반도체 칩이 안착될 수 있는 개구부가 마련되고 주변에 신호리드가 하프 에칭에 의한 돌출부의 형태로 마련된 스트립 상태의 리드프레임을 준비하는 단계;Preparing a lead frame in a strip state in which an opening in which a semiconductor chip is mounted is provided at a center thereof, and a signal lead is formed in the form of a protrusion by half etching;
    상기 리드프레임을 제1 베이스에 부착하고, 상기 리드프레임의 개구부를 통해 상기 제1 베이스 위에 반도체 칩을 탑재하는 단계;Attaching the lead frame to a first base and mounting a semiconductor chip on the first base through an opening of the lead frame;
    상기 반도체 칩 및 리드프레임을 완전히 밀봉하는 봉지재를 형성하는 단계;Forming an encapsulant which completely seals the semiconductor chip and the lead frame;
    상기 봉지재 및 리드프레임의 하프 에칭부를 연마하여 신호리드를 분리하여 노출시키고 상기 제1 베이스를 제거하는 단계;Grinding the half-etched portion of the encapsulant and lead frame to separate and expose the signal leads and to remove the first base;
    상기 결과물에서 상기 제1 베이스가 제거된 방향의 전면에 절연막 패턴을 형성하여 상기 리드프레임의 신호리드 및 반도체 칩의 본드패드를 노출시키는 단계;Forming an insulating film pattern on the entire surface of the resultant in the direction in which the first base is removed to expose the signal lead of the lead frame and the bond pad of the semiconductor chip;
    상기 리드프레임의 신호리드 및 반도체 칩의 본드 패드를 연결하는 하부 금속패턴을 형성하는 단계;Forming a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip;
    상기 하부 금속패턴이 형성된 결과물 전면에 절연막 패턴을 형성하고 상기 하부 금속패턴과 연결되고 절연막 패턴에 의해 외부로 노출된 하부 금속패드를 형성하는 단계;Forming an insulating film pattern on an entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern;
    상기 하부 금속패드 위에 도전성 연결단자를 부착하는 단계; 및Attaching a conductive connection terminal to the lower metal pad; And
    상기 리드프레임 스트립에서 단위 반도체 패키지를 분리하는 싱귤레이션 공정을 진행하는 단계를 포함하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.And a singulation process of separating the unit semiconductor package from the lead frame strip.
  11. 청구항 10에 있어서, The method according to claim 10,
    상기 리드프레임 및 상기 반도체 칩을 상기 제1 베이스에 부착하는 방법은,The method of attaching the lead frame and the semiconductor chip to the first base,
    상기 리드프레임의 돌출부가 아래로 향하고, 상기 반도체 칩에서 회로부가 형성된 활성영역이 아래로 향하도록 부착하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.And attaching the protrusion of the lead frame downward and the active region in which the circuit portion is formed in the semiconductor chip to face downward.
  12. 청구항 10에 있어서, The method according to claim 10,
    상기 봉지재 및 리드프레임의 하프 에칭부를 연마하여 신호리드를 분리하는 방법은,The method for separating the signal lead by grinding the half etching portion of the encapsulant and the lead frame,
    중앙에 탑재된 반도체 칩의 밑면도 함께 연마하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.A method of manufacturing a fan-out semiconductor package using a lead frame, wherein the bottom surface of the semiconductor chip mounted in the center is also polished.
  13. 청구항 10에 있어서, The method according to claim 10,
    상기 봉지재 및 리드프레임의 하프 에칭부를 연마하여 신호리드를 분리하여 노출시키는 단계 후, 상기 제1 베이스를 제거하는 단계 전에,After polishing the half-etched portion of the encapsulant and the lead frame by separating and exposing the signal leads, and before removing the first base,
    상기 노출된 신호리드 위에 상부 금속패드를 형성하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of forming an upper metal pad on the exposed signal lead.
  14. 청구항 10 또는 청구항 13에 있어서, The method according to claim 10 or 13,
    상기 싱귤레이션 공정 후에,After the singulation process,
    상기 싱귤레이션이 진행된 두 개의 반도체 패키지를 상기 도전성 연결단자를 이용하여 상하로 탑재하여 패키지 온 패키지(POP)를 제조하는 단계를 더 진행하는 것을 특징으로 하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.Mounting the two semiconductor packages subjected to the singulation up and down using the conductive connection terminal to further manufacture a package on package (POP), characterized in that the fan-out using the lead frame Semiconductor package manufacturing method.
  15. 청구항 14에 있어서, The method according to claim 14,
    상기 패키지 온 패키지에서 상부 반도체 패키지의 상부 금속패드 위에 수동소자를 탑재하는 단계를 더 진행하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법.The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of mounting the passive element on the upper metal pad of the upper semiconductor package in the package on package.
  16. 반도체 칩;Semiconductor chips;
    상기 반도체 칩의 밑면 및 외곽을 감싸는 봉지재;Encapsulation material surrounding the bottom and the outer surface of the semiconductor chip;
    상기 봉지재 내부에 위치한 리드프레임 재질의 복수개의 신호리드;A plurality of signal leads of a lead frame material located inside the encapsulant;
    상기 반도체 칩의 본드패드와 상기 리드프레임 재질의 복수개의 신호리드를 연결하는 재배선 금속패턴; A redistribution metal pattern connecting the bond pad of the semiconductor chip and the plurality of signal leads of the lead frame material;
    상기 재배선 금속패턴과 연결된 재배선 금속패드; 및A redistribution metal pad connected to the redistribution metal pattern; And
    상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지.And a conductive connection terminal attached to the redistribution metal pad.
  17. 반도체 칩;Semiconductor chips;
    상기 반도체 칩의 외곽을 감싸며, 상기 반도체 칩과 동일 높이를 갖는 봉지재;An encapsulation material surrounding an outer edge of the semiconductor chip and having the same height as the semiconductor chip;
    상기 봉지재 내부에 위치하며 봉지재를 상하 방향으로 관통하는 형태의 리드프레임 재질의 복수개의 신호리드;A plurality of signal leads made of a lead frame material positioned inside the encapsulant and penetrating the encapsulant in an up and down direction;
    상기 반도체 칩의 본드패드와 상기 신호리드를 연결하는 재배선 금속패턴;A redistribution metal pattern connecting the bond pad of the semiconductor chip and the signal lead;
    상기 재배선 금속패턴과 연결된 재배선 금속패드; 및A redistribution metal pad connected to the redistribution metal pattern; And
    상기 재배선 금속패드에 부착된 도전성 연결단자를 구비하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지.And a conductive connection terminal attached to the redistribution metal pad.
  18. 청구항 17에 있어서, The method according to claim 17,
    상기 팬-아웃 반도체 패키지는,The fan-out semiconductor package,
    상기 재배선 금속패턴과 연결되는 반대 방향의 신호리드에 형성된 상하 연결형 상부 금속패드를 더 구비하는 것을 특징으로 하는 리드프레임을 이용한 팬-아웃 반도체 패키지.The fan-out semiconductor package using a lead frame further comprises a vertically connected upper metal pad formed on the signal lead in the opposite direction connected to the redistribution metal pattern.
  19. 청구항 17에 기재된 제1 반도체 패키지; 및A first semiconductor package according to claim 17; And
    상기 제1 반도체 패키지 위에 도전성 연결단자를 통해 탑재되고, 청구항 17에 기재된 제2 반도체 패키지를 구비하는 것을 특징으로 하는 패키지 온 패키지(POP).A package on package (POP) mounted on the first semiconductor package via a conductive connection terminal, comprising a second semiconductor package according to claim 17.
  20. 청구항 19에 있어서, The method according to claim 19,
    상기 제1 및 제2 반도체 패키지는,The first and second semiconductor packages,
    상기 재배선 금속패턴과 연결되는 반대 방향의 신호리드에 형성된 상하 연결형 상부 금속패드를 더 구비하는 것을 특징으로 하는 패키지 온 패키지(POP).The package on package (POP) characterized in that it further comprises a vertically connected upper metal pad formed on the signal lead in the opposite direction connected to the redistribution metal pattern.
  21. 청구항 19에 있어서,The method according to claim 19,
    상기 제2 반도체 패키지는 상기 제1 반도체 패키지와 동일 구조를 갖는 것을 특징으로 하는 패키지 온 패키지(POP).The second semiconductor package has the same structure as the first semiconductor package, the package on package (POP).
PCT/KR2011/009049 2011-11-03 2011-11-25 Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same WO2013065895A1 (en)

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