WO2013060737A1

WO2013060737A1 - Thin film transistor

Info

Publication number: WO2013060737A1
Application number: PCT/EP2012/071075
Authority: WO
Inventors: Michael Jank; Erik TEUBER; Martin LEMBERGER; Jiaye Huang
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 2011-10-24
Filing date: 2012-10-24
Publication date: 2013-05-02
Also published as: DE102011085114A1; DE102011085114B4

Abstract

A thin film transistor comprises a first electrode, a second electrode, a control electrode, an insulator layer and a semiconductor thin film configured on a substrate. The control electrode adjoins the insulator layer on one side, and the semiconductor thin film adjoins the insulator layer on an opposite side. The first and second electrodes adjoin the semiconductor thin film. A channel in the semiconductor film through which an electrical resistance between the first and second electrodes is reduced can be controlled by varying the potential of the control electrode. A section of the first electrode adjoining the semiconductor thin film is arranged on a side of the semiconductor thin film facing the substrate, and a section of the second electrode adjoining the semiconductor thin film is arranged on a side of the semiconductor thin film facing away from the substrate. In addition, a thickness of at least the first electrode or the second electrode is greater than half the thickness of the semiconductor film.

Description

Thin film transistor

description

Embodiments of the present invention relate to a thin film transistor and a method of manufacturing the same. In the prior art, thin film transistors can be used for various devices, such as displays, lighting elements, detector arrays, switches, or memories.

A known embodiment of a thin-film transistor 700 is shown by way of example in FIG. Fig. 7 shows an exemplary construction of a bottom-gate thin-film transistor. Referring to Fig. 7, known thin film transistors consist of a semiconductor thin film 703 contacted by two metal electrodes (source 701-1 and drain 701-2). A third electrode (gate 704) is deposited by an insulator 705 separated from the semiconductor thin film 703 and / or the other electrodes (source and drain electrodes 701-1, 701-2), and serves to form the semiconductor (semiconductor thin film 703). between the source and drain electrodes 701-1, 701-2 to modulate in its conductivity. The fabrication of thin film transistors is independent of substrate material or substrate 709. Typically, thin film transistors are fabricated on insulator materials such as glass, ceramic, or plastic substrates.

In the fabrication of thin film transistors, it is desirable to maximize the controllable current (In) between drain and source. The higher the current is in the on state, the faster circuits can operate, or the smaller the devices can be made to achieve comparable current levels. The current ID between the source and drain of a thin film transistor is determined inter alia by the geometric dimensions, such as width W and length L of the channel (see Fig. 7). From the possible operating states of the conductive transistor (linear region, triode and saturation region), the dependence of the current I _D between drain and source on the geometry, in particular the proportionality of the current ID to the width-to-length ratio (W / L ) of the transistor, and represent according to the following equation: ^D L

That is, the smaller the channel length L of the transistor is made, the larger the controllable current ID between drain and source can be.

For the construction of thin-film transistors, there are the exemplary embodiments shown by way of example in FIGS. 8a to 8d. 8a-8d are a known stacked top-gate thin-film transistor (FIG. 8a), a known stacked bottom-gate thin-film transistor (FIG. 8b), a known coplanar top-gate thin-film transistor (FIG. 8c), and FIG known coplanar bottom-gate thin film transistor (Figure 8d).

The transistors or components shown in FIGS. 8a to 8d differ on the one hand with respect to their top or bottom gate architectures. The use of top or bottom gate architectures primarily affects the formation of the interfaces between the respective thin films used. Moreover, the distinction between the devices in terms of their top or bottom-gate architectures is essentially irrelevant to the electrical properties of the devices.

On the other hand, the transistors or components shown in FIGS. 8a to 8d differ in terms of their stacked or coplanar architectures. The following describes the distinction between stacked and coplanar architecture. In the stacked architecture (Figures 8a, 8b), the source and drain contacts 801-1, 801-2 are not directly on or under the gate insulator (insulator layer 705) but are through the semiconductor thin film 703 thereof separated. As shown in Figs. 8a, 8b, a stack of source and drain contacts 801-1, 801-2 (S / D contact), semiconductors 703, insulator 705, and gate electrode 704 are formed. Assuming a formation of a channel at the insulator / semiconductor interface, this has the consequence that the current from the source or drain contact through the semiconductor must flow into the channel or back to the complementary contact. The generally poorly conductive semiconductor thin film in this case forms an undesirable series resistance, which can be minimized by a large-area design of the contact and the use of a thin semiconductor thin film. In contrast, in the coplanar structure (Figures 8c, 8d), the source and drain contacts 802-1, 802-2 are directly on or under the insulator 705. That is, the source and drain contacts 802-1 , 802-2 in this case adjoin a side of the insulator 705 facing the semiconductor 703 or an opposing insulator interface. The interfaces between source / drain electrodes and insulator are also in one plane with the channel. Although this means that in contrast to the stacked transistor or in the stacked contacts no series resistance occurs. However, due to the typically very small channel thickness, the contact area between the source and drain electrodes and the channel is so small that the coplanar contacts can dominate the electrical properties of the entire device. As a result, on the one hand, an increased series resistance can also result. On the other hand, in the case of rectifying contacts (eg, Schottky contact electrode channel) by the antiserial contact-channel contact arrangement, in any case the characteristic amp having the lower current carrying capacity (ie, the stopband) of one of the contacts will dominate the overall device characteristics.

In the following, various known concepts for defining the gate length will be described. As can be seen from FIGS. 8a to 8d, the source and drain contacts lie in one plane in all the thin-film transistors shown. They are defined either by blanket deposition of a metal film and subsequent structuring (subtractive processing) or by additive application, such as by means of printing processes. In the subtractive processing z. Example, a deposition of photoresist, an exposure, a development of the photoresist, an etching of the metal layer with the photoresist as a mask and a removal of the photoresist.

Limitations on channel length reduction are mainly due to the resolving power of the contact manufacturing process. Which method is chosen here depends essentially on economic aspects. As a rule, costs and costs increase significantly with the resolution. Significant techniques for exposure (see above) in the subtractive patterning technique are, for example, contact / proximity exposure (Mask Aligner), laser direct writing, projection exposure, nanoimprinting, and electron or ion beam direct writing. The techniques are widely available, such as B. in microelectronics production. However, the resolving power greatly increases the demands on the process environment and costs.

In the case of additive structuring techniques in which the shape definition is given by the structured deposition, the essential techniques are, for example, the masked deposition by vapor deposition, sputtering, aerosol and plasma spray through a stencil mask, all printing processes, especially screen printing, inkjet printing, letterpress printing ( Flexographic printing), gravure printing (engraving, Pad printing), offset printing and methods derived therefrom, as well as soft lithographic processes (microcontact printing, micro molding, soft imprinting).

Known techniques for reducing the distance between source and drain contact in thin film transistors with the aim of increasing the drain currents are essentially concerned with reducing the achievable distance between the source and drain electrodes. This was e.g. realized by measures to increase the resolution of the manufacturing process. Known measures for increasing the resolution in the production processes are described, for example, in Sekitani et al, PNAS, vol. 105, pages 4976-4980, 2008 and in Ante et al. IEDM 2010, Tech. Dig., P. 516. A disadvantage with the measures described there is that the source / drain distance must remain finite, since source and drain lie in one level. Furthermore, disadvantages of the coplanar structure (see, eg, Fig. 2d, 6b in Ante et al.) May result, among other things.

Furthermore, in the case of printing techniques, short channel lengths can be achieved by introducing a known self-aligning pattern. In US Pat. No. 6,808,972 B2, US Pat. No. 7,244,669 B2 and US Pat. No. 7,482,207 B2, for example, a prestructuring of trenches is described. A disadvantage of the techniques described therein is that the source and drain again lie in one plane, resulting in a finite gate length. Furthermore, such techniques are described in US 2006/0160277 AI and US 2007/0018151 AI. A disadvantage of the techniques described therein is that the source / drain distance must remain finite, since source and drain lie in one plane. For the structuring of the hydrophobic / oleophobic area, an alternative high-resolution method must also be used. In addition, there may be disadvantages of the coplanar structure. Furthermore, such a technique is described in US Pat. No. 7,407,849 B2. The technique described there is disadvantageous in that the source / drain distance must remain finite, since the source and drain again lie in one plane. In addition, there may be disadvantages of the coplanar structure. Finally, such techniques are described in US 6,838,361 B2, US 2008/0042200 AI and US 2008/0054257 AI. The techniques described there again have the disadvantage that the source / drain distance must remain finite, since source and drain lie in one plane. There may be disadvantages of the coplanar structure.

In addition, by known techniques for the ("linear") vertical placement of the transistor structure at steps or edges, the fabrication of transistors becomes shorter Channel length allows. In N. Stutzmann et al., Science Vol. 299, p. 1881, 2003, for example, such a technique is described. A disadvantage of the technique described therein is that the thickness of the semiconductor thin film should ideally be on the order of the channel depth. However, this can not be made arbitrarily thin here, since the source and drain contacts must have a sufficient extent. As a result, the structure made using the technique described therein can expect high source / drain leakage currents. Furthermore, KR 20050001936 A (see, eg, Figures 4 and 5a-5c) describes such a technique. However, the arrangement of the semiconductor thin film in KR 20050001936 A is such as to produce substantially a stacked top gate structure rotated by 90 °. The technique described there again has the disadvantage that the source / drain contacts lie in one plane. Furthermore, due to a minimum expansion of the metal contacts, a minimum thickness for the isolating insulator must be selected (= gate length). It should be noted that the thicker the insulator is, the longer the channel.

Further, in US 2010/0019231 Al, a known technique for a structure similar or partly identical to the construction shown in KR 20050001936 A is described. The disadvantages of the technique mentioned there are comparable to those mentioned above. US 2010/0019231 A1 describes in paragraph [0083] the structuring of an underlying material over the (and relative to) the metal electrode (here, however, insulator and non-alternative metal). Furthermore, in paragraph [0075] and with reference to FIGS. 3 a and 3 c, the enlargement of the gate width is described by a serpentine-like interlacing. Another known concept is based on the implementation of the transistor as a ("planar") vertical component. Such a known concept is described, for example, in L. Ma, Y. Yang, Appl. Phys. Lett. Vol. 85, no. 21, p. 5084, Nov. 2004 and US 2009/008634 AI. By L. Ma, Y. Yang, Appl. Phys. Lett. Vol. 85, no. 21, p. 5084, Nov. 2004, a Schottky contact is selectively generated at the source contact, while the drain contact is not described. Disadvantages of the concept described there are that a perforated source is realized with cumbersome, difficult to control technology. Furthermore, source and drain inevitably overlap. This leakage currents are difficult to control due to the strong overlap. Incidentally, the structure shown there is produced with elaborate techniques.

US 2009/0008634 AI attacks the work of L. Ma, Y. Yang, Appl. Phys. Lett. Vol. 85, no. 21, p 5084, Nov. 2004 and realizes the perforated electrode with elaborate, such. B. soft lithographic or self-aligned method (see para. [0028]). This in The concept described in US 2009/0008634 A1 in turn has the disadvantages that it is realized with cumbersome or complex techniques. Source and drain inevitably overlap. In addition, leakage currents are difficult to control. It is described in US 2009/0008634 A1 (see paragraphs [0046], [0049], [0053] or [0054]) that the source and drain electrodes are arranged in different layers, wherein either source or drain perforates like a grid or have to be structured like a strip. For the optimum size of the openings, the dimension of the semiconductor thin film thickness is given approximately. In paragraph [0054], the function is differentiated from Ma et al. described. Further, in paragraph [0055], the device function due to the use of organic semiconductors will be described. In paragraph [0056] and with reference to FIGS. 3b and 3c, the use of the grid-like lower electrode for large openings in the electrode grid is described and a similarity to a top contact bottom-gate TFT (thin-film transistor) is indicated. In paragraph [0093] the component is described again. Paragraph [0120] describes the use of insulator layers on the conductive structures in the channel, but this refers to the lateral transistor (channel length truncation) described in parallel and not to the vertical transistor. The purpose of the insulators is therefore not the leakage current suppression. According to the US 2009/0008634 AI source and drain are in different levels, but this refers to a regular (array) structured electrode. Furthermore, the insertion of an additional structure between the source and the semiconductor is described, but the whole-area electrode is the source. This makes the additional layer dispensable, at least in the case of an insulator / dielectric, and in addition the function of the additional layer is described only vaguely (optimization of the injection).

A general problem of the known concepts described above is thus that in the known lateral components, the channel length is typically limited by the resolving power and an optimization of the controllable current or the improvement of the electrical properties is difficult. Furthermore, in the known vertical components, leakage currents typically occur in the switched-off state (leakage current paths), which can impair the function of the components. The known vertical components are also characterized by complex process control or complicated production processes or have limitations in terms of functionality (eg series resistance in the case of ultrathin source or drain electrodes). The object of the present invention is therefore to provide a thin-film transistor which enables a reduction in the channel length and at the same time is distinguished by improved electrical properties. This object is achieved by a thin-film transistor according to claim 1.

Embodiments of the present invention provide a thin film transistor having a first electrode, a second electrode, a control electrode, an insulator layer, and a semiconductor thin film formed on a substrate. The control electrode adjoins the insulator layer on one side, and the semiconductor thin film adjoins the insulator layer on an opposite side. The first and second electrodes abut the semiconductor thin film. By varying the potential at the control electrode, a channel can be formed or driven in the semiconductor thin film, by means of which an electrical resistance between the first and second electrodes can be controlled or reduced. Here, a portion of the first electrode adjacent to the semiconductor thin film is disposed on a side of the semiconductor thin film facing the substrate, and a portion of the second electrode adjacent to the semiconductor thin film is disposed on a side of the semiconductor thin film remote from the substrate. Further, a thickness of at least one of the first electrode and the second electrode is larger than half the thickness of the semiconductor thin film.

The gist of the present invention is that the above-mentioned reduction of the channel length can be achieved with simultaneously improved electrical characteristics of the thin-film transistor, when a portion of the first electrode adjacent to the semiconductor thin film is disposed on a side of the semiconductor thin film facing the substrate and a to the semiconductor thin film adjacent portion of the second electrode is disposed on a side facing away from the substrate side of the semiconductor thin film, wherein a thickness of at least one of the first electrode and the second electrode is greater than half the thickness of the semiconductor thin film. As a result, the channel length can be reduced below the resolution limit set by the known techniques, and the controllable current can be optimized or set better. Thus, on the one hand, the reduction of the channel length can be achieved, and on the other hand, at the same time an optimization of the controllable current or the improvement of the electrical properties of the thin-film transistor can be achieved. In this case, use can be made of a special arrangement of sections of the first and the second electrode on a side of the semiconductor thin film facing away from the substrate and a suitable one Ratio between the thickness of the first and second electrodes and the thickness of the semiconductor thin film can be used.

Embodiments of the present invention will be explained in more detail below with reference to the accompanying figures, in which identical or equivalent elements are designated by the same reference numerals. Show it:

1a, b are side views of thin film transistors according to embodiments of the present invention;

Fig. 2a, b are side views of thin film transistors according to others

Embodiments of the present invention; 3a-c are side views of thin film transistors according to others

Embodiments of the present invention;

Fig. 4a, b are side views of thin film transistors according to others

Embodiments of the present invention;

4c-g are side views of thin film transistors according to others

Embodiments of the present invention;

5 a, b are plan views of electrodes of thin film transistors according to

Embodiments of the present invention;

5 c is a plan view of electrodes of a thin film transistor according to another embodiment of the present invention; Fig. 6a is a side view of an embodiment of a means of pressure and

Spray method produced thin film transistor;

Fig. 6b is a plan view of the embodiment of the thin-film transistor according to

Fig. 6a;

7 is a perspective view of a known bottom-gate

Thin-film transistor according to the prior art; and 8a-d are side views of known prior art stacked and coplanar thin film transistors.

Before the present invention is explained in more detail below with reference to the figures, it is pointed out that in the exemplary embodiments illustrated below, identical elements or functionally identical elements in the figures are provided with the same reference numerals. A description of elements with the same reference numerals is therefore interchangeable and / or applicable to each other in the various embodiments.

1 a shows a side view of a thin-film transistor 100 according to an embodiment of the present invention. In Fig. 1a, a bottom-gate thin-film transistor is shown with mutually coplanar / stacked source and drain electrodes. As shown in FIG. 1a, the thin film transistor 100 (bottom gate thin film transistor) includes a first electrode 101-1, a second electrode 101-2, a control electrode 104, an insulator layer 105, and a semiconductor thin film 103 (such as a semiconductor thin film layer) , The first electrode and the second electrode 101 - 1, 101 - 2, the control electrode 104, the insulator layer 105, and the semiconductor thin film 103 are formed on a substrate 109. The control electrode 104 adjoins the insulator layer 105 on one side 112. The semiconductor thin film 103 adjoins the insulator layer 105 on an opposite side 114. The first and second electrodes 101-1, 101-2 adjoin the semiconductor thin film 103. The thin-film transistor 100 is designed such that by varying the control voltage on the control electrode 104, a channel in the semiconductor thin film 103 can be formed and controlled and removed again, by which an electrical resistance between the first and second electrodes 101-1, 101-2 controls or reduced. The channel represents a relatively thin region in the semiconductor thin film, which is substantially at least partially along the insulator / semiconductor interface 1 14 can be formed. In this case, a very high charge carrier density is typically present in the channel or the channel region. Furthermore, the channel can be formed in particular in the region which can be controlled by the control electrode or the gate electrode. The thin-film transistor 100 shown in FIG. 1a thus has a bottom-gate transistor structure. In the embodiment according to FIG. 1a, a portion 1 1 1-1 of the first electrode 101-1 adjoining the semiconductor thin film 103 is arranged on a side 116 of the semiconductor thin film 103 facing the substrate 109, while a portion 11 adjacent to the semiconductor thin film 103 is arranged 1-2 of the second electrode 101-2 a side facing away from the substrate 109 side 1 18 of the semiconductor thin film 103 is arranged. Due to the special arrangement of the sections 1 11 -1, 111-2 of the first and second electrodes 101-1, 101-2 on a side facing away from the substrate 109 or 116, 1 18 of the semiconductor thin film 103 can essentially a mutually coplanar / stacked mounted source and drain electrode configuration can be realized. For example, the first electrode 101-1 may be a source electrode and the second electrode 101-2 may be a drain electrode, or the second electrode 101-2 may be a source electrode and the first electrode 101-1 may be a drain electrode , Between the source and drain electrodes 101-1, 101-2, by applying the control voltage to the control electrode 104 or a variation of the potential of the control electrode 104, the channel in the semiconductor thin film 103 at least partially at the insulator / semiconductor interface 114 (between the insulator layer 105 and the semiconductor thin film 103). Here, the channel is not only formable, but can also be removed again. By being able to form the channel with the very high carrier density in the semiconductor thin film 103, the electrical resistance between the source and drain electrodes can be reduced. In this way, the thin film transistor can be controlled or adjusted.

In the thin-film transistor 100 shown in Fig. 1a, the thickness D of the first electrode 101-1 and the second electrode 101-2 is larger than half the thickness S of the semiconductor thin film 103. By providing a suitable ratio D / S between the thicknesses D of the first electrode and the second electrode 101-1, 101-2 and the thickness S of the semiconductor thin film 103, a current supplied from the first and second electrodes 101-1, 101-2 can be transported to the device regions without significant resistive losses. where the charge carrier injection into or extraction from the channel takes place.

In the exemplary embodiment shown in FIG. 1 a, the control electrode 104 or gate electrode is also designed as a bottom electrode (bottom-gate electrode). As shown in FIG. 1 a, the control electrode 104 is arranged on the substrate 109. Further, the insulator layer 105 and the semiconductor thin film 103 are disposed on the control electrode 104. The first and second electrodes 101-1, 101-2 are arranged such that portions thereof are adjacent to the semiconductor thin film 103 from the sides 116, 118. In embodiments, the control electrode 104 adjoins a surface of the substrate 109 on another side. Referring to FIG. 1a, in embodiments, the first electrode 101-1 is separated from the control electrode 104 by the insulator layer 105 and not the semiconductor thin film 103. This arrangement of the first electrode 101-1 substantially corresponds to a coplanar electrode of the thin film transistor 100. Further, in embodiments, the second electrode 101-2 is separated from the control electrode 104 by the insulator layer 105 and the semiconductor thin film 103. This arrangement of the second electrode 101-2 substantially corresponds to a stacked electrode of the thin film transistor 100. In the thin film transistor 100 shown in FIG. 1a, the first electrode 101-1 is designed as a coplanar electrode, while the second electrode 101-2 is configured as a stacked electrode is designed. Here, the stacked electrode may be configured to provide a substantially planar injection for the channel, while the coplanar electrode may be configured to provide a substantially point-shaped injection for the channel. For the optimization of the injection mechanisms, among other things, the selection of suitable material combinations, the optimization of the interface properties as well as the optimization of surfaces and peripheral geometries come into question. Incidentally, it should be noted that essentially only the area of the stacked electrode or the one-dimensional (ID) contact line between channel and coplanar electrode has an influence on the actual transport into the channel or out of the channel (or the injection / extraction) to have. Both are not dependent on the thickness. It should also be noted that although the area of the stacked contact is not dependent on the semiconductor thickness, but the series resistance (= area * specific resistance * thickness).

Fig. 1b shows a side view of a thin film transistor 100 according to another embodiment of the present invention. Shown in Figure 1b is a top-gate thin-film transistor with mutually coplanar / stacked source and drain electrodes. The thin-film transistor 100 shown in FIG. 1b with the first electrode 101-1, the second electrode 101-2, the control electrode 104, the insulator layer 105 and the semiconductor layer 103 substantially corresponds to the thin-film transistor of FIG. However, in the embodiment of the thin-film transistor shown in FIG. 1b, the control electrode 104 is designed as an upper electrode (top-gate electrode). As shown in FIG. 1b, the semiconductor thin film 103 and the insulator layer 105 are disposed on the substrate 109. Further, the control electrode 104 is disposed on the insulator layer 105 and separated from the substrate 109 by the insulator layer 105 and the semiconductor thin film 103. In the embodiment According to FIG. 1 b, the first and second electrodes 101 - 1, 101 - 2 are arranged, similar to the exemplary embodiment shown in FIG. 1 a, such that a section 111 - 1 of the first electrode 101 - 1 adjoining the semiconductor thin film 103 adjoins a first electrode 101 - 1 side 111 of the semiconductor thin film 103 facing the substrate 109 is adjacent, while a portion 111-2 of the second electrode 101-2 adjacent to the semiconductor thin film 103 adjoins a side 1 18 of the semiconductor thin film 103 facing away from the substrate 109. By the arrangement of the first and second electrodes 101-1, 101-2, the control electrode 104, the insulator layer 105 and the semiconductor thin film 103 shown in FIG. 1b, a top-gate transistor structure can thus be realized.

In embodiments, the semiconductor thin film 103 adjoins a surface of the substrate 109 on one side.

In the embodiment according to FIG. 1b, the first electrode 101-1 is designed as a stacked electrode, while the second electrode 101-2 is designed as a coplanar electrode. By applying a control voltage to the control electrode 104 (top gate electrode), in turn, a channel can form in the semiconductor thin film 103 at the interface 114 to the insulator 105. Thus, an electrical resistance between the first and second electrodes 101-1, 101 -2 (source and drain electrodes) can be reduced. With reference to FIGS. 1 a and 1 b, a bottom-gate thin-film transistor structure (FIG. 1 a) and a top-gate thin-film transistor structure (FIG. 1 b) are each provided with a coplanarly mounted electrode (coplanar drain or source structure). Contact) and a stacked mounted electrode (stacked source or drain contact) allows. In this case, in Fig. La and lb respectively the substrate 109, the stacked source or drain contact 101-1, 101-2, the corresponding coplanar drain or source contact 101-2, 101-1, the semiconductor thin film or the semiconductor layer 103, the control electrode 104 (gate electrode) and the insulator layer 105 (gate insulator) are shown. In exemplary embodiments according to FIGS. 1 a and 1 b, the thin-film transistor is designed so that the first and second electrodes 101 - 1, 101 - 2 do not overlap in a top view of the substrate 109.

Figures 2a and 2b show side views of thin film transistors 200-1, 200-2 according to further embodiments of the present invention. In this case, the thin-film transistor 200-1 shown in FIG. 2a essentially corresponds to the thin-film transistor 100 shown in FIG. 1a, while the thin-film transistor 200-2 shown in FIG. 2b essentially corresponds to the thin-film transistor 100 shown in FIG. The in Fig. 2a and thin film transistors 200-1, 200-2 shown in FIG. 2b each include a first electrode 201-1, a second electrode 201-2, a control electrode 204, an insulator layer 205, and a semiconductor thin film 203 substantially similar to the first electrode 101-1, the second electrode 101-2, the control electrode 104, the insulator layer 105, and the semiconductor thin film 103 correspond to the thin film transistors 100 shown in FIGS. 1a and 1b. As shown in Figs. 2a and 2b, the elements 201-1, 201-2, 204, 205 and 203 of the thin film transistors 200-1, 200-2 are formed on the substrate 109. However, in contrast to the thin-film transistors 100 shown in FIGS. 1a and 1b, the thin-film transistors 200-1, 200-2 shown in FIGS. 2a and 2b are designed such that the first and second electrodes 201-1, 201-2 are in plan view overlap the substrate 109 in an overlap region 211.

Figure 2a shows a bottom-gate thin-film transistor having mutually coplanar / stacked, overlapping source and drain electrodes. In this case, the control electrode 204 or gate electrode is designed as a bottom electrode (bottom-gate electrode). As shown in FIG. 2a, the control electrode 204 is disposed on the substrate 109. Further, the insulator layer 205 and the semiconductor thin film 203 are disposed on the control electrode 204. The first and second electrodes 201 - 1, 201 - 2 are arranged such that a portion of the first electrode 201 - 1 adjoining the semiconductor thin film 203 adjoins the side 1 16 of the semiconductor thin film 203 facing the substrate 109, and a semiconductor thin film 203 adjacent portion of the second electrode 201-2 adjacent to the side facing away from the substrate 109 side 1 18 of the semiconductor thin film 203 adjacent. Thus, in the thin film transistor 200-1 shown in Fig. 2a, the first electrode 201-1 (source or drain electrode) is designed as a coplanar contact, while the second electrode 201-2 (source or drain electrode ) is designed as a stacked electrode or stacked contact. The thin-film transistor 200-1 shown in FIG. 2a may be configured such that in the overlapping region 211 of the first and second electrodes 201-1, 201-2 (source and drain electrodes), the first electrode 201-1 (coplanar electrode) is adjacent to the substrate 109 facing side 1 16 of the semiconductor thin film 203 and the second electrode 201-2 (stacked electrode) adjacent to the side facing away from the substrate 109 side of the semiconductor thin film 203 203.

In the embodiment shown in Fig. 2a, the first electrode 201-1 is separated from the control electrode 204 by the insulator layer 205 and not the semiconductor thin film 203. Further, the second electrode 201-2 is separated from the control electrode 204 by the insulator layer 205 and the semiconductor thin film 203. Referring now to Figure 2b, a top-gate thin film transistor having mutually coplanar / stacked, overlapping source and drain electrodes is shown. In the exemplary embodiment shown in FIG. 2b, the control electrode 204 or gate electrode is designed as an upper electrode (top-gate electrode). As shown in FIG. 2b, the semiconductor thin film 203 and the insulator layer 205 are disposed on the substrate 109. Further, the control electrode 204 is disposed on the insulator layer 205 and separated from the substrate 109 by the insulator layer 205 and the semiconductor thin film 203. In the embodiment according to FIG. 2 b, the first and the second electrode 201 - 1, 201 - 2 are arranged in a manner similar to the embodiment shown in FIG. 2 a such that a portion of the first electrode 201 - 1 adjoining the semiconductor thin film 203 is connected to one Side 116 of semiconductor thin film 203 facing substrate 109 adjoins, while a section of second electrode 201-2 adjoining semiconductor thin film 203 adjoins side 1 18 of semiconductor thin film 203 facing away from substrate 109. In the thin-film transistor 200-2 shown in Fig. 2b, the first electrode 201-1 is laid out as a stacked contact, while the second electrode 201-2 is designed as a coplanar or coplanar contact.

In embodiments according to FIGS. 2 a and 2 b, an overlap of the source and drain electrodes can thus be obtained in a plan view of the substrate in an overlapping region. Here, in Fig. 2a and 2b respectively the substrate 109, the stacked source or drain contact 201-1, 201-2, the corresponding coplanar drain or source contact 201-2, 201-1, the semiconductor or the semiconductor thin film 203, the control electrode 204 (gate electrode) and the insulator layer 205 (gate insulator) are shown. By overlapping the first and second electrodes 201-1, 201-2 in the overlap region 21 1, the length of the channel (channel length), which is at least partially at the interface 1 14 by applying a control voltage to the control electrode 204 in the semiconductor thin film 203 to the insulator 205 can be reduced as compared with the channel length provided in the semiconductor thin film 103 by the thin film transistors 100 shown in FIGS. 1a and 1b. In that the channel length can be reduced, in turn, the controllable current (drain current), which can flow between the first and second electrode or the source and drain electrodes, can be increased and thus optimized. With the transistor structures shown in FIGS. 2a and 2b, a maximization or optimization of the controllable current between drain and source can thus be achieved.

Figures 3a-3c show side views of thin film transistors 300 according to further embodiments of the present invention. The thin-film transistors 300 shown in FIGS. 3a-3c substantially correspond to those shown in FIG. 2a Thin-film transistor 200-1 (bottom-gate thin-film transistor). The thin film transistors 300 of FIGS. 3a-3c include a first electrode 301-1, a second electrode 301-2, a control electrode 304, an insulator layer 305, and a semiconductor thin film 303 formed on the substrate 109. Here, the elements 301-1, 301-2, 304, 305 and 303 of the thin film transistors 300 of FIGS. 3a-3c substantially correspond to the elements 201-1, 201-2, 204, 205 and 203 of the thin film transistor 200-1 of FIG 2a. As shown in FIGS. 3a-3c, the first and second electrodes 301-1, 301-2 overlap in plan view of the substrate 109 in the overlapping area 211, similar to the embodiment shown in FIG. 2a.

In embodiments according to FIGS. 3 a - 3 c, an insulator 310, 320 or 330 is arranged in the overlap region 21 1 between the first or second electrode 301 - 1, 301 - 2 and the semiconductor thin film 303. Fig. 3a shows a side view of a thin film transistor 300 according to an embodiment of the present invention. Referring now to Figure 3a, a bottom-gate thin film transistor having mutually coplanar / stacked, overlapping source and drain electrodes and an additional insulator layer and / or insulator for suppressing source / drain leakage current is shown. In the exemplary embodiment shown in FIG. 3 a, the second electrode 301 - 2 (stacked electrode) in the overlapping region 211 does not directly adjoin the side of the semiconductor thin film 303 facing away from the substrate 109. As shown in FIG. 3 a, an insulator 310 (additional insulator layer) may be arranged between the semiconductor thin film 303 and the second electrode 301 - 2 in the overlap region 21 1. Due to the overlap of the first and second electrodes 301-1, 301-2 in the overlapping area 211, the length of a channel formed in the semiconductor thin film 303 at least partially at the interface 114 to the insulator 305 of the thin film transistor 200-1 of FIG. 2a can be made clear be shortened. Further, by the arrangement of the insulator 310 and the additional insulator layer between the semiconductor thin film 303 and the second electrode 301-2, a possibly occurring leakage current (source / drain leakage current) between the first and second electrodes 301-1, 301-2 in FIG Overlap area 211 avoided or at least reduced. Thus, the thin film transistor 300 of FIG. 3 a is substantially characterized by a reduced channel length and simultaneously has improved electrical properties.

Fig. 3b shows a side view of a thin film transistor 300 according to another embodiment of the present invention. In Fig. 3b, a bottom-gate thin-film transistor having mutually coplanar / stacked overlapping ones is shown Source and drain electrodes and an additional insulator layer or an additional insulator for suppressing a source / drain leakage current shown, wherein the additional insulator largely surrounds the coplanar contact. In the exemplary embodiment shown in FIG. 3 b, the first electrode 301 - 1 (coplanar electrode) in the overlap region 21 1 does not directly adjoin the side of the semiconductor thin film 303 facing the substrate 109. As shown in FIG. 3b, an insulator 320 (additional insulator layer) may be arranged between the semiconductor thin film 303 and the first electrode 301-1 in the overlap region 21 1. By the overlap of the first electrode and the second electrode 301 -1, 301-2, the length of a channel formed in the semiconductor thin film 303 at least partially at the interface 14 to the insulator 305 of the thin film transistor 300 of Fig. 3b can be shortened significantly. Further, by the arrangement of the insulator 320 and the additional insulator layer between the semiconductor thin film 303 and the first electrode 301-1, a possibly occurring leakage current (source / drain leakage current) between the first and second electrodes 301-1, 301-2 in FIG Overlap area 211 avoided or at least reduced.

In further embodiments, referring to FIG. 3b, the first electrode 301-1 (coplanar electrode) may be separated from the semiconductor thin film 303 by an insulator portion 322 disposed laterally adjacent to the first electrode 301-1 and not extending to the insulator layer 305 be separated. By arranging the insulator section 322 laterally next to the first electrode 301-1, the first electrode 301-1 can be almost completely shielded along its circumference by the second electrode 301-2, so that any leakage currents that may possibly occur at the side can be better suppressed. Due to the fact that the insulator section 322 does not extend to the insulator layer 305 in the thin-film transistor 300 of FIG. 3b, the semiconductor thin-film 303 can still be reliably contacted via a section 315 of the first electrode 301-1. Thus, a current supplied from the first electrode 301 - 1 may be injected into a region of the channel that may be formed in the semiconductor thin film 303 substantially along the insulator / semiconductor interface. Thus, the first electrode 301-1 may be almost completely shielded from the second electrode 301-2 and still provide sufficient current for injection into the channel. Thus, the thin film transistor 300 of FIG. 3b is substantially distinguished by a reduced channel length and at the same time has improved electrical properties.

Fig. 3c shows a side view of a thin film transistor 300 according to another embodiment of the present invention. In Fig. 3c is a bottom-gate Thin film transistor with mutually coplanar / stacked mounted, overlapping source and drain electrodes and an additional insulator layer for suppressing a source / drain leakage current shown. In the exemplary embodiment shown in FIG. 3 c, the first electrode 301 - 1 (coplanar electrode) in the overlap region 21 1 does not directly adjoin the side of the semiconductor thin film 303 facing from the substrate 109. As shown in FIG. 3c, an insulator 330 (additional insulator layer) may be disposed between the semiconductor thin film 303 and the first electrode 301-1 in the overlap region 211. By overlapping the first and second electrodes 301-1, 301-2, the length of a channel formed in the semiconductor thin film 303 at least partially at the interface 114 to the insulator 305 of the thin film transistor 300 of Fig. 3c can be shortened significantly. Further, by the arrangement of the insulator 330 and the additional insulator layer between the semiconductor thin film 303 and the first electrode 301-1, a possibly occurring leakage current (source / drain leakage current) between the first and second electrodes 301-1, 301-2 in the overlap region 211 be avoided or at least reduced. Here, the first electrode 301-1 is effectively shielded by the second electrode 301-2, so that a substantially vertical leakage current can be largely suppressed. Thus, the thin film transistor 300 of FIG. 3 c is substantially characterized by a reduced channel length and at the same time has improved electrical properties.

FIGS. 4a, 4b show side views of thin film transistors 400 according to further embodiments of the present invention. FIG. 4a shows a top-gate thin-film transistor with mutually coplanar / stacked, overlapping source and drain electrodes and an additional isolation structure for extensive isolation of the coplanar electrode from the semiconductor or semiconductor thin film to suppress a source / drain leakage current shown. The thin-film transistors 400 shown in FIGS. 4a and 4b essentially correspond to the thin-film transistor 200-2 (top-gate thin-film transistor) shown in FIG. 2b. The thin-film transistors 400 of FIGS. 4a and 4b include a first electrode 401-1, a second electrode 401-2, a control electrode 404, an insulator layer 405, and a semiconductor thin film 403 formed on the substrate 109. Here, the elements 401-1, 401-2, 404, 405 and 403 of the thin film transistors 400 of FIGS. 4a and 4b substantially correspond to the elements 201-1, 201-2, 204, 205 and 203 of the thin film transistor 200-2 of FIG . 2 B. As shown in Figs. 4a and 4b, the first and second electrodes 401-1, 401-2 overlap in plan view of the substrate 109, similar to the embodiment shown in Fig. 2b, in the overlapping area 211 FIG. 4 a is shown by way of example, the thin-film transistor 400 according to an exemplary embodiment has an additional insulation structure 410. The insulation structure 410 is designed to isolate the second electrode 401-2 (coplanar electrode) preferably in the vicinity of the overlap area 211 from the semiconductor thin film 403 and to minimize the overlap area. As a result, it can be achieved that the second electrode 401-2 is largely insulated from the semiconductor thin film 403 and can still contact the semiconductor thin film 403 in the vicinity of the insulator layer 405. Thus, on the one hand, substantially potential lateral and vertical leakage currents can be suppressed and, on the other hand, injection of the current into a region of the channel which forms at least partially at the insulator / semiconductor interface 114 can thus take place.

Referring to Figure 4b, there is shown a top-gate thin film transistor having coplanar / stacked, overlapping source and drain electrodes and a localized stacked electrode enclosure for suppressing source / drain leakage current. As shown by way of example in FIG. 4 b, the thin-film transistor 400 according to exemplary embodiments has an additional insulation structure 420. The insulating structure 420 is configured to insulate the first electrode 401-1 (stacked electrode) in the overlapping area 21 1 from the second electrode 401-2 (coplanar electrode). Here, the insulation structure 420 is designed such that it comprises the first electrode 401-1 (stacked electrode) locally limited or is arranged on an edge of the stacked electrode in the overlapping region 21 1. Thus, by providing the isolation structure 420, leakage currents that may occur between the first and second electrodes 401-1, 401-2 can be efficiently suppressed.

Thus, in the embodiments shown in FIGS. 3a-3c and 4a, 4b, insulators or isolation structures 310, 320, 330, 410, 420 can be used to reduce the source / drain leakage current. As can be seen from FIGS. 2 a and 2 b, a potentially low-resistance leakage current path between source and drain can occur in the overlapping region of the source and drain contacts 201 - 1, 201 - 2, which in the worst case makes effective switching off of the component difficult. In order to suppress this leakage current path, the insulating auxiliary structures (insulators or insulation structures 310, 320, 330, 410, 420) can be introduced. Such auxiliary structures for bottom-gate transistors are shown in FIGS. 3a-3c, while they are shown in FIGS. 4a and 4b for top-gate transistors. Such isolation structures are similarly usable in the thin-film transistors 100 in which the source and drain electrodes do not overlap.

For example, in FIG. 3c, on the coplanar electrode 301 -1 of the bottom-gate transistor 300, an insulating layer or the insulator 330 is attached to the semiconductor, to reduce the source / drain leakage current. The insulating layer can be patterned together with the coplanar contact or independently of this. In FIG. 3b, the isolation structure or insulator 320 almost completely surrounds the coplanar contact 301-1 in order to largely rule out an interaction between source and drain 301-1, 301-2. However, care should be taken in this case that the coplanar electrode 301-1, for example in the form of a thinned metal structure (section 315 of the first electrode 301-1) of sufficient thickness, is brought to the channel. For example, in Figure 3a, an isolation structure 310 is inserted below a portion of the stacked contact 301-2. Although this typically increases the channel length, it can lead to improved process control reproducibility. In addition, in this arrangement, a partial passivation or encapsulation of the exposed semiconductor surface can be achieved.

Corresponding embodiments for insulation layers or the insulation structures 410, 420 in top-gate thin-film transistors are shown in FIGS. 4a and 4b. For example, in FIG. 4a, an insulator layer or insulation structure 410 isolates the coplanar electrode 401-2 in the overlapping area with the stacked electrode 401-1 from the semiconductor 403. The coplanar electrode 401-2 can be made self-aligned with the insulation structure 410 if necessary. For example, in Fig. 4b, an insulating structure 420 is inserted at the stacked electrode 401-1 in the overlapping area to the coplanar electrode 401-2. Although this typically increases the channel length, it can lead to improved reproducibility of the process control.

FIGS. 4c to 4h show side views of thin film transistors 300, 400 according to further embodiments of the present invention. In the embodiments shown in FIGS. 4c to 4h, the source and drain electrodes do not overlap in plan view of the substrate. The thin film transistors 300, 400 of FIGS. 4c to 4h each include first and second electrodes 301-1, 301-2, 401-1, 401-2, a control electrode 304, 404, an insulator layer 305, 405, and a semiconductor thin film 303 , 403, which are arranged on the substrate 109. Furthermore, the thin-film transistors 300, 400 of FIGS. 4 c to 4 h have insulating structures 310, 320, 330, 410, 420.

The thin-film transistors 300 with the insulation structures 310, 320, 330 shown in FIGS. 4 c to 4 f essentially correspond to the thin-film transistors 300 shown in FIGS. 3 a to 3 c with the insulation structures 310, 320, 330 (bottom-gate thin-film transistors). Furthermore, the thin-film transistors 400 shown in FIGS. 4g and 4h with the insulation structures 410, 420 essentially correspond to those in FIG FIGS. 4a and 4b show thin-film transistors 400 with the insulation structures 410, 420 (top-gate thin-film transistors).

In the thin-film transistors 300 shown in FIGS. 4c and 4d, the isolation structure 330 is provided between a portion of the first electrode 301-1 and a portion of the semiconductor thin film 303. Here, in the thin film transistor 300 shown in FIG. 4c, the second electrode 301-2 does not extend to a vertical edge 122 of the semiconductor thin film 303, while in the thin film transistor 300 shown in FIG. 4d, the second electrode 301-2 extends to the vertical edge 122 of the semiconductor thin film 303.

In the thin-film transistors 300 shown in FIGS. 4e and 4f, the insulating structure 320 is provided between a portion of the first electrode 301 -1 and a portion of the semiconductor thin film 303. Here, in the thin film transistor 300 shown in FIG. 4e, the second electrode 301-2 extends to a vertical edge 122 of the semiconductor thin film 303, whereas in the thin film transistor 300 shown in FIG. 4f, the second electrode 301-2 does not extend to the vertical edge 122 of the semiconductor thin film 303. In the thin-film transistor 400 shown in FIG. 4g, the insulating structure 410 is provided between a portion of the second electrode 401-2 and a portion of the semiconductor thin film 403.

Further, in the thin film transistor 400 of FIG. 4h, the isolation structure 420 is provided between a portion of the first electrode 401-1 and a portion of the semiconductor thin film 403.

In the embodiments according to FIGS. 4c to 4h, one or more isolation structures are provided between a region of the first electrode and a region of the semiconductor thin film and / or between a region of the second electrode and a region of the semiconductor thin film. This makes it possible to efficiently suppress leakage currents between the first and second electrodes. Thus, even in the embodiments of FIGS. 4c to 4h, in which the source and drain electrodes do not overlap, an efficient suppression of the leakage currents can be obtained.

Figures 5a and 5b show plan views of electrodes 501, 502 of thin film transistors according to further embodiments of the present invention. In the in Fig. 5 a and 5b, a first and a second electrode 501, 502 as well as a semiconductor or a semiconductor thin film 503 (dashed boundary line) are shown. The elements in the plan views of FIGS. 5 a and 5 b substantially correspond to those shown in the side views of FIGS. 1a and 1b.

Referring to FIG. 5a, the first and second electrodes 501, 502 have, for example, a square shape (or border). Further, in other embodiments, the first and second electrodes 501, 502 may have a rectangular or round shape. By providing a square, rectangular or round shape for the first and second electrodes 501, 502 (stacked and coplanar electrode), a comparatively small circumference-to-area ratio can be obtained, so that the electrical characteristics of the thin film transistor are mainly from the coplanar Contact to be influenced. This results from the fact that, with a comparatively small circumference-to-area ratio, the total current to be generated between the first and second electrodes is limited primarily by the small line length of the coplanar contact. The circumference-to-area ratio is defined, for example, as the ratio of the circumference of the coplanar to the area of the stacked electrode or contact. In embodiments, an inner electrode (electrode 501) of the first and second electrodes 501, 502 is surrounded by an outer electrode (electrode 502) of the first and second electrodes 501, 502. Here, outer edges 511 of the inner electrode 501 (coplanar electrode) and inner edges 513 face the outer electrode 502 (stacked electrode) (see FIG. 5 a). It should be noted here that the electrode having the comparatively large area (outer electrode 502) is the stacked electrode while the electrode having the comparatively small area (inner electrode 501) is the coplanar electrode.

Furthermore, in further embodiments according to FIG. 5 a, the inner or coplanar electrode 501 and the outer or stacked electrode 502 may overlap in plan view onto the substrate. Thus, in further exemplary embodiments according to FIG. 5 a, an overlap of the inner and outer electrodes 501, 502 similar to the exemplary embodiments shown in FIGS. 2a and 2b may also occur. Referring to FIG. 5b, the first and second electrodes 501, 502 include, for example, a first interdigital structure 501 and a second interdigital structure 502. In exemplary embodiments according to FIG. 5 b, edges 521 of the first interdigital structure 501 and edges 523 of the second interdigital structure 502 are located opposite one another. Furthermore, in further exemplary embodiments according to FIG. 5 b, the first interdigital structure 501 and the second interdigital structure 502 may overlap one another in plan view of the substrate. Thus, in further exemplary embodiments according to FIG. 5b, an overlapping of the first and second interdigital structures 501, 502 may also occur similar to the exemplary embodiments shown in FIGS. 2a and 2b.

In embodiments with an overlap of the electrodes or interdigital structures, the elements in the plan views of FIGS. 5a and 5b essentially correspond to those shown in the side views of FIGS. 2a and 2b.

The interdigital structure of the first and second electrodes 501, 502 shown in FIG. 5b is characterized by a comparatively large circumference-to-area ratio. Due to the comparatively large ratio of the circumference to the area of the respective electrodes 501, 502 or contacts, the electrical properties of the thin-film transistor are influenced predominantly by the stacked electrode or the coplanar contact. It should be understood that the extent of the coplanar contact as well as the area of the stacked contact are primary or essential to the adjustment of the electrical characteristics of the thin film transistor. In contrast, the area of the coplanar contact and the circumference of the stacked contact are only secondary or not essential.

In embodiments according to FIGS. 5a and 5b, the electrical properties of thin-film transistors can thus be set by selecting a suitable circumferential-area ratio of the coplanar or stacked contacts. This allows a targeted suppression or emphasis on the contact properties and thus a targeted adjustment of the operation of the thin-film transistors. In other words, an optimization of the electrical device properties can be made via the circuit design. The asymmetry of the source and drain contacts, ie, an almost line-shaped injection at the coplanar contact as opposed to a flat injection at the stacked contact results in a separate optimization of the source and drain geometries to achieve a maximum current level (Fig. 5 a, 5b) and to limit the current through contact properties. With coplanar and stacked contact lines 501, 502 parallel, it can be assumed that the injection width at the coplanar contact corresponds approximately to the circumference of the stacked contact. By By varying the perimeter area-to-area ratio of the stacked contact, the injection properties of one of the two contacts can be selectively used to limit the total current and thus define the device characteristics. For example, there are the following options.

If, for example, the coplanar contact influences the component properties, the circumference-to-area ratio should be set as low as possible. As a result, the coplanar contact limits the total current. An example of the embodiment with a square geometry of the coplanar contact is shown in Fig. 5a. Other low aspect ratio designs may be designed, for example, with a rectangular or round coplanar contact.

If, for example, the stacked contact influences the component properties, then the circumference-to-area ratio should be set as large as possible. An example of an interdigital design is shown in Fig. 5b. Here, the total area of the stacked contact in Fig. 5a and 5b, for example, the same size. Further embodiments of the electrodes or contacts are, for example, regular point, star, stripe or meander-shaped arrangements. In further embodiments, technically relevant intermediate forms are conceivable for the just mentioned possibilities.

For the above embodiment, with reference to Figs. 5a and 5b, the relative position of the edges of coplanar 501 and stacked electrode 502 is primarily critical, as well as the overlap of stacked electrode 501 and semiconductor 503. Thus, in Figs. 5a and 5b, only those are mentioned Elements in relation set, wherein in the case of the semiconductor 503 only the boundary line of the semiconductor surface is located. In Fig. 5a, a design and plan view of a thin-film transistor with a small circumference-to-area ratio is shown by way of example, while in Fig. 5b, the outline of a thin-film transistor with a high-to-area ratio and the same area of the stacked contact as shown in Fig. 5a. The arrangement shown in FIGS. 5a and 5b is representative of all embodiments similar to those in FIGS. 1a and 1b, and in the case of overlapping of the contacts also as in FIGS. 2a and 2b. Fig. 5c shows a top view of electrodes of a thin film transistor 500 according to another embodiment of the present invention. In the exemplary embodiment shown in FIG. 5 c, again a first and a second electrode 501, 502 as well as a semiconductor thin film 503 (dashed boundary line) are shown. The elements in the Top view of Fig. 5c substantially correspond to those shown in the side views of Fig. La and lb. Not shown are the gate electrode and the gate insulator, which can occupy at least the surface of the semiconductor. For example, referring to FIG. 5c, the first electrode 501 has a comb structure, while the second electrode 502 has a rectangular shape, for example.

The exemplary embodiments of FIGS. 5a to 5c have the common feature that, in the case of the thin-film transistors, in each case a peripheral section of the first or second electrode which adjoins the semiconfilm for forming a channel has a different course from a continuous straight line. In the thin-film transistor according to FIG. 5c, the first or second electrode has a comb structure with a plurality of fingers, wherein finger sections form the peripheral section relevant for the formation of the channel.

In the thin-film transistors according to FIGS. 5a and 5b, the peripheral portion of the first or second electrode relevant to the formation of the channel has, for example, regions arranged on opposite sides of at least a portion of the first or second electrode.

By providing a different from a continuous straight line course of an adjacent to the semiconductor thin film for the formation of a channel relevant Umfangsab section of the first or second electrode (as exemplified in Fig. 5a to 5c) can in particular an individual but coordinated optimization of scope the one and surface of the other electrode can be achieved. Fig. 6a shows a side view of one embodiment of a thin film transistor 600 fabricated by the printing and spraying process. Referring to Figs. 6a and 6b, there is shown by way of example the design of the thin film transistor 600, such as that produced by overlapping printing and spraying of functional materials. Referring to FIG. 6a, the thin film transistor 600 (top gate thin film transistor) includes a first electrode 601-1, a second electrode 601-2, a control electrode 604, an insulator layer 605, and a semiconductor thin film 603. Here, the elements 601-1, 601-2, 604, 605, and 603 of the thin film transistor 600 of FIG. 6a substantially correspond to the elements 101-1, 101-2, 104, 105, and 103 of the thin film transistor 100 of Fig. Ib. However, the elements shown in Figure 6a and the thin film transistor 600, respectively, were produced based on printing and spraying techniques. In this case, for example, the stacked electrode 601-1 is first printed on an insulating substrate, such as preferably on glass, ceramic, insulating coated stainless steel or plastic film, using a metal ink in the form of a line. Inkjet, gravure, offset or flexographic printing processes are preferably used as the printing process, while soft-lithographic processes such as, for example, nanoimprint lithography can also be used. In a second step, the semiconductor 603, for example over the entire surface by means of spraying or patterned from a Präkursortinte (molecular solution, particle dispersion or mixture of both), applied so that it completely surrounds the stacked electrode 601-1. Subsequently, the coplanar electrode 601-2 is also produced in the form of a line, for example by printing a metallic precursor ink. With sufficient overlap of the semiconductor thin film (semiconductor 603) and the electrode structures produced, the insulator 605 or the insulator layer is then applied by spraying or printing process, for example. Subsequently, on the insulator 605, for example, the metallic gate electrode 604 is printed so that it is able to fully control the exposed semiconductor region. In the case of the whole-surface spraying method, the contact with buried electrodes, for example, either by suitable methods for opening contact holes (contact holes 611, 612 in Fig. 6b), localized additive order with the structure boundaries 613, 615, for example by the above-mentioned printing method, or For example, by local shading of the spray coating by means of S chatten masks (dashed lines 613, 615 in Fig. 6b) achieved. Thus, the implementation of a printed top-gate thin-film transistor according to FIG. 6a with mutually attached source and drain electrodes is realized by means of printing and spraying processes. For a better illustration, FIG. 6b shows the top view of the embodiment of the thin-film transistor 600 of FIG. 6a thus produced. As exemplified in FIG. 6b, the thin film transistor 600 has first and second openings 61 1, 612 and contact holes, respectively. Here, the first opening 611 extends through the insulator layer 605 and the semiconductor thin film 603 except for the first electrode 601-1, while the second opening 612 extends through the insulator layer 605 and not the semiconductor thin film 603 to the second electrode 601-2. Through the first and second openings 611, 612, a contacting of the first and second electrodes 601-1, 601-2 or the buried electrodes can be made possible.

In embodiments, the semiconductor thin film is an inorganic layer. In further embodiments, the thickness (S) of the semiconductor thin film is in a range of, for example, 5 nm to 120 nm, preferably in a range of, for example, 30 nm to 120 nm. In further embodiments, a thickness (D) of at least one of the first and second Electrode equal to or greater than 50 nm, preferably equal to or greater than 100 nm, or preferably equal to or greater than 200 nm.

The following describes a method that can be used to fabricate bottom-gate thin film transistors (Figures la and 2a) by conventional vacuum deposition techniques, such as chemical vapor deposition / CVD or physical vapor deposition / PVD. The process is carried out, for example, such that the transistor structure is built up on an insulating substrate (substrate 109), such as a glass carrier or a thermally oxidized silicon wafer. Then, a patterned metal layer is generated as the gate electrode (control electrode 104). This can be done, for example, by deposition of a 100 nm aluminum-silicon (2%) alloy by means of cathode sputtering or by a 100 nm aluminum layer by electron beam evaporation followed by photolithography and dry etching of the aluminum layer. Alternatively, a lift-off method can be used, in which a photoresist is first patterned, then the metal layer is deposited and finally, by means of solvent, the remaining photoresist, including the metal layer deposited on it, is lifted off. Subsequently, as the gate insulator (insulator layer 105), for example, 200 nm of silicon dioxide is deposited, for example by means of plasma assisted CVD or cathode sputtering, and patterned by means of photolithography and dry etching. Subsequently, analogously to the gate electrode production, the coplanar metal contact (first electrode 101-1) is produced, for example, by the deposition of a 100 nm aluminum-silicon alloy plus one of the structuring techniques described above. Subsequently, for example, the deposition of 50 nm or 100 nm zinc oxide by means of sputtering and the structuring by means of the lift-off process. Another possibility would be the whole-area deposition of the zinc oxide layer, photolithography and the subsequent etching of the zinc oxide layer by means of physical or chemical-physical etching. For the annealing of the semiconductor thin film (semiconductor thin film 103), for example, thereafter a thermal treatment is carried out at 400 ° C. in a forming gas atmosphere (for example 95% N ₂ , 5% H ₂ ). Subsequently, the contacts to the gate electrode and possibly to the coplanar electrode are exposed, for example, by means of photolithography and dry etching step. Subsequently, for example, a 300 nm thick aluminum layer (For example, for the second electrode 101-2) by means of electron beam evaporation and lift-off deposited and patterned. For this purpose, the full-area deposition plus photolithography and etching of the layer is alternatively conceivable. Finally, the components are stored for example for 12 hours at 120 ° hot.

As process extensions to the method just described, for example, the following steps may further be performed.

In order to realize an insulator structure (insulator 330) in Fig. 3c, after the deposition of the metal layer to form the coplanar electrode 301-1, an insulator layer, preferably 100 nm of silicon dioxide, is obtained by means of e.g. plasma-enhanced vapor deposition and patterned together with the metallization 301-1 by photolithography and dry etching. In order to realize an insulator structure (insulator 320) in FIG. 3b, the deposition of the metal layer for producing the coplanar electrode 301-1 is carried out, for example, in two layers. As the lower metal layer, a metal layer 315 is selected (such as 20 nm platinum or tungsten), which is not attacked by the dry etching process for the upper metal layer 301-1 (such as 100 nm AISi). As in the previous example, an insulator layer, preferably 100 nm of silicon dioxide, is deposited on the metal layer stack and patterned together with the upper metallization layer 301-1 by photolithography and dry etching. The lower metallization layer 315 is not attacked. Subsequently, for example, a second insulating layer, preferably 20 nm of silicon dioxide, applied in a conformal deposition process and generated by anisotropic etching back a so-called spacer structure 322 for electrical insulation of the flanks. With the aid of a dry etching step and the spacer as masking, the lower metallization layer is finally structured selectively. In order to realize an insulator structure (insulator 310) in Fig. 3a, prior to deposition of the metal layer to make the stacked electrode 301-2, an insulator layer, preferably 100 nm of silicon dioxide, may be obtained by e.g. applied plasma-enhanced vapor deposition and patterned by photolithography and dry etching.

For the fabrication of thin-film transistors in top-gate architecture (Figures lb and 2b) by conventional vacuum deposition techniques, such as chemical vapor deposition / CVD or physical vapor deposition / PVD First, the stacked source or drain electrode 101-1, 201-1 by means of deposition of lOOnm aluminum and lift-off technique or photolithography, plasma etching and removal of the photoresist on an insulating substrate 109, for example glass, plastic, insulating coated stainless steel or oxididertem Silicon carrier produced. In a second step, the production of a preferably 50 to 100 nm thick semiconductor thin film 103, 203, for example zinc oxide, and its structuring by means of lift-off or photolithography and etching technology. The semiconductor can be subjected to the deposition of an oven annealing at> 100 ° C, for example at 400 ° C, for example in Formiergasatmosphäre (5% H ₂ , 95% N ₂ ). Furthermore, the second coplanar electrode 101-2, 201-2, for example 100 nm of aluminum, is deposited by means of vapor deposition or cathode sputtering and patterned with the aid of the lift-off technique or a photolithography sequence. Then, by means of plasma-assisted vapor deposition or with the aid of an alternative deposition method such as atomic layer deposition (ALD) or cathode sputtering, the insulator 205, for example silicon dioxide, aluminum oxide or an alternative dielectric, is deposited and patterned by means of a lift-off technique or photolithography sequence. Finally, to produce the gate electrode 104, 204, a metal layer, for example aluminum, is deposited by means of, for example, vapor deposition or cathode sputtering and patterned by means of a lift-off technique or photolithography sequence.

For realizing an insulator structure (insulator 410) in Fig. 4a, prior to depositing the metal layer to make the coplanar electrode 401-2, an insulator layer, preferably 100 nm of silicon dioxide, may be obtained by e.g. applied plasma-enhanced vapor deposition and patterned by photolithography and dry etching. The metal layer for producing the coplanar electrode 401-2 must be made to pass over the insulator structure 410 into the overlap area 21 1 with the stacked electrode 401-1 and contact the semiconductor thin film. By minimizing the overlap between the stacked electrode 401-1 and the contact area between coplanar electrode 401-2 and semiconductor, the source / drain leakage current is reduced.

In order to realize an insulator structure (insulator 420) in FIG. 4b, before the deposition of the semiconductor thin film 403, an insulator layer, preferably 100 nm silicon dioxide, can be applied by means of eg plasma-assisted vapor deposition and patterned by photolithography and dry etching in such a way that it overlaps the stacked electrode encompasses with the coplanar electrode. Further, the fabrication of thin-film transistors in bottom-gate architecture by printing techniques may be performed according to a method (optionally, by changing the process order and process selection) for fabricating the thin-film transistor 600 shown in FIGS. 6a and 6b.

The above described embodiments are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims, rather than by the specific details presented in the description and explanation of the embodiments herein.

Embodiments of the present invention provide a thin film transistor and a method of manufacturing the same, wherein improvement of the thin film transistor or device with respect to the currents extractable from the device can be achieved. With the thin-film transistor according to the invention, the controllable current between drain and source can be optimized or maximized. This is made possible by the fact that the channel length can be made as low as possible and can even be reduced below the resolution limit specified by the known techniques.

In contrast to the known techniques, in the case of the transistor according to the invention, the geometry and the electrical behavior of source and drain contact can be separately optimized via the dimensioning of the area of the one or the contact line of the other source or drain contact. This can specifically suppress or work out contact effects and their effect on the electrical behavior of the entire component.

The present invention provides the ability to provide overlapping source / drain regions in a thin film transistor. In this case, it was recognized that the thin-film transistor according to the invention is a modification of the standard TFT (thin-film transistor).

Furthermore, embodiments of the present invention provide a thin film transistor having spaced source and drain electrodes, wherein in particular the overlap of the source and drain can be minimized. Incidentally, according to embodiments of the present invention, it is possible to better control leakage currents even with a strong overlap of the source and drain electrodes. Furthermore, insulator layers can be used to suppress source / drain leakage currents.

The present invention also allows a more sophisticated optimization of the device characteristics of the thin film transistor. Here, especially in the case of non-overlapping source and drain electrodes, there is no requirement for a barrier between a lower electrode and the semiconductor or the semiconductor thin film of the thin-film transistor. In general, embodiments of the invention are based on the fact that the source and drain contacts are not made, as usual, in a Metallisierungsebene, but that one of the two contacts as coplanar contact and the other of the two contacts can be performed as a stacked contact. It is not initially determined which of the two contacts is used as a source and which contact as a drain. The resulting structures according to the invention are illustrated by way of example in FIG. 1 a for the bottom-gate thin-film transistor and in FIG. 1b for the top-gate thin-film transistor.

Particular advantages of the electrode configuration of the thin-film transistor according to the invention are that the distance between the source and drain electrodes, which defines the achievable drain current, is not defined by the resolution of the manufacturing process, but by the distance between the boundary edges of metal electrodes made in separate planes. In extreme cases, the aforementioned advantage can be exploited to such an extent that the two electrodes are brought to overlap (see FIGS. 2a and 2b). By the charge carrier injection via either the coplanar or the stacked electrode in the channel region effects such as non-linear characteristic curves, such as a gate-controlled rectifying contact, specifically disclosed and used for use in devices. In addition, such effects can be selectively enhanced or suppressed by selectively selecting different materials for coplanar and stacked contact, as well as the geometry of the component.

In summary, embodiments of the present invention have the following advantages. A reduction of the channel length below the resolution limit specified by the manufacturing or structuring method can be achieved. Furthermore, isolation structures for reducing the source / drain leakage currents are created. In this case, a partial additional passivation of the semiconductor surface can be achieved. Furthermore, a fault-tolerant process control is made possible. Finally, one can Control of the device properties are made possible by targeted adjustment of the properties of coplanar and stacked contact. This is achieved, for example, by a choice of material, an interface treatment, a dimensioning of layer thicknesses and a reinforcement or weakening of the properties of one of the contacts by determining the layout (eg 2D geometry, circumference of the coplanar and surface of the stacked contact). It should be noted in particular that the optimization of thin-film transistors is made possible on the one hand by the control according to the invention, and on the other hand the provision of completely novel electronic components can be realized.

Embodiments of the present invention thus enable a combination of coplanar and stacked contact in a device.

Embodiments of the present invention provide transistors for use in classical semiconductor technologies, i.a. Switching transistors, memory cells, such as SRAM, DRAM or 3D stackable highly integrated memory arrays, light-emitting transistors for optical signal or data transmission and driver transistors for power electronic applications. Further, embodiments of the present invention provide transistors for, for example, printed and large area thin film technologies, i.a. Displays (eg pixel drivers, addressing, data bus drivers and amplifiers as well as light-emitting transistors), light elements such as OLED, electroluminescent lamps, LED illumination (eg driver transistors, control circuits such as dimmers), detector arrays (eg 1D, 2D and 3D detection visible light, UV, X-ray, radioactive or other wavelength electromagnetic radiation, pixel amplifiers, address transistors or phototransistors), switches (eg, low cost logic applications, RFID chips, large power transistors), memory (eg select transistors, sense amplifier transistors, addressing or memory transistors).

Finally, embodiments of the present invention may serve to provide controllable non-linear / rectifying devices, e.g. for the rectification of AC voltage, oscillators for frequency generation, freewheeling diodes, voltage references and temperature sensors. The arrangement of the source / drain electrodes enables novel test structures for a targeted characterization of contact properties on individual contacts.

Claims

claims

Thin film transistor (100; 200-1; 200-2; 300; 400; 600) having a first electrode (101-1; 201-1; 301-1; 401-1; 601-1), a second electrode (101 -2; 201-2; 301-2; 401-2; 601 -2), a control electrode (104; 204; 304; 404; 604), an insulator layer (105; 205; 305; 405; 605) and a semiconductor thin film (103; 203; 303; 403; 603) formed on a substrate (109), wherein the control electrode (104; 204; 304; 404; 604) is attached to the insulator layer (105; 205) on one side (1 12) 305; 405; 605) and the semiconductor thin film (103; 203; 303; 403; 603) is adjacent to the insulator layer (105; 205; 305; 405; 605) on an opposite side (1 14); the second electrode (101-1, 101-2; 201-1, 201-2; 301-1, 301-2; 401-1, 401-2; 601-1, 601-2) is attached to the semiconductor thin film (103; 203; 303; 403; 603), and wherein by varying the potential of the control electrode (104; 204; 304; 404; 604) a channel in the semiconductor thin film (103; 203; 303; 403; 603 ) can be formed and removed again, by which an electrical resistance between the first and second electrodes (101-1, 101-2; 201-1, 201-2; 301-1, 301-2; 401-1, 401-2; 601-1, 601-2), wherein a portion (1 1 1-1) adjacent to the semiconductor thin film (103; 203; 303; 403; 603) of the first electrode (101-1; 201-1; 301-) is controlled. 1; 401-1; 601-1) is arranged on a side (1 16) of the semiconductor thin film (103; 203; 303; 403; 603) facing the substrate (109), and a thin film (103; 203;

303; 403; 603) adjacent to the second electrode (101-2; 201-2; 301-2; 401-2; 601-2) on a side (118) of the semiconductor thin film facing away from the substrate (109) (103; 203; 303; 403; 603), wherein a thickness (D) of at least one of the first electrode and the second

Electrode (101-1, 101-2, 201-1, 201-2, 301-1, 301-2, 401-1, 401-2, 601-1, 601-2) greater than half the thickness (S. ) of the semiconductor thin film (103; 203; 303; 403; 603).

2. The thin film transistor (100) according to claim 1, wherein the first and second electrodes (101-1, 101-2) do not overlap in plan view of the substrate (109).

The thin film transistor (200-1; 200-2; 300; 400; 600) according to claim 1, wherein the first and second electrodes (201-1, 201-2; 301-1, 301-2; 401-1, 401- 2; 601-1, 601 - 2) overlap in a plan view of the substrate (109) in an overlapping area (21 1).

The thin film transistor (100; 200-1; 300) of any one of claims 1 to 3, wherein the control electrode (104; 204; 304) is adjacent to a surface of the substrate (109) on another side.

The thin film transistor (100; 200-1; 300) according to claim 4, wherein the first electrode (101-1; 201-1; 301-1) is penetrated by the insulator layer (105; 205; 305) and not the semiconductor thin film (103; 203 303) is separated from the control electrode (104), and wherein the second electrode (101-2; 201-2; 301-2) is penetrated by the insulator layer (105; 205; 305) and the semiconductor thin film (103; 203; 303) of the control electrode (104; 204; 304) is separated.

The thin film transistor (100; 200-2; 400; 600) according to any one of claims 1 to 3, wherein the semiconductor thin film (103; 203; 403; 603) is abutted on one side to a surface of the substrate (109).

The thin film transistor (100; 200-2; 400; 600) according to claim 6, wherein the first electrode (101-1, 201-1; 401-1; 601-1) is penetrated by the insulator layer (105; 205; 405; 605). and the semiconductor thin film (103; 203; 403; 603) is not separated from the control electrode (104; 204; 404; 604), and wherein the second electrode (101-2; 201-2; 401-2; 601-2) passes through the insulator layer (105; 205; 405; 605) and the semiconductor thin film (103; 203; 403; 603) are separated from the control electrode (104; 204; 404; 604).

The thin-film transistor (200-1; 200-2; 600) according to claim 3, wherein in the overlap region (211), the first electrode (201-1; 601-1) faces the substrate (109) side (1,16) of the Semiconductor thin film (203, 603) is adjacent and the second electrode (201-2, 601-2) to the side facing away from the substrate (109) side (1 18) of the semiconductor thin film (203) adjacent.

The thin film transistor (300; 400) according to claim 3, wherein in the overlapping area (21 1), an insulator (310; 320; 330) is interposed between the first and second electrodes (301-1, 301-2; 401-1, 401-2 ) and the semiconductor thin film (303; 403).

10. The thin film transistor (300) according to claim 9, wherein the first electrode (301-1) is separated from the semiconductor thin film (303) by an insulator portion (322) disposed laterally adjacent to the first electrode (301-1), and wherein the insulator portion (322) does not extend to the insulator layer (305) such that a portion of the first electrode (301-1) contacts the semiconductor thin film (303).

The thin-film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 10, wherein the first and second electrodes (501, 502) have a square, rectangular or round shape.

The thin-film transistor (100; 200-1; 200-2; 300; 400; 600) according to claim 1 1, wherein an inner electrode (501) of the first and second electrodes (501, 502) from an outer electrode (502). the first and second electrodes (501, 502) is surrounded.

13. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) of claim 12, wherein outer edges (511) of the inner electrode (501) and inner edges (513) of the outer electrode (502) are opposite.

14. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) of claim 12, wherein the inner and outer electrodes (501, 502) overlap each other in plan view of the substrate (109).

The thin-film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 10, wherein the first and second electrodes (501, 502) have a first interdigital structure (501) and a second interdigital structure (502).

16. The thin-film transistor (100; 200-1; 200-2; 300; 400; 600) of claim 15, wherein edges (521) of the first interdigital structure (501) and edges (523) of the second interdigital structure (502) are opposite each other.

17. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) of claim 15, wherein the first and second interdigital structures (501, 502) overlap in plan view of the substrate (109).

18. The thin film transistor (600) according to one of claims 1 to 17, further comprising a first and a second opening (61 1, 612), wherein the first opening (61 1) extends through the insulator layer (605) and the semiconductor thin film (603) to the first electrode (601-1), the second opening (612) extending through the insulator layer (605) and not the semiconductor thin film (603) ,

19. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 18, wherein the semiconductor thin film (103; 203; 303; 403; 503; 603) is an inorganic layer.

20. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 19, wherein the thickness (S) of the semiconductor thin film (103; 203; 303; 403; 503; 603) is in a range of 5 nm to 120 nm.

21. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 20, wherein a thickness (D) of the first and second electrodes (101-1, 101-2; 201 -1, 201-2, 301-1, 301-2, 401-1, 401-2, 601-1, 601-2) is equal to or greater than 50 nm.

A thin-film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 21, wherein one adjacent to the semiconductor thin film (103; 203; 303; 403; 603) for forming a semiconductor thin film (103; Channel significant peripheral portion of the first or second electrode (501, 502) has a different course from a continuous straight line.

23. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to claim 22, wherein the first or second electrode (501,502) has a comb structure with a plurality of fingers, finger portions corresponding to those of FIG form the formation of the channel relevant peripheral section.

24. The thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to claim 22, wherein the peripheral portion of the first or second electrode (501,502) defining the channel has areas on opposite sides of at least a portion of the first or second electrode (501, 502) are arranged.

A thin film transistor (100; 200-1; 200-2; 300; 400; 600) according to any one of claims 1 to 24, wherein one or more isolation structures (310; 320; 330; 410; 420) are disposed between a portion of the first Electrode (301-1; 401-1) and a portion of the semiconductor thin film (303; 403) and / or between a portion of the second Electrode (301 -2; 401-2) and a portion of the semiconductor thin film (303; 403) are provided to allow leakage currents between the first and second electrodes (301-1; 401-1, 301-2; 401-2) suppress.