WO2013020867A1

WO2013020867A1 - Methods for the fabrication of back contacted photovoltaic cells

Info

Publication number: WO2013020867A1
Application number: PCT/EP2012/065013
Authority: WO
Inventors: Jörg Horzel; Angel URENA DE CASTRO
Original assignee: Imec
Priority date: 2011-08-05
Filing date: 2012-08-01
Publication date: 2013-02-14
Also published as: TW201310690A

Abstract

A method is described for fabricating back-contacted photovoltaic cells using a crystalline semiconductor substrate of a first conductivity type (e.g. n-type), the substrate having at the front side a p-type emitter region 32. Electrical contacts 34 are formed through the substrate as follows: at the rear side of the substrate 31 a dielectric layer 33 is formed, comprising a pattern of openings at predetermined locations where the electrical contacts are to be made; a layer 36 comprising a predetermined amount of a dopant metal of the second type, e.g. Al, is formed at least at the predetermined locations; the substrate is then heated to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy, leading to the formation of a melt comprising the dopant metal and the semiconductor material. Finally, the substrate is cooled to ambient temperature, thereby forming electrical contacts comprising eutectic regions 34 extending from the rear side of the substrate at least to the emitter region 32. In alternative versions the eutectic can be etched away, leaving vias.

Description

METHODS FOR THE FABRICATION OF BACK CONTACTED

PHOTOVOLTAIC CELLS

FIELD OF THE INVENTION

The disclosed technology relates to methods for fabricating back-contacted photovoltaic cells and to back-contacted photovoltaic cells thus fabricated.

BACKGROUND OF THE INVENTION

N-type crystalline silicon substrates can advantageously be used for fabricating high efficiency silicon photovoltaic cells. Main advantages of using an n-type substrate are a long diffusion length, reduced or no light-induced degradation, and possibly a lower sensitivity to degradation of the minority carrier diffusion length related to the presence of impurity atoms within the substrate as compared to p-type substrates.

Back-contacted photovoltaic cells, i.e. photovoltaic cells having electrical contacts to both n-type regions and p-type regions at the back side of the cells, have the advantage that shadowing losses are avoided or reduced, thus leading to good energy conversion efficiencies.

For example, MWT-type (metal wrap through) cells have at their front side an emitter junction and narrow metal fingers contacting the emitter. The external contacts to the oppositely doped emitter regions and bulk regions are both provided at the rear side of the cell. The current collected from the front side is led through an array of holes or vias through the substrate, the holes being filled with a metal so that an electrical contact is established between the metal fingers contacting the emitter at the front side and a metal contact at the rear side. The holes can for example be formed by laser drilling. Using this approach, shading losses from the front side metallization are strongly reduced. EWT-type (emitter wrap through) cells have an emitter junction at the front side and all electrical contacts at the rear side. An electrical connection between the emitter at the front side and emitter contacts at the rear side is established through an array of holes, wherein the emitter diffusion extends in the walls of the holes, from the front side to the rear side of the substrate. The holes can for example be formed by laser drilling. Using this approach, shading losses from front side metallization are avoided.

In US 7,170,001 a method for the fabrication of back-contacted silicon photovoltaic cells, more particularly EWT-type (emitter wrap through) cells, is described wherein the need for providing holes through the substrate is avoided. The fabrication process comprises a gradient-driven solute transport process, such as thermomigration, to create through a p-type silicon substrate an array of closely spaced n⁺⁺ conductive vias that electrically connect an n⁺ emitter layer at the front surface of a cell to ohmic contacts located at the back side of the cell. This method requires a strong thermal gradient over the wafer (i.e. between the front side and the rear side of the wafer), which may lead to thermal stress in the whole wafer. It requires active cooling of one side of the wafer while heating the opposite side of the wafer, to maintain the thermal gradient. This is not compatible with high-throughput photovoltaic cell processing and may lead to high energy consumption. In addition, the process time is relatively long (several minutes), and temperatures in excess of 1000°C are used, which may lead to degradation and/or contamination of the silicon substrate.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a cost-effective method for fabricating back-contacted photovoltaic cells with good energy conversion efficiency, the method being compatible with high-throughput photovoltaic cell processing. In a first aspect the present invention relates to a method for fabricating back- contacted photovoltaic cells, using a crystalline semiconductor substrate of a first conductivity type having a substrate thickness and having at the front side an emitter region of a second conductivity type opposite to the first conductivity type, the method comprising forming electrical contacts extending from the rear side of the substrate to the emitter region at the front side, wherein forming the electrical contacts comprises:

providing a dielectric layer at the rear side of the substrate; forming a pattern of openings through the dielectric layer by locally removing the dielectric layer at predetermined locations where the electrical contacts through the substrate towards the emitter region are to be formed; providing a layer comprising a dopant metal of the second type at the rear side of the substrate, at least at the predetermined locations where the dielectric layer has been removed; heating the substrate to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy; and cooling down the substrate to ambient temperature.

Heating the substrate to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy leads to the formation of a melt (liquid phase) comprising the dopant metal and the semiconductor material at an interface between the dopant metal and the semiconductor material, whereby the semiconductor material and the dopant metal are dissolved in the melt in a proportion according to the corresponding phase diagram. By selecting (based on the phase diagram and/or experiments) an appropriate amount of dopant metal and an appropriate peak temperature, taking into account the substrate thickness and the thickness of the emitter region, the heating results in penetration of the melt into the substrate till it at least reaches the emitter region at the front side. Cooling down the substrate to ambient temperature results in rejection of doped semiconductor material from the melt, leading to crystallization of doped semiconductor material (forming a doped epitaxial region) at the interface between the semiconductor material and the melt, and, upon reaching the eutectic temperature, solidification of the remaining liquid phase to form eutectic (semiconductor material - dopant metal) regions, the eutectic regions establishing an electrical contact to the emitter region.

In a second aspect, the present invention relates to back-contacted photovoltaic cells such as can be fabricated in accordance with the first aspect. The back-contacted cells according to some embodiments of the present invention comprise: a semiconductor substrate (base region) of a first conductivity type; a doped region of a second conductivity type opposite to the first conductivity type at the front side of the substrate (emitter region); a plurality of electrical contacts extending from the rear side of the substrate at least to the emitter region at the front side, wherein the plurality of electrical contacts comprise a eutectic region (alloyed region) comprising the semiconductor material and a dopant metal of the second type; and a heavily doped epitaxial (epitaxially grown) region at an interface between the semiconductor substrate and the eutectic regions. The method and the photovoltaic cells according to embodiments of the present invention are further described for preferred embodiments wherein the semiconductor substrate is an n-type silicon substrate, e.g. having an electrical resistivity in the range between about 0.5 Ohm-cm and 10 Ohm-cm and a thickness in the range between about 40 micrometer and 200 micrometer, and wherein the p-type dopant metal is aluminum. However, the present invention is not limited thereto. Other p-type dopant metals such as for example Ga, In or Ti can be used or a p-type semiconductor substrate and an n- type metal dopant such as for example Sb or Bi can be used. Other suitable substrate resistivities and other suitable substrate thicknesses may be used. For example, the substrate can also be an epitaxial layer, e.g. formed by epitaxial growth on another substrate followed by lift-off of the epitaxial layer. In such embodiments the thickness of the substrate may for example be in the range between 1 and 40 micrometers or between 1 and 30 micrometers, the present invention not being limited thereto. In some embodiments of the present invention, the semiconductor substrate is a monocrystalline substrate. However, the present invention is not limited thereto, and the semiconductor substrate can for example also be a multicrystalline substrate or a polycrystalline substrate. Embodiments of the present invention relate to a method for fabricating back- contacted photovoltaic cells, using a crystalline semiconductor substrate of a first conductivity type having a substrate thickness and having at the front side an emitter region of a second conductivity type opposite to the first conductivity type, the method comprising forming electrical contacts extending from the rear side of the substrate to the emitter region at the front side, wherein forming the electrical contacts comprises:

providing at the rear side of the substrate a dielectric layer having a pattern of openings through it by local removal of the dielectric layer at predetermined locations where the electrical contacts through the substrate towards the emitter region are to be formed; providing a layer comprising a dopant metal of the second type at the rear side of the substrate, at least at the predetermined locations where the dielectric layer is absent; heating the substrate to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy; and cooling down the substrate to ambient temperature.

Heating the substrate to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy leads to the formation of a melt (liquid phase) comprising the dopant metal and the semiconductor material at the interface between the dopant metal and the semiconductor material, the semiconductor material and the dopant metal dissolving in the melt in a proportion according to the corresponding phase diagram. By selecting (on the basis of the phase diagram) an appropriate amount of dopant metal and an appropriate peak temperature, taking into account the substrate thickness and the thickness of the emitter region, the heating results in penetration of the melt into the substrate till it at least reaches the emitter region. Cooling down the substrate to ambient temperature results in rejection of doped semiconductor material from the melt, leading to crystallization of doped semiconductor material (forming a doped epitaxial region) at an interface between the semiconductor material and the melt, and, upon reaching the eutectic temperature, solidification of the remaining liquid phase to form eutectic semiconductor-material/dopant-metal regions, the eutectic regions establishing an electrical contact to the emitter region at the front side, through the semiconductor substrate.

In embodiments of the present invention, heating the substrate to the peak temperature can for example be performed in a typical firing furnace as used in photovoltaic cell processing. However, the present invention is not limited thereto.

Heating the substrate to a temperature substantially higher than the eutectic temperature can comprise heating the substrate to a temperature higher than the dopant metal melting temperature. It is an advantage of heating the substrate to a temperature higher than the dopant metal melting temperature that in some embodiments all dopant metal can be in exchange with the semiconductor material.

The semiconductor substrate may be a (lOO)-oriented, n-type monocrystalline silicon substrate, e.g. having an electrical resistivity in the range between about

0.5 Ohm-cm and 10 Ohm-cm and a thickness in the range between about 40 micrometer and 200 micrometer, the present invention not being limited thereto. In such

embodiments the dopant metal can for example be aluminum and the peak temperature can for example be in the range between about 750°C and 1000°C. The substrate can for example also be an epitaxial layer, e.g. formed by epitaxial growth on another substrate followed by lift-off of the epitaxial layer. In such embodiments the thickness of the substrate may for example be in the range between 1 micrometer and 40 micrometer or between 1 micrometer and 30 micrometer.

The emitter region can be formed by diffusion of a dopant of the second conductivity type into the semiconductor substrate, or it can be formed by epitaxial growth of a layer having a conductivity type opposite to the substrate conductivity type, or by any other suitable method known to a person skilled in the art. It is an advantage of epitaxially growing the emitter layer that it can be relatively thick (for example in the range between about 1 micrometer and 20 micrometer), leading to a larger process window for contacting the emitter regions from the rear side.

The dielectric layer forms a barrier for the melt, such that the melt cannot penetrate to the underlying semiconductor substrate at locations where the dielectric layer is present. Preferably the dielectric layer also provides a good rear surface passivation of the semiconductor substrate and/or a good rear surface reflection. The dielectric layer can be a single layer or a stack of dielectric layers. It can for example contain Si _x, SiO_x, SiO_xN_y, TiO_x, A10_x or any other suitable material known to a person skilled in the art.

The openings through the dielectric layer can be a regular array of openings. The individual openings can be circular, oval, square, rectangular, or any other suitable shape, or a combination of different shapes. For example, the pattern of openings can comprise a plurality of substantially parallel 'fingers', the fingers having an extended rectangular shape with a width of the same order as the substrate thickness or less (e.g. a width in the range between 10 and 100 micrometers) and with a length of the order of the cell size (i.e. extending between one edge of the cell and the opposite edge of the cell). The pattern of openings can also comprise a plurality of 'dashed fingers' wherein each finger is composed of a plurality of elements having a rectangular shape, arranged in a line.

Preferably the longitudinal direction of such finger-shaped openings is oriented along a direction along which the alloying process is fastest. For example, when using a (100) monocrystalline silicon wafer and a pattern comprising a plurality of rectangular openings, the longitudinal direction of the rectangular openings is preferably oriented parallel to an <110> direction or orthogonal plane orientations. Therefore it may be also advantageous to cut such (100) wafers from the ingot with edges parallel to <110> orientations. Selecting an appropriate amount of dopant metal and an appropriate peak temperature can be done on the basis of the phase diagram for the semiconductor- material/dopant-metal alloy. For example, assuming anisotropic alloying (wherein the alloying process is faster for some crystal orientations than for other crystal orientations), for a given substrate thickness and for a given pattern of openings in the dielectric layer where the dopant metal is in contact with the semiconductor material, it can be calculated how much semiconductor material needs to be dissolved in the melt and how much dopant metal is needed at a given peak temperature to allow penetration of the melt completely through the substrate, or at least till the melt contacts the emitter region. However, the amount of dopant metal needed usually also depends for example on the heating conditions (i.e. the peak temperature, temperature ramp-up rate and cool-down rate, the time at the peak temperature) and on the composition of the layer comprising the dopant metal. A suitable amount of dopant metal can be determined by experiment.

Such methods for fabricating back-contacted photovoltaic cells allow low-cost industrial processing. As compared to some prior-art methods, the need for providing a thermal gradient over the substrate is avoided and/or the need for forming holes or vias through the substrate, such as by laser drilling, is avoided. The electrical contacts comprising alloyed regions extending from the rear side of the substrate to the emitter region have the advantage of a low electrical resistance. This results in photovoltaic cells having a low series resistance between the front side (emitter region) and the electrical (emitter) contacts at the rear side of the cells. Also, the heavily doped regions (epitaxially grown regions) at the interface between the alloyed regions and the substrate (base region of the cell) provide a good shielding of minority carriers from the alloyed regions, thus strongly reducing or avoiding minority carrier

recombination at the electrical contacts.

The alloyed regions can have a triangular cross-section, which may lead to photovoltaic cells with improved light trapping and improved carrier collection. In the case of alloyed regions arising from small, point-like holes in the dielectric layer, the alloy regions may be pyramidal in shape; for narrow elongate slits they may be ridge- shaped with a triangular section.

The present invention allows fabrication of photovoltaic cells having contacts through the substrate that are narrow at the front side of the cells, thus limiting shadowing losses, and at the same time wider at the rear side of the cells, thus allowing a good electrical contact. The present invention further relates to back-contacted photovoltaic cells comprising: a semiconductor substrate (base region) of a first conductivity type; a doped region of a second conductivity type opposite to the first conductivity type at the front side of the substrate (emitter region); a plurality of contacts extending from the rear side of the substrate at least to the emitter region, wherein the plurality of contacts include a eutectic region (alloyed region); and a heavily doped epitaxial region at the interface between the semiconductor substrate and the eutectic regions.

The plurality of contacts preferably has a rectangular shape, such as a finger shape or a 'dashed finger' shape (wherein each finger is composed of a plurality of elements having a rectangular shape, arranged in a line) in a plane substantially parallel to a surface plane of the substrate, and the plurality of contacts preferably has a triangular or trapezoidal cross-section (truncated triangle) in a plane substantially orthogonal to the surface plane of the substrate and to the longitudinal direction of the plurality of rectangular contacts. It is an advantage of such a triangular cross-section that it may lead to improved light trapping and improved carrier collection. It is a further advantage of a triangular cross-section that electrical contacts to the emitter region can be narrow at the front side of the cells, thus limiting shadowing losses (e.g. less than about 4%, particularly less than about 2%, particularly less than about 1% of the total substrate area), and at the same time wider at the rear side of the cells, thus enabling a good electrical contact at the rear side. However, the present disclosure is not limited hereto, and the cross section of the electrical contacts in a plane substantially orthogonal to a surface plane of the substrate and substantially orthogonal to the longitudinal direction of the plurality of rectangular contacts can be different from a triangular cross-section; for example, it can be a cross-section having rounded edges, e.g. a (semi-)circular cross- section, or a cross-section comprising a combination of straight edges and rounded edges, or even irregular.

Such alloyed regions forming the plurality of contacts have a low electrical resistance, thus leading to photovoltaic cells having a low series resistance between the front side (emitter region) and contacts at the rear side of the cells. At the interface between the alloyed region and the substrate (base region) a heavily doped region is present, providing a good shielding of minority carriers from the (recombination active) alloyed region. Certain objects and advantages of various inventive aspects have been described above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the invention. The invention, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description of embodiments, when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 schematically illustrates process steps of a method according to one

embodiment; Figure 2 shows a schematic cross-section of a photovoltaic cell fabricated in

accordance with one embodiment;

Figure 3 shows a variant, having narrow metal finger contacts at the front side;

Figure 4 shows a further variant, wherein the semiconductor-metal alloy is

removed; Figure 5 shows exemplary patterns of openings in the rear side dielectric layer that can be used in methods of the invention;

Figure 6 shows the Al-Si binary phase diagram;

Figure 7 illustrates an exemplary process flow for fabricating photovoltaic cells comprising alloyed contacts in one embodiment; Figure 8 shows an SEM cross-section of a silicon substrate with an alloyed region formed according to a method of the present invention;

Figure 9 shows an example of a typical temperature profile that can be used in a method of the present invention;

Figure 10 shows a micrograph of a silicon substrate with a thick Al layer and an alloyed region formed according to a method of the present invention;

Figure 11 shows a silicon substrate with a thick Al layer and an alloyed region

formed according to a method of the present invention; and

Figure 12 is an SEM picture of a silicon substrate processed in accordance with a method of the present invention, showing a thick Al layer ('finger') on the rear side and Al penetrating through the substrate up to the front side.

In the different drawings, the same reference signs refer to the same or analogous

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention and how it may be practised in particular embodiments. However, it will be understood that the present invention may be practised without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present invention. While the present invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the invention. It is also noted that, in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that certain embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein. It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.

In the context of the present invention, the front surface or front side of a photovoltaic cell is the surface or side adapted for being oriented towards a light source and thus for receiving illumination. The back surface, back side, rear surface or rear side of a photovoltaic cell is the surface or side opposite to the front surface. The front side of a substrate is the side of the substrate corresponding to the front side of the photovoltaic cell to be fabricated, while the rear side or back side of the substrate corresponds to the back side of the photovoltaic cell to be fabricated. A method according to one embodiment of the present invention is schematically illustrated in Figure 1. At the front side 10 of an n-type silicon substrate 31 a p-type doped region is provided, thereby forming an emitter region 32 (Figure 1(a)). At the rear side 20 of the substrate 31 a dielectric layer 33 is provided (Figure 1(a)) such as for example a silicon-oxide layer or a silicon-nitride layer. The dielectric layer 33 can also be a dielectric stack comprising at least two dielectric layers. In the example shown in Figure 1, the front side 10 of the substrate is textured. However, the present invention is not limited thereto.

As illustrated in Figure 1(b), in the next step the dielectric layer 33 is locally removed in such a way that openings 30 are formed in the dielectric layer 33, thereby locally exposing the rear side 20 of the silicon substrate 31 at locations where electrical connections or electrical contacts to the front side emitter region 32 are to be formed through the substrate 31. Making the openings 30 in the dielectric layer 33 or dielectric stack can for example be done by laser ablation or by selective etching or by any other suitable method known to a person skilled in the art. The pattern of openings 30 may comprise openings in the form of dots (e.g. circular openings, oval openings, square openings, ....) or in the form of lines (e.g. rectangular openings, finger-shaped openings, dashed fingers) or any other suitable shape or combinations of shapes. Some examples of suitable patterns are shown in Figure 5. For example, the pattern of openings can comprise a plurality of substantially parallel 'fingers', the fingers having a rectangular shape with a width of the order of the substrate thickness or less (such as for example a width in the range between 10 micrometer and 100 micrometer) and with a length of the order of the cell size (i.e. extending between opposite edges of the cell), as illustrated in the bottom-right drawing of Figure 5. The pattern of openings can for example also comprise a plurality of 'dashed fingers' wherein each finger is composed of a plurality of elements having a rectangular shape, as illustrated in the bottom- left drawing of Figure 5. Preferably the longitudinal direction of such finger-shaped openings or of such dashed fingers is oriented along a direction along which the alloying process is fastest. For example, when using a (100) monocrystalline silicon wafer and a pattern comprising a plurality of rectangular openings, a longitudinal direction of such rectangular openings is preferably oriented parallel to a <110> direction or orthogonal plane orientations.

Next (Figure 1(c)) a sufficiently thick aluminum layer 40 is provided at the rear side, at least at the locations of the openings 30, where the dielectric layer 33 has been removed. The minimum thickness of the aluminum layer 40 depends on the peak temperature to which the substrate is heated in a subsequent step and on the thickness of the silicon substrate 31 , as well as on a number of other parameters such as for example the width of the openings 30, the shape of the openings 30, the distance between neighbouring openings, the heating rate, the time at the peak temperature, and the composition of the aluminum layer 40. The peak temperature determines the amount of silicon that can be dissolved in the aluminum-silicon melt. For example, according to the Al-Si phase diagram (shown in Figure 6) more than about 40 weight% of silicon can be dissolved in the melt at a temperature of about 1000°C. At a temperature of about 900°C about 35 weight% of silicon can be dissolved in the melt. Also, the amount of aluminum needed and thus the minimum thickness of the aluminum layer 40 decreases with decreasing substrate thickness. For example, when providing an rectangular aluminum layer 40 about 400 micrometer wide, covering an rectangular opening 30 about 10 to 100 micrometers wide in the underlying dielectric layer 33, an aluminum layer thickness of about 70 micrometer is needed to alloy through an about 150 micrometer thick silicon substrate at about 900°C. The required Al thickness is proportional to the square of the wafer thickness. It may be advantageous to provide the aluminum layer 40 locally, for example by locally dispensing an Al paste, as a thick deposit (as schematically illustrated in

Figure 1(c)), rather than uniformly. With a view to easy alignment to the openings 30 in the dielectric layer 33, it can be advantageous to apply the aluminum layer 40 according to a pattern that is wider than the openings 30 in the dielectric layer 33. The openings 30 formed in the dielectric layer 33 can for example have a width in the range between about 10 micrometer and 100 micrometer, particularly between about 10 micrometer and 30 micrometer. The width of the aluminum regions 40 can for example be in the range between about 100 micrometer and 500 micrometer. However, the present invention is not limited thereto and other suitable dimensions can be used.

If local point openings 30 (e.g. having a circular shape with a diameter of the order of about 10 micrometer to 20 micrometer) are formed in the dielectric layer 33 it is possible for instance to arrange the local openings along lines (e.g. with a spacing of about 50 to 200 micrometers between the dots) and to print aluminum lines 40 over these openings. After performing the alloying process (as further described), this results in point contacts between the rear side 20 and the front side emitter region 32 and in rear- side contacts interconnecting the point contacts along a line. In case of such point contacts, the amount of aluminum needed can be considerably reduced as compared to line contacts, still allowing alloying through the substrate. However, in this case resistive losses in the emitter region 32 and in the eutectic contacts through the substrate may be larger than with linear openings in the dielectric layer.

If the applied aluminum layer can be sufficiently thick it may also be useful to apply the aluminum layer over the whole rear surface of the substrate. This can be particularly of interest when the alloying process is sufficiently slow to allow all areas of the applied aluminum layer to be in exchange with the silicon areas exposed after making the openings 30 in the dielectric layer 33 of the rear side 20 of the substrate 31.

The aluminum layer 40 can be provided by any suitable deposition technique such as for example paste writing, dispensing, metal jet deposition, flame spraying, printing (such as screen printing, pad printing, offset printing, transfer printing, etc), laser-assisted transfer of metal layers, sputtering, evaporation, and other technologies known to apply metal layers selectively or homogeneously.

The substrate with the aluminum layer 40 (Figure 1(c)) is then heated to an adequate peak temperature higher than the silicon- aluminum eutectic temperature, e.g. to a temperature in the range between about 580°C and 1100°C, particularly between about 750°C and 1000°C, and then cooled down to ambient temperature. In order to realize a high throughput, fast heating may be preferred. It is well known from the Al-Si binary phase diagram (shown in Figure 6) that significant amounts of silicon can be consumed into a melt of silicon and aluminum as long as the temperature is well above the eutectic temperature (577°C). Upon cooling down, recrystallization of highly aluminum-doped silicon takes place at the interface of the melt and the silicon substrate, until the eutectic composition is reached and the remaining melt becomes solid, forming a eutectic region having the eutectic composition (12.6% Si in Al). It is also known that if the interaction between Al and Si at elevated temperatures takes place locally, silicon is consumed faster according to crystal orientations of lower density, thus leaving {111 } oriented interface regions when cooling down. Thus, when using a (lOO)-oriented substrate, an aluminum / silicon eutectic region (electrical contact) 34 is formed that shows, in the case of anisotropic alloying, a triangular cross-section in a plane orthogonal to the surface plane of the substrate, with sidewalls along the {111 } planes, making an angle of 54.7 degrees with the surface plane of the substrate. This is illustrated in Figure 1(d)). In some embodiments, a substrate with (100) orientation is used that has edges with <011> orientations and the elongate (e.g. rectangular) openings in the dielectric layer are arranged with their longitudinal direction parallel to the edges of such a wafer.

Selecting appropriate conditions, it is possible to alloy through the complete silicon substrate 31, resulting in electrical connections or electrical contacts 34 to the front side emitter region 32 through the substrate (or at least extending from the rear side 20 of the substrate 31 to the emitter region 32) as illustrated in Figure 1(d). The alloying process results in a eutectic region 34 (forming electrical connections) inside and through the silicon wafer 31, with a strongly aluminum-doped silicon region 35 at the interface between the eutectic region 34 and the silicon substrate 31. Thus, a method according to the present invention results in simultaneous formation of metal alloy contacts 34 through the substrate and highly doped regions 35 adjacent to these contacts 34. The highly doped recrystallized regions 35 provide a good shielding of the contacts 34 from minority carriers, thus reducing minority-carrier recombination losses in a simple and cost-effective way.

The resulting triangular cross-section of the contacts 34 formed according to embodiments of the present invention is beneficial for optical reasons: the small width of the contacts at the front side of the cell leads to reduced shading losses. The highly doped (and metallized) areas may provide improved light trapping and carrier collection properties. The recrystallized regions 35 provide a good shielding of the metal alloy contacts 34 from the base region, thus reducing minority carrier recombination at the contacts. The contacts 34 are of eutectic composition (-12.6% of Si in Al) and have preferably a triangular cross section that is wide at the rear side 20 of the substrate 31 and narrow at the front side 10 of the substrate 31. For example, the width at the rear side can be of the order of about 60% to 90% of the substrate thickness and the width at the front side can be less than about 50 micrometer, particularly in the range between about 10 micrometer and 30 micrometer. However, the present invention is not limited thereto and other sizes or widths can be used. The thickness of the aluminum-doped regions 35 (formed by crystallization when cooling down) depends on the alloying temperature (peak temperature) used during the heat treatment, the regions 35 being thicker for higher peak temperatures. The thickness of these regions 35 may for example be in the range between about 1 micrometer and 50 micrometer. The heavily doped regions 35 can be considered as part of a selective emitter together with the front side p-type region 32.

Figure 8 shows an SEM cross-section of a silicon substrate 31 with an alloyed region 34 formed according to a method of the present invention. A 5 -micrometer-thick Al layer was provided by Physical Vapor Deposition on a patterned dielectric layer with openings having a width of 20 micrometer, and the sample was heated to a peak temperature of 885°C to induce alloying. It can be seen in Figure 8 that the alloyed region 34 has a triangular, more or less equilateral, cross-section and that it extends partially through the silicon substrate. In the example shown, the thickness of the silicon substrate was about 144 micrometer and the alloyed region extends more than 70 micrometer into the substrate. In other embodiments of the present invention the cross section of the electrical contacts 34 in a plane substantially orthogonal to the surface plane of the substrate can be other than triangular, particularly for larger apertures in the dielectric. For example, it can be a cross section comprising rounded edges, e.g. a (semi-)circular cross section, or a cross section comprising a combination of straight edges and rounded edges. Electrical contacts 34 having such a non-triangular cross-section may be less advantageous because they may lead to larger front-side shading losses as compared to contacts with a triangular cross-section. An example of an alloyed region having such a non-triangular cross-section is shown in Figure 10. An Al layer (Al paste, thickness about 460 μιη) was screen-printed on a patterned dielectric layer with openings having a width of 80 μιη, and the sample was heated to a peak temperature of 1000°C to induce alloying. In Figure 10 also the dopant metal layer (Al layer 40) provided on the silicon substrate can be seen. A commercial Al paste was used containing glass frit and/or other additives (the exact composition not being known). Figure 11 shows a SEM picture of a similar sample wherein the peak temperature was 900°C.

Figure 12 is a SEM picture of a silicon substrate processed in accordance with a method of the present disclosure. The picture is a tilted view of the substrate, showing a thick patterned Al layer ('Finger') on the rear side of the substrate, and showing the front side of the substrate with Al penetrating through the substrate up to the front side. A peak temperature of 1000°C, with a temperature profile as shown in Figure 9, was used for this sample.

As shown in Figure 1(d), after performing the alloying process, layers 36 comprising aluminum or a mixture of silicon and aluminum may remain at the rear side 20 of the substrate. These layers 36 are preferably removed before finishing cell processing, e.g. before providing metal contacts to the alloyed regions and to the substrate.

As described above, by performing an adequate heat treatment, e.g. with a peak temperature in the range between about 750°C and 1000°C, the formation of

anisotropically alloyed regions 34 throughout the complete substrate 31 can be obtained (Figure 1(d)). To determine an adequate heat treatment, the binary phase diagram between Si and Al (shown in Figure 6) is a useful tool. The phase diagram shows how much silicon is consumed in the melt when heating the substrate to a given temperature. Assuming an alloying temperature of just above about 577°C, only about 12.6% of silicon can be incorporated in the melt. For an alloying temperature between about 900°C and 950°C an amount of silicon between 30 and 40 weight-% can be incorporated in the melt (by anisotropic dissolution). Assuming that 35 weight-% of Si is taken up in the Al-Si melt during an alloying process and assuming that rectangular-shaped Al patterns of 200 micrometer width and 150 micrometer height of pure Al are deposited on small linear openings in the rear side dielectric layer 33 (e.g. linear openings with a width of the order of about 20 to 30 micrometers), it is possible to melt (choosing the right orientation of the lines with respect to the crystal orientation) a linear volume with a triangular cross section that entirely extends through a 180 micrometer thick silicon wafer.

Upon cooling, according to the phase diagram silicon is rejected from the melt and solidifies preferably as crystalline silicon. Taking the difference of 22.4 weight-% Si between the eutectic composition (12.6 weight-% Si) at 577°C and the Si share taken up at the maximum alloying temperature (35 weight-% Si) this requires recrystallization of a large volume of silicon. During cooling down after reaching the maximum alloying temperature, recrystallization happens preferentially as epitaxial recrystallization at the interface between the melt and the silicon. In that case a large volume of highly aluminum-doped silicon is formed until the eutectic temperature is reached. When cooling down below the eutectic temperature, the remaining melt solidifies, thereby typically forming a lamella structure of eutectic composition (12.6 weight% Si in Al). Such a slow cooling process is preferred over a faster cooling process in which the silicon cannot recrystallize epitaxially at the interface between the melt and the silicon but wherein silicon solidification rather takes place at various (arbitrary) spots in the solidifying melt volume.

If slow cooling is used (such as for example a cooling rate in the range between 50°C/minute to 100°C/minute till reaching the eutectic temperature, the present invention not being limited thereto), preferably the throughput of the process still meets the industrial requirements to process in a production line an average of about 1

wafer/second.

The amount of silicon that is consumed during the alloying process is mainly controlled by the temperature of the heat treatment and by the amount of Al that is in exchange with the silicon surface, assuming that the silicon volume of the wafer is large compared to the Al volume in exchange with it, and assuming that there is sufficient time in heating up and cooling down to allow interaction as indicated by the Al-Si binary phase diagram.

Figure 2 shows a schematic cross-section of a back-contacted photovoltaic cell fabricated in accordance with one embodiment. In the example shown, an n-type crystalline silicon substrate 31 is used. The front side 10 of the substrate is textured and a p⁺-type region (emitter region 32) is present at the front side. Alloyed regions 34 extend from the rear side 20 of the substrate to the p⁺ emitter region 32 at the front side, the alloyed regions 34 forming electrical contacts to the emitter region 32 and being narrower at the front side than at the rear side. At the interface between the alloyed regions 34 and the bulk region (substrate 31) a heavily doped region 35 is present. At the rear side 20, the cell comprises first metal contacts 41 to the alloyed regions 34 (and thus to the emitter region 32) and second metal contacts 39 to the bulk region 31.

In a back-contacted photovoltaic cell according to embodiments of the present invention, the electrical conductivity of the alloyed regions 34 is sufficiently high to ensure low resistive losses in the contacts 34 between the rear side of the cell and the emitter region 32 at the front side of the cell. The pattern and spacing between the contacts 34 is preferably optimized together with the front emitter 32 optimization, taking into account the emitter sheet resistance, contact resistance between the emitter and the eutectic contacts, and series-resistance losses in the emitter, versus effective shading and emitter recombination losses. A typical spacing between the eutectic contacts 34 reaching from the rear 2 to the front 10 of the substrate can for example be of the order of about 1 mm to 2 mm. This allows the front emitter resistance losses to be kept low and it allows using simple printing technology such as for instance screen printing or dispensing of Al pastes for the Al contact application. However, the present invention is not limited thereto and other spacings between the eutectic contacts 34 can be used.

In photovoltaic cells according to embodiments of the present invention, emitter regions 32 with low surface dopant concentration and deep penetration depth can be used. This can substantially reduce or avoid e.g. shunting issues related to shallow emitters. The second metal contacts 39 to the n-type base region 31 are preferably provided in between the first metal contacts 41 to the eutectic regions 34, as illustrated in Figure 2. These second metal contacts 39 are preferably formed to moderately doped n⁺ regions 37 on the rear side 20 (formed for example by phosphorus diffusion from the rear) or to selective n⁺⁺ regions 38 that may be formed for instance by P paste diffusion or by laser chemical processing. The latter process has the advantage that openings in the dielectric layer 33 and subsequent contact formation (e.g. by plating metal contacts from an aqueous solution) result in a self-aligned process.

In certain embodiments, the formation of second metal contacts 39 to the n -type regions 37 may be done during the alloying step, i.e. during the step of heating the substrate to the peak temperature as used in a method according to one embodiment for forming electrical contacts 34 extending from the rear side of the substrate to the emitter region. However, it may be beneficial to perform the alloying step independently of the formation of metal contacts, because this allows more freedom in selecting the peak temperature and cooling rate of the alloying process.

In the photovoltaic cell illustrated in Figure 2 the front surface 10 is free from metal contacts. However, the present invention is not limited thereto. For example, as illustrated in Figure 3, at the front surface narrow metal lines or contact fingers 40 can be provided, e.g. having a width in the range between 30 micrometer and 90 micrometer. If the alloyed regions 34 completely extend through the substrate 31, these contact fingers 40 are in electrical contact with the alloyed regions 34. In such embodiments, the photogenerated current is collected by the contact fingers 40 at the front side of the cell, and then flows through the alloyed regions 34 formed through the substrate 31 to the first metal contacts 41 at the rear side of the cell. In certain embodiments wherein the alloyed regions 34 only extend to the emitter region 32 and not completely through the substrate, the plurality of contact fingers 40 is in electrical contact with the alloyed regions 34 through the emitter region 32. In such embodiments, the photogenerated current is collected by the contact fingers 40 at the front side of the cell, and then flows through the emitter region 32 towards the alloyed regions 34 to the first metal contacts 41 at the rear side of the cell. It is an advantage of providing contact fingers 40 that it allows reducing the area of eutectic contacts through the substrate, because the emitter resistance is not a limiting factor. It is however a disadvantage of providing the contact fingers 40 that it results in shadowing losses.

In certain embodiments it may be beneficial if the n -doped regions 37 have a doping concentration that is of the same order of magnitude as the doping concentration of the p -doped regions 35 at the interface between the alloyed regions 34 and the silicon substrate 31. In that case it is possible to over-compensate a pre-diffused n⁺- layer 37 by aluminum doping during the alloying process. Preferably the maximum doping concentration in the heavily doped p⁺⁺-Si regions 35 is of the same order as the maximum doping level of the n -Si regions 37. In this case there is no need for taking special care for junction isolation between those regions. However, the invention is not limited thereto and other methods for p-n isolation such as laser ablation, diffusion masking, selective etching and other technologies known to persons skilled the art may be used as well. In certain embodiments, after performing the alloying process, the eutectic alloyed regions 34 can be removed at least partially from the photovoltaic cell. At least partially removing the alloyed regions 34 may be beneficial, for example for reducing stress, for reducing the size of the interface between the silicon base region 31 and the contacts 34 (which may result in a better open-circuit voltage V_oc) and/or for allowing surface passivation. At least partially removing the alloyed regions 34 can be done by performing an etch step, for example in hot orthophosphoric acid, or in a HC1 solution or any other suitable solution known in the art for removing Al layers or Al-rich layers. It is an advantage of removing the eutectic regions 34 that stress resulting from the different thermal expansion coefficient of the eutectic alloy as compared to the silicon substrate may be avoided. Such stress in the silicon substrate may degrade the minority carrier lifetime and thus the performance of the photovoltaic cell.

Complete removal of the alloyed regions 34 results in unfilled vias (e.g. having an inverted pyramid shape) or unfilled grooves e.g. with a triangular cross-section inside the silicon substrate 31, as for example illustrated in Figure 4. The etch step for removing the alloyed regions 34 can be done at an early stage of the photovoltaic cell processing sequence. In this case the surface of the unfilled vias or grooves can be passivated, e.g. by providing a surface passivation layer 42. On top of the surface passivation layer 42 a metal layer 43 can be provided that forms an electrical contact to the front contacts 40, if present, or to the front-side emitter region 32 while keeping the side walls of the vias or grooves through the substrate 31 passivated. The advantage of such a sequence is that the effective metal-to-silicon contact area can be minimized for contacts both to p-type areas and to n-type areas. In such embodiments the metal layer 43 may be applied by evaporation, sputtering or single-side plating. It may be applied using a low-temperature processing step. The metal layer 43 may also serve as a rear side reflector. Examples of metal layers 43 that may be used are stacks of Ag-Sn, Ag-Ti-Cu, Ti-Cu, Ni-Cu, Pd-Ni-Cu, Al/Si(l%)-Al, Al/Si(l%)-Ti-Cu. Separation of contacts 43 to p-type regions and contacts 39 to n-type regions may be achieved by ablation, by selective masking, selective removal, selective etching or other suitable methods known by a person skilled in the art.

In certain embodiments, in addition to removing the alloyed regions 34 the heavily Al doped region 35 formed during the alloying process at the interface between the eutectic regions 34 and the silicon substrate 31 can also be removed at least partially.

A method according to an embodiment of the present invention can also be used in a process for fabricating emitter- wrap-through cells. In this case the alloyed regions 34 are removed after alloying. In particular for high alloying temperatures a thick heavily p⁺⁺-doped region 35 is formed at the interface between the alloyed regions 34 and the silicon substrate 31. After removal of the alloyed regions 34, the p⁺⁺ surfaces of the wrap-through emitter regions (corresponding to heavily doped regions 35) are preferably passivated, e.g. by providing a dielectric layer 42. This dielectric passivation layer may advantageously also serve as an internal reflection layer.

Electrical contacts to the wrapped through emitter regions may be formed in several ways. One of many possibilities is to open, for example by means of laser ablation, areas in the dielectric layers 42 at the rear side 20 just at the location of the p⁺⁺-doped regions 35, and to apply metal contacts by plating or sputtering or evaporation to these regions. Alternatively, metal pastes such as Al or Ag/Al pastes may be applied locally at those regions and fired through the dielectric layer if needed. Preferably the contact area to the p⁺⁺-doped regions 35 is minimized and simultaneously a low contact resistance is realized, for ensuring low series resistance losses.

Certain embodiments are further illustrated by an exemplary process flow for manufacturing back-contacted photovoltaic cells. However, this process flow is just an example illustrating a method in accordance with these embodiments and the invention is not limited thereto.

An exemplary process flow is schematically illustrated in Figure 7. In the example shown, an n-type, (lOO)-oriented monocrystalline Si wafer is used. After alkaline anisotropic texturing, a rear side polishing step is performed, e.g. by etching in aqueous alkaline (for instance NaOH- or KOH-based) or acidic (for instance HN0₃:HF- based) etching solutions. This results in a wafer with a textured front surface and a polished rear surface. Next the wafer is cleaned. In the next step a boron-doped emitter region 32 is formed at the front surface of the substrate 31. The emitter region may be formed by a diffusion process such as for example BBr₃ diffusion in a tube furnace or by applying a boron-doped oxide layer in an LPCVD or APCVD process to the front side of the substrate. Other methods such as for example implantation or the epitaxial growth of a borondoped emitter region may be used. Next, a dopant drive-in step is done at an elevated temperature, for example at a temperature in the range between about 900°C and 1100°C, to form heavily doped emitter regions (particularly more than about 1 micrometer deep). An advantageous B- doped emitter has a B surface concentration in the range between about 1 · 10¹⁸ and 5-10¹⁹ atoms/cm³ and a sheet resistance in the range between about 80 Ohm per square and 160 Ohm per square.

The boron-doped region can be formed at both sides of the wafer. In this case a single-side etching process is performed for removing the boron-doped regions from the rear surface (at least at those areas that will become phosphorus-doped areas in the subsequent process flow). In a subsequent processing step, n-type doped regions 37, 38 are formed at the rear side. Preferably all n⁺ areas 37 that will not be contacted on the rear surface are only relatively weakly doped (typically about 5· 10¹⁸ to 5· 10¹⁹ P atoms/cm³) and have a sheet resistance of about 40 Ohm per square to 160 Ohm per square, depending on the contact pattern that will be applied on the rear and depending on the base doping. The n⁺⁺ areas 38 where in a later stage of the process metal contacts will be provided preferably have a very high doping level with a surface concentration in excess of 10²⁰ P-atoms/cm³ and a local sheet resistance in the range of about 5 Ohm per square to 40 Ohm per square.

After the formation of the n-type regions the remaining PSG and BSG layers are removed and the wafers preferably pass through a cleaning process sequence.

Next, a silicon oxide layer may be provided, possibly only at the rear surface of the substrate. One option is to perform a dry or wet thermal oxidation to grow a high quality oxide layer on the silicon surface(s), resulting in a low surface

recombination velocity. Alternatively, also other methods may be used to apply silicon oxide layers such as CVD methods (LPCVD, APCVD, PECVD) to deposit SiO_x layers of desired thickness to one surface or to the front and the rear sides of the wafer. On the rear side of the wafer a thick SiO_x layer may serve for example at least partially as a mask for the Al-Si alloying process. However also a Si _x:H_y layer may be used as a masking and passivation layer for the rear n-type regions of the photovoltaic cell.

Silicon nitride serves also very effectively as a barrier during Al alloying, preventing Al spikes forming through the dielectric layers at locations where it is not desirable. In this respect it is preferred to have dense SiN_x layers without pinholes.

On the rear surface also a stack comprising different layers may be used, such as for example a stack comprising a SiN_x:H layer and a silicon oxide layer or any other suitable stack of layers known to a person skilled in the art. On the front side, for example a stack comprising a thin A10_x passivation layer and an antireflection coating such as for example a TiO_x antireflection coating may be provided. However, other combinations of passivation layers and antireflection coatings may be used.

Next, the rear- side dielectric layer 33 or dielectric stack is patterned, for example by laser ablation or selective etching, so that openings 30 are formed at locations where electrical connections are to be formed through the substrate. A sufficient quantity of Al is then brought into contact with the silicon and an alloying process in accordance with one embodiment is performed, thereby forming electrical connections through the complete substrate. In embodiments wherein an aluminum layer has been deposited on the entire rear side of the wafer, it may be advantageous to remove the alloyed regions formed on top of the dielectric layer 33. This may be done for instance by printing a polymeric masking paste for masking the regions corresponding to the eutectic contacts 34, and etching off the alloyed regions elsewhere in a hot aqueous solution of H₃PO₄, in HC1 or by other means known to those skilled in the art. The polymeric paste patterning process may in addition include masking regions that later in the process will be dedicated to become busbar regions but that have not been alloyed through the substrate. The polymeric masking step can be avoided by performing an etching step in a hot solution of ortho-phosphoric acid, thereby etching back the alloyed regions over the entire rear surface. The etch-back is preferably performed sufficiently long to remove all eutectic regions present on top of the dielectric layer 33, and it may stop at any depth of the alloyed regions 34 (contacts through the substrate).

When the aluminum layer has been applied selectively (locally) prior to alloying, it may be useful to remove at least part of the layers 36 by an etch-back as described above. The reason is that the rather thick patterns of Al that have been originally applied to those regions on the rear surface may protrude too far above the rear surface.

Depending on the interconnection technology chosen this might be an advantage or a disadvantage. Again it is possible to etch back the alloyed regions 34 at least partially to a predetermined depth.

In the next step metal contacts may be formed to the n⁺⁺-type regions 38. For example, an Ag paste can be applied (for example by screen printing or other

technologies known to be applicable in high-throughput, low-cost industrial photovoltaic cell processing) to those regions that have been selectively doped with a high P-surface concentration. Those areas 38 are typically just in between the alloyed regions 34 reaching to the front surface boron emitter of the photovoltaic cell. The regions 38 where n-type contacts 39 are to be made preferably have a high P surface concentration, enabling a low contact resistance. Busbar regions may also be formed by firing through the dielectric layers in the same process as long as these regions (typically perpendicular to the elongate contact fingers) have an n-type Si surface below the dielectric layer. There is no need to realize a low contact resistance in these busbar regions. Only a good adhesion and a high electrical conductivity need to be achieved in those busbar regions. This allows for example using different pastes for finger and busbar regions on the rear surface. The busbar paste does not need to be fired through the dielectric layers. The use of such a paste has the advantage that the effective contact area to silicon is minimized, thus reducing the effective minority carrier recombination.

It may be advantageous to provide only point contacts to the n-doped layers and interconnecting the point contacts in a separate step. This allows for instance applying comparatively thin and small dots of Ag paste by technologies such as inkjet or

Aerosoljet printing. The interconnection of the point contact regions may be done with a different metallization layer such as a metal paste of different composition (not necessarily firing through dielectrics) allowing for subsequent plating processes. It may also be a metal layer that is evaporated or sputtered to the wafer rear side. Such a metal layer may serve several purposes in an advantageous way. It may serve as a barrier layer for subsequent Cu plating, preventing Cu atoms from having a chance to enter the silicon substrate during processing of the photovoltaic cell or during its operation in a solar module. The metal layer may also serve as a back side reflector that improves the internal reflectance of light at the rear of those cell areas that are covered by dielectric passivation layers. The metal layer may also serve as a layer that enables module interconnection (for instance by adding a solderable surface finish). Finally the metal layer may help to reduce series-resistance losses and/or contact-resistance losses.

If a metal layer is applied to the complete rear side of the substrate, there is a need to separate the contacts to n-type regions and those to p-type regions. This can be achieved by masking, by selective removal of the metal layers (mechanical removal, laser ablation, selective etching, selective lift-off, ....) or by any other suitable method known to a person skilled in the art.

Depending on the pattern that has been selected for the alloyed regions 34 forming an electrical contact to the emitter regions 32 at the front side, there may be a need to provide additional emitter contacts 40 (fingers in adequate spacing and arrangement) at the front side of the photovoltaic cell. Those metal fingers 40 may be applied as well by Ag paste and fired through the respective front side dielectrics (preferably in a co-firing step with rear contact formation by Ag paste). Alternatively, laser chemical processing followed by plating contacts to the areas that get selectively opened and doped at the same time is an adequate solution to form front contacts. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practised in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the invention with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the spirit of the invention.

Claims

1. A method for fabricating back-contacted photovoltaic cells using a crystalline

semiconductor substrate (31) of a first conductivity type, the substrate (31) having a substrate thickness and comprising at the front side an emitter region (32) of a second conductivity type opposite to the first conductivity type, the method including the formation of conductive regions (34) extending through the

substrate (31) from the rear side of the substrate to the emitter region (32), wherein forming the conductive regions (34) comprises:

providing at the rear side of the substrate (31) a dielectric layer (33) comprising a pattern of openings (30) at predetermined locations where the conductive regions (34) are to be formed;

providing at the rear side of the substrate (31) a layer (40) comprising a predetermined amount of a dopant metal of the second type, at least at the predetermined locations;

heating the substrate (31) to a peak temperature substantially higher than the eutectic temperature of the semiconductor-material/dopant-metal alloy, leading to the formation of a melt comprising the dopant metal and the semiconductor material; and

cooling down the substrate (31) to ambient temperature, thereby forming eutectic regions (34) corresponding to the conductive regions and extending from the rear side of the substrate (31) at least to the emitter region (32), while epitaxially growing at the interface between the semiconductor substrate (31) and the eutectic regions (34) a heavily doped region (35) of the second conductivity type.

2. A method according to claim 1, wherein the semiconductor substrate (31) is a silicon substrate.

3. A method according to claim 2, wherein the semiconductor substrate (31) is an n- type silicon substrate and wherein the dopant metal is Al.

4. A method according to any of the preceding claims, wherein providing the patterned dielectric layer (33) comprises providing a dielectric layer at the rear side of the substrate and forming a pattern of openings through the dielectric layer by locally removing the dielectric layer at the predetermined locations where the conductive regions (34) are to be formed.

5. A method according to any of the preceding claims, wherein individual

openings (30) through the dielectric layer (33) have a circular shape, an oval shape, a square shape, a rectangular shape or a combination of different shapes.

6. A method according to any of the preceding claims, wherein the semiconductor substrate (31) is a (100) monocrystalline substrate and wherein the pattern of openings (30) through the dielectric layer (33) comprises openings having an elongate or rectangular shape, the longitudinal direction of the elongate or rectangular shapes being oriented along an <110> direction.

7. A method according to any of the preceding claims, wherein the pattern of

openings (30) comprises openings with a lateral size in the range between 10 micrometer and 100 micrometer.

8. A method according any of the preceding claims, wherein the predetermined amount of the dopant metal and the peak temperature are selected on the basis of the substrate thickness and the semiconductor-material/dopant-metal phase diagram, so as to allow penetration of the melt through the substrate (31) till it reaches at least the emitter region (32).

9. The method according to any of the preceding claims, wherein the peak temperature is higher than the melting temperature of the dopant metal.

10. A method according to any of the preceding claims, wherein the peak temperature is in the range between about 750°C and 1000°C.

11. A method according to any preceding claim and including the further step of

removing part or all of the eutectic regions (34), and possibly part or all of the epitaxial heavily doped regions (35), so as to form recesses or grooves in the substrate.

12. A method according to claim 11 and involving complete removal of the eutectic regions (34), whereupon the resulting surface is passivated and emitter contacts (43) are applied in the recesses or grooves.

13. A back-contacted photovoltaic cell comprising a semiconductor substrate (31) of a first conductivity type, an emitter region (32) of a second conductivity type opposite to the first conductivity type at the front side of the substrate and a plurality of electrical connections (34) extending through the substrate (31) from the rear side of the substrate at least to the emitter region (32),

wherein the electrical connections (34) are composed of an alloyed region comprising the semiconductor material and a dopant metal of the second type; and

wherein the photovoltaic cell further comprises heavily doped epitaxially grown regions (35) of the second conductivity type at the interface between the semiconductor substrate (31) and the alloyed regions (34).

14. The photovoltaic cell according to claim 11 wherein the semiconductor

substrate (31) is an n-type silicon substrate and wherein the dopant metal is Al.

15. The photovoltaic cell according to any of claims 11 to 12, wherein the plurality of electrical connections (34) has a triangular cross-section in a plane substantially orthogonal to the surface plane of the substrate.

16. The photovoltaic cell according to any of claims 11 to 13, further comprising narrow metal lines 40 at the front side, the narrow metal lines 40 being in electrical contact with the plurality of electrical connections (34).

17. The photovoltaic cell according to any of claims 11 to 14, further comprising at the rear side first metal contacts (41) in electrical contact with the electrical

connections (34) and second metal contacts (39) in electrical contact with the substrate (31).