WO2012155150A1 - System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects - Google Patents
System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects Download PDFInfo
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- WO2012155150A1 WO2012155150A1 PCT/US2012/037855 US2012037855W WO2012155150A1 WO 2012155150 A1 WO2012155150 A1 WO 2012155150A1 US 2012037855 W US2012037855 W US 2012037855W WO 2012155150 A1 WO2012155150 A1 WO 2012155150A1
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- H01L31/0296—Inorganic materials including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/555—Constructional details for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
Definitions
- the disclosure relates generally to electromagnetic sensing and sensors and also relates to low energy electromagnetic input conditions as well as low energy
- the disclosure relates more particularly, but not necessarily entirely, to optimizing the pixel array area and using a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates and associated systems, methods and features, which may also include maximizing pixel array size/die size (area optimization).
- imaging/camera technology The use of imaging/camera technoloy is not limited to the consumer electronics industry. Various other fields of use also utilize imaging/camera technology, including various industrial applications, medical applications, home and business security/surveillance applications, and many more. In fact, imaging/camera technology is utilized in nearly all industries.
- the device, system and methods of the disclosure may be utilized in any imaging application where size and form factor are considerations.
- imaging sensors such as a charged-couple device (CCD), or a complementary metal-oxide semiconductor (CMOS), or any other image sensor currently known or that may become known in the future.
- CCD charged-couple device
- CMOS complementary metal-oxide semiconductor
- CMOS image sensors typically mount the entire pixel array and related circuitry, such as analog-digital converters and/or amplifiers, on a single chip. Because of the physical constraints of the chip size itself and the physical space occupied by related circuitry involved in a conventional CMOS image sensor, the area that the pixel array may occupy on the chip is often limited. Thus, even if the pixel array were maximized on a substrate that also contains the related circuitry, the pixel array is physically limited in area due to the amount of physical area and space that the related circuitry for signal processing and other functions occupies on the chip.
- the application or field of use in which the CMOS image sensor may be used often requires the CMOS image sensor to be limited to a certain size also limiting the physical area in which the pixel array may occupy.
- the size limitations of a CMOS image sensor often require trade-offs between image quality and other important functions, such as signal processing, due to the number of considerations that must be accounted for in the design and manufacture of a CMOS image sensor.
- increasing the pixel array area may come with a trade-off in other areas, such as A/D conversion or other signal processing functions, because of the decreased area in which the related circuitry may occupy.
- the disclosure optimizes and maximizes the pixel array without sacrificing quality of the signal processing by optimizing and maximizing the pixel array on a first substrate and stacking related circuitry on subsequent substrates.
- the disclosure utilizes advancements in back-side illumination and other areas to take advantage of optimizing the area of the pixel array on a substrate.
- the stacking scheme and structure allow highly functional, large-scale circuits to be utilized while maintaining a small chip size.
- FIG. 1 illustrates an embodiment of an imaging sensor built on a plurality of substrates and also illustrating an embodiment of the specific placement of support circuits in accordance with the teachings and principles of the disclosure;
- FIG. 2 illustrates an embodiment of a pixel array wherein interconnects are spaced relative to pixels within the pixel array in accordance with the teachings and principles of the disclosure
- FIG. 3 illustrates an embodiment of a pixel array wherein interconnects are spaced relative to columns within the pixel array in accordance with the teachings and principles of the disclosure
- FIG. 4 illustrates an embodiment of a pixel array wherein a interconnects are spaced relative to areas within the pixel array in accordance with the teachings and principles of the disclosure
- FIG. 5 illustrates a perspective view of an embodiment of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate and showing an electrical connection and communication between one column of pixels to its associated or corresponding column of circuitry via interconnects, wherein interconnects may be spaced relative to defined pixel areas within the pixel array in accordance with the teachings and principles of the disclosure;
- FIGS. 6 - 10 illustrate top views of various embodiments of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate and showing an electrical connection and communication between one column of pixels to its associated or corresponding column of circuitry via interconnects, wherein interconnects may be spaced relative to defined pixel areas within the pixel array in accordance with the teachings and principles of the disclosure;
- FIG. 1 1 i llustrates a top view of an embodiment of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns and sub-columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate and showing an electrical connection and communication between one column of pixels to its associated or corresponding column of circuitry;
- FIG. 12 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that together form a pixel array located on a first substrate and a plurality of circuit columns located on a second substrate and showing an electrical connection and communication between one sub-column of pixels to its associated or corresponding column of circuitry in accordance with the teachings and principles of the disclosure;
- FIGS. 12a - 12c illustrate perspective, front and side views, respectively, of a single column of pixels that have been formed into two separate sub-columns of pixels, wherein each pixel sub-column is attached to a different pixel column read bus, and illustrating two columns of circuitry taken from FIG. 12 showing an electrical connection therebetween;
- FIG. 13 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that together form a pixel array located on a first substrate and a plurality of circuit columns dedicated to one or more pixel sub-columns located on a second substrate and showing an electrical connection and communication between one column of pixels to its associated or corresponding column of circuitry in accordance with the teachings and principles of the disclosure;
- FIG. J 3a illustrates a perspective view of a single column of pixels that have been formed into two separate sub-columns of pixels, wherein both pixel sub-columns are attached to a different pixel column read bus, and illustrating an electrical connection between the read buses to a column of circuitry taken from FIG. 13;
- FIG. 14 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that together form a pixel array located on a first substrate and a plurality of circuit columns located on a second substrate and showing an electrical connection and communication between each sub-column of pixels to its associated or corresponding column of circuitry in accordance with the teachings and principles of the disclosure;
- FIGS. 14a - 14c illustrate perspective, front and side views, respectively, of a single column of pixels that have been formed into two separate sub-columns of pixels, wherein each pixel sub-column is attached to a different pixel column read bus, and illustrating two columns of circuitry taken from FIG. 14 showing an electrical connection therebetween;
- FIGS. 15 - 1 8 illustrate top views of various embodiments of a plurality of columns and sub-columns that together form a pixel array located on a first substrate and a plurality of circuit columns located on a second substrate and showing an electrical connection and communication between each sub-column of pixels to its associated or corresponding column of circuitry in accordance with the teachings and principles of the disclosure.
- proximal shall refer broadly to the concept of a portion nearest an origin.
- distal shall generally refer to the opposite of proximal, and thus to the concept of a portion farther from an origin, or a furthest portion, depending upon the context.
- an imaging sensor may include a pixel array and supporting circuits that are disposed on at least one substrate.
- Devices usually have practical and optimal constraints on the form factor of the imaging sensor depending upon the application. Often it is not the pixel array that is the only consideration for fitment, but it is the supporting circuitry that needs to be accommodated.
- the supporting circuits may be, but are not necessarily limited to, analog to digital converters, power circuits, power harvesters, amplifier circuits, dedicated signal processors and filters, serializers for transmission preparation, etc.
- physical property elements may be required, such as light filters and lenses.
- Each of the pixels must be read from the pixel array and have the data processed by the supporting circuits. With the increase in the number of pixels in an array, more data must be handled. In regard to movie data the sensor must dump its data and be ready to operate again in short order.
- On-chip systems allow for reduced pad count; and Faster operation can be achieved (more serial on-chip operation, reduced stray capacitances and resistances). With larger and larger arrays, the need to read and processes the data created therein is paramount.
- the disclosure also contemplates an image sensor that might otherwise be manufactured with its pixel array and supporting circuitry on a single, monolithic substrate/chip and separating the pixel array from all or a majority of the supporting circuitry.
- the disclosure may use at least two substrates/chips, which will be stacked together using three-dimensional stacking technology. The first of the two
- substrates/chips may be processed using an image CMOS process.
- the first substrate/chip may be comprised either of a pixel array exclusively or a pixel array surrounded by limited circuitry.
- the second or subsequent substrate/chip may be processed using any process, and does not have to be from an image CMOS process.
- the second substrate/chip may be, but is not limited to, a highly dense digital process in order to integrate a variety and number of functions in a very limited space or area on the substrate/chip, or a mixed-mode or analog process in order to integrate for example precise analog functions, or a RF process in order to implement wireless capability, or MEMS (Micro-Electro-Mechanical Systems) in order to integrate MEMS devices.
- MEMS Micro-Electro-Mechanical Systems
- the image CMOS substrate/chip may be stacked with the second or subsequent substrate/chip using any three-dimensional technique.
- the second substrate/chip may support most, or a majority, of the circuitry that would have otherwise been implemented in the first image CMOS chip (if implemented on a monolithic substrate/chip) as peripheral circuits and therefore have increased the overall system area while keeping the pixel array size constant and optimized to the fullest extent possible.
- the electrical connection between the two substrates/chips may be done through interconnects, which may be wirebonds, ⁇ and/or TSV (Through Silicon Via).
- a pixel array 450 may be disposed on a first substrate 452.
- the first substrate 452 may be made of silicon or of another material in order to control light transmission characteristics. Solder balls, bumps or vias 421 may be used to electrically connect one substrate to another.
- An embodiment of a stacked image sensor may comprise a pixel array 450 on a first substrate 452.
- the pixel array 450 may cover at least forty percent of a first surface 45 1 of the first substrate 452.
- a pixel array may be disposed on the backside of said first substrate.
- the substrate 452 may be thinned for controlling light transmission therethough.
- the first substrate may be made of primarily silicon material, or the first substrate may be made of primarily of "High-Z" semiconductor material (Cadmium Telluride e.g.), or the first substrate may be made primarily of 111- V semiconductor materials (Gallium Arsenide e.g.).
- a pixel array 450 may cover a majority of the first surface 45 1 of a first substrate 452. In such an embodiment the pixel array 450 may be situated or located on any portion of said first surface 45 1 . The remaining space on the first surface 45 1 may be used for secondary circuit placement if desired. Situations may arise where a secondary circuit may be sized such that central placement of the pixel array is not practical.
- FIG. 2 illustrates a situation where the pixels 1726 have been formed in a plurality of columns, such as 1728. Using a pixel column (1728) format in a pixel array, a very high frame rate can be achieved by using a rolling type shutter.
- a rolling type shutter reads an entire row of pixels substantially simultaneously at one time and then reads or moves from the top of the pixel columns to the bottom of the pixel columns.
- the first row of pixels may be read followed by the next, adjacent row of pixels as data is read from the plurality of pixel columns, and the reading starts at the top of the pixel columns and then rolls down the columns, pixel by pixel at a time, and moves in a predetermined and calculated pattern over the entirety of the pixel array.
- a rol ling shutter only one read bus 1730 need be present per pixel column 1728, and one read bus 1740 per circuit column.
- FIG.2 illustrates a bumping configuration or scheme using one bump 1724 per pixel 1 726, which approximates a global shutter operation.
- the bump pitch equals or substantially equals the pixel pitch in both the X and Y axes or directions.
- FIG. 3 illustrates a bumping configuration or scheme using one
- FIG. 3 i llustrates a plurality of columns 1728, where each column 1728 is comprised of a plural ity of pixels 1 726. Each column of pixels may run in the Y direction (y-axis) for a distance and may be one pixel in width as illustrated. Each column of pixels may be read through a single connection point at one end of each column 1 728.
- FIG. 4 illustrates a bumping configuration that is even further relaxed than that shown in FIGS. 2 or 3.
- the bump pitch is relaxed (e.g., the distance between bumps has increased in comparison to FIGS. 2 and 3) and half of the interconnects/bumps 1 724 can be used to process data at each side of the pixel array 17 10.
- This can be accomplished by adding or introducing a second set of interconnects 1724 that alternate with respect column read buses and at opposing ends of the column read buses (e.g., an interconnect 1724 is used to connect read buses 1 730, 1740 and may be located at every other column read bus on one side of the pixel array 7 10 and the opposite may be done on the other side of the pixel army 7 1 0).
- an interconnect 1724 is used to connect read buses 1 730, 1740 and may be located at every other column read bus on one side of the pixel array 7 10 and the opposite may be done on the other side of the pixel army 7 1 0).
- the second set of interconnects 1 724b may be used in combination with the first set of interconnects 1 724a and may be employed to allow half of the data to be processed or read at each side of the pixel array 1710.
- Such a configuration may allow for nearly double the size of bump pitch (interconnect pitch) as compared to the pixel pitch in at least one dimension, which would greatly decrease the cost of producing image sensors 1700.
- more than one interconnect or bump 1724 per pixel column 1728 may be utilized per read bus, such that data may be read from either end of the pixel column 1728.
- FIGS. 5 - 10 illustrate embodiments and configurations of a pixel array 1810 having staggered interconnect or bump 1824 positioning on a substrate/chip.
- the interconnect/bump 1 824 may be placed anywhere along the superimposed path of the buses within the column.
- the bump distance may be increased from column to column by shifting the next column bump 1824 either up or down (in the Y direction) in the next column.
- pixel pitch may be about 5 ⁇ and pixel column may be any length, for example between about 2mm and about 15mm long.
- bump pitch is a function of pixel pitch, such that the pixel pitch will be determinative of an ideal bump pitch. For example, assuming there is a desired bump pitch of approximately 1 ⁇ , placing a first interconnect or bump 1824 may then be accomplished by starting at the top of the first column and shifting down the next column interconnect or bump by 1 ⁇ . All other bumps are similarly positioned until the interconnect or bump in the 20th column of the line will be located at the bottom of the pixel column.
- the interconnect or bump 1 824 in the 21 st column may again be placed at the top of the pixel column 1828. This same pattern may then be repeated until the end of the pixel array 1 810.
- a first column 1828 of pixels 1826 may be electrically accessed via a first interconnect 1824a.
- a second pixel column 1 832 may be electrically accessed through a second interconnect 1824b, which has been positioned during manufacture in a staggered configuration relative to said first interconnect 1824a.
- the location or position of the second interconnect 1824b may be at least two pixel widths away from the position of the first interconnect 1824b (and from any other interconnect 1 824) in both the X and Y dimensions or directions.
- a third interconnect 1824c may then be positioned in like manner in a third pixel column and so on for N-number of interconnects 1824 across the pixel array 1 810.
- Such a configuration provides for an interconnect pitch that is at least three times that of the pixel pitch. It will be appreciated that the gain in interconnect pitch may be much greater than three times that of the pixel pitch under standard conditions. However, it will be appreciated that the gain in interconnect pitch may be at least three times the pixel pitch as noted above.
- interconnect gains may be made with area based spacing rather than column-by-column based connectivity (see figures illustrating a pixel column aspect ratio of 6/ 1 and circuit column aspect ratio of 6/1 and 3/2, or a pixel column aspect ratio of 8/1 and circuit column aspect ratio of 2/4). This can be accomplished with the addition of more bus structures or use of direct reading to a subsequent substrate. In either configuration, the interconnect pitch may be described thusly:
- wwhheerree NN iiss tthhee nnuummbbeerr ooff ppiixxeellss bbeettwweeeenn ttwwoo aaddjjaacceenntt iinntteerrccoonnnneeccttss iinn tthhee XX--ddiirreeccttiioonn aanndd MM iiss tthhee nuummbbeerr ooff ppiixxeellss bbeettwweeeenn ttwwoo aaddjjaacceenntt iinntteerrccoonnnneeccttss iinn tthhee YY--ddiirreeccttiioonn..
- IInn FFIIGG.. 66 tthhee aarreeaa aavvaaiillaabbllee ffoorr ssuuppppoortrt cciirrccuuiitt placement may be equal to one pixel unit wide by sixty-four pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect 1 824 between the substrates in FIG. 6 must fall somewhere within the sixty-four pixel unit area in order to read that column, since the pixel column read bus and the column circuit read bus are superimposed along the path of the sixty-four pixels, such that the interconnect 1824 may be placed anywhere along those sixty-four pixels to connect the read buses.
- the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, the interconnect range in order to read the corresponding pixel column is 1 pixel wide and 64 pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
- the exemplary aspect ratio of the support circuit area in FIG. 6 is illustrated as 1/64.
- the interconnect 1824 may then be chosen by the designer so as to allow the desired spacing from interconnect to interconnect. For example, as illustrated best in FIGS. 6 - 1 0, it will be appreciated that in an embodiment in which the
- interconnects or bumps 1 824 are in a staggered configuration, there may be one interconnect or bump 1 824 per group of pixels 1826.
- each interconnect 1 824 may be utilized depending on the desired application. As discussed above, larger dedicated support circuits may be employed to process the data read through each interconnect 1 824. The staggering of the position of each interconnect/bump 1 824 may also provide even greater space for support circuits relative to each area or group of pixels within the pixel array 1810.
- the area available for support circuit placement may be equal to two pixel units wide by thirty-two pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect 1 824 between the substrates 1 852 and 1 854 must fall somewhere in the sixty-four pixel unit area in order to read that column. It should be noted that the aspect ratio of the support circuit area in this example is 2/32. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.
- the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and thirty-two pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
- the area available for support circuit placement may be equal to four pixel units wide by sixteen pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 4/1 6. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.
- the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and sixteen pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
- the area available for support circuit placement may be equal to eight pixel units wide by eight pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect 1824 between the substrates 1 852 and 1854 must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 8/8.
- Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.
- the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and eight pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
- the area available for support circuit placement may be equal to sixteen pixel units wide by four pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 1 6/4, this example shows the flexibility that these methods and apparatuses disclosed herein can provide.
- Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column.
- the choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.
- the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and four pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
- the pattern of the association of the support circuit to the pixel column may be different than that of FIGS. 6 - 10 and such association may ultimately provide the optimal distance of the interconnects away from each other.
- the interconnects may be optimally placed at least two pixel widths apart, four pixel widths apart, eight pixel widths apart, or more from each other.
- a designer may optimally determine the distance that the interconnects may be placed apart from one another based on two degrees of freedom: ( 1 ) the number of pixels per column, and (2) the circuit aspect ratio and location.
- the interconnects 1824 may be located about eight pixels away from each other.
- other designs may be implemented without departing from the spirit or scope of the disclosure.
- each of the interconnects 1824 may be located eight pixels in length and one pixel in width away from each other. Because the circuit columns each have an aspect ratio of one pixel in width and sixty-four pixels in length, the interconnects 1824 may then be located eight pixels away from each other in adjacent columns as illustrated in FIG. 6, until the bottom of the circuit 1 800 is reached, in which case the interconnects ! 824 are then moved to the top of the next column and continue for the entire width of the pixel array 1 810. Conversely, in FIG. 10, the interconnects 1 824 are still located eight pixels in length and one pixel in width away from each other. However, in this example, the circuit column aspect ratio is now four pixels in length and sixteen pixels in width.
- the interconnects 1824 to be at least eight pixels away from each other, one circuit column 1 856b must be skipped since the aspect ratio is only four pixels in length, such that the interconnects 1 824 maintain optimal spacing.
- placing an interconnect 1824 in the upper left corner of the pixel array 18 10 in FIG. 10 (on the first pixel of the first column 1828) and then moving to the next pixel column 1832 and counting down eight pixels in length, the next interconnect 1824 may then be placed in the third circuit column 1856c, skipping the second circuit column 1856b altogether. This pattern may be used throughout the pixel array.
- the second, skipped circuit column 1856b is then connected to the pixel array by an interconnect 1824a that is placed in the ninth pixel column and the pattern is repeated for all skipped circuit columns.
- interconnect 1824a that is placed in the ninth pixel column and the pattern is repeated for all skipped circuit columns.
- a pixel array 1810 having columns and sub-columns will be discussed. As can be seen in FIG. 1 1 , a portion of a pixel array 1 810 is illustrated having six columns therein, each column running from the top of the portion of the pixel array illustrated to the bottom of the pixel array. It will be appreciated that the modern circuit 1800 will have a pixel array 1810 that comprises many more pixel columns (a plurality of pixels running in the Y-direction in the figure) and rows (a plurality of pixels running in the X-direction in the figure) forming the array 1 810. Only a limited number of pixel columns and rows are shown herein for illustration purposes and for the sake of discussion and simplicity.
- Each of the pixel columns 1 828 in the pixel array 18 10 may be divided into sub- columns.
- the sub-columns may be defined as a plurality of pixels within a column that is less than the entire column of pixels and that are electrically connected to a pixel sub- column bus. Thus, there may be a plurality of pixel sub-columns per pixel column 1828.
- Each of the sub-columns may have a contact pad and/or an interconnect illustrated as 5 1 , 52, 53 and 54 to electrically connect each of the sub-column buses on the first substrate to an associated or corresponding circuit column bus located on the supporting substrate.
- At least one pixel column bus may be used to provide an electrical connection for every pixel in the column 1828.
- the column 1828 may be divided into a plurality of sub- columns, where at least one pixel sub-column bus is present per pixel sub-column.
- the sub-column buses may be differentiated by dividers 62, 63, 64, which dividers may be a physical space or gap or other device for electrically isolating the pixel sub-column and/or sub-column bus from another sub-column and/or sub-column bus.
- the data from the pixels may be read in a rolling type shutter manner, which is substantially simultaneous from each row of pixels in each of the sub-columns (illustrated as four sub- columns in FIG. 1 1 ).
- the read time may be substantially reduced due to the number of sub-columns that are connected to dedicated circuit columns via the pixel sub-column read bus and the circuit column read bus and the interconnects that electrically connect the buses together.
- the read time in the embodiment illustrated may be theoretically reduced (i.e., reading speed is increased) for the entire column (which in FIG. 1 1 includes four sub-columns) by the number of sub-column buses.
- FIG. 1 1 includes four sub-columns
- the rolling shutter may operate row by row at the beginning of each sub-column incrementally reading each pixel in the sub- column to the end of the sub-column simultaneously with the other sub-columns
- the column may be divided into any number of sub- columns, with each division of the column (e.g., addition of a sub-column) approximating a global shutter functionality.
- the contact pads and interconnect locations can be staggered in each of the columns.
- Other iterations of sub-columns and interconnect staggering are possible for N number of columns.
- FIGS. 12 through 14c there is illustrated various views of an embodiment of an imaging sensor 1200 built on a plurality of substrates having sub- column read functionality and remotely located support circuits.
- FIGS. 12 and 14 illustrate a plurality of pixel columns 1252 and 1452 forming the pixel array 1250 and 1450 on the first substrate 1210, 1410 and a plurality of circuit columns 1256, 1456 (that represent the supporting circuitry 1270, 1470) on the second substrate 121 1 , 14 1 1 .
- a pixel array 1250 may be divided into a plurality of columns and sub-columns 1252.
- the size of the columns and sub-columns may , for example, be based on the size of the associated circuitry 1270 and circuit columns 1256.
- the pixel sub-column 1252 may be one pixel in width and "N" number of pixels long (in FIGS. 12 - 12c, the pixel sub-columns are illustrated as being one pixel wide and six pixels long) and the circuit columns 1256 are illustrated as having an aspect ratio of one pixel wide by six pixels long.
- the size or area of the circuit column 1256 may dictate or direct the size of the pixel sub-column 1252, since the pixel sub-column 1252 should have substantially the same area as the circuit column 1256.
- the pixel sub-column 1 252 may be directly associated with circuit column 1256 through an electrical connection between an interconnect 1224 that electrically connects the pixel read bus 1230 to the circuit read bus 1240.
- the figures show an example of a connection between each pixel sub-column 1252 to its associated circuitry 1270 in a circuit column 1256 through read buses 1230 and 1240.
- the figures also show one read bus 1230 per pixel sub-column 1252 and one read bus 1240 per circuit column 1256.
- the associated circuitry 1270 in a circuit column 1256 is one pixel wide and six pixels long, but it will be appreciated that any circuit column aspect ratio may be utilized by the disclosure.
- FIGS. 12- 12c the columns have all been divided into two sub-columns 1287, 1288.
- pixel column read bus 1230 may be manufactured into corresponding pixel sub-column read buses 1230a and 1230b.
- Each pixel sub-column 1287, 1288 may be connected to a pixel column bus 1230a or 1230b first and then to supporting circuitry 1270 and circuit column 1256, or each sub-column 1287, 1288 may connect directly to the circuitry 1270 and circuit column 1256 through their own interconnect 1224a and 1224b, respectively, to an associated circuit bus 1240a and 1240b.
- each pixel sub-column 1252 may be electrically associated or connected to one pixel sub-column bus 1230, and each circuit column 1256 may be electrically associated or connected to one circuit column bus 1240.
- FIGS. 1 2a- 1 2c illustrate a perspective view, a front view and a side view, respectively, of a single pixel column 1252 divided into sub-columns 1287, 1288 and two associated circuit columns 1256 separated from the plurality of pixel columns 1252 and plurality of circuit columns 1256 illustrated in FIG. 12.
- Two supporting circuits (one support circuit per pixel sub-column read bus.
- there is an aspect ratio of the circuit column is 6/1
- the aspect ratio of the pixel sub-column is also 6/ 1
- the aspect ratio of the whole pixel column is 12/1 .
- FIG. 1 2a- 12c also further illustrate the electrical connection between the pixel sub- column buses 1230a and 1230b of the pixel sub-columns 1287, 1288 and the circuit columns 1 256 using one or more interconnects 1224 per sub-column connection. While the pixel sub-buses 1230a and 1230b and buses 1240a and 1240b may be electrically connected using one or more interconnects 1224, the figures illustrate that the
- interconnects 1224 may be located anywhere along the superimposed path of the pixel sub-buses 1230a and 1230b and buses 1 240 without departing from the spirit or scope of the disclosure.
- FIGS. 13 and 13a illustrate an alternative embodiment in which the pixel column has been divided into a plurality of sub-columns, each having their own bus. However, the sub-columns are illustrated as being connected by their individual buses to a single circuit column.
- FIGS. 14 - 14c illustrate a pixel array 1450 being divided into a plurality of columns and sub-columns 1452.
- the size of the columns and sub-columns may, for example, be based on the size of the associated circuitry 1470 and circuit columns 1456.
- the pixel sub-column 1452 may be one pixel in width and "N" number of pixels long (in FIGS. 14 - 14c, the pixel sub-columns are illustrated as being one pixel wide and six pixels long, whereas the entire column is illustrated as being one pixel wide and twelve pixels long) and the circuit columns 1456 are illustrated as having an aspect ratio of two pixels wide by three pixels long.
- the size or area of the circuit column 1456 may dictate or direct the size of the pixel sub- column 1452, since the pixel sub-column 1452 should have substantially the same area as the circuit column 1456.
- the pixel sub-column 1452 may be directly associated with circuit column 1456 through an electrical connection between an interconnect 1424 that electrically connects the pixel read bus 1430 to the circuit read bus 1440.
- the figures show an example of a connection between each pixel sub-column 1452 to its associated circuitry 1470 in a circuit column 1456 through read buses 1430 and 1440.
- the figures also show one read bus 1430 per pixel sub-column 1452 and one read bus 1440 per circuit column 1456.
- the associated circuitry 1470 in a circuit column 1456 is two pixels wide and three pixels long, but it will be appreciated that any circuit column aspect ratio may be utilized by the disclosure.
- the columns As can be seen in FIGS. 14- 14c, the columns have all been divided into two sub-columns 1487, 1488.
- pixel column read bus 1430 may be manufactured into corresponding pixel sub-column read buses 1430a and 1430b.
- Each pixel sub-column 1487, 1488 may be connected to a pixel column bus 1430a or 1430b first and then to supporting circuitry 1470 and circuit column 1456, or each sub-column 1487, 1488 may connect directly to the circuitry 1470 and circuit column 1456 through their own interconnect 1424a and 1424b, respectively, to an associated circuit bus 1440a and 1440b.
- each pixel sub-column 1452 may be electrically associated or connected to one pixel sub-column bus 1430
- each circuit column 1456 may be electrically associated or connected to one circuit column bus 1440.
- FIGS. 14a- 14c illustrate a perspective view, a front view and a side view, respectively, of a single pixel column 1452 divided into sub-columns 1487, 1488 and two associated circuit columns 1456 separated from the plurality of pixel columns 1452 and plurality of circuit columns 1456 illustrated in FIG. 14.
- FIGS. 14a- 14c there are two read buses present for the entire pixel column.
- the presence of the two read buses 1430a, 1430b are illustrated as being separate and distinct buses that are not electrically connected to each other, such that there is a separation or divider (as discussed above in relation to FIG. 1 1 ) that separates the column into two sub-columns.
- there may also be two supporting circuits and circuit column read buses (one support circuit and circuit column bus per pixel sub-column read bus).
- FIG. 14a- 14c further illustrate the electrical connection between the pixel sub- column buses 1430a and 1430b of the pixel sub-columns 1487, 1488 and the circuit columns 1456 using one or more interconnects 1424 per sub-column connection. While the pixel sub-buses 1430a and 1430b and circuit column buses 1440a and 1440b may be electrically connected using one or more interconnects 1424, the Figures illustrate that the interconnects 1424 may be located anywhere along the superimposed path of the pixel sub-buses 1430a and 1430b and circuit column buses 1440 without departing from the spirit or scope of the disclosure.
- FIGS. 14 - 14c also illustrate how differing aspect ratios between the substrates can allow for flexibility in bus contact points.
- the column circuit bus 1440 has been designed with a general "u" shape that so as to occupy the area of the circuit column 1456 more evenly, thereby providing options for connecting the interconnect 1424 throughout the entire circuit column 1456.
- the pixel column bus 1430 is not generally u-shaped, but the circuit column bus 1440 may be generally u-shaped, so that the same column circuit 1456 may be used with the two adjacent, but different pixel column configurations.
- the first leg of the u-shaped circuit column buses 1440a and 1440b may be superimposed to the read buses 1430a and 1430b of the pixel sub-columns 1487 and 1488 (as illustrated in FIG. 14a).
- the second leg of the u-shaped circuit column bus 1442that is located between circuit column buses 1440a and 1440b may be superimposed to the read bus 1430 of the next, adjacent pixel column 1452 (as illustrated best in FIG. 14).
- FIGS. I 4a- 14c illustratea single set of pixel sub-columns 1487 and 1488 taken from the pixel array 1450 of FIG. 14.
- circuit column 1456 is illustrated as being two pixels wide by three pixels long, which is one half the length of the corresponding pixel sub-columns 1487 and 1488, the interconnect 1424 location options are only available for a portion of the pixel sub-column length.
- FIG. 14b illustrates that for a complex bus shape there may be two interconnect location path options along buses 1440a and 1440b in a circuit column 1456 having twice the width of the pixel sub-column 1487 and 1488 it supports.
- FIG. 14b illustrates a front view of the superimposition of the first leg of the u-shaped circuit column bus 1440b to the read bus 1430b of the pixel sub-column 1488 and uses the outer most portion ofthe bus 1440b for locating the interconnect 1424 as opposed to the innermost portion of the bus 1440b as illustrated in FIGS. 14 and 14a for locating the interconnect 1424 to the next, adjacent pixel column 1452.
- FIG. 14 illustrates the next pixel sub-column 1452 located to the left of and relative to the pixel sub-columns 1487 and 1488 illustrated in FIGS. 14a- 14c.
- the bus 1430 of the next pixel sub-column 1452 illustrated in FIG. 14 may be electrically connected to a different circuit bus 1442that may be located between circuit bus 1440a and 1440b as illustrated.
- the superimposition of the pixel sub-column bus 1430 to the circuit column bus 1442 requires the second leg of the circuit column bus 1442 to be generally u-shaped to thereby allow a natural match or superimposition of the bus 1442 with respect to the next pixel sub-column 1452 and its corresponding bus (with respect to the sub-column 1487) illustrated in FIG. 14.
- FIG. 15 illustrates an embodiment and configuration of a pixel array 1 810 having staggered interconnect or bump 1 24 positioning and sub-columns on a substrate/chip.
- the interconnect/bump 1824 may be placed anywhere along the superimposed path of the sub-column bus and the circuit column bus.
- a divider 1866 which may be a physical space or gap or some other device for electrically isolating the pixel sub-column and/or sub-column bus from another sub- column and/or sub-column bus, divides the pixel column bus into pixel sub-column buses.
- a first sub-column 1 828a of pixels 1 826 may be electrically connected to its corresponding circuit column 1 856 via a first interconnect 1824a that is connected to the buses 1830 and 1 840, and a second sub-column 1828b by a second interconnect 1 824b in a similar manner.
- the second pixel column may be electrically accessed through a second set of sub column interconnects, which has been positioned during manufacture in a sub-column configuration relative to said first column interconnects.
- the location or position of the second interconnect may be two pixel widths away from the position of the first interconnect in both the X and Y dimensions or directions.
- a third set of interconnects may then be positioned in like manner in a third pixel column and so on for N-number of interconnect sets across the pixel array 181 0.
- FIG. 16 illustrates a pixel array that is configured into such that each column is divided into two sub-columns and then staggered.
- the area available for locating support circuits for a first pixel column ] 88 1 correlates to the pixel sub-column configuration as described above.
- the support circuit area directly correlates to the area of a pixel column to which it corresponds.
- the area available for support circuit placement may be equal to one pixel unit wide by sixty-four pixel units long, which is shown as the heavier vertical lines in the figure.
- each circuit column may correlate to one of the sub-columns or, in the alternative, the circuit column may also be in a manner that corresponds to the pixel column.
- the exemplary aspect ratio of the support circuit area in FIG. 16 is illustrated as 1/64. There are many options to locate or place the interconnects for the sub-columns within that area and the ultimate location may then be chosen by the designer so as to allow the desired spacing from interconnect to interconnect.
- FIG. 17 illustrates a schematically large image sensor showing the scalability of the principles and teaching of the disclosure.
- the area available for support circuit placement may be equal to four pixel units wide by sixteen pixel units long, which is shown as the heavier vertical lines in the figure.
- the aspect ratio of the support circuit area in this example is 4/1 6, the sub column aspect ratio is 1 /64 and the pixel column is 1 /128. Therefore there are pixel sub- columns per pixel column.
- the frame read time one rolling cycle
- the whole pixel array can be regarded as two independent, self consistent sub-arrays.
- Such in embodiment lends itself to support circuitry that directly corresponds to the pixel sub-columns.
- the choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. As the figure illustrates, by repeating the methods of this disclosure even the latest imaging sensor technology can be used with these methods.
- FIG. 18 illustrates a schematically large image sensor showing the scalability of the principles and teaching of the disclosure.
- the plurality of interconnects 2616, 261 8 per column indicate that the pixel column has been divided into sub-columns.
- the area available for support circuit placement for the pixel sub-columns may be equal to two pixel units wide by thirty-two pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel sub-columns.
- the aspect ratio of the support circuit area is 2/32.
- the choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. As the figure illustrates, by repeating the methods of this disclosure even the latest imaging sensor technology can be used with these methods.
Abstract
Description
Claims
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JP2014510549A JP6348061B2 (en) | 2011-05-12 | 2012-05-14 | Sub-row parallel digitizer system and method for hybrid stacked image sensor using vertical interconnect |
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EP12782104.9A EP2706911B1 (en) | 2011-05-12 | 2012-05-14 | System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects |
CN201280033746.1A CN103648378B (en) | 2011-05-12 | 2012-05-14 | For using the system and method for the vertically sub-row parallel digitizers of the hybrid stack-ups imageing sensor of interconnection |
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IL229398A IL229398A0 (en) | 2011-05-12 | 2013-11-11 | System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects |
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