WO2012085724A1 - Method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling - Google Patents

Method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling Download PDF

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Publication number
WO2012085724A1
WO2012085724A1 PCT/IB2011/055519 IB2011055519W WO2012085724A1 WO 2012085724 A1 WO2012085724 A1 WO 2012085724A1 IB 2011055519 W IB2011055519 W IB 2011055519W WO 2012085724 A1 WO2012085724 A1 WO 2012085724A1
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Prior art keywords
flip chip
bumps
bump
electrical coupling
electrical
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PCT/IB2011/055519
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French (fr)
Inventor
Wojtek Sudol
Carmine Decicco
Michael SCARSELLA
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Koninklijke Philips Electronics N.V.
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Publication of WO2012085724A1 publication Critical patent/WO2012085724A1/en

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
    • A61B8/4483—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer
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Abstract

A method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling, according to the invention, provide a reciprocal bump and contact-pad arrangement in the flip chip element wherein the bumps are formed from a layer of bump material by subtractive process. Such flip chip elements are highly suitable for use in many devices but are particularly applicable to the field of ultrasound imaging where they may be included to couple and connect the acoustic transducer stack to an ASIC.

Description

Method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling
FIELD OF THE INVENTION
The invention relates to the field of interconnection methods and devices which utilize a flip chip type of electrical interconnection with a formed electrical pad connection. In particular, the invention relates to a flip chip connection for use in ultrasound transducer devices.
The invention further relates to a method of fabricating a flip chip electrical coupling between first and second electrical components, the flip chip coupling comprising a reciprocal bump-contact pad arrangement,
and further to a flip chip electrical coupling between first and second electrical components comprising a reciprocal bump-contact pad arrangement,
and further to a device comprising a flip chip electrical coupling between first and second electrical components comprising a reciprocal bump-contact pad arrangement.
BACKGROUND OF THE INVENTION
A flip chip electrical coupling, utilizing a reciprocal bump and contact pad arrangement for electrical interconnection between first and second electrical components, is known in the art.
Patent application WO 2008/001283 describes an example of a type of flip chip electrical coupling. The coupling includes a bump and a contact pad. A first electrical component is arranged associated with the bump and a second electrical component with the contact pad. By formation of the bump-contact pad coupling, the two electrical components are electrically coupled to each other. Such flip chip components are described as
manufactured by many fabrication methods. Bumps may be formed by several processes, such as plating, forming, or electro lithography. Bumps are usually formed by deposition processes, for example there is described a deposition process in which small balls of solder are laid down on the contact pads, then electrically connected by low temperature pressure bonding. Contact pads may be formed by several processes, such as deposition by sputtering, photo deposition, or electrolysis plating. Patent application WO2006/018805 discusses flip chip electrical couplings, and their design, in the context of integrated circuit technology, and of providing flip chip electrical couplings for use with ultrasound transducer devices for various clinical applications. In particular, this document details dimensioning and fabrication of the (high aspect ratio, i.e. aspect ratio greater than 1) bumps which, typically patterned as additions to one of the electrical components, are often being added to an integrated circuit substrate. The corresponding conductive adhesive dots, cementing the bump-contact pad connection, are positioned on the bottom of the acoustic element. Photolithography process is described for patterning the process used to lay down the bumps. After several layers are laid down, photo-resist between the bumps is removed to leave the bumps free. A process of underfilling the bumps is also described. Underfill material is applied to the edge of the integrated circuit and acoustic stack, filling in the gap between the acoustic stack and the underlying integrated circuit in order to add mechanical strength and provide good hermetic sealing of the joint.
Different flip chip techniques are known in the industry. Bumps are normally a contact point to an ASIC, protruding above a surface. Bumps are usually produced using an additive process, which also compromises the area available for circuitry. They are usually metallic, e.g. bumps may be made of gold (Au) or solder, with variations of low and high temperature processing. The physical join may be effected by use of (isotropically conductive or nonconductive) adhesive. In the context of the ultrasound transducer application, however, the choice of manufacturing techniques for the bump-contact pad arrangement is limited. The customary choice for the bump is gold (Au) or mixed gold- nickel (Au-Ni) bumps, mounted or processed onto the ASIC, in combination with
isotropically conductive adhesive (e.g. epoxy) to connect the bump to the contact pad located on the transducer stack. Such processing is challenging. Modern designs demand high aspect ratio (ratio of bump height to bump width) bumps and fine dicing of the wafer to release individual components. This puts stress on the flip chip connections. The fine pitch requirements have resulted in some solutions placing the bumps on the acoustic stack instead of on the ASIC - such a design is sometimes known as a "reverse" flip chip connection.
A problem with flip chip electrical couplings, common to elements manufactured by the current processing techniques, and to different types of flip chip and reverse flip chip designs, is the issue of uniformity of height across the tops of the bumps, which critically impacts the provision of adhesive to the bumps. SUMMARY OF THE INVENTION
It is an object of the invention to reduce the variability of bump height in a flip chip assembly.
According to the invention this object is achieved by a method of fabricating a flip chip electrical coupling between first and second electrical components, the flip chip coupling comprising a reciprocal bump-contact pad arrangement, comprising :
Providing a bump layer, arranged in association with one of the electrical components, a material of the bump layer being suitable to fulfill the electrical and mechanical requirements of the bumps
Fabricating the bumps in the bump layer by a subtractive process, wherein the material of the bump layer is removed to form the bumps.
This method has many advantages. Primarily, the provision of a bump layer gives the opportunity to make sure the layer is smooth and flat to within desired tolerances (e.g. preferably to within 15μιη flatness) at the beginning of processing. The layer surface will become the top of the bumps after subtractive processing. Thus the height of the bumps can be very carefully controlled for target height and, more importantly, consistency of height between bumps. Typically bump height ranges from 30μιη to 250μιη, with a preferred bump height being 150μιη (preferred height to be used in a CMUT device). In addition, the uniformity of the bump height is advantageously uniform (preferably to within 15μιη flatness).
The invention also helps to overcome the problem of adhesive variability: if bump heights are variable then volumes of adhesive (e.g. conductive epoxy), applied to the top of the bumps, also vary. In addition, by using a subtractive process, there is a high degree of freedom with the bump design to allow optimization of the amount of adhesive pick up during the fabrication process.
Another advantage of the method according to the invention is that it is possible to produce very fine pitch bumps (e.g. pitch of 150μιη). Such bumps are almost impossible to produce with other fabrication methods.
The method according to the invention is also very inexpensive in comparison to other techniques.
The bumps are produced, according to the invention, by removing material rather than adding material. This gives the advantage of good adhesion to the backing surface, which is important for the strength of the fabricated flip chip element as deployed in a device. In a further embodiment of the invention, the method comprises the step of: Underfilling the bump layer, to fill in gaps between the bumps.
The purpose of the underfill is to provide mechanical stability and strength to the flip chip element. Epoxy resin materials provide good underfill. For underfill, the epoxy should be non-conductive so as to avoid interference with the electrical effects of the bumps.
In a further embodiment of the invention, the subtractive process used to remove material between the bumps may include mechanical removal, etching by laser, etching by abrasion, etching by electrical discharge machining (edm), etching by chemical. These processes may be used singly or in combination in order to achieve the desired shapes and profiles for the bumps.
In a further embodiment of the invention, the method further comprises:
Providing an ultrasound transducer element acoustic stack as the first electrical component
Providing an ASIC (application specific integrated circuit) as the second electrical component
The method of the invention is particularly suited to the required processing during the manufacture of ultrasound transducer elements to be deployed in ultrasound arrays and devices. The production of flip chip interconnections for ultrasound applications can be very limited due to the materials requirements and tolerances of the design, particularly the fine pitch requirements which currently are in the order of 125 μιη compared to previous pitch requirements of around 190 μιη. Use of a method according to the invention is an enabling technology for the production of flip chip interconnections for ultrasound applications.
In a further embodiment of the invention, the method further allows for arranging the bump layer in association with the ultrasound transducer element acoustic stack.
This is most advantageous for the design of the contact pad. When bumps are fabricated on the surface of the ASIC, the contact pad is often sized in the order of 70 to 80 μιη. By placing the bumps on the acoustic stack, the size of the contact pads can be reduced to around 20 μιη. This not only enables fine pitch dicing to release the individual elements, it liberates the space requirements for the contact pad and gives flexibility to the design of the ASIC. A flip chip design with the bumps on the acoustic stack is often referred to as a "reverse" flip chip design.
In a further embodiment of the invention the method comprises: Providing graphite as the material of the bump layer.
Graphite is a material which is relatively soft and machinable, which is an advantage for a process which requires the removal of material in a controlled and accurate manner. Graphite also conducts electricity and therefore is suitable as a bump material. The method according to the invention is not limited to graphite, although graphite is the preferred material. Other electrically conductive materials can be used in a method according to the invention, especially electrically conducting composite materials, or conductive epoxy or tungsten carbide. These materials are also easy to machine as part of a subtractive process to remove material from the bump layer.
Ease of machining also allows great flexibility in the design of the bumps.
The bumps may be shaped as pillars or round bumps, e.g. with square, round or hexagonal profiles. The bumps may also be provided with patterning, if desired.
In a further aspect of the invention, there is provided a flip chip electrical coupling between first and second electrical components, comprising a reciprocal bump- contact pad arrangement, fabricated according to the methods as described above.
In a further aspect of the invention, there is provided a flip chip electrical coupling between first and second electrical components, comprising a reciprocal bump- contact pad arrangement, further comprising a bump layer arranged in association with one of the electrical components, a material of the bump layer being suitable to fulfill the electrical and mechanical requirements of the bumps and comprising bumps integral to the bump layer.
This method has many advantages. Primarily, the provision of a bump layer gives the opportunity to make sure the layer is smooth and flat to within desired tolerances (e.g. preferably to within 15μιη flatness) at the beginning of processing. The layer surface will become the top of the bumps after subtractive processing. Thus the height of the bumps can be very carefully controlled for target height and, more importantly, consistency of height between bumps. Typically bump height ranges from 30μιη to 250μιη, with a preferred bump height being 150μιη (preferred height to be used in a CMUT device). In addition, the uniformity of the bump height is advantageously uniform (preferably to within 15μιη flatness).
The invention also helps to overcome the problem of adhesive variability: if bump heights are variable then volumes of adhesive (e.g. conductive epoxy), applied to the top of the bumps, also vary. In addition, by using a subtractive process, there is a high degree of freedom with the bump design to allow optimization of the amount of adhesive pick up during the fabrication process. Another advantage of the method according to the invention is that it is possible to produce very fine pitch bumps (e.g. pitch of 150μιη). Such bumps are almost impossible to produce with other fabrication methods.
The method according to the invention is also very inexpensive in comparison to other techniques.
The bumps are produced, according to the invention, by removing material rather than adding material. This gives the advantage of good adhesion to the backing surface, which is important for the strength of the fabricated flip chip element as deployed in a device.
In a further embodiment of the invention, the flip chip electrical coupling further comprises underfill material arranged in the spaces between the bumps.
The purpose of the underfill is to provide mechanical stability and strength to the flip chip element. Epoxy resin materials provide good underfill. For underfill, the epoxy should be non-conductive so as to avoid interference with the electrical effects of the bumps.
In a further embodiment of the invention, the material of the bump layer is graphite.
Graphite is a material which is relatively soft and machinable, which is an advantage for a process which requires the removal of material in a controlled and accurate manner. Graphite also conducts electricity and therefore is suitable as a bump material. The method according to the invention is not limited to graphite, although graphite is the preferred material. Other electrically conductive materials can be used in a method according to the invention, especially electrically conducting composite materials, or conductive epoxy or tungsten carbide. These materials are also easy to machine as part of a subtractive process to remove material from the bump layer.
Ease of machining also allows great flexibility in the design of the bumps.
The bumps may be shaped as pillars or round bumps, e.g. with square, round or hexagonal profiles. The bumps may also be provided with patterning, if desired.
In a further aspect of the invention, there is provided a device comprising the flip chip electrical coupling as described above.
A flip chip electrical coupling according to the invention may be utilized in any device, especially those devices which require a fine pitch and /or high aspect ratio of the bumps and a reduced footprint on an ASIC.
In a further aspect of the invention, there is provided an ultrasound device comprising the flip chip electrical coupling as described above, wherein the first electrical component is arranged as an ultrasound transducer element acoustic stack and the second electrical component as an ASIC (application specific integrated circuit).
The method of the invention is particularly suited to the required processing during the manufacture of ultrasound transducer elements to be deployed in ultrasound arrays and devices. The production of flip chip interconnections for ultrasound applications can be very limited due to the materials requirements and tolerances of the design, particularly the fine pitch requirements which currently are in the order of 125 μιη compared to previous pitch requirements of around 190 μιη. Use of a method according to the invention is an enabling technology for the production of flip chip interconnections for ultrasound applications.
In a further embodiment of the invention, the bump layer is arranged in association with the ultrasound transducer stack.
This is most advantageous for the design of the contact pad. When bumps are fabricated on the surface of the ASIC, the contact pad is often sized in the order of 70 to 80 μιη. By placing the bumps on the acoustic stack, the size of the contact pads can be reduced to around 20 μιη. This not only enables fine pitch dicing to release the individual elements, it liberates the space requirements for the contact pad and gives flexibility to the design of the ASIC. A flip chip design with the bumps on the acoustic stack is often referred to as a "reverse" flip chip design.
BRIEF DESCRIPTION OF THE FIGURES
The invention will now be further elucidated by reference to the following figures:
Fig. 1 : a schematic illustration of a flip chip electrical coupling, suitable for inclusion in an ultrasound transducer device, according to the prior art
Fig. 2: a flow chart illustrating method of fabricating a flip chip electrical coupling according to the present invention
Fig. 3: a schematic diagram of a flip chip electrical coupling, according to the present invention, during fabrication
Fig. 4a: a schematic diagram illustrating process steps to fabricate bumps according to one embodiment of the present invention
Fig. 4b: a picture of bumps fabricated according to the present invention
Fig. 5a: a schematic diagram of a flip chip electrical coupling according to the present invention during fabrication before a dicing process Fig. 5b: a schematic diagram of a flip chip electrical coupling according to the present invention as implemented in an ultrasound transducer device
Fig. 5c: a schematic diagram of a flip chip electrical coupling according to the present invention as implemented in an ultrasound transducer device, wherein the bumps have a high aspect ratio
DETAILED DESCRIPTION OF EMBODIMENTS
Fig. 1 shows an example of a prior art flip chip electrical coupling 10 designed to provide connection between a first and a second electrical component. Although many types of flip chip electrical coupling are available in the art, this example shows materials and features which are suitable for inclusion in an ultrasound transducer device. The flip chip electrical coupling 10 facilitates electrical and mechanical contact between part of a silicon based integrated circuit 11 and a contact pad 12 associated with an ultrasound transducer stack (not shown). The flip chip electrical coupling 10 comprises a bump 13, designed to reciprocate with the contact pad 12. This bump 13 has been added to the integrated circuit 11, by standard processing methods, to produce a ball of conductive material attached to the integrated circuit 11. Typically the bump 13 is made from gold (Au) or a gold-nickel alloy (Au-Ni). In order to complete the coupling between the integrated circuit 11 and the contact pad 12 of the ultrasound transducer stack (not shown), a blob of adhesive 14 is added to the contact pad 12 or added to the bump 13, by a dipping process, before being contacted and fixed against the contact pad 12. This type of flip chip electrical connection facilitates electrical contact between the integrated circuit 11 and contact pad 12, but the bumps 13 take up much space on the integrated circuit layout and must be carefully incorporated into any design. Fig. 1 illustrates a single bump, but it should be noted that more than one bump may be used to connect the two electrical components. Further, these connections are often made in large numbers based on a silicon wafer which is diced after processing to form individual connection elements.
Fig. 2 shows a flow chart illustrating method of fabricating a flip chip electrical coupling according to the present invention. The prior art flip chip devices are fabricated by adding a material which individually constitutes the bumps. According to the present invention, however, a method of fabricating a flip chip electrical coupling between first and second electrical components, the flip chip electrical coupling comprising a reciprocal bump-contact pad arrangement, comprises providing a bump layer, arranged in association with one of the electrical components, the material of the bump layer being suitable to fulfill the electrical and mechanical requirements of the bumps 21. The bumps are required to allow electrical connection between the two electrical components, thus it is clear that such a material must be a conducting material and not an insulator. The material must also be mechanically suitable to withstand the rigors of processing, including the dicing of the mass produced product into individual flip chip electrical elements or components, and the working of the device into which the flip chip electrical couplings are placed. Providing a bump layer on one of the electrical components involves placing a layer of material on a surface. In terms of complexity of process, spreading such a layer can be considered as an improvement on the fabricating of individual additive bumps over a wide area. The techniques for layering are easier to control. This allows tighter tolerances on uniformity of the layers and more control over the process. In the next step of the method according to the invention, the bumps are fabricated in the bump layer by a subtractive process, wherein the material of the bump layer is removed to form bumps 22. As the bump layer is selectively removed, the top of the bump layer forms the top of the bumps, thus giving a uniformity and consistency to the bumps formed. Further, the bump layer may not be completely removed at the base of the bumps, thereby improving the strength of the bump to component bond.
Further method steps, as in prior art methods, are added to complete the flip chip manufacture. In particular, the addition of (conductive)adhesive to the bumps is made easier by the more uniform bump height. Variability of adhesive across mass produced components is reduced.
Fig. 3 shows a schematic diagram of a flip chip electrical coupling according to the present invention 30 during fabrication. The flip chip electrical coupling connects a first electrical component 31 with a second electrical component 32. In this particular embodiment the bumps 33, 34, 35, 36 are arranged in association with the second electrical component 32. The contact pad layer 37 (comprising individual contact pads, not shown, spaced out over the contact pad layer 37 and which reciprocate with the bumps 33, 34, 35, 36), is arranged in association with the first electrical component 31. The bumps 33, 34, 35, 36 have been produced by one or more subtractive processes from bump layer 38. Part of bump layer 38 remains after the bumps are formed, however this is optional. To complete the fabrication of the flip chip electrical coupling, adhesive will be applied to the tops of bumps 33, 34, 35, 36 and the bumps 33, 34, 35, 36 will be brought into reciprocal contact with the reciprocal contact pads (not shown) of the contact pad layer 37. Once this physical contact is established, an underfill process will be applied to fill in the gaps between the bumps 33, 34, 35, 36 with an underfill material (not shown), such as a non-conductive epoxy adhesive. This adds mechanical strength to the flip chip element.
Fig. 4 is in two parts. Fig. 4a is a schematic diagram illustrating process steps to fabricate bumps according to one embodiment of the present invention, in particular stages in the fabrication of bumps according to the present invention 40, a picture of said bumps being presented in Fig. 4b.
Consider first Fig. 4a. An already etched bump layer, comprising bumps, is shown 41. A bump 43, identical to the other bumps, can be seen to have been made via a two step subtractive process. In the first step of the process, a first coarse subtractive process, e.g. a mechanical etch, had been applied to the bump layer material to produce a pillar which has width dimension as shown in first bump portion 43a. This forms the first separations of the individual bumps. A second subtractive process, with finer tolerance, has then been applied to narrow the tops of the already defined bump portion 43 a to produce a second bump portion 43b. Many subtractive processes can be applied to the bump layer in order to remove the bump layer material. Some of these processes are more accurate than others and different bump designs call for different techniques for their implementation. By the subtractive methods applied to bump layer 41, bumps 40 are fabricated as shown in Fig. 4b.
Fig. 4a also illustrates the situation 42 where adhesive 44 is applied to the bump 43 and the other bumps. This can be achieved by a dipping process.
Fig. 5a shows a schematic diagram of a flip chip electrical coupling according to the present invention 50 during fabrication before a dicing process. In this particular embodiment, the bumps 51-56 are fabricated by subtractive process from bump layer 60. This bump layer 60 has been arranged in association with the acoustic stack 61 of the ultrasound transducer. The acoustic stack 61 comprises a pair of matching layers 62 and 63, a layer of piezoelectric material 64, for production and detection of acoustic signal, and a dematching layer 65. The acoustic stack 61 and the bump layer 60 are coupled to an ASIC 66 (application specific integrated circuit) by means of the bumps 51-56. The ASIC 66 is provided with an attenuative backing 67. The bumps are underfilled by an underfill layer 68 to provide mechanical stability. The bump layer 60 is fabricated in graphite. (In a variation of process, the porosity of the graphite may be filled with a nickel material, during a process in which the nickel metal is raised to high temperature so that the metal is liquid). This material is highly suitable for machining and particularly suitable for the production of fine structures and fine pitch bumps 51-56. The bumps 51-56 are designed to connect to individual contact pads (not shown) on the ASIC 66. In order for the individual bump-contact pad co-operations to function independently, it is necessary to dice or cut through the bump layer 60 between the individual bumps 51-56, so that the individual bumps 51-56 are electrically isolated from each other. When this is achieved, it also has the effect of creating separate pillars of the acoustic stack 61, above each individual bump 51-56, to produce a flip chip coupling 70. This is shown in Fig. 5b and in Fig. 5c. The bumps 51-53 of Fig.5c are depicted with a high aspect ratio (ratio of bump height to bump width), the method of the present invention being particularly suitable to production of high aspect ratio bumps. Each bump 51-53 is shown in contact with its individual reciprocal contact pad 69a-69c, respectively. High aspect ratio bumps in a flip chip electrical coupling 71 are very suitable for inclusion in an ultrasound transducer device.
Application of flip chip electrical coupling to ultrasound applications tends towards the use of fine pitch bumps and high aspect ratio (ratio of width to height) bumps. The fabrication of bumps according to the invention, by subtractive method according to the invention, is particularly suitable to such an application. However, it should be noted that this is by no means limiting, and flip chip electrical couplings according to the present invention may also be applied to a wide range of other applications.
The figures are not drawn to scale but are merely schematic in order to illustrate the principles of the invention. However for the ultrasound transducer application it may be noted that current bump dimensions are of the order of, but not limited to, bump widths of 20 to 250μιη and bump heights of 30 to 250μιη.
List of reference numerals
10. prior art flip chip electrical coupling
11. Integrated circuit
12. Contact pad
13. bump
14. adhesive
20. method according to the invention
21. Method step according to the invention
22. Method step according to the invention
30. flip chip electrical coupling according to the invention
31. First electrical component
32. Second electrical component
33. Bump
34. Bump
35. Bump
36. Bump
37. Contact pad layer (comprising individual contact pads)
38. bump layer
40. bumps according to the invention
41. Etched bump layer comprising bumps
42. Etched bump layer comprising bumps with adhesive
43. Bump
a. Bump portion
b. Bump portion
44. adhesive
50. flip chip electrical coupling according to the invention during fabrication before a process
51. Bump
52. Bump 53. Bump
54. Bump
55. Bump
56. Bump
60. Bump layer
61. Acoustic stack
62. Matching layer
63. Matching layer
64. Layer of piezoelectric material
65. Dematching layer
66. ASIC
67. Attenuative backing
68. Underfill
69.
a. Individual contact pad
b. Individual contact pad
c. Individual contact pad
70. flip chip electrical coupling according to the invention as implemented in an ultrasound transducer device.
71. flip chip electrical coupling according to the invention as implemented in an ultrasound transducer device, wherein the bumps have a high aspect ratio.

Claims

CLAIMS:
1. A method of fabricating a flip chip electrical coupling between first and second electrical components, the flip chip coupling comprising a reciprocal bump-contact pad arrangement, comprising the steps of:
providing a bump layer, arranged in association with one of the electrical components, a material of the bump layer being suitable to fulfill the electrical and mechanical requirements of the bumps
fabricating the bumps in the bump layer by a subtractive process, wherein the material of the bump layer is removed to form the bumps.
2. A method of fabricating a flip chip electrical coupling according to claim 1, comprising an additional step of:
underfilling the bump layer, to fill in gaps between the bumps.
3. A method of fabricating a flip chip electrical coupling according to any of the above claims, wherein the subtractive process comprises removal of material of the bump layer by at least one of the following:
mechanical removal,
etching by laser,
etching by abrasion,
etching by electrical discharge machining,
etching by chemical.
4. A method of fabricating a flip chip electrical coupling according to any of the above claims comprising the further steps of:
providing an ultrasound transducer element acoustic stack as the first electrical component
providing an ASIC (application specific integrated circuit) as the second electrical component.
5. A method of fabricating a flip chip electrical coupling according to claim 4, comprising the further step of:
arranging the bump layer in association with the ultrasound transducer element acoustic stack.
6. A method of fabricating a flip chip electrical coupling according to any of the above claims, comprising the further step of:
providing graphite as the material of the bump layer.
7. A flip chip electrical coupling between first and second electrical components, comprising a reciprocal bump-contact pad arrangement, fabricated according to the method of claims 1, 2, 3, 4, 5 or 6.
8. A flip chip electrical coupling between first and second electrical components, comprising a reciprocal bump-contact pad arrangement, further comprising
a bump layer arranged in association with one of the electrical components, a material of the bump layer being suitable to fulfill the electrical and mechanical requirements of the bumps
bumps integral to the bump layer.
9. A flip chip electrical coupling according to claim 8 further comprising
underfill material arranged in the spaces between the bumps.
10. A flip chip electrical coupling according to claim 8 or 9, wherein the material of the bump layer is graphite.
11. A device comprising the flip chip electrical coupling of any of the claims 7 to 10.
12. An ultrasound device comprising the flip chip electrical coupling, according to any of the claims 7 to 11, wherein the first electrical component is arranged as an ultrasound transducer element acoustic stack and the second electrical component as an ASIC
(application specific integrated circuit).
13. An ultrasound device according to claim 12 wherein the bump layer is arranged in association with the ultrasound transducer element acoustic stack.
PCT/IB2011/055519 2010-12-21 2011-12-07 Method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling WO2012085724A1 (en)

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US61/425,309 2010-12-21

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