WO2012067177A1 - Wiring board and method for producing same - Google Patents

Wiring board and method for producing same Download PDF

Info

Publication number
WO2012067177A1
WO2012067177A1 PCT/JP2011/076489 JP2011076489W WO2012067177A1 WO 2012067177 A1 WO2012067177 A1 WO 2012067177A1 JP 2011076489 W JP2011076489 W JP 2011076489W WO 2012067177 A1 WO2012067177 A1 WO 2012067177A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
wiring board
wiring
support substrate
forming
Prior art date
Application number
PCT/JP2011/076489
Other languages
French (fr)
Japanese (ja)
Inventor
孝治 本戸
Original Assignee
株式会社フジクラ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社フジクラ filed Critical 株式会社フジクラ
Priority to JP2012544292A priority Critical patent/JPWO2012067177A1/en
Publication of WO2012067177A1 publication Critical patent/WO2012067177A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09118Moulded substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10287Metal wires as connectors or conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228Cutting, sawing, milling or shearing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a wiring board for mounting an electronic component and a manufacturing method thereof.
  • the terminal pitch on one side of the wiring board is wider than the terminal pitch on the other side.
  • a through wiring board in which oblique fine holes are formed in a material by a laser or the like and a conductive material is filled in the fine holes to form oblique through wirings (see, for example, Patent Document 1). ).
  • An object of the present invention is to provide a wiring board and a method for manufacturing the wiring board that can easily form a through wiring that performs electrical connection between electronic components mounted on both sides.
  • the first end portion having an insulating layer and an end surface having a height substantially matching the height of the upper surface of the insulating layer and the end surface having a height substantially matching the height of the lower surface of the insulating layer are provided.
  • a wiring board having a second end portion having a through wiring made of a metal wire is provided.
  • the insulating layer includes a first end portion having an end surface having a height substantially matching the height of the upper surface of the insulating layer, and an end surface substantially coplanar with the side surface of the insulating layer.
  • a wiring board having a second end and provided with a through wiring made of a metal wire is provided.
  • a method of manufacturing a wiring board including a step of forming a pair of through wirings each having a second end portion in contact with the upper surface of the support substrate, and a step of removing the support substrate.
  • the step of forming a curved metal line on the upper surface of the support substrate so that both ends of the support substrate are in contact with each other, and the support substrate so as to cover at least a part of the metal line Forming an insulating layer on the upper surface; and removing a portion of the metal wire to expose the uppermost portion of the metal wire; the exposed uppermost portion as a first end portion; and both ends as second and third ends.
  • a method for manufacturing a wiring board including a step of forming a through-wiring serving as a portion and a step of removing a support substrate.
  • a step of forming an insulating layer on the upper surface of the support substrate so as to cover at least a part of the metal wire, and by removing a part of the metal wire, an end surface having a height substantially equal to the height of the upper surface of the insulating layer is formed.
  • a method for manufacturing a wiring board including a step of forming a through wiring having a second end portion and a step of removing a support substrate.
  • FIG. 7 is a process cross-sectional view subsequent to FIG. 6 for describing an example of the method for manufacturing the wiring board according to the embodiment of the present invention.
  • FIG. 10 is a process cross-sectional view subsequent to FIG. 9 for describing an example of the method for manufacturing the wiring board according to the embodiment of the present invention. It is process sectional drawing following FIG. 10 for demonstrating an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 1st modification of embodiment of this invention.
  • FIG. 17 is a process cross-sectional view subsequent to FIG. 16 for illustrating the example of the method for manufacturing the wiring board according to the fourth modification example of the embodiment of the present invention.
  • FIG. 18 is a process cross-sectional view subsequent to FIG.
  • FIG. 17 for describing the example of the method for manufacturing the wiring board according to the fourth modification example of the embodiment of the present invention. It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 5th modification of embodiment of this invention.
  • FIG. 20 is a process cross-sectional view subsequent to FIG. 19 for describing an example of the method of manufacturing the wiring board according to the fifth modification example of the embodiment of the present invention.
  • FIG. 21 is a process cross-sectional view subsequent to FIG. 20 for illustrating the example of the method for manufacturing the wiring board according to the fifth modification example of the embodiment of the present invention. It is sectional drawing which shows an example of the wiring board which concerns on other embodiment of this invention. It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on other embodiment of this invention.
  • the wiring board according to the embodiment of the present invention includes an insulating layer 1, a first end portion (upper end) having an end surface having a height substantially matching the height of the upper surface of the insulating layer 1, and The second end portion (lower end) having an end surface with a height substantially equal to the height of the lower surface of the insulating layer 1, and the through wires 11a to 16a, 11b to 16b made of metal wires, and the through wires 11a to 16a, Upper surface side pads 2a to 2l connected to the upper ends of 11b to 16b and lower surface side pads 3a to 3l connected to the lower ends of the through wirings 11a to 16a and 11b to 16b.
  • the “metal wire” means a metal member that is linear before being covered with the insulating layer 1 such as a bonding wire, a wire, or a stud bump.
  • the insulating layer 1 has a thickness of about 50 ⁇ m to 1 mm, for example.
  • a material of the insulating layer 1 an epoxy resin, an inorganic material, or the like can be used, and is not particularly limited as long as it is an insulating material.
  • the through wirings 11a to 16a and 11b to 16b have a wire diameter of about 20 ⁇ m to 100 ⁇ m, for example.
  • bonding wires made of a material such as gold (Au) or copper (Cu) can be used.
  • the through wirings 11 a to 16 a extend parallel to the thickness direction of the insulating layer 1.
  • the through wirings 11 b to 16 b extend obliquely with respect to the thickness direction of the insulating layer 1.
  • the intervals between the lower ends of the through wirings 11b to 16b may be increased toward the outer periphery, or the lower ends of the through wirings 11b to 16b may be arranged at equal intervals. Assuming a ball grid array, the grids are usually located at equal intervals, so that the lower ends of the through wirings 11b to 16b are arranged at equal intervals, so that they can be efficiently mounted.
  • the pair of through wirings 11a and 11b is formed by dividing one bonding wire.
  • the through wiring 11 a includes a first bonding portion 111 connected to the lower surface side pad 3 a, a ball portion 112 on the first bonding portion 111, and a first wiring on the ball portion 112. Part 113.
  • the first joint portion 111, the ball portion 112, and the first wiring portion 113 are integrally formed.
  • the through wiring 11b includes a second bonding portion 114 connected to the lower surface side pad 3b and a second wiring portion 115 on the second bonding portion 114.
  • the second bonding portion 114 and the second wiring portion 115 are integrally formed.
  • FIG. 3 shows an example of a layout of a plurality of through wirings 11x arranged in the insulating layer 1x.
  • the upper ends of the through wirings 11x are arranged at equal intervals.
  • the lower end of the through wiring 11x is arranged so as to spread toward the outer periphery.
  • the material of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l shown in FIG. 1 copper (Cu) or the like can be used.
  • the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l have cross-sectional areas larger than the cross-sectional areas of the upper and lower ends of the through wirings 11a to 16a and 11b to 16b, respectively.
  • electronic components are mounted on the upper and lower surfaces of the wiring board shown in FIG. 1, electronic components having different terminal positions are electrically connected via the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l. Can do.
  • the pitch of the upper surface side pads 2a to 2l is, for example, about 50 ⁇ m, and the pitch of the lower surface side pads 3a to 3l is, for example, about 150 ⁇ m.
  • the pitch of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l can be appropriately adjusted according to the thickness of the insulating layer 1 and the layout of the through wirings 11a to 16a and 11b to 16b.
  • the wiring board according to the embodiment of the present invention can be applied to an electronic device as shown in FIG.
  • the electronic device includes a wiring board 10, an electronic component 20 flip-chip mounted on the upper surface of the wiring board 10, and an electronic component 30 flip-chip mounted on the lower surface of the wiring board 10.
  • the electronic component 20 is, for example, an IC chip, and includes a base body 21 and a plurality of electrodes 22 that are disposed on the lower surface of the base body 21 and are respectively connected to the upper surface side pads 2a to 2l of the wiring board 10 via a plurality of bumps 71. .
  • a part of the surfaces of the plurality of electrodes 22 of the electronic component 20 and the upper surface side pads 2a to 2l of the wiring board 10 are covered with solder resists 73 and 74, respectively.
  • the plurality of electrodes 22 of the electronic component 20 and exposed portions of the upper surface side pads 2a to 2l of the wiring board 10 are connected to the plurality of bumps 71, respectively. Between the electronic component 20 and the wiring board 10 is sealed with an underfill 75.
  • the electronic component 30 is, for example, a mother board, and includes a base 31 and a plurality of electrodes 32 disposed on the top surface of the base 31 and connected to the bottom surface pads 3a to 3l of the wiring board 10 via a plurality of bumps 72, respectively. Part of the surfaces of the lower surface side pads 3a to 3l of the wiring board 10 and the plurality of electrodes 32 of the electronic component 30 are covered with solder resists 76 and 77, respectively. The exposed portions of the lower surface side pads 3a to 3l of the wiring board 10 and the plurality of electrodes 32 of the electronic component 30 are connected to the plurality of bumps 72, respectively. The electronic component 30 and the wiring board 10 are sealed with an underfill 78.
  • the electrode 22 of the electronic component 20 and the electrode 32 of the electronic component 30 have different arrangement positions and intervals.
  • FIG. 4 the electronic device in which the single-layer wiring board 10 is interposed between the electronic components 20 and 30 has been described. However, a plurality of wiring boards are provided between the electronic components according to the arrangement positions and intervals of the electrodes of the electronic components. Layer stacking is also possible.
  • the electronic parts 20 and 30 in which the electrodes 22 and 32 are arranged with high density and different layouts are formed without using a multilayer wiring structure. It becomes possible to freely connect the electrodes 22 and 32 of the electronic components 20 and 30 mounted on both surfaces of the wiring board 10.
  • through-hole wirings 11a to 16a and 11b to 16b made of bonding wires are used, a fine hole is formed by a laser or the like, and then compared to a through-wiring made of a conductive material filled in the fine hole by plating or printing. Since conduction can be ensured without bubbles, connection reliability can be improved.
  • a plate-like support substrate 4 of about 50 ⁇ to 1 mm having rigidity such as a metal plate such as stainless steel or a silicon substrate is prepared.
  • a 1 mm thick stainless steel plate is used.
  • the material of the support substrate 4 is not particularly limited as long as wire bonding can be performed in a later process.
  • a substrate in which a metal layer such as copper (Cu), gold (Au), or nickel (Ni) is deposited on the upper surface of the support substrate 4 by sputtering or the like may be prepared.
  • FIG. 6 it is made of curved copper (Cu) or gold (Au) or the like so that both ends thereof are in contact with the support substrate 4 by wire bonding such as ultrasonic thermocompression bonding.
  • the bonding wires 11 to 16 are formed, for example, with a wire diameter of about 20 ⁇ m and a minimum pad pitch of about 50 ⁇ m.
  • the “curved shape” includes not only a loop-like smooth curve but also a shape in which a plurality of linear portions are bent. For example, when forming the bonding wire 11, as shown in FIG.
  • a gold ball is formed using a capillary (not shown), and the gold ball is pressed on the support substrate 4 using the capillary to support the support substrate 4.
  • a first joint portion 111 and a ball portion 112 to be joined to each other are formed.
  • the capillary is moved to form the loop-shaped first wiring part 113 and the second wiring part 115.
  • a second bonding portion 114 that is pressed onto the support substrate 4 using a capillary and bonded to the support substrate 4 is formed.
  • the gold wire is cut to complete one cycle.
  • FIG. 8 shows an example of a layout in which a plurality of bonding wires 11y are formed on the support substrate 4x. The plurality of bonding wires 11y are formed so as to pass through the upper layer as the length is relatively long.
  • the insulating layer 1 is formed by curing at 30 ° C. for 30 minutes. Examples of the method for forming the insulating layer 1 include a method of printing a polyimide varnish, a method of forming a glass layer by a sol-gel method, a method of laminating a semi-cured green sheet for a ceramic substrate, and sintering at about 1000 ° C. Can also be used.
  • the material of the insulating layer 1 may be an inorganic material and is not particularly limited as long as it is an insulating material.
  • each of the bonding wires 11 to 16 and the upper portion of the insulating layer 1 are removed to a predetermined thickness by polishing or the like, and each of the bonding wires 11 to 16 is divided into two.
  • through wirings 11a to 16a and 11b to 16b having upper ends each having an end surface whose height substantially coincides with the height of the upper surface of the insulating layer 1 are formed.
  • the through wirings 11 a to 16 a extend parallel to the thickness direction of the insulating layer 1.
  • the through wirings 11 b to 16 b extend obliquely with respect to the thickness direction of the insulating layer 1.
  • the through wirings 11b to 16b may be formed so that the lower end intervals are widened toward the outer periphery, or may be formed so that the lower ends are equally spaced.
  • (E) The support substrate 4 is removed as shown in FIG. As a result, the lower ends of the through wirings 11a to 16a and 11b to 16b are exposed. Thereafter, as shown in FIG. 1, upper surface side pads 2a to 2l and lower surface side pads 3a to 3l are respectively formed on the surfaces of the through wirings 11a to 16a, 11b to 16b by copper (Cu) plating or the like. Is completed. Furthermore, if necessary, nickel (Ni) plating, gold (Au) plating, or the like can be applied to at least one of the upper and lower surfaces of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l. In addition, as shown in FIG. 4, the electronic device can be manufactured by flip-chip mounting the electronic components 20 and 30 on both surfaces of the wiring board 10.
  • the through wires 11a to 16a and 11b to 16b including the bonding wires 11 to 16 formed by wire bonding are formed.
  • the through wirings 11a to 16a and 11b to 16b are formed.
  • the through wirings 11a to 16a and 11b to 16b can be uniformly formed with a desired wire diameter and shape.
  • the insulating layer 1 is formed with a predetermined thickness so that the upper portions of the bonding wires 11 to 16 are exposed.
  • the bonding wires 11 to 16 are removed to the height of the upper surface of the insulating layer 1 by polishing or the like. As a result, a structure similar to the structure shown in FIG. 10 is obtained. Since the subsequent steps are substantially the same as the manufacturing steps according to the embodiment of the present invention, a duplicate description is omitted.
  • the step of removing a part of the insulating layer 1 can be omitted as compared with the method of manufacturing a wiring board according to the embodiment of the present invention.
  • the through wirings 11a to 16a and 11b to 16b can be easily formed. Furthermore, since the insulating layer 1 is formed at a predetermined height not to be removed, the material of the insulating layer 1 can be saved.
  • the wiring board according to the second modification of the embodiment of the present invention has a first end portion (upper end) having an end surface whose height substantially coincides with the height of the upper surface of the insulating layer 1. And curved through-holes each having a second end and a third end (lower end) that branch from the upper end and extend in different directions and have end faces having a height substantially equal to the height of the lower surface of the insulating layer 1
  • the point provided with the wirings 11 and 14 differs from the wiring board which concerns on embodiment of this invention.
  • the upper ends of the through wirings 11 and 14 are elliptical.
  • upper surface side pads 2 m and 2 n connected to the through wirings 11 and 14 are arranged.
  • Other configurations are substantially the same as those of the wiring board according to the embodiment of the present invention, and a duplicate description is omitted.
  • the wiring board according to the second modification of the embodiment of the present invention is effective in that it can be branched and wired without using a multilayer wiring structure when the electronic components are branched and wired. .
  • the insulating layer 1 is placed at a predetermined height so that the uppermost portions of the bonding wires 11 and 14 are exposed.
  • the upper portions of the bonding wires 11 to 16 may be removed to the height of the insulating layer 1 by polishing or the like.
  • a part of the insulating layer 1 and a part of the bonding wires 11 to 16 are cut to a height that does not divide the bonding wires 11 and 14 into two. Both may be removed.
  • the wiring board according to the third modified example of the embodiment of the present invention has end portions where the through wirings 13 b and 16 b have end surfaces that are substantially on the same plane as the side surface of the insulating layer 1. It differs from the wiring board according to the embodiment of the present invention.
  • the wiring board according to the embodiment of the present invention On the side surface of the insulating layer 1, side surface pads 3m and 3n connected to the end portions of the through wirings 13b and 16b are arranged.
  • the insulating layer 1 and the through wiring 11a are polished by polishing or the like.
  • Part of the outer peripheries of .about.16a, 11b.about.16b is removed, and the through wirings 13b, 16b are exposed from the side surfaces of the insulating layer 1.
  • the side pads 3m and 3n connected to the through wirings 13b and 16b may be formed by plating or the like.
  • the support substrate 4 is formed by the stud bump method as shown in FIG. Stud bumps 42a to 42l having protrusions 41a to 41l formed thereon are formed.
  • the protrusions 41a to 41l and the stud bumps 42a to 42l constitute metal wires extending in different directions with respect to the upper surface of the support substrate 4.
  • the insulating layer 1 is formed on the upper surface of the support substrate 4 at a predetermined height so as to cover a part of the protrusions 41a to 41l. Thereafter, as shown in FIG. 18, a part of the protrusions 41a to 41l is removed to the height of the upper surface of the insulating layer 1 by polishing or the like.
  • a part of the protrusions 41 a to 41 l and a part of the insulating layer 1 are removed. May be.
  • the wiring board can be easily manufactured even when the stud bump method is used instead of wire bonding.
  • an odd number of through wirings can be formed and the through wirings can be individually arranged as compared with the case where a pair of through wirings are formed by dividing one metal wire.
  • the degree of freedom of arrangement becomes high.
  • the support substrate 4 is penetrated by etching or the like as shown in FIG. Holes 51a to 51l are formed.
  • the metal wires 61 to 66 made of gold (Au), copper (Cu), aluminum (Al) or the like prepared in advance are bent and inserted into the through holes 51a to 51l and fixed.
  • the insulating layer 1 is formed on the upper surface of the support substrate 4 so as to expose part of the metal wires 61 to 66.
  • a part of the metal wires 61 to 66 is removed to the height of the upper surface of the insulating layer 1 by polishing or the like.
  • a part of the metal lines 61 to 66 and a part of the insulating layer 1 may be removed.
  • the support substrate 4 is removed, and part of the metal wires 61 to 66 protruding from the lower surface of the insulating layer 1 is removed by polishing or the like.
  • thermocompression bonding wire bonding has been described, but wire bonding such as thermocompression bonding or ultrasonic bonding may be used.
  • wire bonding such as thermocompression bonding or ultrasonic bonding may be used.
  • the ultrasonic method it is possible to perform bonding at room temperature using, for example, an aluminum wire.
  • the interposer having the through wirings 11b to 16b extending obliquely so that the lower end extends toward the outer periphery with respect to the thickness direction of the insulating layer 1 has been described as an example.
  • the present invention can also be applied to a wiring board having only through wirings parallel to the thickness direction of the insulating layer 1.
  • the penetration wirings 11a to 16a extending in parallel with the thickness direction of the insulating layer 1 and the penetration wirings 11b to 16b extending obliquely with respect to the thickness direction of the insulating layer 1 have been described. By adjusting, it can be applied to a wiring board having only through wirings extending obliquely with respect to the thickness direction of the insulating layer 1.
  • the through wirings 11a to 16a may extend obliquely with respect to the thickness direction of the insulating layer 1 like the through wirings 11b to 16b.
  • the wiring board shown in FIG. 22 can be manufactured by previously forming portions of the bonding wires 11 to 16 to be the through wirings 11a to 16a shown in FIG.

Abstract

The present invention provides a wiring board in which feed-through wirings for electrically connecting electronic parts mounted on the opposite surfaces of the wiring board can be formed easily. The wiring board includes an insulating layer (1) and feed-through wirings (11a-16a, 11b-16b), each feed-through wiring being made of a metal wire and having: a first terminal having a terminal surface at a level substantially matching the level of the upper surface of the insulating layer (1); and a second terminal having a terminal surface at a level substantially matching the level of the lower surface of the insulating layer (1).

Description

配線板及びその製造方法Wiring board and manufacturing method thereof
 本発明は、電子部品を実装するための配線板及びその製造方法に関する。 The present invention relates to a wiring board for mounting an electronic component and a manufacturing method thereof.
 電子機器の小型化、高機能化に伴って、機器に組み込まれる電子部品(デバイス)も小型化、高集積化が進んでいる。 As electronic devices become smaller and more functional, electronic components (devices) built into the devices are also becoming smaller and more integrated.
 配線板(基板)の両面にそれぞれ実装された電子部品間で電気的接続を行う場合において、実装する電子部品が異種である場合には、電子部品毎に必要な電極の配置が異なるため、電極の配置に応じた表面配線が必要となる。 When electrical connections are made between electronic components mounted on both sides of the wiring board (substrate), if the electronic components to be mounted are different, the arrangement of the necessary electrodes differs for each electronic component. The surface wiring according to the arrangement of is required.
 しかしながら、表面配線同士の短絡や電気信号の干渉を避けるために、表面配線間に所定の間隔を設ける必要があり、配線板表面における表面配線の占有面積が増大し、電子部品の配置の制約が厳しくなるという問題がある。また、表面配線が長いと、信号遅延が発生したり、高周波特性が劣化したりする問題がある。 However, in order to avoid short-circuiting between surface wirings and interference of electrical signals, it is necessary to provide a predetermined interval between the surface wirings, increasing the area occupied by the surface wiring on the surface of the wiring board, and limiting the placement of electronic components. There is a problem of becoming severe. In addition, if the surface wiring is long, there are problems that signal delay occurs and high frequency characteristics deteriorate.
 また、配線板の両面にそれぞれ実装された電子部品間で電気的接続を行う他の手法として、配線板の一方の面の端子ピッチを他方の面の端子ピッチよりも拡げるため、ガラス等の基材にレーザー等により斜めの微細孔を設け、微細孔内に導電性物質を充填して、斜めの貫通配線を形成した貫通配線基板(インターポーザ)が知られている(例えば、特許文献1参照。)。 As another method for electrical connection between electronic components mounted on both sides of the wiring board, the terminal pitch on one side of the wiring board is wider than the terminal pitch on the other side. There is known a through wiring board (interposer) in which oblique fine holes are formed in a material by a laser or the like and a conductive material is filled in the fine holes to form oblique through wirings (see, for example, Patent Document 1). ).
 しかしながら、この方法では、レーザー等により基材に微細孔を設ける必要があるため、貫通配線を形成するのは困難であった。 However, in this method, since it is necessary to provide fine holes in the substrate with a laser or the like, it is difficult to form the through wiring.
特開2006-303360号公報JP 2006-303360 A
 本発明の目的は、両面に実装される電子部品間の電気的接続を行う貫通配線を容易に形成することが可能な配線板及びその製造方法を提供することである。 An object of the present invention is to provide a wiring board and a method for manufacturing the wiring board that can easily form a through wiring that performs electrical connection between electronic components mounted on both sides.
 本発明の一態様によれば、絶縁層と、絶縁層の上面の高さと略一致する高さの端面を有する第1の端部及び絶縁層の下面の高さと略一致する高さの端面を有する第2の端部を有し、金属線からなる貫通配線とを備える配線板が提供される。 According to one aspect of the present invention, the first end portion having an insulating layer and an end surface having a height substantially matching the height of the upper surface of the insulating layer and the end surface having a height substantially matching the height of the lower surface of the insulating layer are provided. A wiring board having a second end portion having a through wiring made of a metal wire is provided.
 本発明の他の態様によれば、絶縁層と、絶縁層の上面の高さと略一致する高さの端面を有する第1の端部及び絶縁層の側面と略同一平面上にある端面を有する第2の端部を有し、金属線からなる貫通配線とを備える配線板が提供される。 According to another aspect of the present invention, the insulating layer includes a first end portion having an end surface having a height substantially matching the height of the upper surface of the insulating layer, and an end surface substantially coplanar with the side surface of the insulating layer. A wiring board having a second end and provided with a through wiring made of a metal wire is provided.
 本発明の更に他の態様によれば、支持基板の上面に、支持基板と両端が接するように曲線状の金属線を形成する工程と、金属線の少なくとも一部を覆うように、支持基板の上面に絶縁層を形成する工程と、金属線の一部を除去することにより金属線を分断し、前記絶縁層の上面の高さと略一致する高さの端面を有する第1の端部と、前記支持基板の上面に接する第2の端部とをそれぞれ有する一対の貫通配線を形成する工程と、支持基板を除去する工程とを含む配線板の製造方法が提供される。 According to still another aspect of the present invention, the step of forming a curved metal line on the upper surface of the support substrate so that both ends of the support substrate are in contact with each other, and the support substrate so as to cover at least a part of the metal line. A step of forming an insulating layer on the upper surface; a first end portion having an end surface with a height substantially equal to a height of the upper surface of the insulating layer, by dividing the metal wire by removing a part of the metal wire; There is provided a method of manufacturing a wiring board including a step of forming a pair of through wirings each having a second end portion in contact with the upper surface of the support substrate, and a step of removing the support substrate.
 本発明の更に他の態様によれば、支持基板の上面に、支持基板と両端が接するように曲線状の金属線を形成する工程と、金属線の少なくとも一部を覆うように、支持基板の上面に絶縁層を形成する工程と、金属線の一部を除去することにより金属線の最上部を露出させ、露出した最上部を第1の端部とし、両端を第2及び第3の端部とする貫通配線を形成する工程と、支持基板を除去する工程とを含む配線板の製造方法が提供される。 According to still another aspect of the present invention, the step of forming a curved metal line on the upper surface of the support substrate so that both ends of the support substrate are in contact with each other, and the support substrate so as to cover at least a part of the metal line. Forming an insulating layer on the upper surface; and removing a portion of the metal wire to expose the uppermost portion of the metal wire; the exposed uppermost portion as a first end portion; and both ends as second and third ends Provided is a method for manufacturing a wiring board including a step of forming a through-wiring serving as a portion and a step of removing a support substrate.
 本発明の更に他の態様によれば、支持基板の上面に、支持基板の上面と接する第1の端部を有し、支持基板の上面と異なる方向に延伸する金属線を形成する工程と、金属線の少なくとも一部を覆うように、支持基板の上面に絶縁層を形成する工程と、金属線の一部を除去することにより、絶縁層の上面の高さと略一致する高さの端面を有する第2の端部を有する貫通配線を形成する工程と、支持基板を除去する工程とを含む配線板の製造方法が提供される。 According to still another aspect of the present invention, the step of forming a metal wire having a first end in contact with the upper surface of the support substrate on the upper surface of the support substrate and extending in a direction different from the upper surface of the support substrate; A step of forming an insulating layer on the upper surface of the support substrate so as to cover at least a part of the metal wire, and by removing a part of the metal wire, an end surface having a height substantially equal to the height of the upper surface of the insulating layer is formed. There is provided a method for manufacturing a wiring board, including a step of forming a through wiring having a second end portion and a step of removing a support substrate.
本発明の実施の形態に係る配線板の一例を示す断面図である。It is sectional drawing which shows an example of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の一部を拡大した断面図である。It is sectional drawing to which a part of wiring board concerning an embodiment of the invention was expanded. 本発明の実施の形態に係る配線板の貫通配線のレイアウトの一例を示す斜視図である。It is a perspective view which shows an example of the layout of the penetration wiring of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板に電子部品を実装した電子装置の一例を示す断面図である。It is sectional drawing which shows an example of the electronic device which mounted the electronic component in the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための図5に引き続く工程断面図である。It is process sectional drawing following FIG. 5 for demonstrating an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための断面図である。It is sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の製造方法におけるワイヤボンディングのレイアウトの一例を説明するための上面図である。It is a top view for demonstrating an example of the layout of wire bonding in the manufacturing method of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための図6に引き続く工程断面図である。FIG. 7 is a process cross-sectional view subsequent to FIG. 6 for describing an example of the method for manufacturing the wiring board according to the embodiment of the present invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための図9に引き続く工程断面図である。FIG. 10 is a process cross-sectional view subsequent to FIG. 9 for describing an example of the method for manufacturing the wiring board according to the embodiment of the present invention. 本発明の実施の形態に係る配線板の製造方法の一例を説明するための図10に引き続く工程断面図である。It is process sectional drawing following FIG. 10 for demonstrating an example of the manufacturing method of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態の第1の変形例に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 1st modification of embodiment of this invention. 本発明の実施の形態の第2の変形例に係る配線板の一例を示す断面図である。It is sectional drawing which shows an example of the wiring board which concerns on the 2nd modification of embodiment of this invention. 本発明の実施の形態の第2の変形例に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 2nd modification of embodiment of this invention. 本発明の実施の形態の第3の変形例に係る配線板の一例を示す断面図である。It is sectional drawing which shows an example of the wiring board which concerns on the 3rd modification of embodiment of this invention. 本発明の実施の形態の第4の変形例に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 4th modification of embodiment of this invention. 本発明の実施の形態の第4の変形例に係る配線板の製造方法の一例を説明するための図16に引き続く工程断面図である。FIG. 17 is a process cross-sectional view subsequent to FIG. 16 for illustrating the example of the method for manufacturing the wiring board according to the fourth modification example of the embodiment of the present invention. 本発明の実施の形態の第4の変形例に係る配線板の製造方法の一例を説明するための図17に引き続く工程断面図である。FIG. 18 is a process cross-sectional view subsequent to FIG. 17 for describing the example of the method for manufacturing the wiring board according to the fourth modification example of the embodiment of the present invention. 本発明の実施の形態の第5の変形例に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on the 5th modification of embodiment of this invention. 本発明の実施の形態の第5の変形例に係る配線板の製造方法の一例を説明するための図19に引き続く工程断面図である。FIG. 20 is a process cross-sectional view subsequent to FIG. 19 for describing an example of the method of manufacturing the wiring board according to the fifth modification example of the embodiment of the present invention. 本発明の実施の形態の第5の変形例に係る配線板の製造方法の一例を説明するための図20に引き続く工程断面図である。FIG. 21 is a process cross-sectional view subsequent to FIG. 20 for illustrating the example of the method for manufacturing the wiring board according to the fifth modification example of the embodiment of the present invention. 本発明のその他の実施の形態に係る配線板の一例を示す断面図である。It is sectional drawing which shows an example of the wiring board which concerns on other embodiment of this invention. 本発明のその他の実施の形態に係る配線板の製造方法の一例を説明するための工程断面図である。It is process sectional drawing for demonstrating an example of the manufacturing method of the wiring board which concerns on other embodiment of this invention.
 次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
 また、以下に示す実施の形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。この発明の技術的思想は、請求の範囲において、種々の変更を加えることができる。 Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.
(配線板の構造)
 本発明の実施の形態に係る配線板は、図1に示すように、絶縁層1と、絶縁層1の上面の高さと略一致する高さの端面を有する第1の端部(上端)及び絶縁層1の下面の高さと略一致する高さの端面を有する第2の端部(下端)を有し、金属線からなる貫通配線11a~16a,11b~16bと、貫通配線11a~16a,11b~16bの上端に接続された上面側パッド2a~2lと、貫通配線11a~16a,11b~16bの下端に接続された下面側パッド3a~3lとを備える。
(Structure of wiring board)
As shown in FIG. 1, the wiring board according to the embodiment of the present invention includes an insulating layer 1, a first end portion (upper end) having an end surface having a height substantially matching the height of the upper surface of the insulating layer 1, and The second end portion (lower end) having an end surface with a height substantially equal to the height of the lower surface of the insulating layer 1, and the through wires 11a to 16a, 11b to 16b made of metal wires, and the through wires 11a to 16a, Upper surface side pads 2a to 2l connected to the upper ends of 11b to 16b and lower surface side pads 3a to 3l connected to the lower ends of the through wirings 11a to 16a and 11b to 16b.
 本発明の実施の形態において、「金属線」とは、ボンディングワイヤ、針金又はスタッドバンプ等の、絶縁層1により周囲を覆われる前に予め線状となっている金属部材を意味する。 In the embodiment of the present invention, the “metal wire” means a metal member that is linear before being covered with the insulating layer 1 such as a bonding wire, a wire, or a stud bump.
 絶縁層1は、例えば50μm~1mm程度の厚さを有する。絶縁層1の材料としては、エポキシ系樹脂や無機材料等が使用可能であり、絶縁性の材料であれば特に限定されない。 The insulating layer 1 has a thickness of about 50 μm to 1 mm, for example. As a material of the insulating layer 1, an epoxy resin, an inorganic material, or the like can be used, and is not particularly limited as long as it is an insulating material.
 貫通配線11a~16a,11b~16bは、例えば20μm~100μm程度の線径を有する。貫通配線11a~16a,11b~16bとしては、例えば金(Au)又は銅(Cu)等の材料からなるボンディングワイヤが使用可能である。 The through wirings 11a to 16a and 11b to 16b have a wire diameter of about 20 μm to 100 μm, for example. As the through wirings 11a to 16a and 11b to 16b, for example, bonding wires made of a material such as gold (Au) or copper (Cu) can be used.
 貫通配線11a~16aは、絶縁層1の厚さ方向に対して平行に延伸する。一方、貫通配線11b~16bは、絶縁層1の厚さ方向に対して斜めに延伸する。このように貫通配線11b~16bを斜めに延伸させることにより、多層にせずに単層の配線板で電子部品間を接続することができる。貫通配線11b~16bの下端の間隔は、外周に向かうにつれて広がっていても良いし、貫通配線11b~16bの下端が等間隔に配置されていても良い。ボールグリッドアレイを想定した場合、その格子は等間隔に位置するのが通常であるので、貫通配線11b~16bの下端を等間隔に配置することにより、効率よく実装することができる。 The through wirings 11 a to 16 a extend parallel to the thickness direction of the insulating layer 1. On the other hand, the through wirings 11 b to 16 b extend obliquely with respect to the thickness direction of the insulating layer 1. By extending the through wirings 11b to 16b obliquely in this way, it is possible to connect the electronic components with a single-layer wiring board without using multiple layers. The intervals between the lower ends of the through wirings 11b to 16b may be increased toward the outer periphery, or the lower ends of the through wirings 11b to 16b may be arranged at equal intervals. Assuming a ball grid array, the grids are usually located at equal intervals, so that the lower ends of the through wirings 11b to 16b are arranged at equal intervals, so that they can be efficiently mounted.
 貫通配線11a,11bの対は、一本のボンディングワイヤを分断することにより形成されている。図2に示すように、貫通配線11aは、下面側パッド3aに接続された第1の接合部111と、第1の接合部111上のボール部112と、ボール部112上の第1の配線部113を有する。第1の接合部111、ボール部112及び第1の配線部113は一体に形成されている。一方、貫通配線11bは、下面側パッド3bに接続された第2の接合部114と、第2の接合部114上の第2の配線部115を有する。第2の接合部114及び第2の配線部115は一体に形成されている。 The pair of through wirings 11a and 11b is formed by dividing one bonding wire. As shown in FIG. 2, the through wiring 11 a includes a first bonding portion 111 connected to the lower surface side pad 3 a, a ball portion 112 on the first bonding portion 111, and a first wiring on the ball portion 112. Part 113. The first joint portion 111, the ball portion 112, and the first wiring portion 113 are integrally formed. On the other hand, the through wiring 11b includes a second bonding portion 114 connected to the lower surface side pad 3b and a second wiring portion 115 on the second bonding portion 114. The second bonding portion 114 and the second wiring portion 115 are integrally formed.
 図1に示した貫通配線12a,12bの対、貫通配線13a,13bの対、貫通配線14a,14bの対、貫通配線15a,15bの対及び貫通配線16a,16bの対のそれぞれも、貫通配線11a,11bの対と同様に、一本のボンディングワイヤを分断することにより形成されている。 The pair of through wires 12a and 12b, the pair of through wires 13a and 13b, the pair of through wires 14a and 14b, the pair of through wires 15a and 15b, and the pair of through wires 16a and 16b shown in FIG. Similarly to the pair of 11a and 11b, it is formed by dividing one bonding wire.
 図3に、絶縁層1x内に配置された複数の貫通配線11xのレイアウトの一例を示す。貫通配線11xの上端は等間隔に配置されている。貫通配線11xの下端は、外周に向かって広がるように配置されている。 FIG. 3 shows an example of a layout of a plurality of through wirings 11x arranged in the insulating layer 1x. The upper ends of the through wirings 11x are arranged at equal intervals. The lower end of the through wiring 11x is arranged so as to spread toward the outer periphery.
 図1に示した上面側パッド2a~2l及び下面側パッド3a~3lの材料としては、銅(Cu)等が使用可能である。上面側パッド2a~2l及び下面側パッド3a~3lは、貫通配線11a~16a,11b~16bの上端及び下端の断面積よりも大きい断面積をそれぞれ有する。図1に示した配線板の上面及び下面に電子部品を実装したときに、上面側パッド2a~2l及び下面側パッド3a~3lを介して、端子位置の異なる電子部品を電気的に接続することができる。上面側パッド2a~2lのピッチは例えば50μm程度であり、下面側パッド3a~3lのピッチは例えば150μm程度である。上面側パッド2a~2l及び下面側パッド3a~3lのピッチは、絶縁層1の厚さと貫通配線11a~16a,11b~16bのレイアウトにより適宜調整することが可能である。 As the material of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l shown in FIG. 1, copper (Cu) or the like can be used. The upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l have cross-sectional areas larger than the cross-sectional areas of the upper and lower ends of the through wirings 11a to 16a and 11b to 16b, respectively. When electronic components are mounted on the upper and lower surfaces of the wiring board shown in FIG. 1, electronic components having different terminal positions are electrically connected via the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l. Can do. The pitch of the upper surface side pads 2a to 2l is, for example, about 50 μm, and the pitch of the lower surface side pads 3a to 3l is, for example, about 150 μm. The pitch of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l can be appropriately adjusted according to the thickness of the insulating layer 1 and the layout of the through wirings 11a to 16a and 11b to 16b.
 本発明の実施の形態に係る配線板は、図4に示すような電子装置に適用可能である。電子装置は、配線板10と、配線板10の上面にフリップチップ実装された電子部品20と、配線板10の下面にフリップチップ実装された電子部品30を備える。 The wiring board according to the embodiment of the present invention can be applied to an electronic device as shown in FIG. The electronic device includes a wiring board 10, an electronic component 20 flip-chip mounted on the upper surface of the wiring board 10, and an electronic component 30 flip-chip mounted on the lower surface of the wiring board 10.
 電子部品20は例えばICチップであり、基体21と、基体21の下面に配置され、配線板10の上面側パッド2a~2lに複数のバンプ71を介してそれぞれ接続された複数の電極22を有する。電子部品20の複数の電極22及び配線板10の上面側パッド2a~2lの表面の一部が、ソルダーレジスト73,74でそれぞれ覆われている。そして、電子部品20の複数の電極22及び配線板10の上面側パッド2a~2lの露出した一部が、複数のバンプ71にそれぞれ接続されている。電子部品20と配線板10の間は、アンダーフィル75により封止されている。 The electronic component 20 is, for example, an IC chip, and includes a base body 21 and a plurality of electrodes 22 that are disposed on the lower surface of the base body 21 and are respectively connected to the upper surface side pads 2a to 2l of the wiring board 10 via a plurality of bumps 71. . A part of the surfaces of the plurality of electrodes 22 of the electronic component 20 and the upper surface side pads 2a to 2l of the wiring board 10 are covered with solder resists 73 and 74, respectively. The plurality of electrodes 22 of the electronic component 20 and exposed portions of the upper surface side pads 2a to 2l of the wiring board 10 are connected to the plurality of bumps 71, respectively. Between the electronic component 20 and the wiring board 10 is sealed with an underfill 75.
 電子部品30は例えばマザーボードであり、基体31と、基体31の上面に配置され、配線板10の下面側パッド3a~3lに複数のバンプ72を介してそれぞれ接続された複数の電極32を有する。配線板10の下面側パッド3a~3l及び電子部品30の複数の電極32の表面の一部が、ソルダーレジスト76,77でそれぞれ覆われている。そして、配線板10の下面側パッド3a~3l及び電子部品30の複数の電極32の露出した一部が複数のバンプ72にそれぞれ接続されている。電子部品30と配線板10の間は、アンダーフィル78により封止されている。 The electronic component 30 is, for example, a mother board, and includes a base 31 and a plurality of electrodes 32 disposed on the top surface of the base 31 and connected to the bottom surface pads 3a to 3l of the wiring board 10 via a plurality of bumps 72, respectively. Part of the surfaces of the lower surface side pads 3a to 3l of the wiring board 10 and the plurality of electrodes 32 of the electronic component 30 are covered with solder resists 76 and 77, respectively. The exposed portions of the lower surface side pads 3a to 3l of the wiring board 10 and the plurality of electrodes 32 of the electronic component 30 are connected to the plurality of bumps 72, respectively. The electronic component 30 and the wiring board 10 are sealed with an underfill 78.
 電子部品20の電極22と電子部品30の電極32とは配置位置・間隔が異なっている。なお、図4では電子部品20,30間に単層の配線板10を介在させた電子装置を説明したが、電子部品の電極の配置位置・間隔に応じて、電子部品間に配線板を複数層積層させることも可能である。 The electrode 22 of the electronic component 20 and the electrode 32 of the electronic component 30 have different arrangement positions and intervals. In FIG. 4, the electronic device in which the single-layer wiring board 10 is interposed between the electronic components 20 and 30 has been described. However, a plurality of wiring boards are provided between the electronic components according to the arrangement positions and intervals of the electrodes of the electronic components. Layer stacking is also possible.
 このように、本発明の実施の形態に係る配線板10によれば、電極22,32が高密度かつ異なるレイアウトで配置された電子部品20,30に対して、多層配線構造にすることなく、配線板10の両面に実装される電子部品20,30の電極22,32同士を自由に接続することが可能となる。 As described above, according to the wiring board 10 according to the embodiment of the present invention, the electronic parts 20 and 30 in which the electrodes 22 and 32 are arranged with high density and different layouts are formed without using a multilayer wiring structure. It becomes possible to freely connect the electrodes 22 and 32 of the electronic components 20 and 30 mounted on both surfaces of the wiring board 10.
 更に、ボンディングワイヤからなる貫通配線11a~16a,11b~16bを用いるので、レーザー等により微細孔を形成した後、めっきや印刷等により微細孔に充填した導電性物質からなる貫通配線と比較して、気泡が入ることなく確実に導通できるので、接続信頼性を向上させることができる。 Furthermore, since through-hole wirings 11a to 16a and 11b to 16b made of bonding wires are used, a fine hole is formed by a laser or the like, and then compared to a through-wiring made of a conductive material filled in the fine hole by plating or printing. Since conduction can be ensured without bubbles, connection reliability can be improved.
(配線板の製造方法)
 次に、本発明の実施の形態に係る配線板の製造方法の一例を、図5~図11を用いて説明する。なお、以下に示す製造方法は一例であり特に限定されるものではない。本発明の実施の形態に係る配線板は種々の製造方法により製造することが可能である。
(Manufacturing method of wiring board)
Next, an example of a method for manufacturing a wiring board according to an embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method shown below is an example and is not specifically limited. The wiring board according to the embodiment of the present invention can be manufactured by various manufacturing methods.
 (イ)図5に示すように、ステンレス等の金属板やシリコン基板等の剛性を有する50μ~1mm程度の板状の支持基板4を用意する。本発明の実施の形態では、1mm厚のステンレス板を用いる。支持基板4の材料としては、後の工程でワイヤボンディングができるものであれば特に限定されない。また、支持基板4の上面にスパッタリング等により銅(Cu)、金(Au)又はニッケル(Ni)等の金属層が堆積されたものを用意しても良い。 (A) As shown in FIG. 5, a plate-like support substrate 4 of about 50 μ to 1 mm having rigidity such as a metal plate such as stainless steel or a silicon substrate is prepared. In the embodiment of the present invention, a 1 mm thick stainless steel plate is used. The material of the support substrate 4 is not particularly limited as long as wire bonding can be performed in a later process. Alternatively, a substrate in which a metal layer such as copper (Cu), gold (Au), or nickel (Ni) is deposited on the upper surface of the support substrate 4 by sputtering or the like may be prepared.
 (ロ)次に、図6に示すように、超音波熱圧着方式等のワイヤボンディングにより、支持基板4上に両端が接するように、曲線状の銅(Cu)又は金(Au)等からなるボンディングワイヤ11~16を例えば線径20μm程度、最小パッドピッチ50μm程度で形成する。本発明の実施の形態において、「曲線状」とは、ループ状の滑らかな曲線を含む他、複数の直線部分が折れ曲がった形状も含む。例えば、ボンディングワイヤ11を形成するときは、図7に示すように、まず図示を省略したキャピラリを用いて金ボールを形成し、支持基板4上で金ボールをキャピラリを用いて押さえつけ、支持基板4と接合する第1の接合部111及びボール部112を形成する。引き続き、キャピラリを移動させ、ループ状の第1の配線部113及び第2の配線部115を形成する。そして、支持基板4上でキャピラリを用いて押さえつけ、支持基板4と接合する第2の接合部114を形成する。その後、金線を切断して1サイクルが終了する。図8に、支持基板4x上に複数のボンディングワイヤ11yを形成したレイアウトの一例を示す。複数のボンディングワイヤ11yは、相対的に長いものほど上層を通過するように形成されている。 (B) Next, as shown in FIG. 6, it is made of curved copper (Cu) or gold (Au) or the like so that both ends thereof are in contact with the support substrate 4 by wire bonding such as ultrasonic thermocompression bonding. The bonding wires 11 to 16 are formed, for example, with a wire diameter of about 20 μm and a minimum pad pitch of about 50 μm. In the embodiment of the present invention, the “curved shape” includes not only a loop-like smooth curve but also a shape in which a plurality of linear portions are bent. For example, when forming the bonding wire 11, as shown in FIG. 7, first, a gold ball is formed using a capillary (not shown), and the gold ball is pressed on the support substrate 4 using the capillary to support the support substrate 4. A first joint portion 111 and a ball portion 112 to be joined to each other are formed. Subsequently, the capillary is moved to form the loop-shaped first wiring part 113 and the second wiring part 115. Then, a second bonding portion 114 that is pressed onto the support substrate 4 using a capillary and bonded to the support substrate 4 is formed. Thereafter, the gold wire is cut to complete one cycle. FIG. 8 shows an example of a layout in which a plurality of bonding wires 11y are formed on the support substrate 4x. The plurality of bonding wires 11y are formed so as to pass through the upper layer as the length is relatively long.
 (ハ)図9に示すように、支持基板4の上面に、ボンディングワイヤ11~16全体を覆うように、例えば厚さ100μm程度の半硬化状態のエポキシ系樹脂フィルムを100℃でラミネートし、180℃、30分でキュアをすることにより絶縁層1を形成する。絶縁層1を形成する方法としては、ポリイミドワニス等を印刷する手法、ゾルゲル法によるガラス層を形成する方法、セラミックス基板用の半硬化状態のグリーンシートをラミネートし1000℃程度で焼結する方法等も使用可能である。絶縁層1の材料としては、無機材料でもよく、絶縁性の材料であれば特に限定されない。 (C) As shown in FIG. 9, a semi-cured epoxy resin film having a thickness of about 100 μm, for example, is laminated on the upper surface of the support substrate 4 at 100 ° C. so as to cover the entire bonding wires 11 to 16. The insulating layer 1 is formed by curing at 30 ° C. for 30 minutes. Examples of the method for forming the insulating layer 1 include a method of printing a polyimide varnish, a method of forming a glass layer by a sol-gel method, a method of laminating a semi-cured green sheet for a ceramic substrate, and sintering at about 1000 ° C. Can also be used. The material of the insulating layer 1 may be an inorganic material and is not particularly limited as long as it is an insulating material.
 (ニ)図10に示すように、ボンディングワイヤ11~16の上部及び絶縁層1の上部を研磨等により所定の厚さまで除去し、ボンディングワイヤ11~16のそれぞれを2本に分断する。この結果、絶縁層1の上面の高さと略一致する高さの端面を有する上端を有する貫通配線11a~16a,11b~16bが形成される。貫通配線11a~16aは、絶縁層1の厚さ方向に平行に延伸する。貫通配線11b~16bは、絶縁層1の厚さ方向に対して斜めに延伸する。貫通配線11b~16bは、下端の間隔が外周に向けて広がるように形成しても良いし、下端が等間隔になるように形成しても良い。 (D) As shown in FIG. 10, the upper portions of the bonding wires 11 to 16 and the upper portion of the insulating layer 1 are removed to a predetermined thickness by polishing or the like, and each of the bonding wires 11 to 16 is divided into two. As a result, through wirings 11a to 16a and 11b to 16b having upper ends each having an end surface whose height substantially coincides with the height of the upper surface of the insulating layer 1 are formed. The through wirings 11 a to 16 a extend parallel to the thickness direction of the insulating layer 1. The through wirings 11 b to 16 b extend obliquely with respect to the thickness direction of the insulating layer 1. The through wirings 11b to 16b may be formed so that the lower end intervals are widened toward the outer periphery, or may be formed so that the lower ends are equally spaced.
 (ホ)支持基板4を図11に示すように除去する。この結果、貫通配線11a~16a,11b~16bの下端が露出する。その後、図1に示すように、銅(Cu)めっき等により、貫通配線11a~16a,11b~16bの表面上に上面側パッド2a~2l及び下面側パッド3a~3lをそれぞれ形成し、配線板が完成する。更に、必要に応じて、上面側パッド2a~2l及び下面側パッド3a~3lの上面又は下面の少なくともいずれかに、ニッケル(Ni)めっき又は金(Au)めっき等を施すことも可能である。また、図4に示すように配線板10の両面に電子部品20,30をフリップチップ実装することにより電子装置を製造することができる。 (E) The support substrate 4 is removed as shown in FIG. As a result, the lower ends of the through wirings 11a to 16a and 11b to 16b are exposed. Thereafter, as shown in FIG. 1, upper surface side pads 2a to 2l and lower surface side pads 3a to 3l are respectively formed on the surfaces of the through wirings 11a to 16a, 11b to 16b by copper (Cu) plating or the like. Is completed. Furthermore, if necessary, nickel (Ni) plating, gold (Au) plating, or the like can be applied to at least one of the upper and lower surfaces of the upper surface side pads 2a to 2l and the lower surface side pads 3a to 3l. In addition, as shown in FIG. 4, the electronic device can be manufactured by flip-chip mounting the electronic components 20 and 30 on both surfaces of the wiring board 10.
 本発明の実施の形態に係る配線板の製造方法によれば、ワイヤボンディングにより形成したボンディングワイヤ11~16からなる貫通配線11a~16a,11b~16bを形成するので、レーザー等により基材に微細孔を設け、めっきや印刷等により微細孔に導電性物質を充填する方法と比較して、低コストで容易に貫通配線11a~16a,11b~16bを形成することが可能となる。 According to the method for manufacturing a wiring board according to the embodiment of the present invention, the through wires 11a to 16a and 11b to 16b including the bonding wires 11 to 16 formed by wire bonding are formed. Compared with the method of providing holes and filling the fine holes with a conductive material by plating or printing, it is possible to easily form the through wirings 11a to 16a and 11b to 16b at a low cost.
 更に、レーザー等により基材に微細孔を設け、めっきや印刷等により微細孔に導電性物質を充填する方法では、導電性物質を充填する時に気泡が入り込む場合があるのに対して、本発明の実施の形態に係る配線板の製造方法によれば、予め形成されたボンディングワイヤ11~16を用いるので、確実に導通でき、接続信頼性の高い貫通配線11a~16a,11b~16bを形成することが可能となる。 Furthermore, in the method in which micropores are provided in the substrate with a laser or the like and the conductive material is filled into the micropores by plating or printing, bubbles may enter when the conductive material is filled, whereas the present invention According to the method of manufacturing a wiring board according to the embodiment, since the bonding wires 11 to 16 formed in advance are used, the through wirings 11a to 16a and 11b to 16b having high connection reliability can be formed. It becomes possible.
 更に、絶縁層1を形成する前に、予めボンディングワイヤ11~16を形成するので、貫通配線11a~16a,11b~16bを所望の線径及び形状で均質に形成することができる。 Furthermore, since the bonding wires 11 to 16 are formed in advance before the insulating layer 1 is formed, the through wirings 11a to 16a and 11b to 16b can be uniformly formed with a desired wire diameter and shape.
(第1の変形例)
 本発明の実施の形態の第1の変形例として、配線板の製造方法の他の一例を説明する。
(First modification)
Another example of the method for manufacturing a wiring board will be described as a first modification of the embodiment of the present invention.
 本発明の実施の形態の第1の変形例に係る配線板の製造方法では、図6に示したボンディングワイヤ11~16を形成する工程の後、図12に示すように、支持基板4の上面に、ボンディングワイヤ11~16の上部を露出するように絶縁層1を所定の厚さで形成する点が、本発明の実施の形態に係る配線板の製造方法と異なる。 In the method for manufacturing a wiring board according to the first modification of the embodiment of the present invention, after the step of forming the bonding wires 11 to 16 shown in FIG. 6, as shown in FIG. In addition, it differs from the method for manufacturing a wiring board according to the embodiment of the present invention in that the insulating layer 1 is formed with a predetermined thickness so that the upper portions of the bonding wires 11 to 16 are exposed.
 その後、ボンディングワイヤ11~16を研磨等により絶縁層1の上面の高さまで除去する。この結果、図10に示した構造と同様の構造が得られる。後の工程は、本発明の実施の形態に係る製造工程と実質的に同様であるので、重複した説明を省略する。 Thereafter, the bonding wires 11 to 16 are removed to the height of the upper surface of the insulating layer 1 by polishing or the like. As a result, a structure similar to the structure shown in FIG. 10 is obtained. Since the subsequent steps are substantially the same as the manufacturing steps according to the embodiment of the present invention, a duplicate description is omitted.
 本発明の実施の形態の第1の変形例によれば、本発明の実施の形態に係る配線板の製造方法と比較して、絶縁層1の一部を除去する工程を省略することができ、容易に貫通配線11a~16a,11b~16bを形成することが可能となる。更に、絶縁層1を所定の除去しない高さで形成するので、絶縁層1の材料を節約することができる。 According to the first modification of the embodiment of the present invention, the step of removing a part of the insulating layer 1 can be omitted as compared with the method of manufacturing a wiring board according to the embodiment of the present invention. The through wirings 11a to 16a and 11b to 16b can be easily formed. Furthermore, since the insulating layer 1 is formed at a predetermined height not to be removed, the material of the insulating layer 1 can be saved.
(第2の変形例)
 本発明の実施の形態の第2の変形例に係る配線板は、図13に示すように、絶縁層1の上面の高さと略一致する高さの端面を有する第1の端部(上端)と、上端から分岐して互いに異なる方向に延伸し、絶縁層1の下面の高さと略一致する高さの端面を有する第2及び第3の端部(下端)とをそれぞれ有する曲線状の貫通配線11,14を備える点が、本発明の実施の形態に係る配線板と異なる。
(Second modification)
As shown in FIG. 13, the wiring board according to the second modification of the embodiment of the present invention has a first end portion (upper end) having an end surface whose height substantially coincides with the height of the upper surface of the insulating layer 1. And curved through-holes each having a second end and a third end (lower end) that branch from the upper end and extend in different directions and have end faces having a height substantially equal to the height of the lower surface of the insulating layer 1 The point provided with the wirings 11 and 14 differs from the wiring board which concerns on embodiment of this invention.
 貫通配線11,14の上端は、楕円形状である。絶縁層1の上面には、貫通配線11,14に接続された上面側パッド2m,2nが配置されている。他の構成は、本発明の実施の形態に係る配線板と実質的に同様であるので、重複した説明を省略する。 The upper ends of the through wirings 11 and 14 are elliptical. On the upper surface of the insulating layer 1, upper surface side pads 2 m and 2 n connected to the through wirings 11 and 14 are arranged. Other configurations are substantially the same as those of the wiring board according to the embodiment of the present invention, and a duplicate description is omitted.
 本発明の実施の形態の第2の変形例に係る配線板は、電子部品間を分岐して配線する場合に、多層配線構造にすることなく分岐して配線することができる点で有効である。 The wiring board according to the second modification of the embodiment of the present invention is effective in that it can be branched and wired without using a multilayer wiring structure when the electronic components are branched and wired. .
 本発明の実施の形態の第2の変形例に係る配線板の製造方法は、図14に示すように、ボンディングワイヤ11,14の最上部を露出するように絶縁層1を所定の高さで形成した後、研磨等によりボンディングワイヤ11~16の上部を絶縁層1の高さまで除去すれば良い。或いは、ボンディングワイヤ11~16の全体を覆うように絶縁層1を形成した後、ボンディングワイヤ11,14を2本に分断しない高さまで絶縁層1の一部及びボンディングワイヤ11~16の一部の双方を除去しても良い。 In the method for manufacturing a wiring board according to the second modification of the embodiment of the present invention, as shown in FIG. 14, the insulating layer 1 is placed at a predetermined height so that the uppermost portions of the bonding wires 11 and 14 are exposed. After the formation, the upper portions of the bonding wires 11 to 16 may be removed to the height of the insulating layer 1 by polishing or the like. Alternatively, after forming the insulating layer 1 so as to cover the entire bonding wires 11 to 16, a part of the insulating layer 1 and a part of the bonding wires 11 to 16 are cut to a height that does not divide the bonding wires 11 and 14 into two. Both may be removed.
(第3の変形例)
 本発明の実施の形態の第3の変形例に係る配線板は、図15に示すように、貫通配線13b,16bが、絶縁層1の側面と略同一平面上にある端面を有する端部を有する点が、本発明の実施の形態に係る配線板と異なる。絶縁層1の側面には、貫通配線13b,16bの端部に接続する側面側パッド3m,3nが配置されている。
(Third Modification)
As shown in FIG. 15, the wiring board according to the third modified example of the embodiment of the present invention has end portions where the through wirings 13 b and 16 b have end surfaces that are substantially on the same plane as the side surface of the insulating layer 1. It differs from the wiring board according to the embodiment of the present invention. On the side surface of the insulating layer 1, side surface pads 3m and 3n connected to the end portions of the through wirings 13b and 16b are arranged.
 本発明の実施の形態の第3の変形例に係る配線板の製造方法は、図10に示した支持基板4を図11に示すように除去した後、研磨等により絶縁層1及び貫通配線11a~16a,11b~16bの外周の一部を除去し、貫通配線13b,16bを絶縁層1の側面から露出させる。その後、めっき等により貫通配線13b,16bに接続した側面側パッド3m,3nを形成すれば良い。 In the method for manufacturing a wiring board according to the third modification of the embodiment of the present invention, after the support substrate 4 shown in FIG. 10 is removed as shown in FIG. 11, the insulating layer 1 and the through wiring 11a are polished by polishing or the like. Part of the outer peripheries of .about.16a, 11b.about.16b is removed, and the through wirings 13b, 16b are exposed from the side surfaces of the insulating layer 1. Thereafter, the side pads 3m and 3n connected to the through wirings 13b and 16b may be formed by plating or the like.
(第4の変形例)
 本発明の実施の形態の第4の変形例として、ワイヤボンディングをする代わりに、スタッドバンプ法を用いる配線板の製造方法の一例を説明する。
(Fourth modification)
As a fourth modification of the embodiment of the present invention, an example of a method for manufacturing a wiring board using a stud bump method instead of wire bonding will be described.
 本発明の実施の形態の第4の変形例に係る配線板の製造方法では、図5に示すように支持基板4を用意した後、図16に示すように、スタッドバンプ法により、支持基板4上に突起41a~41lが形成されたスタッドバンプ42a~42lを形成する。突起41a~41l及びスタッドバンプ42a~42lにより、支持基板4の上面に対して異なる方向に延伸する金属線が構成される。 In the method for manufacturing a wiring board according to the fourth modification of the embodiment of the present invention, after preparing the support substrate 4 as shown in FIG. 5, the support substrate 4 is formed by the stud bump method as shown in FIG. Stud bumps 42a to 42l having protrusions 41a to 41l formed thereon are formed. The protrusions 41a to 41l and the stud bumps 42a to 42l constitute metal wires extending in different directions with respect to the upper surface of the support substrate 4.
 引き続き、図17に示すように、支持基板4の上面に、突起41a~41lの一部を覆うように所定の高さで絶縁層1を形成する。その後、図18に示すように、研磨等により、突起41a~41lの一部を絶縁層1の上面の高さまで除去する。或いは、図17及び図18の手順の代わりに、突起41a~41lの全体を覆うように絶縁層1を形成した後、突起41a~41lの一部及び絶縁層1の一部の双方を除去しても良い。 Subsequently, as shown in FIG. 17, the insulating layer 1 is formed on the upper surface of the support substrate 4 at a predetermined height so as to cover a part of the protrusions 41a to 41l. Thereafter, as shown in FIG. 18, a part of the protrusions 41a to 41l is removed to the height of the upper surface of the insulating layer 1 by polishing or the like. Alternatively, instead of the procedure of FIG. 17 and FIG. 18, after forming the insulating layer 1 so as to cover the whole of the protrusions 41 a to 41 l, a part of the protrusions 41 a to 41 l and a part of the insulating layer 1 are removed. May be.
 本発明の実施の形態の第4の変形例に係る配線板の製造方法によれば、ワイヤボンディングをする代わりに、スタッドバンプ法を用いた場合でも容易に配線板を製造可能となる。この場合、一本の金属線を分断して一対の貫通配線を形成する場合と比較して、奇数本の貫通配線を形成することができ、且つ、貫通配線を個別に配置することができるので配置の自由度が高くなる。 According to the method for manufacturing a wiring board according to the fourth modification of the embodiment of the present invention, the wiring board can be easily manufactured even when the stud bump method is used instead of wire bonding. In this case, an odd number of through wirings can be formed and the through wirings can be individually arranged as compared with the case where a pair of through wirings are formed by dividing one metal wire. The degree of freedom of arrangement becomes high.
(第5の変形例)
 本発明の実施の形態の第5の変形例として、ワイヤボンディングの代わりに、予め作製した金属線を用いた配線板の製造方法の一例を説明する。
(Fifth modification)
As a fifth modification of the embodiment of the present invention, an example of a method for manufacturing a wiring board using a metal wire prepared in advance instead of wire bonding will be described.
 本発明の実施の形態の第5の変形例に係る配線板の製造方法では、図5に示すように支持基板4を用意した後、図19に示すように、支持基板4にエッチング等により貫通孔51a~51lを形成する。 In the method for manufacturing a wiring board according to the fifth modification of the embodiment of the present invention, after preparing the support substrate 4 as shown in FIG. 5, the support substrate 4 is penetrated by etching or the like as shown in FIG. Holes 51a to 51l are formed.
 図20に示すように、予め作製された金(Au)、銅(Cu)又はアルミニウム(Al)等からなる金属線61~66を曲げて貫通孔51a~51lに挿入し、固定した後、図21に示すように支持基板4の上面に金属線61~66の一部を露出するように絶縁層1を形成する。 As shown in FIG. 20, the metal wires 61 to 66 made of gold (Au), copper (Cu), aluminum (Al) or the like prepared in advance are bent and inserted into the through holes 51a to 51l and fixed. As shown in FIG. 21, the insulating layer 1 is formed on the upper surface of the support substrate 4 so as to expose part of the metal wires 61 to 66.
 その後、研磨等により、金属線61~66の一部を絶縁層1の上面の高さまで除去する。或いは、金属線61~66の全体を覆うように絶縁層1を形成した後、金属線61~66の一部及び絶縁層1の一部の双方を除去しても良い。その後、支持基板4を除去するとともに、研磨等により絶縁層1の下面から突出している金属線61~66の一部を除去する。 Thereafter, a part of the metal wires 61 to 66 is removed to the height of the upper surface of the insulating layer 1 by polishing or the like. Alternatively, after the insulating layer 1 is formed so as to cover the entire metal lines 61 to 66, a part of the metal lines 61 to 66 and a part of the insulating layer 1 may be removed. Thereafter, the support substrate 4 is removed, and part of the metal wires 61 to 66 protruding from the lower surface of the insulating layer 1 is removed by polishing or the like.
 本発明の実施の形態の第5の変形例に係る配線板の製造方法によれば、ワイヤボンディングの代わりに、予め作製した金属線61~66を用いた場合でも容易に配線板を製造可能となる。 According to the method for manufacturing a wiring board according to the fifth modification of the embodiment of the present invention, it is possible to easily manufacture a wiring board even when using metal wires 61 to 66 prepared in advance instead of wire bonding. Become.
(その他の実施の形態)
 上記のように、本発明は実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
 既に述べた実施の形態の説明においては、超音波熱圧着方式のワイヤボンディングを説明したが、熱圧着方式又は超音波方式等のワイヤボンディングを使用しても良い。超音波方式では、例えばアルミニウム線を用いて室温にて接合を行うことが可能である。 In the description of the embodiment described above, the ultrasonic thermocompression bonding wire bonding has been described, but wire bonding such as thermocompression bonding or ultrasonic bonding may be used. In the ultrasonic method, it is possible to perform bonding at room temperature using, for example, an aluminum wire.
 本発明の実施の形態に係る配線板としては、絶縁層1の厚さ方向に対して外周に向けて下端が広がるように斜めに延伸する貫通配線11b~16bを有するインターポーザを一例として説明したが、絶縁層1の厚さ方向に平行な貫通配線のみを有する配線板にも適用可能である。 As the wiring board according to the embodiment of the present invention, the interposer having the through wirings 11b to 16b extending obliquely so that the lower end extends toward the outer periphery with respect to the thickness direction of the insulating layer 1 has been described as an example. The present invention can also be applied to a wiring board having only through wirings parallel to the thickness direction of the insulating layer 1.
 また、絶縁層1の厚さ方向に平行に延伸する貫通配線11a~16aと、絶縁層1の厚さ方向に対して斜めに延伸する貫通配線11b~16bを説明したが、ボンディングワイヤのレイアウトを調整することにより、絶縁層1の厚さ方向に対して斜めに延伸する貫通配線のみを有する配線板にも適用可能である。例えば、図22に示すように、貫通配線11b~16bと同様に、貫通配線11a~16aが絶縁層1の厚さ方向に対して斜めに延伸していても良い。図22に示した配線板は、図23に示すように、ボンディングワイヤ11~16の図22に示した貫通配線11a~16aとなる部分を予め斜めに形成することにより製造可能である。 In addition, the penetration wirings 11a to 16a extending in parallel with the thickness direction of the insulating layer 1 and the penetration wirings 11b to 16b extending obliquely with respect to the thickness direction of the insulating layer 1 have been described. By adjusting, it can be applied to a wiring board having only through wirings extending obliquely with respect to the thickness direction of the insulating layer 1. For example, as shown in FIG. 22, the through wirings 11a to 16a may extend obliquely with respect to the thickness direction of the insulating layer 1 like the through wirings 11b to 16b. As shown in FIG. 23, the wiring board shown in FIG. 22 can be manufactured by previously forming portions of the bonding wires 11 to 16 to be the through wirings 11a to 16a shown in FIG.
 このように、本発明はここでは記載していない様々な実施の形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な請求の範囲に係る発明特定事項によってのみ定められるものである。 Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

Claims (15)

  1.  絶縁層と、
     前記絶縁層の上面の高さと略一致する高さの端面を有する第1の端部及び前記絶縁層の下面の高さと略一致する高さの端面を有する第2の端部を有し、金属線からなる貫通配線
     とを備えることを特徴とする配線板。
    An insulating layer;
    A first end portion having an end surface having a height substantially matching the height of the upper surface of the insulating layer, and a second end portion having an end surface having a height substantially matching the height of the lower surface of the insulating layer; A wiring board comprising a through wiring made of a wire.
  2.  絶縁層と、
     前記絶縁層の上面の高さと略一致する高さの端面を有する第1の端部及び前記絶縁層の側面と略同一平面上にある端面を有する第2の端部を有し、金属線からなる貫通配線
     とを備えることを特徴とする配線板。
    An insulating layer;
    A first end portion having an end surface having a height substantially matching the height of the upper surface of the insulating layer, and a second end portion having an end surface substantially coplanar with the side surface of the insulating layer; A wiring board comprising: a through-wiring.
  3.  前記貫通配線が、前記絶縁層の厚さ方向に対して斜めに延伸することを特徴とする請求項1又は2に記載の配線板。 The wiring board according to claim 1, wherein the through wiring extends obliquely with respect to the thickness direction of the insulating layer.
  4.  前記貫通配線の前記第2の端部が、互いに等間隔に配置されていることを特徴とする請求項1に記載の配線板。 The wiring board according to claim 1, wherein the second end portions of the through wiring are arranged at equal intervals.
  5.  前記第1の端部に接続された第1のパッド、及び前記第2の端部に接続された第2のパッドの少なくとも一方を更に備えることを特徴とする請求項1~4のいずれか1項に記載の配線板。 5. The apparatus according to claim 1, further comprising at least one of a first pad connected to the first end and a second pad connected to the second end. Wiring board according to item.
  6.  前記貫通配線が、前記絶縁層の厚さ方向に平行に延伸することを特徴とする請求項1又は4に記載の配線板。 The wiring board according to claim 1 or 4, wherein the through wiring extends in parallel with a thickness direction of the insulating layer.
  7.  前記金属線が、スタッドバンプであることを特徴とする請求項1~6のいずれか1項に記載の配線板。 The wiring board according to any one of claims 1 to 6, wherein the metal wire is a stud bump.
  8.  前記貫通配線が、前記第1の端部から分岐して前記第2の端部とは異なる方向に延伸し、前記絶縁層の下面の高さと略一致する高さの端面を有する第3の端部を更に有することを特徴とする請求項1又は2に記載の配線板。 A third end having an end surface branched from the first end and extending in a direction different from the second end, and having a height substantially matching the height of the lower surface of the insulating layer; The wiring board according to claim 1, further comprising a portion.
  9.  支持基板の上面に、前記支持基板と両端が接するように曲線状の金属線を形成する工程と、
     前記金属線の少なくとも一部を覆うように、前記支持基板の上面に絶縁層を形成する工程と、
     前記金属線の一部を除去することにより前記金属線を分断し、前記絶縁層の上面の高さと略一致する高さの端面を有する第1の端部と、前記支持基板の上面に接する第2の端部とをそれぞれ有する一対の貫通配線を形成する工程と、
     前記支持基板を除去する工程
     とを含むことを特徴とする配線板の製造方法。
    Forming a curved metal line on the upper surface of the support substrate so that both ends of the support substrate are in contact with each other;
    Forming an insulating layer on the upper surface of the support substrate so as to cover at least a part of the metal wire;
    The metal line is divided by removing a part of the metal line, and a first end portion having an end surface having a height substantially coincident with the height of the upper surface of the insulating layer, and a first surface in contact with the upper surface of the support substrate. Forming a pair of through wires each having two end portions;
    And a step of removing the support substrate.
  10.  前記貫通配線を形成する工程は、前記絶縁層の厚さ方向に対して斜めに延伸するように前記貫通配線を形成することを特徴とする請求項9に記載の配線板の製造方法。 10. The method of manufacturing a wiring board according to claim 9, wherein in the step of forming the through wiring, the through wiring is formed so as to extend obliquely with respect to a thickness direction of the insulating layer.
  11.  前記貫通配線を形成する工程は、前記貫通配線の前記第2の端部が、互いに等間隔となるように前記貫通配線を形成することを特徴とする請求項9又は10に記載の配線板の製造方法。 11. The wiring board according to claim 9, wherein in the step of forming the through wiring, the through wiring is formed so that the second end portions of the through wiring are equally spaced from each other. Production method.
  12.  前記支持基板を除去する工程の後に、前記絶縁層の一部及び貫通配線の一部を除去し、前記第2の端部を前記絶縁層の側面から露出させる工程を更に含むことを特徴とする請求項9~11のいずれか1項に記載の配線板の製造方法。 After the step of removing the support substrate, the method further includes a step of removing a part of the insulating layer and a part of the through wiring and exposing the second end portion from a side surface of the insulating layer. The method for manufacturing a wiring board according to any one of claims 9 to 11.
  13.  支持基板の上面に、前記支持基板と両端が接するように曲線状の金属線を形成する工程と、
     前記金属線の少なくとも一部を覆うように、前記支持基板の上面に絶縁層を形成する工程と、
     前記金属線の一部を除去することにより前記金属線の最上部を露出させ、前記露出した最上部を第1の端部とし、前記両端を第2及び第3の端部とする貫通配線を形成する工程と、
     前記支持基板を除去する工程
     とを含むことを特徴とする配線板の製造方法。
    Forming a curved metal line on the upper surface of the support substrate so that both ends of the support substrate are in contact with each other;
    Forming an insulating layer on the upper surface of the support substrate so as to cover at least a part of the metal wire;
    By removing a part of the metal line, the uppermost part of the metal line is exposed, the exposed uppermost part is used as a first end part, and the both ends are second and third end parts. Forming, and
    And a step of removing the support substrate.
  14.  支持基板の上面に、前記支持基板の上面と接する第1の端部を有し、前記支持基板の上面と異なる方向に延伸する金属線を形成する工程と、
     前記金属線の少なくとも一部を覆うように、前記支持基板の上面に絶縁層を形成する工程と、
     前記金属線の一部を除去することにより、前記絶縁層の上面の高さと略一致する高さの端面を有する第2の端部を有する貫通配線を形成する工程と、
     前記支持基板を除去する工程
     とを含むことを特徴とする配線板の製造方法。
    Forming a metal wire having a first end in contact with the upper surface of the support substrate on the upper surface of the support substrate and extending in a direction different from the upper surface of the support substrate;
    Forming an insulating layer on the upper surface of the support substrate so as to cover at least a part of the metal wire;
    Forming a through-wiring having a second end portion having an end surface having a height substantially matching the height of the upper surface of the insulating layer by removing a part of the metal wire;
    And a step of removing the support substrate.
  15.  前記金属線を形成する工程は、スタッドバンプ法によりスタッドバンプを形成することを特徴とする請求項14に記載の配線板の製造方法。 15. The method of manufacturing a wiring board according to claim 14, wherein the step of forming the metal wire forms a stud bump by a stud bump method.
PCT/JP2011/076489 2010-11-17 2011-11-17 Wiring board and method for producing same WO2012067177A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012544292A JPWO2012067177A1 (en) 2010-11-17 2011-11-17 Wiring board and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-256427 2010-11-17
JP2010256427 2010-11-17

Publications (1)

Publication Number Publication Date
WO2012067177A1 true WO2012067177A1 (en) 2012-05-24

Family

ID=46084098

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/076489 WO2012067177A1 (en) 2010-11-17 2011-11-17 Wiring board and method for producing same

Country Status (3)

Country Link
JP (1) JPWO2012067177A1 (en)
TW (1) TW201244560A (en)
WO (1) WO2012067177A1 (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129363A (en) * 2010-12-15 2012-07-05 Fujitsu Ltd Substrate with built-in electronic component and method of manufacturing the same
WO2013123435A1 (en) * 2012-02-17 2013-08-22 Invensas Corporation Heat spreading substrate with embedded interconnects
KR20150075385A (en) * 2013-12-25 2015-07-03 니치아 카가쿠 고교 가부시키가이샤 Light emitting device
WO2015184153A1 (en) * 2014-05-29 2015-12-03 Invensas Corporation Low cte component with wire bond interconnects
EP2880683A4 (en) * 2012-08-03 2016-03-30 Invensas Corp Bva interposer
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
JP2018503984A (en) * 2015-05-27 2018-02-08 深▲セン▼市華星光電技術有限公司 Light emitting device assembly structure
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
JP2019012864A (en) * 2013-12-25 2019-01-24 日亜化学工業株式会社 Light-emitting device
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI775430B (en) * 2021-05-11 2022-08-21 日商新川股份有限公司 Manufacturing method of semiconductor device and wire bonding apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002314244A (en) * 2001-04-11 2002-10-25 Ngk Insulators Ltd Core board, its manufacturing method, method for manufacturing multilayer core board using the same, and method for manufacturing multilayer laminated board
JP2007096246A (en) * 2005-08-30 2007-04-12 Kyocera Corp Wiring substrate and electronic device using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101215A (en) * 1998-05-06 2000-04-07 Ngk Insulators Ltd Producing method for board material for printed circuit
JP2001230546A (en) * 2000-02-15 2001-08-24 Ngk Insulators Ltd Method for manufacturing printed circuit board material
JP4646417B2 (en) * 2001-02-21 2011-03-09 京セラ株式会社 Ceramic circuit board
JP2006303360A (en) * 2005-04-25 2006-11-02 Fujikura Ltd Through-wire board, composite board, and electronic apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002314244A (en) * 2001-04-11 2002-10-25 Ngk Insulators Ltd Core board, its manufacturing method, method for manufacturing multilayer core board using the same, and method for manufacturing multilayer laminated board
JP2007096246A (en) * 2005-08-30 2007-04-12 Kyocera Corp Wiring substrate and electronic device using the same

Cited By (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
JP2012129363A (en) * 2010-12-15 2012-07-05 Fujitsu Ltd Substrate with built-in electronic component and method of manufacturing the same
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
WO2013123435A1 (en) * 2012-02-17 2013-08-22 Invensas Corporation Heat spreading substrate with embedded interconnects
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
EP2880683A4 (en) * 2012-08-03 2016-03-30 Invensas Corp Bva interposer
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
KR20150075385A (en) * 2013-12-25 2015-07-03 니치아 카가쿠 고교 가부시키가이샤 Light emitting device
JP2015144263A (en) * 2013-12-25 2015-08-06 日亜化学工業株式会社 light-emitting device
KR102267394B1 (en) 2013-12-25 2021-06-21 니치아 카가쿠 고교 가부시키가이샤 Light emitting device
US10297737B2 (en) 2013-12-25 2019-05-21 Nichia Corporation Method of manufacturing light emitting device with exposed wire end portions
JP2019012864A (en) * 2013-12-25 2019-01-24 日亜化学工業株式会社 Light-emitting device
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
WO2015184153A1 (en) * 2014-05-29 2015-12-03 Invensas Corporation Low cte component with wire bond interconnects
US10475726B2 (en) 2014-05-29 2019-11-12 Invensas Corporation Low CTE component with wire bond interconnects
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
JP2018503984A (en) * 2015-05-27 2018-02-08 深▲セン▼市華星光電技術有限公司 Light emitting device assembly structure
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Also Published As

Publication number Publication date
JPWO2012067177A1 (en) 2014-05-12
TW201244560A (en) 2012-11-01

Similar Documents

Publication Publication Date Title
WO2012067177A1 (en) Wiring board and method for producing same
US10297582B2 (en) BVA interposer
JP5193898B2 (en) Semiconductor device and electronic device
EP2172089B1 (en) Method for manufacturing a multilayer wiring element having pin interface
JP5330065B2 (en) Electronic device and manufacturing method thereof
JP5500870B2 (en) Substrate with connection terminal and socket for electronic parts
JP4198566B2 (en) Manufacturing method of electronic component built-in substrate
JP2015517745A (en) Substrate-less stackable packages using wirebond interconnects
JP2004343030A (en) Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board
JPWO2007032213A1 (en) Printed wiring board and semiconductor package
JP2000164618A (en) Metal foil with bumps, circuit board and semiconductor device using the same
JP6027905B2 (en) Semiconductor device
JP5406572B2 (en) Electronic component built-in wiring board and manufacturing method thereof
JP2009252942A (en) Component built-in wiring board, and method of manufacturing component built-in wiring board
EP1041618A1 (en) Semiconductor device and manufacturing method thereof, circuit board and electronic equipment
US9585246B2 (en) Electronic device
WO2013061500A1 (en) Flexible wiring board and method for manufacturing same
JP4417974B2 (en) Manufacturing method of stacked semiconductor device
JP3851585B2 (en) Connection method of bare chip semiconductor element to printed wiring board
JP3785661B2 (en) Method for manufacturing double-sided wiring board and method for manufacturing semiconductor device
JP5275123B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2012227320A (en) Semiconductor device
JP4342577B2 (en) Semiconductor chip mounting structure
JPH11354582A (en) Mounting structure for semiconductor chip
JP4619104B2 (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11841121

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2012544292

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11841121

Country of ref document: EP

Kind code of ref document: A1