WO2012061199A3 - No flow underfill - Google Patents

No flow underfill Download PDF

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Publication number
WO2012061199A3
WO2012061199A3 PCT/US2011/058080 US2011058080W WO2012061199A3 WO 2012061199 A3 WO2012061199 A3 WO 2012061199A3 US 2011058080 W US2011058080 W US 2011058080W WO 2012061199 A3 WO2012061199 A3 WO 2012061199A3
Authority
WO
WIPO (PCT)
Prior art keywords
conductive elements
posts
conductive
microelectronic
dielectric element
Prior art date
Application number
PCT/US2011/058080
Other languages
French (fr)
Other versions
WO2012061199A2 (en
Inventor
Belgacem Haba
Ilyas Mohammed
Ellis Chau
Sang Ii Lee
Kishor Desai
Original Assignee
Tessera, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera, Inc. filed Critical Tessera, Inc.
Priority to KR1020137014121A priority Critical patent/KR20130140759A/en
Priority to CN201180063433.6A priority patent/CN103283007B/en
Priority to KR1020187015041A priority patent/KR101967322B1/en
Priority to JP2013537704A priority patent/JP5649739B2/en
Publication of WO2012061199A2 publication Critical patent/WO2012061199A2/en
Publication of WO2012061199A3 publication Critical patent/WO2012061199A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
PCT/US2011/058080 2010-11-02 2011-10-27 No flow underfill WO2012061199A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020137014121A KR20130140759A (en) 2010-11-02 2011-10-27 No flow underfill
CN201180063433.6A CN103283007B (en) 2010-11-02 2011-10-27 Not flow underfill glue
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JP2013541858A (en) 2013-11-14
JP5649739B2 (en) 2015-01-07
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US20120104595A1 (en) 2012-05-03
US9196581B2 (en) 2015-11-24
TWI564972B (en) 2017-01-01
US20140217584A1 (en) 2014-08-07
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KR20180061419A (en) 2018-06-07
CN103283007B (en) 2016-02-03

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