WO2011163407A3 - Region based technique for accurately predicting memory accesses - Google Patents

Region based technique for accurately predicting memory accesses Download PDF

Info

Publication number
WO2011163407A3
WO2011163407A3 PCT/US2011/041511 US2011041511W WO2011163407A3 WO 2011163407 A3 WO2011163407 A3 WO 2011163407A3 US 2011041511 W US2011041511 W US 2011041511W WO 2011163407 A3 WO2011163407 A3 WO 2011163407A3
Authority
WO
WIPO (PCT)
Prior art keywords
region based
ptb
memory accesses
based technique
accurately predicting
Prior art date
Application number
PCT/US2011/041511
Other languages
French (fr)
Other versions
WO2011163407A2 (en
Inventor
Livio Soares
Naveen Cherukuri
Akhilesh Kumar
Mani Azimi
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201180041024.6A priority Critical patent/CN103038748B/en
Priority to JP2013516745A priority patent/JP5697279B2/en
Priority to KR1020127034132A priority patent/KR101485651B1/en
Priority to EP11798876.6A priority patent/EP2585916B1/en
Publication of WO2011163407A2 publication Critical patent/WO2011163407A2/en
Publication of WO2011163407A3 publication Critical patent/WO2011163407A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching

Abstract

In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
PCT/US2011/041511 2010-06-23 2011-06-22 Region based technique for accurately predicting memory accesses WO2011163407A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201180041024.6A CN103038748B (en) 2010-06-23 2011-06-22 The technology based on region for accurate predicting access of storage
JP2013516745A JP5697279B2 (en) 2010-06-23 2011-06-22 Area-based technology to accurately predict memory access
KR1020127034132A KR101485651B1 (en) 2010-06-23 2011-06-22 Region based technique for accurately predicting memory accesses
EP11798876.6A EP2585916B1 (en) 2010-06-23 2011-06-22 Region based technique for accurately predicting memory accesses

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/821,935 US9418011B2 (en) 2010-06-23 2010-06-23 Region based technique for accurately predicting memory accesses
US12/821,935 2010-06-23

Publications (2)

Publication Number Publication Date
WO2011163407A2 WO2011163407A2 (en) 2011-12-29
WO2011163407A3 true WO2011163407A3 (en) 2012-04-12

Family

ID=45353674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/041511 WO2011163407A2 (en) 2010-06-23 2011-06-22 Region based technique for accurately predicting memory accesses

Country Status (7)

Country Link
US (1) US9418011B2 (en)
EP (1) EP2585916B1 (en)
JP (1) JP5697279B2 (en)
KR (1) KR101485651B1 (en)
CN (2) CN106294212B (en)
TW (2) TWI603264B (en)
WO (1) WO2011163407A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104995597A (en) * 2013-03-13 2015-10-21 英特尔公司 Techniques for enabling bit-parallel wide string matching with a SIMD register

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418011B2 (en) 2010-06-23 2016-08-16 Intel Corporation Region based technique for accurately predicting memory accesses
US8683136B2 (en) * 2010-12-22 2014-03-25 Intel Corporation Apparatus and method for improving data prefetching efficiency using history based prefetching
US9092341B2 (en) 2012-07-10 2015-07-28 International Business Machines Corporation Methods of cache preloading on a partition or a context switch
JP6088951B2 (en) * 2013-09-20 2017-03-01 株式会社東芝 Cache memory system and processor system
US9513805B2 (en) 2014-04-15 2016-12-06 International Business Machines Corporation Page table including data fetch width indicator
US9582282B2 (en) * 2014-07-17 2017-02-28 Arm Limited Prefetching using a prefetch lookup table identifying previously accessed cache lines
WO2016097809A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
US20160255169A1 (en) * 2015-02-27 2016-09-01 Futurewei Technologies, Inc. Method and system for smart object eviction for proxy cache
US9594678B1 (en) 2015-05-27 2017-03-14 Pure Storage, Inc. Preventing duplicate entries of identical data in a storage device
US10482010B2 (en) * 2017-06-29 2019-11-19 Intel Corporation Persistent host memory buffer
KR20200085522A (en) 2019-01-07 2020-07-15 에스케이하이닉스 주식회사 Main memory device having heterogeneous memories, computer system including the same and data management method thereof
CN110442382B (en) * 2019-07-31 2021-06-15 西安芯海微电子科技有限公司 Prefetch cache control method, device, chip and computer readable storage medium
KR20210108749A (en) * 2020-02-26 2021-09-03 삼성전자주식회사 Accelerator, method for operating the same and accelerator system including the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535966B1 (en) * 2000-05-17 2003-03-18 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
US6804769B1 (en) * 2000-02-18 2004-10-12 Hewlett-Packard Development Company, L.P. Unified buffer for tracking disparate long-latency operations in a microprocessor
US20080235458A1 (en) * 2005-11-30 2008-09-25 Red Hat, Inc. Method for tracking of non-resident pages
US20090182947A1 (en) * 2005-11-30 2009-07-16 Red Hat, Inc. Method of tuning a cache

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04259048A (en) 1991-02-14 1992-09-14 Fujitsu Ltd Pre-read data control system using statistic information
US5931945A (en) * 1994-04-29 1999-08-03 Sun Microsystems, Inc. Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits
US6055621A (en) * 1996-02-12 2000-04-25 International Business Machines Corporation Touch history table
US5752261A (en) * 1996-11-07 1998-05-12 Ncr Corporation Method and apparatus for detecting thrashing in a cache memory
US5960454A (en) * 1996-12-19 1999-09-28 International Business Machines Corporation Avoiding cache collisions between frequently accessed, pinned routines or data structures
US6317810B1 (en) * 1997-06-25 2001-11-13 Sun Microsystems, Inc. Microprocessor having a prefetch cache
US6047363A (en) * 1997-10-14 2000-04-04 Advanced Micro Devices, Inc. Prefetching data using profile of cache misses from earlier code executions
US5941981A (en) 1997-11-03 1999-08-24 Advanced Micro Devices, Inc. System for using a data history table to select among multiple data prefetch algorithms
US6490654B2 (en) * 1998-07-31 2002-12-03 Hewlett-Packard Company Method and apparatus for replacing cache lines in a cache memory
US6223309B1 (en) * 1998-10-02 2001-04-24 International Business Machines Corporation Method and apparatus for ECC logic test
JP3512678B2 (en) * 1999-05-27 2004-03-31 富士通株式会社 Cache memory control device and computer system
US6678795B1 (en) * 2000-08-15 2004-01-13 International Business Machines Corporation Method and apparatus for memory prefetching based on intra-page usage history
EP1182559B1 (en) * 2000-08-21 2009-01-21 Texas Instruments Incorporated Improved microprocessor
US6523093B1 (en) 2000-09-29 2003-02-18 Intel Corporation Prefetch buffer allocation and filtering system
US6640285B1 (en) * 2000-10-26 2003-10-28 Emc Corporation Method and apparatus for improving the efficiency of cache memories using stored activity measures
US6832296B2 (en) * 2002-04-09 2004-12-14 Ip-First, Llc Microprocessor with repeat prefetch instruction
US7020762B2 (en) * 2002-12-24 2006-03-28 Intel Corporation Method and apparatus for determining a dynamic random access memory page management implementation
US7194582B1 (en) * 2003-05-30 2007-03-20 Mips Technologies, Inc. Microprocessor with improved data stream prefetching
US7467131B1 (en) * 2003-09-30 2008-12-16 Google Inc. Method and system for query data caching and optimization in a search engine system
US7356651B2 (en) * 2004-01-30 2008-04-08 Piurata Technologies, Llc Data-aware cache state machine
US7975108B1 (en) * 2004-03-25 2011-07-05 Brian Holscher Request tracking data prefetcher apparatus
US7386679B2 (en) 2004-04-15 2008-06-10 International Business Machines Corporation System, method and storage medium for memory management
US7950012B2 (en) * 2005-03-16 2011-05-24 Oracle America, Inc. Facilitating communication and synchronization between main and scout threads
US7496730B2 (en) * 2005-04-15 2009-02-24 Microsoft Corporation System and method for reducing the number of translation buffer invalidates an operating system needs to issue
JP4160589B2 (en) 2005-10-31 2008-10-01 富士通株式会社 Arithmetic processing device, information processing device, and memory access method for arithmetic processing device
WO2007068122A1 (en) * 2005-12-16 2007-06-21 Univ Western Ontario System and method for cache management
GB0603552D0 (en) * 2006-02-22 2006-04-05 Advanced Risc Mach Ltd Cache management within a data processing apparatus
US7478197B2 (en) * 2006-07-18 2009-01-13 International Business Machines Corporation Adaptive mechanisms for supplying volatile data copies in multiprocessor systems
JP2008102745A (en) 2006-10-19 2008-05-01 Toshiba Corp Pre-fetching mechanism of instruction cache memory
US7797503B2 (en) * 2007-06-26 2010-09-14 International Business Machines Corporation Configurable memory system and method for providing atomic counting operations in a memory device
US8423715B2 (en) * 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US9569363B2 (en) * 2009-03-30 2017-02-14 Via Technologies, Inc. Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
US8161246B2 (en) * 2009-03-30 2012-04-17 Via Technologies, Inc. Prefetching of next physically sequential cache line after cache line that includes loaded page table entry
US8677049B2 (en) * 2009-04-13 2014-03-18 Advanced Micro Devices, Inc. Region prefetcher and methods thereof
US8332587B2 (en) * 2009-05-28 2012-12-11 International Business Machines Corporation Cache line use history based done bit modification to I-cache replacement scheme
US8291169B2 (en) * 2009-05-28 2012-10-16 International Business Machines Corporation Cache line use history based done bit modification to D-cache replacement scheme
CN101719105B (en) * 2009-12-31 2012-01-04 中国科学院计算技术研究所 Optimization method and optimization system for memory access in multi-core system
US9418011B2 (en) 2010-06-23 2016-08-16 Intel Corporation Region based technique for accurately predicting memory accesses

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804769B1 (en) * 2000-02-18 2004-10-12 Hewlett-Packard Development Company, L.P. Unified buffer for tracking disparate long-latency operations in a microprocessor
US6535966B1 (en) * 2000-05-17 2003-03-18 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
US20080235458A1 (en) * 2005-11-30 2008-09-25 Red Hat, Inc. Method for tracking of non-resident pages
US20090182947A1 (en) * 2005-11-30 2009-07-16 Red Hat, Inc. Method of tuning a cache

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2585916A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104995597A (en) * 2013-03-13 2015-10-21 英特尔公司 Techniques for enabling bit-parallel wide string matching with a SIMD register
CN104995597B (en) * 2013-03-13 2018-03-13 英特尔公司 The apparatus and method for performing String matching

Also Published As

Publication number Publication date
JP5697279B2 (en) 2015-04-08
EP2585916B1 (en) 2019-09-11
WO2011163407A2 (en) 2011-12-29
EP2585916A4 (en) 2014-03-19
EP2585916A2 (en) 2013-05-01
US9418011B2 (en) 2016-08-16
CN106294212A (en) 2017-01-04
JP2013529815A (en) 2013-07-22
TWI590156B (en) 2017-07-01
TWI603264B (en) 2017-10-21
US20110320762A1 (en) 2011-12-29
CN103038748A (en) 2013-04-10
KR20130040952A (en) 2013-04-24
KR101485651B1 (en) 2015-01-22
CN103038748B (en) 2016-10-05
CN106294212B (en) 2020-02-21
TW201224923A (en) 2012-06-16
TW201528136A (en) 2015-07-16

Similar Documents

Publication Publication Date Title
WO2011163407A3 (en) Region based technique for accurately predicting memory accesses
GB2511957A (en) Processor with kernel mode access to user space virtual addresses
WO2014001803A3 (en) Memory protection
IN2015DN02742A (en)
GB2518785A (en) Concurrent control for a page miss handler
GB2506073A (en) Store storage class memory information command
WO2015084493A3 (en) Data processing apparatus with memory rename table for mapping memory addresses to registers
WO2012096503A3 (en) Storage device for adaptively determining a processing technique with respect to a host request based on partition data and an operating method for the storage device
EP2660752A3 (en) Memory protection circuit, processing unit, and memory protection method
WO2013016345A3 (en) Method and apparatus for tlb shoot-down in a heterogeneous computing system supporting shared virtual memory
GB2484881A (en) Transactional memory system with efficient cache support
WO2012103367A3 (en) Guest to native block address mappings and management of native code storage
JP2010102719A5 (en)
WO2012094481A3 (en) Memory address translation
DE602009000463D1 (en) HT ADJUSTING LIST OF INDIRECT DATA ADDRESSES
BR112013028501A2 (en) hardware-based secure data processing apparatus and method using temporary storage memory address range rules
WO2013016567A3 (en) System and method for virtual partition monitoring
WO2011041047A3 (en) Home agent data and memory management
WO2012015766A3 (en) Cache memory that supports tagless addressing
WO2011123361A3 (en) Mapping rdma semantics to high speed storage
GB2520856A (en) Enabling Virtualization of a processor resource
BR112015019392A2 (en) memory latency management
GB2514500A (en) Hybrid Address Translation
WO2016105923A3 (en) Energy efficient wireless data transfer
WO2012116009A3 (en) Methods and apparatuses for addressing memory caches

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180041024.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11798876

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011798876

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2013516745

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 10625/CHENP/2012

Country of ref document: IN

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127034132

Country of ref document: KR

Kind code of ref document: A