WO2011112504A1 - Semiconductor devices with heterojunction barrier regions and methods of fabricating same - Google Patents

Semiconductor devices with heterojunction barrier regions and methods of fabricating same Download PDF

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Publication number
WO2011112504A1
WO2011112504A1 PCT/US2011/027383 US2011027383W WO2011112504A1 WO 2011112504 A1 WO2011112504 A1 WO 2011112504A1 US 2011027383 W US2011027383 W US 2011027383W WO 2011112504 A1 WO2011112504 A1 WO 2011112504A1
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Prior art keywords
region
drift region
heterojunction
contact
junction
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PCT/US2011/027383
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French (fr)
Inventor
Qingchun Zhang
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Cree, Inc.
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Priority to JP2012557150A priority Critical patent/JP5663045B2/en
Priority to EP11753868.6A priority patent/EP2545587B1/en
Publication of WO2011112504A1 publication Critical patent/WO2011112504A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to semiconductor devices and the fabrication of semiconductor devices and more particularly, to Junction Barrier Schottky (JBS) diodes, and the fabrication of such diodes.
  • JBS Junction Barrier Schottky
  • High voltage silicon carbide (SiC) Schottky diodes which may have voltage blocking ratings between, for example, about 600V and about 2.5 kV, are expected to compete with silicon PIN diodes having similar voltage ratings. Such diodes may handle as much as about 100 amps or more of forward current, depending on their active area design. High voltage Schottky diodes have a number of important applications, particularly in the field of power conditioning, distribution and control.
  • SiC Schottky diode An important characteristic of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices typically exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based Schottky devices are theoretically capable of much higher switching speeds, for example, in excess of about 100 times better than silicon. In addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.
  • a conventional SiC Schottky diode structure has an n-type SiC substrate on which an n- epitaxial layer, which functions as a drift region, is formed.
  • the device typically includes a Schottky contact formed directly on the n- layer.
  • a junction termination region such as a guard ring and/or p-type JTE (junction termination extension) region, is typically formed to surround the Schottky junction active region.
  • the purpose of junction termination region is to reduce or prevent electric field crowding at the edges of the Schottky junction, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device.
  • Other termination techniques include field plates and floating field rings that may be more strongly influenced by surface effects.
  • a channel stop region may also be formed by implantation of n-type dopants in order to prevent the depletion region from extending to the edge of the device.
  • JBS diodes are sometimes referred to as Merged PIN - Schottky (MPS) diodes.
  • a conventional JBS diode 10 is illustrated in Figure 1 , As shown therein, a conventional JBS diode includes an n-type substrate 12 on which an n- drift layer 14 is formed.
  • a plurality of p+ regions 16 are formed, typically by ion implantation, in the surface of the n- drift layer 14.
  • a metal anode contact 18 is formed on the surface of the n- drift layer 14 in contact with both the n- drift layer 14 and the p+ regions 16.
  • the anode contact 18 forms a Schottky junction with the exposed portions of the drift layer 14, and may form an ohmic contact with the p+ regions 16.
  • a cathode contact 20 is formed on the substrate 12.
  • Silicon carbide-based JBS diodes are described, for example, in U.S. Patent Nos. 6,104,043 and 6,524,900.
  • the junction J1 between the anode contact 18 and the drift layer 14 turns on before the junction J2 between the p+ regions 16 and the drift layer 14.
  • the device exhibits Schottky diode behavior. That is, current transport in the device is dominated by majority carriers (electrons) injected across the Schottky junction J1 at low forward voltages.
  • majority carriers electrons
  • JBS diodes have fast switching speeds characteristic of Schottky diodes.
  • the JBS diode 10 behaves like a PIN diode.
  • the voltage blocking ability of the device 10 is typically determined by the thickness and doping of the drift layer 14 and the design of the edge termination.
  • An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer.
  • the p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region and the p- type junction barrier region is electrically connected to the contact.
  • the Schottky junction between the contact and the drift region may be configured to turn on at a lower forward voltage than the P-N heterojunction between the junction barrier region and the drift region.
  • the contact may form an ohmic contact to the p-type polysilicon region, and the P-N heterojunction between the heterojunction barrier region and the drift region may be configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
  • the electronic device may further include a guard ring termination region at a surface of the silicon carbide layer laterally adjacent to the contact.
  • the guard ring termination region may include a second p-type polysilicon region on the drift region, the second p-type polysilicon region being electrically isolated from the contact under zero bias conditions.
  • the electronic device may further include a junction termination region at the surface of the silicon carbide layer having a conductivity type opposite the conductivity type of the drift region, the second p-type polysilicon region extends into the junction termination region.
  • the junction barrier region may include a plurality of p-type polysilicon regions in the drift region and at least one p-type polysilicon minority injector pad in the drift region beneath the contact and electrically connected to the contact.
  • the minority injector pad may have a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is larger than a surface area in the horizontal plane of one of the plurality of p- type polysilicon regions in the junction barrier region.
  • the minority carrier injector pad may have a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is at least about 10% of a surface area of the drift region in the horizontal plane below the contact.
  • the electronic device may further include an n+ silicon carbide contact layer on the drift region opposite the contact, and a second contact on the contact layer.
  • An electronic device includes a drift region having a first conductivity type, a contact forming a junction with the drift region, and a junction barrier region on the drift region, the junction barrier region having a second conductivity type opposite the first conductivity type and including a heterojunction barrier region on the drift region.
  • the heterojunction barrier region forms a P-N heterojunction with the drift region and is in electrical contact with the contact.
  • the Schottky junction between the contact and the drift region may be configured to turn on at a lower forward voltage than the P-N heterojunction between the heterojunction barrier region and the drift region.
  • the contact may form an ohmic contact to the heterojunction barrier region, and the P-N heterojunction between the heterojunction barrier region and the drift region may be configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
  • the electronic device may further include a guard ring termination region on the drift region and laterally adjacent to the Schottky junction.
  • the guard ring termination region may include a second
  • the heterojunction barrier region may include a plurality of p- type polysilicon regions on the drift region and at least one p-type polysilicon minority injector pad on the drift region beneath the contact and electrically connected to the contact.
  • the minority carrier injection pad may have a width that is greater than a width of the junction barrier region.
  • the minority injector pad may have a horizontal surface area that is larger than a horizontal surface area of one of the plurality of p-type polysilicon regions in the junction barrier region.
  • the drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type polysilicon.
  • the drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type gallium nitride.
  • Some embodiments include a termination region at a surface of the drift region and defining an active region of the device within the termination region, wherein a ratio of a surface area of the active region occupied by the heterojunction barrier regions to a total surface area of the active region is about 2% to about 40%. In some embodiments, the ratio is about 4% to about 30%. In some other embodiments, the ratio is about 10% to about 30%, and in further embodiments the ratio is about 20% to about 30%.
  • Methods of forming an electronic device include providing a drift region having a first conductivity type, providing a heterojunction barrier region on the drift region, the heterojunction barrier region including a material different from the drift region and having a conductivity type opposite the conductivity type of the drift region and providing a P-N heterojunction with the drift region, and forming a contact on the drift region and on the heterojunction barrier region, the contact forming a Schottky junction with the drift region and forming an ohmic junction with the heterojunction barrier region.
  • the drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type polysilicon.
  • the methods may further include providing a guard ring termination region on the drift region laterally adjacent to the Schottky junction, the guard ring termination region may include a second
  • heterojunction barrier region on the drift region is a heterojunction barrier region on the drift region.
  • Providing the heterojunction barrier region may include etching a recess in the drift region, depositing a polysilicon layer in the recess, doping the polysilicon layer to have a conductivity type opposite the conductivity type of the drift region, and patterning the polysilicon layer.
  • An electronic device includes a silicon carbide layer including a drift region having a first conductivity type, a contact on a surface of the drift region and forming a Schottky junction with the drift region, and a guard ring in contact with the surface of the silicon carbide layer adjacent to the Schottky junction.
  • the guard ring has a conductivity type opposite the conductivity type of the drift region and includes a material that forms a heterojunction with the silicon carbide layer.
  • the guard ring may include polysilicon and/or gallium nitride.
  • Figure 1 is a cross-sectional view of a conventional JBS diode.
  • Figure 2 is a top view of a JBS diode according to some embodiments of the present invention.
  • Figure 3, 4 and 5 are cross-sectional views of JBS diodes according to some embodiments of the present invention.
  • Figure 6 is a cross-sectional detail of portions of a JBS diode according to some embodiments of the invention.
  • Figure 7 is a graph that schematically illustrates various regions in a current-voltage characteristic of a JBS diode according to some embodiments of the invention.
  • Figure 8 is a graph illustrating simulated forward current-voltage curves at operating temperatures ranging from 25 °C to 200 °C for a device according to some embodiments.
  • Figures 9-12 are cross-sectional views illustrating the formation of JBS diodes according to some embodiments of the present invention.
  • Figures 13A and 13B are cross-sectional views of JBS diodes according to some embodiments of the present invention.
  • Figure 14 is a graph illustrating simulated horizontal electric field distributions for a device according to some embodiments.
  • Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention.
  • the thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.
  • embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
  • an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • n-type material has a majority equilibrium concentration of negatively charged electrons
  • p-type material has a majority equilibrium concentration of positively charged holes.
  • Some material may be designated with a "+" or "-" (as in ⁇ +, ⁇ -, ⁇ +, p-, n++, n ⁇ , p++, p-, or the like), to indicate a relatively larger ("+") or smaller (“- ”) concentration of majority carriers compared to another layer or region.
  • a junction barrier Schottky diode includes features, such as junction barrier regions and/or edge termination features, on or in a drift layer, wherein the junction barrier regions and/or edge termination features are provided by regions of a different material type than the drift layer, and form respective heterojunctions with the drift layer.
  • the features, such as junction barrier regions and/or edge termination features may include doped polysilicon, which can be formed, for example, using conventional processes that may not require ion implantation.
  • Figure 2 is a top view of a diode 100 according to some embodiments of the invention
  • Figure 3 is a partial cross-sectional view of the diode 100 taken along line A-A of Figure 2.
  • Figures 4 and 5 are similar cross sectional illustrations of diodes 100' and 100", respectively, according to other embodiments. The dimensions of some features of the diodes 100, 100', 100" are exaggerated for clarity.
  • the diode 100 includes an optional substrate 1 12 on which a layer 1 13 including a drift region 1 14 is formed.
  • the layer 1 13 has an upper surface, opposite the substrate, in which a plurality of heterojunction barrier regions 130 are formed.
  • a Schottky contact 118 is on the drift region 1 14 .
  • the Schottky contact 1 18 contacts the surface of the drift region 1 14 and forms a Schottky junction with the drift region 1 14.
  • the Schottky contact 1 18 also contacts the plurality of heterojunction barrier regions 130.
  • the layer 1 13 may be formed, for example, from n-type silicon carbide of the 2H, 4H, 6H, 3C and/or 15R polytype.
  • the drift region 1 14 may have a dopant concentration of about 2 x 10 14 to about 1 x 10 17 cm "3 , depending on design requirements for voltage blocking and on-resistance for the diode 100.
  • Other types of semiconductor materials such as GaN, GaAs, silicon or germanium may be used.
  • the drift region 1 14 includes 4H-SiC doped with n-type dopants at a concentration of about 5 x 10 5 cm "3 .
  • the heterojunction barrier regions 130 are formed from a semiconducting material that is different from the material of the drift region 1 14.
  • the heterojunction barrier regions 130 have a conductivity type that is opposite the conductivity type of the drift region 1 14. Accordingly, the heterojunction barrier regions 130 form P-N heterojunctions with the drift region 1 14. Furthermore, the Schottky contact 1 18 may form an ohmic junction with the heterojunction barrier regions 130.
  • the barrier height of the P-N is the barrier height of the P-N
  • heterojunction J3 between the heterojunction barrier regions 130 and the drift layer may be higher than a barrier height of a Schottky junction J4 between a Schottky contact 1 18 and the drift region 1 14, so that the P-N heterojunction will turn on at a higher forward voltage than the Schottky junction J4 between the drift region 1 4 and the Schottky contact 1 18, as will be discussed in more detail below.
  • the heterojunction barrier regions 130 are formed as stripe-shaped regions in the drift region 1 14.
  • the heterojunction barrier regions 130 may be formed in other shapes, such as islands, squares, dots, hexagons, or any other desired shape.
  • the heterojunction barrier regions 130 may be provided as regions of doped polysilicon.
  • the heterojunction barrier regions 130 may include polysilicon regions doped to have a conductivity that is opposite the conductivity type of the drift region 1 14, so that the heterojunction barrier regions 130 form P-N heterojunctions J3 with the drift region 1 14.
  • the heterojunction barrier regions 130 may be doped with p- type dopants, such as boron and/or aluminum, at a concentration of about 1 x 10 17 to about 1 x 10 20 cm “3 , and may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14 from the surface of the drift region 1 14.
  • the heterojunction barrier regions 130 may be doped at a dopant concentration of about 5 x 10 18 cm "3 , and may extend to a depth of about 0.3 pm into the drift region 1 14 from the surface of the drift region 1 14.
  • One or more current surge pads 116 may also be provided in the drift region 1 14.
  • the current surge pads 1 16 may be formed of the same material as the heterojunction barrier regions 130.
  • the current surge pads 1 16 may be provided as polysilicon regions doped with p-type dopants, such as boron and/or aluminum, at a concentration of about 1 x 10 18 to about 1 x 10 20 cm “3 , and may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14.
  • the current surge pads 1 16 may be doped at a dopant concentration of about 5 x 10 18 cm "3 , and may extend to a depth of about 0.3 pm into the drift region 1 14.
  • the current surge pads 1 16 have a larger width than the heterojunction barrier regions 130 to encourage the flow of surge current through the current surge pads at high forward voltages, as will be discussed in more detail below.
  • the current surge pads 1 16 may have a width of about 10 pm to about 250 pm. In particular embodiments, the current surge pads 1 16 may have a width of about 20 pm.
  • the current surge pads 1 16 and/or heterojunction barrier regions 130 may be formed of other types of materials that can be doped to have a conductivity that is opposite the conductivity of the drift region 1 14 and can form a heterojunction with the drift region 114.
  • the drift region comprises n-type silicon carbide
  • a material such as p-type gallium nitride can be used to form the current surge pads 1 16 and/or heterojunction barrier regions 130.
  • FIGS. 2 and 3 are provided as spaced apart striped regions that expose portions 1 14A of the surface of the drift region 1 14 and that extend across an active region 1 10 of the drift region 1 14 (except for the exposed portions 1 14A of the drift layer and the current surge pads 1 16).
  • a metal Schottky contact 1 18 covers the drift region 1 14 and forms Schottky rectifying junctions with the exposed portions 1 14A of the drift region 1 14 as well as the heterojunction barrier regions 130 and the current surge pads 1 16.
  • the term "active region” ijefers to the two dimensional area of the device in which the Schottky metal contacts the drift layer, and includes the exposed portions 1 14A of the drift region 1 14, the heterojunction barrier 130 and the current surge pads 1 16. Accordingly, the active region includes the Schottky junction area but does not include, for example, the edge termination region described below.
  • the diode 100 may include an edge termination region 1 15 surrounding the active region 1 10 of the diode 100.
  • the edge termination region 1 15 may include a junction termination extension (JTE) region, field rings, field plates, guard rings, and/or a combination of the foregoing or other terminations.
  • the device 100 may include a plurality of guard rings 125, which may be formed of the same material as the heterojunction barrier regions 130 and the current surge pad 16 and may also be doped to have a conductivity opposite the conductivity type of the drift region 1 4.
  • a passivation layer, such as a field oxide layer 127, may be formed on the drift layer and may cover the guard rings 125.
  • the guard rings 125 may be floating guard rings that are electrically isolated from the anode contact 1 18 under zero bias conditions.
  • the edge termination region 1 15 includes a robust guard ring (RGR) termination as described in U.S. Patent No.
  • the RGR termination may include an implanted region 160 of dopants having a conductivity opposite the conductivity of the drift layer.
  • the implanted region 160 may extend to a depth in the drift region 14 that is greater or less than the depth of the guard rings 125.
  • the implanted region 160 may have a net concentration of dopants having a conductivity opposite the conductivity type of the drift region 1 14 of about 1x10 17 cm "3 .
  • the current surge pads 1 16 and the heterojunction barrier regions 130 may be formed within recesses in the drift region 1 14, and may protrude above an upper surface of the drift region 1 14. As the current surge pads 1 16 and the heterojunction barrier regions 130 have an opposite conductivity type from the drift region 1 14, the heterojunction barrier regions 30 form P-N junctions J3 with the drift region 14, while the current surge pads 1 16 form P-N junctions J5 with the drift region 1 14.
  • the current surge pads 1 16', the heterojunction barrier regions 130' and the guard rings 125' are formed within recesses in the drift region 1 14, and are flush with the upper surface of the drift region 1 14.
  • polysilicon may be deposited into the recesses in the drift region 1 14 and planarized using a chemical- mechanical polish (CMP) or etch back technique to form the current surge pads 1 16', the heterojunction barrier regions 130', and/or the guard rings 125', as shown in Figure 4.
  • CMP chemical- mechanical polish
  • the current surge pads 1 6", the heterojunction barrier regions 130" and the guard rings 125" are formed as discrete regions on the upper surface of the drift region 1 14, and do not extend into the drift region 1 14.
  • polysilicon may be deposited onto the drift region 1 14 and patterned using photolithography to form the current surge pads 1 16", the heterojunction barrier regions 130", and/or the guard rings 125", as shown in Figure 5.
  • the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may affect both the reverse leakage current of the device 100 and the forward voltage drop of the device 100. For example, if the area occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 is increased relative to the total area of the active region 1 10, the reverse leakage current may be reduced, but the forward voltage drop of the device 100 may increase.
  • the selection of the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may entail a trade-off between reverse leakage current and forward voltage drop.
  • the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may be between about 2% and 40%.
  • the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may be between about 4% and 30%.
  • the ratio may be about 10% to about 30%, and in still further embodiments, the ratio may be about 20% to about 30%.
  • the Schottky contact 118 on the surface of the drift region 1 14 forms a Schottky junction J4 with the exposed portions 1 14A of the drift region 1 14 between adjacent heterojunction barrier regions 130.
  • the anode contact 1 18 may include a metal, such as aluminum, titanium and/or nickel. In some embodiments, the anode contact 1 18 may form an ohmic contact with the current surge pad 1 16.
  • a metal overlayer 1 19 may be formed on the Schottky contact 1 18.
  • the metal overlayer 1 19 may comprise TiW/AI, for example, and may be provided as a contact layer on the Schottky contact 1 18.
  • a cathode contact 120 is formed on a side of the substrate 1 12 opposite the drift region 1 14 and/or directly on the drift region 1 14.
  • the cathode contact 120 may include a metal, such as nickel, that is capable of forming an ohmic contact to n-type silicon carbide.
  • the depletion regions formed by the p-n junctions J3 between the heterojunction barrier regions 130 and the drift region 1 14, as well as the depletion region of the p-n junction J5, may expand to block reverse current through the device 100, protecting the
  • the diode 100 may function substantially like a PIN diode.
  • the Schottky junction J4 between the anode contact 1 18 and the exposed portions 14A of the drift region 14 turns on before the heterojunction J3 and the junction J5 between the current surge pad 1 16 and the drift region 1 14.
  • the device exhibits Schottky diode behavior, and the operation of the diode 100 will be dominated by the injection of majority carriers across the Schottky junctions J3 and J4. Due to the absence of minority carrier injection under normal operating conditions, the diode 100 may have a very fast switching capability, which is characteristic of Schottky diodes in general.
  • the current surge pad 1 16 may be designed to begin to conduct at a forward voltage that is higher than the turn-on voltage of the Schottky junction J3.
  • the p-n junction J5 will begin to conduct.
  • the operation of the diode 100 is dominated by the injection and recombination of minority carriers across the p-n junction J5.
  • the forward voltage drop of the diode 100 may be clamped, which may decrease the amount of power dissipated by the diode 100 for a given level of current.
  • turn-on of the p-n junction J5 when the forward voltage of the diode 100 increases may reduce and/or prevent forward current runaway in the diode 100.
  • the turn-on of the p-n junctions J3 and J5 may occur in stages.
  • the Schottky junction J4 between the drift region 1 14 and the Schottky contact 1 18 may turn on, resulting in majority carrier conduction.
  • majority carriers may be injected across the P-N heterojunction J3, allowing for further reduction in on- resistance.
  • the turn on of junction J5 may occur in stages, resulting in minority carrier injection allowing for surge current capability.
  • FIG. 6 is a magnified illustration of a portion of a drift region 1 14 include a current surge pad 1 16 and two heterojunction barrier regions 130. Forward current components 40, 41 and 42 are illustrated in Figure 6.
  • Figure 7 is a schematic graph of current density (J) versus forward voltage (V) for a Schottky diode according to some embodiments. As shown in Figure 7, the current-voltage characteristic of a Schottky diode according to some embodiments may have three distinct regions of operation, shown in Figure 7 as Region 1 , Region 2 and Region 3.
  • Region 1 in the graph of Figure 7, where the forward voltage of the device is between V1 and V2.
  • V1 represents the turn-on voltage of the Schottky junction J4
  • V2 represents the turn-on voltage of the heterojunction J3 between the heterojunction barrier region 130 and the drift region 1 14.
  • the turn-on voltage of the Schottky junction J4 may be about 0.8 V when the Schottky contact 1 18 is titanium and the drift region 114 is n-type silicon carbide, while the turn-on voltage of the junction J3 between the heterojunction barrier region 130 and the drift region 1 14 may be about 1.5 V.
  • the Schottky current 40 spreads laterally beneath the current surge pad 1 16 and the heterojunction barrier regions 130, resulting in spreading resistance in the device.
  • the current-voltage curve shown in Figure 7 may have a relatively low slope in Region 1 .
  • the heterojunction J3 between the heterojunction barrier region 130 and the drift region 1 14 and the heterojunction J5 between the current surge pad 1 16 and the drift region 1 14 may turn on, resulting in unipolar injection of electrons 41 into the drift region.
  • the device may still exhibit some spreading resistance.
  • the overall resistance of the device may decrease, resulting in a increased slope in Region 2 of the current-voltage curve shown in Figure 7 relative to Region 1.
  • the junction J5 between the current surge pad 1 16 and the drift layer will tend to turn on before the junctions between the heterojunction barrier regions 130 and the drift region 1 14.
  • curve 191 a current-voltage curve according to some embodiments at 200 °C is illustrated as curve 192 .
  • curve 192 a current-voltage curve according to some embodiments at 200 °C is illustrated as curve 192.
  • These curves indicate that surge capability of diodes according to some embodiments is enhanced at high temperature, as the slope of the curves increases with temperature and forward voltage.
  • the device illustrated in Figure 8 starts conducting at about 1 .8 V instead of the Ti-SiC Schottky turn- on voltage of 0.8V because polysilicon was used as the anode contact 1 8.
  • FIGS 9-12 illustrate methods of forming devices according to some embodiments.
  • a drift region 1 4 is provided.
  • the drift region 1 14 may be provided on a substrate 1 12.
  • the substrate 1 12 is optional and may be removed or omitted in some embodiments.
  • the drift region 1 14 may be formed, for example, from n-type silicon carbide of the 2H, 4H, 6H, 3C and/or 15R polytype having a dopant concentration of about 2 x 10 14 to about 1 x 10 17 cm "3 , depending on design requirements for voltage blocking and on-resistance for the diode 100.
  • Other types of semiconductor materials such as GaN, GaAs, silicon or germanium may be used.
  • the drift region 1 14 includes 4H-SiC doped with n-type dopants at a concentration of about 5 x 10 15 cm "3 .
  • Optional implanted regions 160 may be formed at the device periphery to provide a robust guard ring termination.
  • a plurality of recesses 170, 171 and 172 are formed in a surface of a drift region 1 14, for example by masking and etching techniques which are well known in the art.
  • the recesses 170, 71 and 172 may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14 from the surface of the drift region 1 14.
  • a layer of a material 180, such as polysilicon, which forms a heterojunction with the drift layer, is deposited on the surface of the drift layer and into the recesses 170, 171 , 172.
  • the layer 180 of polysilicon may be doped with p-type dopants, such as boron and/or aluminum, at a concentration of about 1 x 10 18 to about 1 x 10 19 cm “3 , and in particular embodiments at a dopant concentration of about 5 x 10 18 cm "3 .
  • the layer 180 of polysilicon may be doped using any conventional doping technique, such as in-situ doping, spinning-on, diffusion and drive-in annealing, etc.
  • the layer 180 may be patterned using photolithographic techniques to form respective current surge pads 116, heterojunction barrier regions 130 and/or guard rings 125 that protrude above the surface of the drift region 1 14 ( Figure 10).
  • the layer 180 may be planarized using chemical-mechanical polish and/or etchback techniques to form respective current surge pads 1 16, heterojunction barrier regions 130 and guard rings 125 that are flush with the surface of the drift region 1 14 ( Figure 1 1 ).
  • a Schottky contact 118 may be formed on the drive region 114 and may include a metal, such as aluminum, titanium and/or nickel. In some embodiments, the contact 118 may form an ohmic contact with the current surge pad 1 16 and a Schottky contact with the drift region 1 14.
  • a metal overlayer 1 19 may be formed on the Schottky contact 1 18. The metal overlayer 1 19 may comprise TiW/AI, for example, and may be provided as a contact layer on the Schottky contact 1 18.
  • a cathode contact 120 is formed on a side of the substrate 1 12 opposite the drift region 1 14.
  • the cathode contact 120 may include a metal, such as nickel, that is capable of forming an ohmic contact to n-type silicon carbide.
  • An implanted region 160 of dopants having a conductivity opposite the conductivity of the drift layer may be formed beneath the guard rings 125 to probed a robust guard ring (RGR) termination.
  • the implanted region 160 may extend to a depth in the drift layer that is greater or less than the depth of the guard rings, and may have a net concentration of dopants having a conductivity opposite the conductivity type of the drift region 1 14 of about 1x10 17 cm "3 .
  • a field oxide layer 127 may be formed on the drift layer and may cover the guard rings 125.
  • Figures 13A and 13B are a cross-sectional views of devices 300 and 300', respectively, that have a mesa termination (Figure 13A) and a beveled edge termination (Figure 13B), as opposed to guard ring termination.
  • Figure 14 is a graph illustrating simulated horizontal electric field distributions for a device according to some embodiments including
  • heterojunction barrier regions and a heterojunction guard ring termination (curve 201 ) and a device according to some embodiments including
  • a peak electric field 201 P for the device represented by curve 201 may be substantially higher than a peak electric field 202P for the device represented by curve 202.
  • Embodiments of the present invention provide junction barrier Schottky semiconductor devices that may require no, or fewer, implantation steps compared to conventional JBS devices. Thus, cost and/or complexity of fabrication of such devices can be reduced. Furthermore, some embodiments use doped polysilicon features in a JBS diode. Polysilicon can be doped in many conventional techniques, and polysilicon processing techniques are compatible with high throughput processing. Furthermore, p-type polysilicon can act as a minority injector in surge current conditions in some
  • the surge capability may be further enhanced at high temperature operation.

Abstract

An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Description

SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices and the fabrication of semiconductor devices and more particularly, to Junction Barrier Schottky (JBS) diodes, and the fabrication of such diodes.
BACKGROUND
[0002] High voltage silicon carbide (SiC) Schottky diodes, which may have voltage blocking ratings between, for example, about 600V and about 2.5 kV, are expected to compete with silicon PIN diodes having similar voltage ratings. Such diodes may handle as much as about 100 amps or more of forward current, depending on their active area design. High voltage Schottky diodes have a number of important applications, particularly in the field of power conditioning, distribution and control.
[0003] An important characteristic of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices typically exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based Schottky devices are theoretically capable of much higher switching speeds, for example, in excess of about 100 times better than silicon. In addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.
[0004] A conventional SiC Schottky diode structure has an n-type SiC substrate on which an n- epitaxial layer, which functions as a drift region, is formed. The device typically includes a Schottky contact formed directly on the n- layer. A junction termination region, such as a guard ring and/or p-type JTE (junction termination extension) region, is typically formed to surround the Schottky junction active region. The purpose of junction termination region is to reduce or prevent electric field crowding at the edges of the Schottky junction, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. Other termination techniques include field plates and floating field rings that may be more strongly influenced by surface effects. A channel stop region may also be formed by implantation of n-type dopants in order to prevent the depletion region from extending to the edge of the device.
[0005] Regardless of the type of termination used, the Schottky diode will fail if a large enough reverse voltage is applied to the junction. Such failures are generally catastrophic, and may damage or destroy the device. Furthermore, even before the junction has failed, a Schottky diode may experience large reverse leakage currents. In order to reduce such leakage currents, the junction barrier Schottky (JBS) diode was developed. JBS diodes are sometimes referred to as Merged PIN - Schottky (MPS) diodes. A conventional JBS diode 10 is illustrated in Figure 1 , As shown therein, a conventional JBS diode includes an n-type substrate 12 on which an n- drift layer 14 is formed. A plurality of p+ regions 16 are formed, typically by ion implantation, in the surface of the n- drift layer 14. A metal anode contact 18 is formed on the surface of the n- drift layer 14 in contact with both the n- drift layer 14 and the p+ regions 16. The anode contact 18 forms a Schottky junction with the exposed portions of the drift layer 14, and may form an ohmic contact with the p+ regions 16. A cathode contact 20 is formed on the substrate 12. Silicon carbide-based JBS diodes are described, for example, in U.S. Patent Nos. 6,104,043 and 6,524,900.
[0006] In forward operation, the junction J1 between the anode contact 18 and the drift layer 14 turns on before the junction J2 between the p+ regions 16 and the drift layer 14. Thus, at low forward voltages, the device exhibits Schottky diode behavior. That is, current transport in the device is dominated by majority carriers (electrons) injected across the Schottky junction J1 at low forward voltages. As there may be no minority carrier injection (and thus no minority charge storage) in the device at normal operating voltages, JBS diodes have fast switching speeds characteristic of Schottky diodes.
[0007] Under reverse bias conditions, however, the depletion regions formed by the PN junctions J2 between the p+ regions 16 and the drift layer 14 expand to block reverse current through the device 10, protecting the Schottky junction J and limiting reverse leakage current in the device 0. Thus, in reverse bias, the JBS diode 10 behaves like a PIN diode. The voltage blocking ability of the device 10 is typically determined by the thickness and doping of the drift layer 14 and the design of the edge termination.
SUMMARY
[0008] An electronic device according to some embodiments includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region and the p- type junction barrier region is electrically connected to the contact.
[0009] The Schottky junction between the contact and the drift region may be configured to turn on at a lower forward voltage than the P-N heterojunction between the junction barrier region and the drift region.
[0010] The contact may form an ohmic contact to the p-type polysilicon region, and the P-N heterojunction between the heterojunction barrier region and the drift region may be configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
[0011] The electronic device may further include a guard ring termination region at a surface of the silicon carbide layer laterally adjacent to the contact. The guard ring termination region may include a second p-type polysilicon region on the drift region, the second p-type polysilicon region being electrically isolated from the contact under zero bias conditions.
[0012] The electronic device may further include a junction termination region at the surface of the silicon carbide layer having a conductivity type opposite the conductivity type of the drift region, the second p-type polysilicon region extends into the junction termination region.
[0013] The junction barrier region may include a plurality of p-type polysilicon regions in the drift region and at least one p-type polysilicon minority injector pad in the drift region beneath the contact and electrically connected to the contact.
[0014] The minority injector pad may have a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is larger than a surface area in the horizontal plane of one of the plurality of p- type polysilicon regions in the junction barrier region.
[0015] The minority carrier injector pad may have a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is at least about 10% of a surface area of the drift region in the horizontal plane below the contact.
[0016] The electronic device may further include an n+ silicon carbide contact layer on the drift region opposite the contact, and a second contact on the contact layer.
[0017] An electronic device according to further embodiments includes a drift region having a first conductivity type, a contact forming a junction with the drift region, and a junction barrier region on the drift region, the junction barrier region having a second conductivity type opposite the first conductivity type and including a heterojunction barrier region on the drift region. The heterojunction barrier region forms a P-N heterojunction with the drift region and is in electrical contact with the contact.
[0018] The Schottky junction between the contact and the drift region may be configured to turn on at a lower forward voltage than the P-N heterojunction between the heterojunction barrier region and the drift region.
[0019] The contact may form an ohmic contact to the heterojunction barrier region, and the P-N heterojunction between the heterojunction barrier region and the drift region may be configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
[0020] The electronic device may further include a guard ring termination region on the drift region and laterally adjacent to the Schottky junction. The guard ring termination region may include a second
heterojunction barrier region. [0021] The heterojunction barrier region may include a plurality of p- type polysilicon regions on the drift region and at least one p-type polysilicon minority injector pad on the drift region beneath the contact and electrically connected to the contact.
[0022] The minority carrier injection pad may have a width that is greater than a width of the junction barrier region.
[0023] The minority injector pad may have a horizontal surface area that is larger than a horizontal surface area of one of the plurality of p-type polysilicon regions in the junction barrier region.
[0024] The drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type polysilicon. In some embodiments, the drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type gallium nitride.
[0025] Some embodiments include a termination region at a surface of the drift region and defining an active region of the device within the termination region, wherein a ratio of a surface area of the active region occupied by the heterojunction barrier regions to a total surface area of the active region is about 2% to about 40%. In some embodiments, the ratio is about 4% to about 30%. In some other embodiments, the ratio is about 10% to about 30%, and in further embodiments the ratio is about 20% to about 30%.
[0026] Methods of forming an electronic device according to some embodiments include providing a drift region having a first conductivity type, providing a heterojunction barrier region on the drift region, the heterojunction barrier region including a material different from the drift region and having a conductivity type opposite the conductivity type of the drift region and providing a P-N heterojunction with the drift region, and forming a contact on the drift region and on the heterojunction barrier region, the contact forming a Schottky junction with the drift region and forming an ohmic junction with the heterojunction barrier region.
[0027] The drift region may include n-type silicon carbide and the heterojunction barrier region may include p-type polysilicon.
[0028] The methods may further include providing a guard ring termination region on the drift region laterally adjacent to the Schottky junction, the guard ring termination region may include a second
heterojunction barrier region on the drift region.
[0029] Providing the heterojunction barrier region may include etching a recess in the drift region, depositing a polysilicon layer in the recess, doping the polysilicon layer to have a conductivity type opposite the conductivity type of the drift region, and patterning the polysilicon layer.
[0030] An electronic device according to further embodiments includes a silicon carbide layer including a drift region having a first conductivity type, a contact on a surface of the drift region and forming a Schottky junction with the drift region, and a guard ring in contact with the surface of the silicon carbide layer adjacent to the Schottky junction. The guard ring has a conductivity type opposite the conductivity type of the drift region and includes a material that forms a heterojunction with the silicon carbide layer. The guard ring may include polysilicon and/or gallium nitride.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiment(s) of the invention. In the drawings:
[0032] Figure 1 is a cross-sectional view of a conventional JBS diode.
[0033] Figure 2 is a top view of a JBS diode according to some embodiments of the present invention.
[0034] Figure 3, 4 and 5 are cross-sectional views of JBS diodes according to some embodiments of the present invention.
[0035] Figure 6 is a cross-sectional detail of portions of a JBS diode according to some embodiments of the invention.
[0036] Figure 7 is a graph that schematically illustrates various regions in a current-voltage characteristic of a JBS diode according to some embodiments of the invention.
[0037] Figure 8 is a graph illustrating simulated forward current-voltage curves at operating temperatures ranging from 25 °C to 200 °C for a device according to some embodiments. [0038] Figures 9-12 are cross-sectional views illustrating the formation of JBS diodes according to some embodiments of the present invention.
[0039] Figures 13A and 13B are cross-sectional views of JBS diodes according to some embodiments of the present invention.
[0040] Figure 14 is a graph illustrating simulated horizontal electric field distributions for a device according to some embodiments.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0041] Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
[0042] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" "comprising," "includes" and/or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. [0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0045] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
[0046] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
[0047] Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
[0048] Some embodiments of the invention are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a "+" or "-" (as in η+, η-, ρ+, p-, n++, n~, p++, p-, or the like), to indicate a relatively larger ("+") or smaller ("- ") concentration of majority carriers compared to another layer or region.
However, such notation does not imply the existence of a particular
concentration of majority or minority carriers in a layer or region.
[0049] According to some embodiments, a junction barrier Schottky diode includes features, such as junction barrier regions and/or edge termination features, on or in a drift layer, wherein the junction barrier regions and/or edge termination features are provided by regions of a different material type than the drift layer, and form respective heterojunctions with the drift layer. In some embodiments, the features, such as junction barrier regions and/or edge termination features, may include doped polysilicon, which can be formed, for example, using conventional processes that may not require ion implantation.
[0050] Figure 2 is a top view of a diode 100 according to some embodiments of the invention, and Figure 3 is a partial cross-sectional view of the diode 100 taken along line A-A of Figure 2. Figures 4 and 5 are similar cross sectional illustrations of diodes 100' and 100", respectively, according to other embodiments. The dimensions of some features of the diodes 100, 100', 100" are exaggerated for clarity. [0051] Referring to Figures 2 and 3, the diode 100 includes an optional substrate 1 12 on which a layer 1 13 including a drift region 1 14 is formed. The layer 1 13 has an upper surface, opposite the substrate, in which a plurality of heterojunction barrier regions 130 are formed. A Schottky contact 118 is on the drift region 1 14 . The Schottky contact 1 18 contacts the surface of the drift region 1 14 and forms a Schottky junction with the drift region 1 14. The Schottky contact 1 18 also contacts the plurality of heterojunction barrier regions 130.
[0052] The layer 1 13 may be formed, for example, from n-type silicon carbide of the 2H, 4H, 6H, 3C and/or 15R polytype. The drift region 1 14 may have a dopant concentration of about 2 x 1014 to about 1 x 1017 cm"3, depending on design requirements for voltage blocking and on-resistance for the diode 100. Other types of semiconductor materials, such as GaN, GaAs, silicon or germanium may be used. In particular embodiments, the drift region 1 14 includes 4H-SiC doped with n-type dopants at a concentration of about 5 x 10 5 cm"3.
[0053] The heterojunction barrier regions 130 are formed from a semiconducting material that is different from the material of the drift region 1 14. The heterojunction barrier regions 130 have a conductivity type that is opposite the conductivity type of the drift region 1 14. Accordingly, the heterojunction barrier regions 130 form P-N heterojunctions with the drift region 1 14. Furthermore, the Schottky contact 1 18 may form an ohmic junction with the heterojunction barrier regions 130.
[0054] In some embodiments, the barrier height of the P-N
heterojunction J3 between the heterojunction barrier regions 130 and the drift layer may be higher than a barrier height of a Schottky junction J4 between a Schottky contact 1 18 and the drift region 1 14, so that the P-N heterojunction will turn on at a higher forward voltage than the Schottky junction J4 between the drift region 1 4 and the Schottky contact 1 18, as will be discussed in more detail below.
[0055] In the embodiments of Figures 2 and 3, the heterojunction barrier regions 130 are formed as stripe-shaped regions in the drift region 1 14. However, the heterojunction barrier regions 130 may be formed in other shapes, such as islands, squares, dots, hexagons, or any other desired shape.
[0056] In some embodiments, the heterojunction barrier regions 130 may be provided as regions of doped polysilicon. For example, the heterojunction barrier regions 130 may include polysilicon regions doped to have a conductivity that is opposite the conductivity type of the drift region 1 14, so that the heterojunction barrier regions 130 form P-N heterojunctions J3 with the drift region 1 14.
[0057] The heterojunction barrier regions 130 may be doped with p- type dopants, such as boron and/or aluminum, at a concentration of about 1 x 1017 to about 1 x 1020 cm"3, and may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14 from the surface of the drift region 1 14. In particular embodiments, the heterojunction barrier regions 130 may be doped at a dopant concentration of about 5 x 1018 cm"3, and may extend to a depth of about 0.3 pm into the drift region 1 14 from the surface of the drift region 1 14.
[0058] One or more current surge pads 116 may also be provided in the drift region 1 14. The current surge pads 1 16 may be formed of the same material as the heterojunction barrier regions 130. For example, the current surge pads 1 16 may be provided as polysilicon regions doped with p-type dopants, such as boron and/or aluminum, at a concentration of about 1 x 1018 to about 1 x 1020 cm"3, and may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14. In particular embodiments, the current surge pads 1 16 may be doped at a dopant concentration of about 5 x 1018 cm"3, and may extend to a depth of about 0.3 pm into the drift region 1 14. The current surge pads 1 16 have a larger width than the heterojunction barrier regions 130 to encourage the flow of surge current through the current surge pads at high forward voltages, as will be discussed in more detail below. For example, the current surge pads 1 16 may have a width of about 10 pm to about 250 pm. In particular embodiments, the current surge pads 1 16 may have a width of about 20 pm.
[0059] In some embodiments, the current surge pads 1 16 and/or heterojunction barrier regions 130 may be formed of other types of materials that can be doped to have a conductivity that is opposite the conductivity of the drift region 1 14 and can form a heterojunction with the drift region 114. For example, when the drift region comprises n-type silicon carbide, a material such as p-type gallium nitride can be used to form the current surge pads 1 16 and/or heterojunction barrier regions 130.
[0060] The heterojunction barrier regions 130 shown in the
embodiments of Figures 2 and 3 are provided as spaced apart striped regions that expose portions 1 14A of the surface of the drift region 1 14 and that extend across an active region 1 10 of the drift region 1 14 (except for the exposed portions 1 14A of the drift layer and the current surge pads 1 16). A metal Schottky contact 1 18 covers the drift region 1 14 and forms Schottky rectifying junctions with the exposed portions 1 14A of the drift region 1 14 as well as the heterojunction barrier regions 130 and the current surge pads 1 16.
[0061] As used herein, the term "active region" ijefers to the two dimensional area of the device in which the Schottky metal contacts the drift layer, and includes the exposed portions 1 14A of the drift region 1 14, the heterojunction barrier 130 and the current surge pads 1 16. Accordingly, the active region includes the Schottky junction area but does not include, for example, the edge termination region described below.
[0062] The diode 100 may include an edge termination region 1 15 surrounding the active region 1 10 of the diode 100. The edge termination region 1 15 may include a junction termination extension (JTE) region, field rings, field plates, guard rings, and/or a combination of the foregoing or other terminations. In particular, the device 100 may include a plurality of guard rings 125, which may be formed of the same material as the heterojunction barrier regions 130 and the current surge pad 16 and may also be doped to have a conductivity opposite the conductivity type of the drift region 1 4. A passivation layer, such as a field oxide layer 127, may be formed on the drift layer and may cover the guard rings 125. The guard rings 125 may be floating guard rings that are electrically isolated from the anode contact 1 18 under zero bias conditions.
[0063] In some embodiments, the edge termination region 1 15 includes a robust guard ring (RGR) termination as described in U.S. Patent No.
7,026,650, which is assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference as if set forth fully. In particular, the RGR termination may include an implanted region 160 of dopants having a conductivity opposite the conductivity of the drift layer. The implanted region 160 may extend to a depth in the drift region 14 that is greater or less than the depth of the guard rings 125. The implanted region 160 may have a net concentration of dopants having a conductivity opposite the conductivity type of the drift region 1 14 of about 1x1017 cm"3.
[0064] Additional conventional terminations of SiC Schottky diodes are described in "Planar Terminations in 4H-SiC Schottky Diodes With Low Leakage And High Yields" by Singh et al., ISPSD '97, pp. 157 160. A p-type epitaxy guard ring termination for a SiC Schottky Barrier Diode is described in "The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes" by Ueno et al., IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331 332. Additionally, other termination techniques are described in published PCT Application No. WO 97/08754 entitled "SiC Semiconductor Device Comprising A PN Junction With A Voltage Absorbing Edge."
[0065] The current surge pads 1 16 and the heterojunction barrier regions 130 may be formed within recesses in the drift region 1 14, and may protrude above an upper surface of the drift region 1 14. As the current surge pads 1 16 and the heterojunction barrier regions 130 have an opposite conductivity type from the drift region 1 14, the heterojunction barrier regions 30 form P-N junctions J3 with the drift region 14, while the current surge pads 1 16 form P-N junctions J5 with the drift region 1 14.
[0066] In the diode 100' illustrated in Figure 4, the current surge pads 1 16', the heterojunction barrier regions 130' and the guard rings 125' are formed within recesses in the drift region 1 14, and are flush with the upper surface of the drift region 1 14. For example, polysilicon may be deposited into the recesses in the drift region 1 14 and planarized using a chemical- mechanical polish (CMP) or etch back technique to form the current surge pads 1 16', the heterojunction barrier regions 130', and/or the guard rings 125', as shown in Figure 4.
[0067] In the diode 100" illustrated in Figure 5, the current surge pads 1 6", the heterojunction barrier regions 130" and the guard rings 125" are formed as discrete regions on the upper surface of the drift region 1 14, and do not extend into the drift region 1 14. For example, For example, polysilicon may be deposited onto the drift region 1 14 and patterned using photolithography to form the current surge pads 1 16", the heterojunction barrier regions 130", and/or the guard rings 125", as shown in Figure 5.
[0068] Referring again to Figure 3, the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may affect both the reverse leakage current of the device 100 and the forward voltage drop of the device 100. For example, if the area occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 is increased relative to the total area of the active region 1 10, the reverse leakage current may be reduced, but the forward voltage drop of the device 100 may increase. Thus, the selection of the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may entail a trade-off between reverse leakage current and forward voltage drop. In some embodiments, the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may be between about 2% and 40%. In some other embodiments, the ratio of the surface area of the active region 1 10 of the device 100 occupied by the heterojunction barrier regions 130 and the current surge pads 1 16 to the total surface area of the active region 1 10 may be between about 4% and 30%. In further embodiments, the ratio may be about 10% to about 30%, and in still further embodiments, the ratio may be about 20% to about 30%.
[0069] The Schottky contact 118 on the surface of the drift region 1 14 forms a Schottky junction J4 with the exposed portions 1 14A of the drift region 1 14 between adjacent heterojunction barrier regions 130. The anode contact 1 18 may include a metal, such as aluminum, titanium and/or nickel. In some embodiments, the anode contact 1 18 may form an ohmic contact with the current surge pad 1 16. A metal overlayer 1 19 may be formed on the Schottky contact 1 18. The metal overlayer 1 19 may comprise TiW/AI, for example, and may be provided as a contact layer on the Schottky contact 1 18. [0070] A cathode contact 120 is formed on a side of the substrate 1 12 opposite the drift region 1 14 and/or directly on the drift region 1 14. The cathode contact 120 may include a metal, such as nickel, that is capable of forming an ohmic contact to n-type silicon carbide.
[0071] Under reverse bias conditions, the depletion regions formed by the p-n junctions J3 between the heterojunction barrier regions 130 and the drift region 1 14, as well as the depletion region of the p-n junction J5, may expand to block reverse current through the device 100, protecting the
Schottky junction J4 and limiting reverse leakage current in the device 100. Thus, in reverse bias, the diode 100 may function substantially like a PIN diode.
[0072] In forward operation, the Schottky junction J4 between the anode contact 1 18 and the exposed portions 14A of the drift region 14 turns on before the heterojunction J3 and the junction J5 between the current surge pad 1 16 and the drift region 1 14. Thus, at low forward voltages, the device exhibits Schottky diode behavior, and the operation of the diode 100 will be dominated by the injection of majority carriers across the Schottky junctions J3 and J4. Due to the absence of minority carrier injection under normal operating conditions, the diode 100 may have a very fast switching capability, which is characteristic of Schottky diodes in general.
[0073] The current surge pad 1 16 may be designed to begin to conduct at a forward voltage that is higher than the turn-on voltage of the Schottky junction J3. Thus, in the event of a current surge that causes the forward voltage of the diode 100 to increase, the p-n junction J5 will begin to conduct. Once the p-n junction J5 begins to conduct, the operation of the diode 100 is dominated by the injection and recombination of minority carriers across the p-n junction J5. In that case, the forward voltage drop of the diode 100 may be clamped, which may decrease the amount of power dissipated by the diode 100 for a given level of current. Thus, turn-on of the p-n junction J5 when the forward voltage of the diode 100 increases may reduce and/or prevent forward current runaway in the diode 100.
[0074] Furthermore, in a device according to some embodiments, the turn-on of the p-n junctions J3 and J5 may occur in stages. In a first stage, the Schottky junction J4 between the drift region 1 14 and the Schottky contact 1 18 may turn on, resulting in majority carrier conduction. In a second stage, as the bias on the P-N heterojunction J3 increases, majority carriers may be injected across the P-N heterojunction J3, allowing for further reduction in on- resistance. Furthermore, in a device according to some embodiments, the turn on of junction J5 may occur in stages, resulting in minority carrier injection allowing for surge current capability.
[0075] Forward current operation of a device according to some embodiments is illustrated in Figures 6 and 7. In particular, Figure 6 is a magnified illustration of a portion of a drift region 1 14 include a current surge pad 1 16 and two heterojunction barrier regions 130. Forward current components 40, 41 and 42 are illustrated in Figure 6. Figure 7 is a schematic graph of current density (J) versus forward voltage (V) for a Schottky diode according to some embodiments. As shown in Figure 7, the current-voltage characteristic of a Schottky diode according to some embodiments may have three distinct regions of operation, shown in Figure 7 as Region 1 , Region 2 and Region 3.
[0076] Referring to Figure 6, when a forward voltage is applied to the Schottky contact 1 18 relative to the drift region 1 14 that is sufficient to turn on the Schottky junction J4 between the Schottky contact 118 and the drift region 1 14, majority carriers (e.g., electrons in the case of an n-type drift layer) are injected into the drift layer, resulting in a Schottky current component 40. Before the P-N heterojunction J5 between the current surge pad 116 and the drift region 1 14 and the ohmic junction J6 between the anode contact 1 18 and the current surge pad 1 16 have turned on, the Schottky current component 40 is the only component of the device current. This is illustrated as Region 1 in the graph of Figure 7, where the forward voltage of the device is between V1 and V2. V1 represents the turn-on voltage of the Schottky junction J4, while V2 represents the turn-on voltage of the heterojunction J3 between the heterojunction barrier region 130 and the drift region 1 14.
[0077] In particular embodiments, the turn-on voltage of the Schottky junction J4 may be about 0.8 V when the Schottky contact 1 18 is titanium and the drift region 114 is n-type silicon carbide, while the turn-on voltage of the junction J3 between the heterojunction barrier region 130 and the drift region 1 14 may be about 1.5 V. [0078] As shown in Figure 6, the Schottky current 40 spreads laterally beneath the current surge pad 1 16 and the heterojunction barrier regions 130, resulting in spreading resistance in the device. Thus, the current-voltage curve shown in Figure 7 may have a relatively low slope in Region 1 .
[0079] When the forward voltage of the device reaches V2, the heterojunction J3 between the heterojunction barrier region 130 and the drift region 1 14 and the heterojunction J5 between the current surge pad 1 16 and the drift region 1 14 may turn on, resulting in unipolar injection of electrons 41 into the drift region. The device may still exhibit some spreading resistance. However, the overall resistance of the device may decrease, resulting in a increased slope in Region 2 of the current-voltage curve shown in Figure 7 relative to Region 1.
[0080] As the voltage on the device increases, the Schottky current through junction J4 increases. The voltage drop AV across the current surge pad 1 16 also increases to the point where the P-N heterojunction J5 between the current surge pad 1 16 and the drift region 1 14 begins to inject minority carriers 42 (e.g., holes in the case of an n-type drift layer) into the drift region 1 14. This condition is illustrated as Region 3 of Figure 7. The resistance of the device is further reduced, increasing the slope of the current-voltage curve in Region 3.
[0081] It will be appreciated that the voltage drop AV across the half- width of the current surge pad 1 16, which is greater than the half-width of the heterojunction barrier regions 130, where "half-width" refers to the minimum lateral distance from an edge of the feature to a center of the feature, i.e., the minimum distance that laterally spreading current must travel to reach the center point of the feature. As the width of the current surge pad 1 16 is greater than the widths of the heterojunction barrier regions 130, the junction J5 between the current surge pad 1 16 and the drift layer will tend to turn on before the junctions between the heterojunction barrier regions 130 and the drift region 1 14.
[0082] Empirical forward current-voltage curves at operating
temperatures ranging from 25 °C to 200 °C for a device according to some embodiments with p+ polysilicon as the Schottky contact are illustrated in Figure 8. For example, a current-voltage curve according to some
embodiments at 25 °C is illustrated as curve 191 , while to a current-voltage curve according to some embodiments at 200 °C is illustrated as curve 192. These curves indicate that surge capability of diodes according to some embodiments is enhanced at high temperature, as the slope of the curves increases with temperature and forward voltage. The device illustrated in Figure 8 starts conducting at about 1 .8 V instead of the Ti-SiC Schottky turn- on voltage of 0.8V because polysilicon was used as the anode contact 1 8.
[0083] Figures 9-12 illustrate methods of forming devices according to some embodiments. Referring to Figure 9, a drift region 1 4 is provided. The drift region 1 14 may be provided on a substrate 1 12. However, it will be appreciated that the substrate 1 12 is optional and may be removed or omitted in some embodiments.
[0084] The drift region 1 14 may be formed, for example, from n-type silicon carbide of the 2H, 4H, 6H, 3C and/or 15R polytype having a dopant concentration of about 2 x 1014 to about 1 x 1017 cm"3, depending on design requirements for voltage blocking and on-resistance for the diode 100. Other types of semiconductor materials, such as GaN, GaAs, silicon or germanium may be used. In particular embodiments, the drift region 1 14 includes 4H-SiC doped with n-type dopants at a concentration of about 5 x 1015 cm"3.
[0085] Optional implanted regions 160 may be formed at the device periphery to provide a robust guard ring termination.
[0086] A plurality of recesses 170, 171 and 172 are formed in a surface of a drift region 1 14, for example by masking and etching techniques which are well known in the art. The recesses 170, 71 and 172 may extend to a depth of about 0.3 to about 0.5 pm into the drift region 1 14 from the surface of the drift region 1 14. A layer of a material 180, such as polysilicon, which forms a heterojunction with the drift layer, is deposited on the surface of the drift layer and into the recesses 170, 171 , 172. The layer 180 of polysilicon may be doped with p-type dopants, such as boron and/or aluminum, at a concentration of about 1 x 1018 to about 1 x 1019 cm"3, and in particular embodiments at a dopant concentration of about 5 x 1018 cm"3. The layer 180 of polysilicon may be doped using any conventional doping technique, such as in-situ doping, spinning-on, diffusion and drive-in annealing, etc. [0087] The layer 180 may be patterned using photolithographic techniques to form respective current surge pads 116, heterojunction barrier regions 130 and/or guard rings 125 that protrude above the surface of the drift region 1 14 (Figure 10). In some embodiments, the layer 180 may be planarized using chemical-mechanical polish and/or etchback techniques to form respective current surge pads 1 16, heterojunction barrier regions 130 and guard rings 125 that are flush with the surface of the drift region 1 14 (Figure 1 1 ).
[0088] Referring to Figure 12, a Schottky contact 118 may be formed on the drive region 114 and may include a metal, such as aluminum, titanium and/or nickel. In some embodiments, the contact 118 may form an ohmic contact with the current surge pad 1 16 and a Schottky contact with the drift region 1 14. A metal overlayer 1 19 may be formed on the Schottky contact 1 18. The metal overlayer 1 19 may comprise TiW/AI, for example, and may be provided as a contact layer on the Schottky contact 1 18.
[0089] A cathode contact 120 is formed on a side of the substrate 1 12 opposite the drift region 1 14. The cathode contact 120 may include a metal, such as nickel, that is capable of forming an ohmic contact to n-type silicon carbide.
[0090] An implanted region 160 of dopants having a conductivity opposite the conductivity of the drift layer may be formed beneath the guard rings 125 to probed a robust guard ring (RGR) termination. The implanted region 160 may extend to a depth in the drift layer that is greater or less than the depth of the guard rings, and may have a net concentration of dopants having a conductivity opposite the conductivity type of the drift region 1 14 of about 1x1017 cm"3. Finally, a field oxide layer 127 may be formed on the drift layer and may cover the guard rings 125.
[0091] Further embodiments are illustrated in Figures 13A and 13B, which are a cross-sectional views of devices 300 and 300', respectively, that have a mesa termination (Figure 13A) and a beveled edge termination (Figure 13B), as opposed to guard ring termination.
[0092] Figure 14 is a graph illustrating simulated horizontal electric field distributions for a device according to some embodiments including
heterojunction barrier regions and a heterojunction guard ring termination (curve 201 ) and a device according to some embodiments including
heterojunction barrier regions and a heterojunction guard ring termination with a robust guard ring termination including implanted regions 160 (curve 202). As can be seen in Figure 14, a peak electric field 201 P for the device represented by curve 201 may be substantially higher than a peak electric field 202P for the device represented by curve 202.
[0093] Embodiments of the present invention provide junction barrier Schottky semiconductor devices that may require no, or fewer, implantation steps compared to conventional JBS devices. Thus, cost and/or complexity of fabrication of such devices can be reduced. Furthermore, some embodiments use doped polysilicon features in a JBS diode. Polysilicon can be doped in many conventional techniques, and polysilicon processing techniques are compatible with high throughput processing. Furthermore, p-type polysilicon can act as a minority injector in surge current conditions in some
embodiments, and the surge capability may be further enhanced at high temperature operation.
[0094] While embodiments of the present invention have been described with reference to particular sequences of operations, as will be appreciated by those of skill in the art, certain operations within the sequence may be reordered while still benefiting from the teachings of the present invention. Accordingly, the present invention should not be construed as limited to the exact sequence of operations described herein.
[0095] In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

That which is claimed is: . An electronic device, comprising:
a silicon carbide layer including an n-type drift region therein;
a contact forming a Schottky junction with the drift region; and a p-type junction barrier region on the silicon carbide layer, the p-type junction barrier region including a p-type polysilicon region forming a P-N heterojunction with the drift region and the p-type junction barrier region being electrically connected to the contact.
2. The electronic device of Claim 1 , wherein the Schottky junction between the contact and the drift region is configured to conduct current at a lower forward voltage than the P-N heterojunction between the junction barrier region and the drift region.
3. The electronic device of Claim 2, wherein the contact forms an ohmic contact to the p-type polysilicon region, and wherein the P-N
heterojunction between the heterojunction barrier region and the drift region is configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
4. The electronic device of Claim 1 , further comprising:
a guard ring termination region at a surface of the silicon carbide layer laterally adjacent to the contact, wherein the guard ring termination region includes a second p-type polysilicon region on the drift region, the second p- type polysilicon region being electrically isolated from the contact under zero bias conditions.
5. The electronic device of Claim 4, further comprising a junction termination region at the surface of the silicon carbide layer having a conductivity type opposite the conductivity type of the drift region, wherein the second p-type polysilicon region extends into the junction termination region.
6. The electronic device of Claim 1 , wherein the junction barrier region comprises a plurality of p-type polysilicon regions in the drift region and at least one p-type polysilicon minority injector pad in the drift region beneath the contact and electrically connected to the contact.
7. The electronic device of Claim 6, wherein the minority injector pad has a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is larger than a surface area in the horizontal plane of one of the plurality of p-type polysilicon regions in the junction barrier region.
8. The electronic device of Claim 6, wherein the minority carrier injector pad has a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is at least about 10% of a surface area of the drift region in the horizontal plane below the contact.
9. The electronic device of Claim 1 , wherein the contact comprises a first contact, the device further comprising an n+ silicon carbide contact layer on the drift region opposite the contact, and a second contact on the contact layer.
10. An electronic device, comprising:
a drift region having a first conductivity type;
a contact on the drift region and forming a junction with the drift region; and
a junction barrier region on the drift region, the junction barrier region having a second conductivity type opposite the first conductivity type and including a heterojunction barrier region on the drift region, wherein the heterojunction barrier region forms a P-N heterojunction with the drift region and is in electrical contact with the contact.
1 1. The electronic device of Claim 10, wherein the junction between the contact and the drift region comprises a Schottky junction that is configured to conduct current at a lower forward voltage than the P-N heterojunction between the heterojunction barrier region and the drift region.
12. The electronic device of Claim 10, wherein the contact forms an ohmic contact to the heterojunction barrier region, and wherein the P-N heterojunction between the heterojunction barrier region and the drift region is configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.
13. The electronic device of Claim 10, further comprising:
a guard ring termination region on the drift region and laterally adjacent to the junction, wherein the guard ring termination region includes a second heterojunction barrier region.
14. The electronic device of Claim 10, wherein the heterojunction barrier region comprises a plurality of p-type polysilicon regions on the drift region and at least one p-type polysilicon minority injector pad on the drift region beneath the contact and electrically connected to the contact.
15. The electronic device of Claim 14, wherein the minority carrier injection pad has a width that is greater than a width of the junction barrier region.
16. The electronic device of Claim 14, wherein the minority injector pad has a horizontal surface area that is larger than a horizontal surface area of one of the plurality of p-type polysilicon regions in the junction barrier region.
17. The electronic device of Claim 10, wherein the drift region comprises n-type silicon carbide and the heterojunction barrier region comprises p-type polysilicon.
18. The electronic device of Claim 10, wherein the drift region comprises n-type silicon carbide and the heterojunction barrier region comprises p-type gallium nitride.
19. The electronic device of Claim 10, further comprising:
a termination region at a surface of the drift region and defining an active region of the device within the termination region;
wherein a ratio of a surface area of the active region occupied by the heterojunction barrier regions to a total surface area of the active region is about 2% to about 40%.
20. The electronic device of Claim 19, wherein the ratio of the surface area of the active region occupied by the heterojunction barrier regions to the total surface area of the active region is about 10% to about 30%.
21. The electronic device of Claim 19, wherein the ratio of the surface area of the active region occupied by the heterojunction barrier regions to the total surface area of the active region is about 20% to about 30%.
22. A method of forming an electronic device, comprising:
providing a drift region having a first conductivity type;
providing a heterojunction barrier region on the drift region, the heterojunction barrier region comprising a material different from the drift region and having a conductivity type opposite the conductivity type of the drift region and forming a P-N heterojunction with the drift region; and
providing a contact on the drift region and on the heterojunction barrier region, the contact forming a Schottky junction with the drift region and forming an ohmic junction with the heterojunction barrier region.
23. The method of Claim 22, wherein the drift region comprises n- type silicon carbide and the heterojunction barrier region comprises p-type polysilicon.
24. The method of Claim 22, further comprising:
providing a guard ring termination region on the drift region laterally adjacent to the Schottky junction, wherein the guard ring termination region includes a second heterojunction barrier region on the drift region.
25. The method of Claim 22, wherein providing the heterojunction barrier region comprises etching a recess in the drift region, depositing a polysilicon layer in the recess, doping the polysilicon layer to have a conductivity type opposite the conductivity type of the drift region, and patterning the polysilicon layer.
26. An electronic device, comprising:
a silicon carbide layer including a drift region having a first conductivity type;
a contact on a surface of the drift region and forming a junction with the drift region; and
a guard ring in contact with the surface of the silicon carbide layer adjacent to the junction, the guard ring having a conductivity type opposite the conductivity type of the drift region and including a material forming a heterojunction with the silicon carbide layer.
27. The electronic device of Claim 26, wherein the guard ring comprises polysilicon.
28. The electronic device of Claim 26, wherein the guard ring comprises gallium nitride.
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US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) * 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8778788B2 (en) * 2011-10-11 2014-07-15 Avogy, Inc. Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode
US9224828B2 (en) 2011-10-11 2015-12-29 Avogy, Inc. Method and system for floating guard rings in gallium nitride materials
US10164043B2 (en) * 2012-01-11 2018-12-25 Infineon Technologies Ag Semiconductor diode and method for forming a semiconductor diode
JP6050891B2 (en) * 2012-05-17 2016-12-21 ゼネラル・エレクトリック・カンパニイ Semiconductor device with junction termination extension
JP6384944B2 (en) * 2012-05-31 2018-09-05 富士電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
US8969994B2 (en) * 2012-08-14 2015-03-03 Avogy, Inc. Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back
US9064887B2 (en) * 2012-09-04 2015-06-23 Infineon Technologies Austria Ag Field-effect semiconductor device and manufacturing method therefor
JP6029397B2 (en) * 2012-09-14 2016-11-24 三菱電機株式会社 Silicon carbide semiconductor device
US8952481B2 (en) * 2012-11-20 2015-02-10 Cree, Inc. Super surge diodes
JP6089733B2 (en) * 2013-01-30 2017-03-08 富士電機株式会社 Semiconductor device
US10181532B2 (en) * 2013-03-15 2019-01-15 Cree, Inc. Low loss electronic devices having increased doping for reduced resistance and methods of forming the same
CN104282732B (en) * 2013-07-01 2017-06-27 株式会社东芝 Semiconductor device
JP6197995B2 (en) * 2013-08-23 2017-09-20 富士電機株式会社 Wide band gap insulated gate semiconductor device
JP6053645B2 (en) * 2013-09-10 2016-12-27 三菱電機株式会社 Method for manufacturing SiC semiconductor device
DE102013019851B4 (en) * 2013-11-26 2015-10-22 Infineon Technologies Ag Schottky diode with reduced forward voltage
US9552993B2 (en) * 2014-02-27 2017-01-24 Semiconductor Components Industries, Llc Semiconductor device and manufacturing method thereof
EP2942805B1 (en) * 2014-05-08 2017-11-01 Nexperia B.V. Semiconductor device and manufacturing method
WO2016043247A1 (en) 2014-09-17 2016-03-24 富士電機株式会社 Semiconductor device
US11430882B2 (en) 2016-06-24 2022-08-30 Wolfspeed, Inc. Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
US10892356B2 (en) 2016-06-24 2021-01-12 Cree, Inc. Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same
CN106898638B (en) * 2017-01-16 2019-09-10 中国电子科技集团公司第五十五研究所 A kind of SiC schottky diode structure and preparation method improving surge capacity
US10083952B2 (en) * 2017-02-02 2018-09-25 Globalfoundries Inc. Diode-triggered schottky silicon-controlled rectifier for Fin-FET electrostatic discharge control
JP6999106B2 (en) * 2017-07-08 2022-01-18 株式会社Flosfia Semiconductor device
KR20230044336A (en) * 2017-07-08 2023-04-03 가부시키가이샤 플로스피아 Semiconductor device
SE541291C2 (en) * 2017-09-15 2019-06-11 Ascatron Ab Feeder design with high current capability
CN108281491B (en) * 2017-12-28 2021-04-16 厦门市三安集成电路有限公司 Silicon carbide power device with step structure and preparation method thereof
JP7132719B2 (en) * 2018-01-19 2022-09-07 ローム株式会社 semiconductor equipment
US11251282B2 (en) 2018-02-09 2022-02-15 Mitsubishi Electric Corporation Power semiconductor device
WO2020013244A1 (en) * 2018-07-12 2020-01-16 株式会社Flosfia Semiconductor apparatus
EP3823043A4 (en) * 2018-07-12 2022-04-13 Flosfia Inc. Semiconductor apparatus
JPWO2020013242A1 (en) * 2018-07-12 2021-08-05 株式会社Flosfia Semiconductor device
US10593760B2 (en) 2018-08-02 2020-03-17 Semiconductor Components Industries, Llc Method for forming trench semiconductor device having Schottky barrier structure
CN109004023A (en) * 2018-08-13 2018-12-14 济南晶恒电子有限责任公司 A kind of low cost SiC schottky diode chip and preparation method thereof
WO2020042221A1 (en) * 2018-08-29 2020-03-05 无锡新洁能股份有限公司 Silicon carbide diode having high surge current capability and manufacturing method thereof
CN109449085A (en) * 2018-09-12 2019-03-08 秦皇岛京河科学技术研究院有限公司 A kind of 4H-SiC Schottky diode and preparation method thereof that Surge handling capability is enhanced
CN109461654A (en) * 2018-09-12 2019-03-12 秦皇岛京河科学技术研究院有限公司 A kind of SiC Schottky diode and preparation method thereof of no injection type termination end structure
CN109801958B (en) * 2019-01-21 2020-09-15 厦门市三安集成电路有限公司 Silicon carbide groove Schottky diode device and preparation method thereof
US11195922B2 (en) * 2019-07-11 2021-12-07 Fast SiC Semiconductor Incorporated Silicon carbide semiconductor device
CN112216746A (en) * 2019-07-11 2021-01-12 即思创意股份有限公司 Silicon carbide semiconductor device
WO2021144851A1 (en) * 2020-01-14 2021-07-22 三菱電機株式会社 Schottky barrier diode
CN111244189B (en) * 2020-01-20 2022-08-26 西安理工大学 SiC MPS diode containing NiO/SiC heterojunction
KR102226206B1 (en) * 2020-02-06 2021-03-11 포항공과대학교 산학협력단 Memory device including double PN junctions and driving method thereof
US11164979B1 (en) * 2020-08-06 2021-11-02 Vanguard International Semiconductor Corporation Semiconductor device
CN113053997B (en) * 2020-12-28 2022-06-10 全球能源互联网研究院有限公司 Junction terminal extension structure of high-voltage silicon carbide device and manufacturing method thereof
US11929428B2 (en) 2021-05-17 2024-03-12 Wolfspeed, Inc. Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
US20220367695A1 (en) * 2021-05-17 2022-11-17 Cree, Inc. Circuits and group iii-nitride transistors with buried p-layers and controlled gate voltages and methods thereof
CN117316766A (en) * 2023-11-29 2023-12-29 深圳基本半导体有限公司 Preparation method of silicon carbide diode device and device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766433A (en) 1993-08-26 1995-03-10 Hitachi Ltd Semiconductor rectifier element
US20060255423A1 (en) * 2005-05-11 2006-11-16 Sei-Hyung Ryu Silicon carbide junction barrier schottky diodes with supressed minority carrier injection
US7183575B2 (en) 2002-02-19 2007-02-27 Nissan Motor Co., Ltd. High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode
US20080121993A1 (en) * 2006-11-03 2008-05-29 Allen Hefner Power switching semiconductor devices including rectifying junction-shunts
US20080191304A1 (en) * 2007-02-09 2008-08-14 Cree, Inc. Schottky Diode Structure with Silicon Mesa and Junction Barrier Schottky Wells
US20080296587A1 (en) * 2007-05-30 2008-12-04 Denso Corporation Silicon carbide semiconductor device having junction barrier schottky diode

Family Cites Families (326)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3439189A (en) 1965-12-28 1969-04-15 Teletype Corp Gated switching circuit comprising parallel combination of latching and shunt switches series-connected with input-output control means
US3629011A (en) 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US3924024A (en) 1973-04-02 1975-12-02 Ncr Co Process for fabricating MNOS non-volatile memories
FR2347780A1 (en) 1976-07-21 1977-11-04 Bicosa Recherches IMPROVEMENTS MADE TO A BISTABLE ELEMENT AND SWITCH CIRCUIT CONTAINING SUCH A BISTABLE ELEMENT
US4242690A (en) 1978-06-06 1980-12-30 General Electric Company High breakdown voltage semiconductor device
US4466172A (en) 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
JPS59104165A (en) 1982-12-06 1984-06-15 Mitsubishi Electric Corp Power transistor
US4570328A (en) 1983-03-07 1986-02-18 Motorola, Inc. Method of producing titanium nitride MOS device gate electrode
US4469022A (en) 1983-04-01 1984-09-04 Permanent Label Corporation Apparatus and method for decorating articles of non-circular cross-section
US4641174A (en) 1983-08-08 1987-02-03 General Electric Company Pinch rectifier
US4581542A (en) 1983-11-14 1986-04-08 General Electric Company Driver circuits for emitter switch gate turn-off SCR devices
US4644637A (en) 1983-12-30 1987-02-24 General Electric Company Method of making an insulated-gate semiconductor device with improved shorting region
JPS60177266U (en) 1984-05-02 1985-11-25 株式会社　大井製作所 door check device
JPS60240158A (en) 1984-05-14 1985-11-29 Mitsubishi Electric Corp Semiconductor circuit
EP0176778B1 (en) 1984-09-28 1991-01-16 Siemens Aktiengesellschaft Method of producing a pu junction with a high disruptive breakdown voltage
JPS61191071A (en) 1985-02-20 1986-08-25 Toshiba Corp Conductivity modulation type semiconductor device and manufacture thereof
JPS62136072A (en) * 1985-12-10 1987-06-19 Fuji Electric Co Ltd Manufacture of schottky barrier diode
JP2633536B2 (en) 1986-11-05 1997-07-23 株式会社東芝 Method for manufacturing junction type semiconductor substrate
US5041881A (en) 1987-05-18 1991-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Whiskerless Schottky diode
US4811065A (en) 1987-06-11 1989-03-07 Siliconix Incorporated Power DMOS transistor with high speed body diode
JPS6449273A (en) 1987-08-19 1989-02-23 Mitsubishi Electric Corp Semiconductor device and its manufacture
US4875083A (en) 1987-10-26 1989-10-17 North Carolina State University Metal-insulator-semiconductor capacitor formed on silicon carbide
US4866005A (en) 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US5011549A (en) 1987-10-26 1991-04-30 North Carolina State University Homoepitaxial growth of Alpha-SiC thin films and semiconductor devices fabricated thereon
US4945394A (en) 1987-10-26 1990-07-31 North Carolina State University Bipolar junction transistor on silicon carbide
JPH0614763Y2 (en) 1988-01-29 1994-04-20 一雄 上田 Evacuation equipment
JP2667477B2 (en) 1988-12-02 1997-10-27 株式会社東芝 Schottky barrier diode
JP2680083B2 (en) 1988-12-06 1997-11-19 富士通株式会社 Semiconductor substrate and method of manufacturing the same
JPH02275675A (en) 1988-12-29 1990-11-09 Fuji Electric Co Ltd Mos type semiconductor device
CA2008176A1 (en) 1989-01-25 1990-07-25 John W. Palmour Silicon carbide schottky diode and method of making same
EP0389863B1 (en) 1989-03-29 1996-12-18 Siemens Aktiengesellschaft Process for manufacturing a high-voltage withstanding planar p-n junction
US5111253A (en) 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US4927772A (en) 1989-05-30 1990-05-22 General Electric Company Method of making high breakdown voltage semiconductor device
JPH0766971B2 (en) 1989-06-07 1995-07-19 シャープ株式会社 Silicon carbide semiconductor device
US5028977A (en) 1989-06-16 1991-07-02 Massachusetts Institute Of Technology Merged bipolar and insulated gate transistors
JP2623850B2 (en) 1989-08-25 1997-06-25 富士電機株式会社 Conductivity modulation type MOSFET
JPH0750791B2 (en) 1989-09-20 1995-05-31 株式会社日立製作所 Semiconductor rectifier diode, power supply device using the same, and electronic computer
US4946547A (en) 1989-10-13 1990-08-07 Cree Research, Inc. Method of preparing silicon carbide surfaces for crystal growth
JPH03157974A (en) 1989-11-15 1991-07-05 Nec Corp Vertical type field effect transistor
US5166760A (en) 1990-02-28 1992-11-24 Hitachi, Ltd. Semiconductor Schottky barrier device with pn junctions
JPH03225870A (en) 1990-01-31 1991-10-04 Toshiba Corp Manufacture of heterojunction bipolar transistor
US5210051A (en) 1990-03-27 1993-05-11 Cree Research, Inc. High efficiency light emitting diodes from bipolar gallium nitride
JP2542448B2 (en) 1990-05-24 1996-10-09 シャープ株式会社 Field effect transistor and method of manufacturing the same
US5292501A (en) 1990-06-25 1994-03-08 Degenhardt Charles R Use of a carboxy-substituted polymer to inhibit plaque formation without tooth staining
US5200022A (en) 1990-10-03 1993-04-06 Cree Research, Inc. Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon carbide thereon and resulting product
US5345100A (en) 1991-03-29 1994-09-06 Shindengen Electric Manufacturing Co., Ltd. Semiconductor rectifier having high breakdown voltage and high speed operation
JPH04302172A (en) 1991-03-29 1992-10-26 Kobe Steel Ltd Diamond schottky diode
US5262669A (en) 1991-04-19 1993-11-16 Shindengen Electric Manufacturing Co., Ltd. Semiconductor rectifier having high breakdown voltage and high speed operation
US5192987A (en) 1991-05-17 1993-03-09 Apa Optics, Inc. High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions
US5270554A (en) 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
US5155289A (en) 1991-07-01 1992-10-13 General Atomics High-voltage solid-state switching devices
US5170455A (en) 1991-10-30 1992-12-08 At&T Bell Laboratories Optical connective device
US5242841A (en) 1992-03-25 1993-09-07 Texas Instruments Incorporated Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate
US6344663B1 (en) 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
US5459107A (en) 1992-06-05 1995-10-17 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5612260A (en) 1992-06-05 1997-03-18 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5726463A (en) 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
US5587870A (en) 1992-09-17 1996-12-24 Research Foundation Of State University Of New York Nanocrystalline layer thin film capacitors
JP3146694B2 (en) 1992-11-12 2001-03-19 富士電機株式会社 Silicon carbide MOSFET and method of manufacturing silicon carbide MOSFET
US5506421A (en) 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
KR100305123B1 (en) 1992-12-11 2001-11-22 비센트 비.인그라시아, 알크 엠 아헨 Static Random Access Memory Cells and Semiconductor Devices Containing These
US5342803A (en) 1993-02-03 1994-08-30 Rohm, Co., Ltd. Method for isolating circuit elements for semiconductor device
JP3117831B2 (en) 1993-02-17 2000-12-18 シャープ株式会社 Semiconductor device
JPH0799312A (en) 1993-02-22 1995-04-11 Texas Instr Inc <Ti> Semiconductor device and its manufacturing process
JPH06268227A (en) 1993-03-10 1994-09-22 Hitachi Ltd Insulated gate bipolar transistor
JP2811526B2 (en) 1993-04-19 1998-10-15 東洋電機製造株式会社 Static induction semiconductor device with static induction Schottky short circuit
US6097046A (en) 1993-04-30 2000-08-01 Texas Instruments Incorporated Vertical field effect transistor and diode
US5371383A (en) 1993-05-14 1994-12-06 Kobe Steel Usa Inc. Highly oriented diamond film field-effect transistor
US5539217A (en) 1993-08-09 1996-07-23 Cree Research, Inc. Silicon carbide thyristor
US5479316A (en) 1993-08-24 1995-12-26 Analog Devices, Inc. Integrated circuit metal-oxide-metal capacitor and method of making same
JPH07122749A (en) 1993-09-01 1995-05-12 Toshiba Corp Semiconductor device and its manufacture
US5510630A (en) 1993-10-18 1996-04-23 Westinghouse Electric Corporation Non-volatile random access memory cell constructed of silicon carbide
US5393993A (en) 1993-12-13 1995-02-28 Cree Research, Inc. Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices
US5396085A (en) 1993-12-28 1995-03-07 North Carolina State University Silicon carbide switching device with rectifying-gate
JPH07221327A (en) 1994-02-01 1995-08-18 Murata Mfg Co Ltd Semiconductor device
US5385855A (en) 1994-02-24 1995-01-31 General Electric Company Fabrication of silicon carbide integrated circuits
US5399887A (en) 1994-05-03 1995-03-21 Motorola, Inc. Modulation doped field effect transistor
US5488236A (en) 1994-05-26 1996-01-30 North Carolina State University Latch-up resistant bipolar transistor with trench IGFET and buried collector
CN1040814C (en) 1994-07-20 1998-11-18 电子科技大学 Surface withstand voltage zone for semiconductor device
TW286435B (en) 1994-07-27 1996-09-21 Siemens Ag
US5523589A (en) 1994-09-20 1996-06-04 Cree Research, Inc. Vertical geometry light emitting diode with group III nitride active layer and extended lifetime
JPH0897441A (en) 1994-09-26 1996-04-12 Fuji Electric Co Ltd Manufacture of silicon carbide schottky diode
JPH08213607A (en) 1995-02-08 1996-08-20 Ngk Insulators Ltd Semiconductor device and its manufacturing method
US5510281A (en) 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
JP3521246B2 (en) 1995-03-27 2004-04-19 沖電気工業株式会社 Field effect transistor and method of manufacturing the same
DE69512021T2 (en) 1995-03-31 2000-05-04 Cons Ric Microelettronica DMOS array structure and method of manufacture
SE9501310D0 (en) 1995-04-10 1995-04-10 Abb Research Ltd A method for introducing an impurity dopant into SiC, a semiconductor device formed by the method and using a highly doped amorphous layer as a source for dopant diffusion into SiC
US6057352A (en) 1995-05-17 2000-05-02 E. I. Du Pont De Nemours And Company Fungicidal cyclic amides
JPH08316164A (en) 1995-05-17 1996-11-29 Hitachi Ltd Manufacture of semiconductor element
US5734180A (en) 1995-06-02 1998-03-31 Texas Instruments Incorporated High-performance high-voltage device structures
US6078090A (en) 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
JP3555250B2 (en) 1995-06-23 2004-08-18 株式会社デンソー Automotive alternators and Schottky barrier diodes
US6693310B1 (en) 1995-07-19 2004-02-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
DE19530525A1 (en) 1995-08-19 1997-02-20 Daimler Benz Ag Circuit with monolithically integrated PIN / Schottky diode arrangement
US5967795A (en) 1995-08-30 1999-10-19 Asea Brown Boveri Ab SiC semiconductor device comprising a pn junction with a voltage absorbing edge
US6573534B1 (en) 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
FR2738394B1 (en) 1995-09-06 1998-06-26 Nippon Denso Co SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF
JPH11261061A (en) 1998-03-11 1999-09-24 Denso Corp Silicon carbide semiconductor device and its manufacture
JP4001960B2 (en) 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド Method for manufacturing a semiconductor device having a nitrided oxide dielectric layer
US5972801A (en) 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
US6136728A (en) 1996-01-05 2000-10-24 Yale University Water vapor annealing process
US6133587A (en) 1996-01-23 2000-10-17 Denso Corporation Silicon carbide semiconductor device and process for manufacturing same
JPH09205202A (en) 1996-01-26 1997-08-05 Matsushita Electric Works Ltd Semiconductor device
SE9601174D0 (en) 1996-03-27 1996-03-27 Abb Research Ltd A method for producing a semiconductor device having a semiconductor layer of SiC and such a device
US5877045A (en) 1996-04-10 1999-03-02 Lsi Logic Corporation Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition
US5612567A (en) 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
US5719409A (en) 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5763905A (en) 1996-07-09 1998-06-09 Abb Research Ltd. Semiconductor device having a passivation layer
SE9602745D0 (en) 1996-07-11 1996-07-11 Abb Research Ltd A method for producing a channel region layer in a SiC layer for a voltage controlled semiconductor device
US6002159A (en) 1996-07-16 1999-12-14 Abb Research Ltd. SiC semiconductor device comprising a pn junction with a voltage absorbing edge
US5917203A (en) 1996-07-29 1999-06-29 Motorola, Inc. Lateral gate vertical drift region transistor
SE9602993D0 (en) 1996-08-16 1996-08-16 Abb Research Ltd A bipolar semiconductor device having semiconductor layers of SiC and a method for producing a semiconductor device of SiC
DE19633184B4 (en) 1996-08-17 2006-10-05 Daimlerchrysler Ag Process for producing a semiconductor device with impurities introduced by ion implantation
DE19633183A1 (en) 1996-08-17 1998-02-19 Daimler Benz Ag Semiconductor component with foreign atoms introduced by ion implantation and method for its production
US5939763A (en) 1996-09-05 1999-08-17 Advanced Micro Devices, Inc. Ultrathin oxynitride structure and process for VLSI applications
EP0837508A3 (en) 1996-10-18 1999-01-20 Hitachi, Ltd. Semiconductor device and electric power conversion apparatus therewith
US6028012A (en) 1996-12-04 2000-02-22 Yale University Process for forming a gate-quality insulating layer on a silicon carbide substrate
US5837572A (en) 1997-01-10 1998-11-17 Advanced Micro Devices, Inc. CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein
SE9700141D0 (en) 1997-01-20 1997-01-20 Abb Research Ltd A schottky diode of SiC and a method of production thereof
SE9700156D0 (en) 1997-01-21 1997-01-21 Abb Research Ltd Junction termination for Si C Schottky diode
US6180958B1 (en) 1997-02-07 2001-01-30 James Albert Cooper, Jr. Structure for increasing the maximum voltage of silicon carbide power transistors
JP3206727B2 (en) 1997-02-20 2001-09-10 富士電機株式会社 Silicon carbide vertical MOSFET and method of manufacturing the same
DE19809554B4 (en) 1997-03-05 2008-04-03 Denso Corp., Kariya silicon carbide semiconductor device
EP0865085A1 (en) 1997-03-11 1998-09-16 STMicroelectronics S.r.l. Insulated gate bipolar transistor with high dynamic ruggedness
JPH10284718A (en) 1997-04-08 1998-10-23 Fuji Electric Co Ltd Insulated gate type thyristor
JP3287269B2 (en) 1997-06-02 2002-06-04 富士電機株式会社 Diode and manufacturing method thereof
DE19723176C1 (en) 1997-06-03 1998-08-27 Daimler Benz Ag Semiconductor device with alternate p-n and Schottky junctions
US5969378A (en) 1997-06-12 1999-10-19 Cree Research, Inc. Latch-up free power UMOS-bipolar transistor
US6121633A (en) 1997-06-12 2000-09-19 Cree Research, Inc. Latch-up free power MOS-bipolar transistor
JP3618517B2 (en) 1997-06-18 2005-02-09 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US6063698A (en) 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5877041A (en) 1997-06-30 1999-03-02 Harris Corporation Self-aligned power field effect transistor in silicon carbide
DE19832329A1 (en) 1997-07-31 1999-02-04 Siemens Ag Silicon carbide semiconductor structure manufacturing method
JP3180895B2 (en) 1997-08-18 2001-06-25 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device
WO1999009598A1 (en) 1997-08-20 1999-02-25 Siemens Aktiengesellschaft Semiconductor structure comprising an alpha silicon carbide zone, and use of said semiconductor structure
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
EP1018163A1 (en) 1997-09-10 2000-07-12 Infineon Technologies AG Semiconductor component with a drift zone
SE9704150D0 (en) 1997-11-13 1997-11-13 Abb Research Ltd Semiconductor device of SiC with insulating layer a refractory metal nitride layer
JP3085272B2 (en) 1997-12-19 2000-09-04 富士電機株式会社 Method for forming thermal oxide film on silicon carbide semiconductor device
JPH11191559A (en) 1997-12-26 1999-07-13 Matsushita Electric Works Ltd Manufacture of mosfet
JPH11251592A (en) 1998-01-05 1999-09-07 Denso Corp Carbon silicon semiconductor device
JP3216804B2 (en) 1998-01-06 2001-10-09 富士電機株式会社 Manufacturing method of silicon carbide vertical FET and silicon carbide vertical FET
JPH11266017A (en) 1998-01-14 1999-09-28 Denso Corp Silicon carbide semiconductor device and manufacture thereof
JPH11238742A (en) 1998-02-23 1999-08-31 Denso Corp Manufacture of silicon carbide semiconductor device
EP1062692A1 (en) 1998-03-09 2000-12-27 Harris Corporation Devices formable by low temperature direct bonding
JP3893725B2 (en) 1998-03-25 2007-03-14 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JPH11330468A (en) 1998-05-20 1999-11-30 Hitachi Ltd Manufacture of semiconductor integrated circuit device
US6627539B1 (en) 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6107142A (en) 1998-06-08 2000-08-22 Cree Research, Inc. Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion
US6100169A (en) 1998-06-08 2000-08-08 Cree, Inc. Methods of fabricating silicon carbide power devices by controlled annealing
US6316793B1 (en) 1998-06-12 2001-11-13 Cree, Inc. Nitride based transistors on semi-insulating silicon carbide substrates
JP4123636B2 (en) 1998-06-22 2008-07-23 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US5960289A (en) 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
JP3959856B2 (en) 1998-07-31 2007-08-15 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6221700B1 (en) 1998-07-31 2001-04-24 Denso Corporation Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities
JP2000106371A (en) 1998-07-31 2000-04-11 Denso Corp Fabrication of silicon carbide semiconductor device
US6246076B1 (en) 1998-08-28 2001-06-12 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
US6972436B2 (en) 1998-08-28 2005-12-06 Cree, Inc. High voltage, high temperature capacitor and interconnection structures
JP3616258B2 (en) 1998-08-28 2005-02-02 株式会社ルネサステクノロジ Schottky diode and power converter using the same
SE9802909L (en) 1998-08-31 1999-10-13 Abb Research Ltd Method for preparing a pn junction for a SiC semiconductor device and a SiC semiconductor pn junction device
JP2000133633A (en) 1998-09-09 2000-05-12 Texas Instr Inc <Ti> Etching of material using hard mask and plasma activating etchant
JP3361062B2 (en) 1998-09-17 2003-01-07 株式会社東芝 Semiconductor device
JP4186337B2 (en) 1998-09-30 2008-11-26 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6048766A (en) 1998-10-14 2000-04-11 Advanced Micro Devices Flash memory device having high permittivity stacked dielectric and fabrication thereof
US6204203B1 (en) 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control
US6239466B1 (en) 1998-12-04 2001-05-29 General Electric Company Insulated gate bipolar transistor for zero-voltage switching
US6190973B1 (en) 1998-12-18 2001-02-20 Zilog Inc. Method of fabricating a high quality thin oxide
JP2002535840A (en) 1999-01-12 2002-10-22 オイペツク オイロペーイツシエ ゲゼルシヤフト フユール ライスツングスハルプライター エムベーハー ウント コンパニイ コマンデイートゲゼルシヤフト Power semiconductor device with mesa edge
US6252288B1 (en) 1999-01-19 2001-06-26 Rockwell Science Center, Llc High power trench-based rectifier with improved reverse breakdown characteristic
US6228720B1 (en) 1999-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Method for making insulated-gate semiconductor element
JP3943749B2 (en) 1999-02-26 2007-07-11 株式会社日立製作所 Schottky barrier diode
JP3443589B2 (en) 1999-03-01 2003-09-02 独立行政法人産業技術総合研究所 Method for manufacturing semiconductor device
JP2000261006A (en) 1999-03-12 2000-09-22 Nippon Inter Electronics Corp Semiconductor substrate for forming schottky junction, semiconductor element using the same, and schottky battier diode
US6448160B1 (en) 1999-04-01 2002-09-10 Apd Semiconductor, Inc. Method of fabricating power rectifier device to vary operating parameters and resulting device
US6399996B1 (en) 1999-04-01 2002-06-04 Apd Semiconductor, Inc. Schottky diode having increased active surface area and method of fabrication
US6420225B1 (en) 1999-04-01 2002-07-16 Apd Semiconductor, Inc. Method of fabricating power rectifier device
US6238967B1 (en) 1999-04-12 2001-05-29 Motorola, Inc. Method of forming embedded DRAM structure
US6218680B1 (en) 1999-05-18 2001-04-17 Cree, Inc. Semi-insulating silicon carbide without vanadium domination
US6137139A (en) 1999-06-03 2000-10-24 Intersil Corporation Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery
JP2000349081A (en) 1999-06-07 2000-12-15 Sony Corp Method for formation of oxide film
US6218254B1 (en) 1999-09-22 2001-04-17 Cree Research, Inc. Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices
US6329675B2 (en) 1999-08-06 2001-12-11 Cree, Inc. Self-aligned bipolar junction silicon carbide transistors
US6365932B1 (en) 1999-08-20 2002-04-02 Denso Corporation Power MOS transistor
JP3630594B2 (en) 1999-09-14 2005-03-16 株式会社日立製作所 SiC Schottky diode
JP4192353B2 (en) 1999-09-21 2008-12-10 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
ATE288623T1 (en) 1999-09-22 2005-02-15 Siced Elect Dev Gmbh & Co Kg SIC SEMICONDUCTOR DEVICE WITH A SCHOTTKY CONTACT AND METHOD FOR THE PRODUCTION THEREOF
US6373076B1 (en) 1999-12-07 2002-04-16 Philips Electronics North America Corporation Passivated silicon carbide devices with low leakage current and method of fabricating
US6303508B1 (en) 1999-12-16 2001-10-16 Philips Electronics North America Corporation Superior silicon carbide integrated circuits and method of fabricating
US7186609B2 (en) 1999-12-30 2007-03-06 Siliconix Incorporated Method of fabricating trench junction barrier rectifier
US6703642B1 (en) 2000-02-08 2004-03-09 The United States Of America As Represented By The Secretary Of The Army Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state
US7125786B2 (en) 2000-04-11 2006-10-24 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
US6475889B1 (en) 2000-04-11 2002-11-05 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
US6784486B2 (en) 2000-06-23 2004-08-31 Silicon Semiconductor Corporation Vertical power devices having retrograded-doped transition regions therein
JP3523156B2 (en) 2000-06-30 2004-04-26 株式会社東芝 Semiconductor device and manufacturing method thereof
US6429041B1 (en) 2000-07-13 2002-08-06 Cree, Inc. Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation
DE10036208B4 (en) 2000-07-25 2007-04-19 Siced Electronics Development Gmbh & Co. Kg Semiconductor structure with buried island area and contact area
US6956238B2 (en) 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
US6767843B2 (en) 2000-10-03 2004-07-27 Cree, Inc. Method of N2O growth of an oxide layer on a silicon carbide layer
US7067176B2 (en) 2000-10-03 2006-06-27 Cree, Inc. Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
US6610366B2 (en) 2000-10-03 2003-08-26 Cree, Inc. Method of N2O annealing an oxide layer on a silicon carbide layer
US6593620B1 (en) 2000-10-06 2003-07-15 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
JP3881840B2 (en) 2000-11-14 2007-02-14 独立行政法人産業技術総合研究所 Semiconductor device
US6548333B2 (en) 2000-12-01 2003-04-15 Cree, Inc. Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
JP3940560B2 (en) 2001-01-25 2007-07-04 独立行政法人産業技術総合研究所 Manufacturing method of semiconductor device
US6551865B2 (en) 2001-03-30 2003-04-22 Denso Corporation Silicon carbide semiconductor device and method of fabricating the same
JP4892787B2 (en) 2001-04-09 2012-03-07 株式会社デンソー Schottky diode and manufacturing method thereof
US6524900B2 (en) 2001-07-25 2003-02-25 Abb Research, Ltd Method concerning a junction barrier Schottky diode, such a diode and use thereof
US20030025175A1 (en) 2001-07-27 2003-02-06 Sanyo Electric Company, Ltd. Schottky barrier diode
JP4026339B2 (en) 2001-09-06 2007-12-26 豊田合成株式会社 SiC electrode and manufacturing method thereof
JP4064085B2 (en) 2001-10-18 2008-03-19 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP3559971B2 (en) 2001-12-11 2004-09-02 日産自動車株式会社 Silicon carbide semiconductor device and method of manufacturing the same
JP4044332B2 (en) 2001-12-26 2008-02-06 関西電力株式会社 High voltage semiconductor device
JP3778153B2 (en) 2002-02-19 2006-05-24 日産自動車株式会社 Silicon carbide Schottky diode and manufacturing method thereof
US6855970B2 (en) 2002-03-25 2005-02-15 Kabushiki Kaisha Toshiba High-breakdown-voltage semiconductor device
DE10392870B4 (en) 2002-06-28 2009-07-30 National Institute Of Advanced Industrial Science And Technology Semiconductor production comprises forming gate insulating film on semiconductor region, forming gate electrode on insulating film and forming electrode in semiconductor region
JP4319810B2 (en) 2002-07-16 2009-08-26 日本インター株式会社 Semiconductor device and manufacturing method thereof
SE525574C2 (en) 2002-08-30 2005-03-15 Okmetic Oyj Low-doped silicon carbide substrate and its use in high-voltage components
JP4086602B2 (en) 2002-09-17 2008-05-14 株式会社日立製作所 Control device and control method for multi-cylinder engine
US7217950B2 (en) 2002-10-11 2007-05-15 Nissan Motor Co., Ltd. Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
US7132321B2 (en) 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch
DE10259373B4 (en) 2002-12-18 2012-03-22 Infineon Technologies Ag Overcurrent Schottky diode with low reverse current
US7221010B2 (en) 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US7026650B2 (en) 2003-01-15 2006-04-11 Cree, Inc. Multiple floating guard ring edge termination for silicon carbide devices
JP2004247545A (en) 2003-02-14 2004-09-02 Nissan Motor Co Ltd Semiconductor device and its fabrication process
WO2004079789A2 (en) 2003-03-05 2004-09-16 Rensselaer Polytechnic Institute Interstage isolation in darlington transistors
US7217954B2 (en) 2003-03-18 2007-05-15 Matsushita Electric Industrial Co., Ltd. Silicon carbide semiconductor device and method for fabricating the same
KR100900562B1 (en) 2003-03-24 2009-06-02 페어차일드코리아반도체 주식회사 MOS-gated transistor having improved UIS capability
US6979863B2 (en) 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7074643B2 (en) 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
US20050012143A1 (en) 2003-06-24 2005-01-20 Hideaki Tanaka Semiconductor device and method of manufacturing the same
US7138668B2 (en) 2003-07-30 2006-11-21 Nissan Motor Co., Ltd. Heterojunction diode with reduced leakage current
JP2005057080A (en) 2003-08-05 2005-03-03 Nippon Inter Electronics Corp Semiconductor device
US20050104072A1 (en) 2003-08-14 2005-05-19 Slater David B.Jr. Localized annealing of metal-silicon carbide ohmic contacts and devices so formed
US7973381B2 (en) 2003-09-08 2011-07-05 International Rectifier Corporation Thick field oxide termination for trench schottky device
US7018554B2 (en) 2003-09-22 2006-03-28 Cree, Inc. Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices
CA2545628A1 (en) 2003-11-12 2005-05-26 Cree, Inc. Methods of processing semiconductor wafer backsides having light emitting devices (leds) thereon and leds so formed
JP2005167035A (en) 2003-12-03 2005-06-23 Kansai Electric Power Co Inc:The Silicon carbide semiconductor device and manufacturing method thereof
WO2005065385A2 (en) 2003-12-30 2005-07-21 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7005333B2 (en) 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US7407837B2 (en) 2004-01-27 2008-08-05 Fuji Electric Holdings Co., Ltd. Method of manufacturing silicon carbide semiconductor device
JP2005303027A (en) 2004-04-13 2005-10-27 Nissan Motor Co Ltd Semiconductor device
DE102005017814B4 (en) 2004-04-19 2016-08-11 Denso Corporation Silicon carbide semiconductor device and process for its production
US7071518B2 (en) 2004-05-28 2006-07-04 Freescale Semiconductor, Inc. Schottky device
US7118970B2 (en) 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
EP1779435B8 (en) 2004-07-08 2012-03-07 Ss Sc Ip, Llc Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same
EP1619276B1 (en) 2004-07-19 2017-01-11 Norstel AB Homoepitaxial growth of SiC on low off-axis SiC wafers
US20060211210A1 (en) 2004-08-27 2006-09-21 Rensselaer Polytechnic Institute Material for selective deposition and etching
JP4777630B2 (en) 2004-09-21 2011-09-21 株式会社日立製作所 Semiconductor device
JP3914226B2 (en) 2004-09-29 2007-05-16 株式会社東芝 High voltage semiconductor device
JP4954463B2 (en) 2004-10-22 2012-06-13 三菱電機株式会社 Schottky barrier diode
JP4899405B2 (en) 2004-11-08 2012-03-21 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
DE102004053761A1 (en) * 2004-11-08 2006-05-18 Robert Bosch Gmbh Semiconductor device and method for its production
US7304363B1 (en) 2004-11-26 2007-12-04 United States Of America As Represented By The Secretary Of The Army Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device
US7247550B2 (en) 2005-02-08 2007-07-24 Teledyne Licensing, Llc Silicon carbide-based device contact and contact fabrication method
US7737522B2 (en) 2005-02-11 2010-06-15 Alpha & Omega Semiconductor, Ltd. Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction
US9419092B2 (en) 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US7544963B2 (en) 2005-04-29 2009-06-09 Cree, Inc. Binary group III-nitride based high electron mobility transistors
US7615774B2 (en) 2005-04-29 2009-11-10 Cree.Inc. Aluminum free group III-nitride based high electron mobility transistors
US7679223B2 (en) 2005-05-13 2010-03-16 Cree, Inc. Optically triggered wide bandgap bipolar power switching devices and circuits
US7414268B2 (en) 2005-05-18 2008-08-19 Cree, Inc. High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities
JP4942134B2 (en) 2005-05-20 2012-05-30 日産自動車株式会社 Method for manufacturing silicon carbide semiconductor device
US7528040B2 (en) 2005-05-24 2009-05-05 Cree, Inc. Methods of fabricating silicon carbide devices having smooth channels
US20060267021A1 (en) 2005-05-27 2006-11-30 General Electric Company Power devices and methods of manufacture
JP4777699B2 (en) 2005-06-13 2011-09-21 本田技研工業株式会社 Bipolar semiconductor device and manufacturing method thereof
GB0512095D0 (en) 2005-06-14 2005-07-20 Unilever Plc Fabric softening composition
US7548112B2 (en) 2005-07-21 2009-06-16 Cree, Inc. Switch mode power amplifier using MIS-HEMT with field plate extension
JP2007036052A (en) 2005-07-28 2007-02-08 Toshiba Corp Semiconductor rectifier element
JP5303819B2 (en) 2005-08-05 2013-10-02 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
EP2546865B1 (en) 2005-09-16 2023-12-06 Wolfspeed, Inc. Methods of processing semiconductor wafers having silicon carbide power devices thereon
US7304334B2 (en) 2005-09-16 2007-12-04 Cree, Inc. Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same
JP2007103784A (en) 2005-10-06 2007-04-19 Matsushita Electric Ind Co Ltd Hetero-junction bipolar transistor
US7345310B2 (en) 2005-12-22 2008-03-18 Cree, Inc. Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
JP2007220889A (en) 2006-02-16 2007-08-30 Central Res Inst Of Electric Power Ind Schottky junction semiconductor device and its manufacturing method
JP4257921B2 (en) 2006-03-02 2009-04-30 シャープ株式会社 Foldable portable electronic device
JP4781850B2 (en) 2006-03-03 2011-09-28 ナップエンタープライズ株式会社 Voice input ear microphone
US20070228505A1 (en) 2006-04-04 2007-10-04 Mazzola Michael S Junction barrier schottky rectifiers having epitaxially grown p+-n junctions and methods of making
JP2007305609A (en) * 2006-04-10 2007-11-22 Matsushita Electric Ind Co Ltd Semiconductor device
JP5560519B2 (en) 2006-04-11 2014-07-30 日産自動車株式会社 Semiconductor device and manufacturing method thereof
JP2007287782A (en) 2006-04-13 2007-11-01 Hitachi Ltd Mesa bipolar transistor
US7728403B2 (en) 2006-05-31 2010-06-01 Cree Sweden Ab Semiconductor device
US7372087B2 (en) 2006-06-01 2008-05-13 Northrop Grumman Corporation Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage
US7883949B2 (en) 2006-06-29 2011-02-08 Cree, Inc Methods of forming silicon carbide switching devices including P-type channels
JP4921880B2 (en) 2006-07-28 2012-04-25 株式会社東芝 High voltage semiconductor device
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
EP2631951B1 (en) 2006-08-17 2017-10-11 Cree, Inc. High power insulated gate bipolar transistors
US7595241B2 (en) 2006-08-23 2009-09-29 General Electric Company Method for fabricating silicon carbide vertical MOSFET devices
JP5046083B2 (en) 2006-08-24 2012-10-10 独立行政法人産業技術総合研究所 Method for manufacturing silicon carbide semiconductor device
JP5098293B2 (en) 2006-10-30 2012-12-12 富士電機株式会社 Insulated gate type semiconductor device using wide band gap semiconductor and manufacturing method thereof
JP2008147362A (en) 2006-12-08 2008-06-26 Toyota Central R&D Labs Inc Semiconductor device
JP4314277B2 (en) 2007-01-11 2009-08-12 株式会社東芝 SiC Schottky barrier semiconductor device
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
JP4450241B2 (en) 2007-03-20 2010-04-14 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JP4620075B2 (en) 2007-04-03 2011-01-26 株式会社東芝 Power semiconductor device
JP4356767B2 (en) 2007-05-10 2009-11-04 株式会社デンソー Silicon carbide semiconductor device having junction barrier Schottky diode
US8866150B2 (en) 2007-05-31 2014-10-21 Cree, Inc. Silicon carbide power devices including P-type epitaxial layers and direct ohmic contacts
JP4539684B2 (en) 2007-06-21 2010-09-08 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP4333782B2 (en) 2007-07-05 2009-09-16 株式会社デンソー Silicon carbide semiconductor device having junction barrier Schottky diode
US7687825B2 (en) 2007-09-18 2010-03-30 Cree, Inc. Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication
US8492771B2 (en) 2007-09-27 2013-07-23 Infineon Technologies Austria Ag Heterojunction semiconductor device and method
KR101494935B1 (en) 2007-11-09 2015-02-23 크리,인코포레이티드 Power semiconductor devices with mesa structures and buffer layers including mesa steps
JP2009141062A (en) 2007-12-05 2009-06-25 Panasonic Corp Semiconductor device and manufacturing method thereof
US7989882B2 (en) 2007-12-07 2011-08-02 Cree, Inc. Transistor with A-face conductive channel and trench protecting well region
JP2009177028A (en) 2008-01-25 2009-08-06 Toshiba Corp Semiconductor apparatus
US9640609B2 (en) 2008-02-26 2017-05-02 Cree, Inc. Double guard ring edge termination for silicon carbide devices
JP5361861B2 (en) 2008-03-17 2013-12-04 三菱電機株式会社 Semiconductor device
US7851881B1 (en) 2008-03-21 2010-12-14 Microsemi Corporation Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode
US7842590B2 (en) 2008-04-28 2010-11-30 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate including laser annealing
JP5415018B2 (en) 2008-05-13 2014-02-12 新電元工業株式会社 Semiconductor device
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8097919B2 (en) 2008-08-11 2012-01-17 Cree, Inc. Mesa termination structures for power semiconductor devices including mesa step buffers
US8497552B2 (en) 2008-12-01 2013-07-30 Cree, Inc. Semiconductor devices with current shifting regions and related methods
US8536582B2 (en) 2008-12-01 2013-09-17 Cree, Inc. Stable power devices on low-angle off-cut silicon carbide crystals
US8288220B2 (en) 2009-03-27 2012-10-16 Cree, Inc. Methods of forming semiconductor devices including epitaxial layers and related structures
US20100277839A1 (en) 2009-04-29 2010-11-04 Agilent Technologies, Inc. Overpower protection circuit
JP5600411B2 (en) 2009-10-28 2014-10-01 三菱電機株式会社 Silicon carbide semiconductor device
US8372738B2 (en) 2009-10-30 2013-02-12 Alpha & Omega Semiconductor, Inc. Method for manufacturing a gallium nitride based semiconductor device with improved termination scheme
JP2011171551A (en) 2010-02-19 2011-09-01 Toyota Motor Corp Method of manufacturing semiconductor device
US8704292B2 (en) 2010-02-23 2014-04-22 Donald R. Disney Vertical capacitive depletion field effect transistor
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9557895B2 (en) 2011-01-27 2017-01-31 Hewlett Packard Enterprise Development Lp Electronic book with changeable paths
JP6139524B2 (en) 2011-08-04 2017-05-31 スリーエム イノベイティブ プロパティズ カンパニー Barrier assembly
US8680587B2 (en) * 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766433A (en) 1993-08-26 1995-03-10 Hitachi Ltd Semiconductor rectifier element
US7183575B2 (en) 2002-02-19 2007-02-27 Nissan Motor Co., Ltd. High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode
US20060255423A1 (en) * 2005-05-11 2006-11-16 Sei-Hyung Ryu Silicon carbide junction barrier schottky diodes with supressed minority carrier injection
US20080121993A1 (en) * 2006-11-03 2008-05-29 Allen Hefner Power switching semiconductor devices including rectifying junction-shunts
US20080191304A1 (en) * 2007-02-09 2008-08-14 Cree, Inc. Schottky Diode Structure with Silicon Mesa and Junction Barrier Schottky Wells
US20080296587A1 (en) * 2007-05-30 2008-12-04 Denso Corporation Silicon carbide semiconductor device having junction barrier schottky diode

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2545587A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013140824A (en) * 2011-12-28 2013-07-18 Rohm Co Ltd Semiconductor device and method of manufacturing the same
EP3051593A1 (en) * 2015-01-30 2016-08-03 Nxp B.V. Semiconductor device
US9735290B2 (en) 2015-01-30 2017-08-15 Nexperia B.V. Semiconductor device
EP3540780A1 (en) * 2018-03-17 2019-09-18 Ixys, Llc Embedded field plate field effect transistor
US11239323B2 (en) 2018-08-22 2022-02-01 Mitsubishi Electric Corporation Oxide semiconductor device and method for manufacturing same

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