WO2011087514A1 - Etch stop microcrystalline thin film transistor - Google Patents

Etch stop microcrystalline thin film transistor Download PDF

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Publication number
WO2011087514A1
WO2011087514A1 PCT/US2010/021323 US2010021323W WO2011087514A1 WO 2011087514 A1 WO2011087514 A1 WO 2011087514A1 US 2010021323 W US2010021323 W US 2010021323W WO 2011087514 A1 WO2011087514 A1 WO 2011087514A1
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WO
WIPO (PCT)
Prior art keywords
silicon layer
layer
etch stop
amorphous silicon
depositing
Prior art date
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PCT/US2010/021323
Other languages
French (fr)
Inventor
Helinda Nominanda
Tae Kyung Won
Soo Young Choi
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Applied Materials, Inc.
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Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to PCT/US2010/021323 priority Critical patent/WO2011087514A1/en
Priority to TW099103391A priority patent/TW201126613A/en
Publication of WO2011087514A1 publication Critical patent/WO2011087514A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • Embodiments of the present invention generally relate to a thin film transistor (TFT) and methods for its fabrication.
  • TFT thin film transistor
  • LCDs Liquid Crystal Displays
  • TFTs have been used to separately address the pixels of the LCD at very fast rates.
  • the modern display panel there are millions of pixels which each are separately addressed by a corresponding TFT.
  • a bottom gate TFT contains a gate electrode formed over a substrate, a gate dielectric layer formed over the gate electrode, an active material layer such as microcrystalline silicon, a doped amorphous silicon layer as the ohmic contact, and source and drain electrodes.
  • the active material permits the current to pass from the source to the drain electrode whenever the gate electrode is turned on. Once the current passes to the drain electrode, the pixel is addressed.
  • the bottom gate TFT oftentimes has an etch stop structure over the active channel between the source and drain electrodes.
  • the etch stop structure is formed by depositing an etch stop material layer over the active material layer and then etching the etch stop material layer.
  • the etch stop material layer is etched, the underlying microcrystalline silicon layer may be damaged. The damage to the microcrystalline silicon layer may result in a high subthreshold slope for the TFT. [0005] Therefore, there is a need in the art for a bottom gate TFT having an etch stop structure that has a lower subthreshold slope.
  • the present invention generally relates to a TFT and methods for its fabrication.
  • Some TFTs have an etch stop structure formed thereon in the active channel.
  • the etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and depositing an etch stop layer over the amorphous silicon layer. The method also includes etching the etch stop layer to form an etch stop structure and expose at least a portion of the amorphous silicon layer. The method also includes depositing a doped amorphous silicon layer over the amorphous silicon layer and the etch stop structure.
  • a metal contact layer may be deposited over the doped amorphous silicon layer, the metal contact layer may be etched to form a source electrode and a drain electrode and the doped amorphous silicon layer may be etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode may be formed over a substrate and a gate dielectric layer may be deposited over the gate electrode and the substrate.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an etch stop layer over the first microcrystalline silicon layer, and etching the etch stop layer to form an etch stop structure.
  • the method also includes depositing a doped amorphous silicon layer over the first microcrystalline silicon layer and the etch stop structure.
  • the doped amorphous silicon layer has a resistivity of less than 1 ohm-cm.
  • a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and exposing the amorphous silicon layer to a plasma containing an element selected from the group consisting of hydrogen, nitrogen, and combinations thereof.
  • the method also includes depositing an etch stop layer over the first microcrystalline silicon layer, etching the etch stop layer to form an etch stop structure, and depositing a doped amorphous silicon layer over the etch stop structure.
  • a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
  • FIGS 1A-1G show a TFT 100 at various stages of production according to one embodiment.
  • FIG. 2 is a schematic cross sectional view of a TFT 200 according to another embodiment.
  • Figure 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs.
  • Figure 4 is a graph showing the drain current compared to the gate voltage applied for two separate TFTs that have ohmic contact layers with different resistivities.
  • Figure 5 is a graph showing the drain current compared to the gate voltage applied for three separate TFTs having different plasma treatments.
  • the present invention generally relates to a TFT and methods for its fabrication.
  • Some TFTs have an etch stop structure formed thereon in the active channel.
  • the etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.
  • PECVD plasma enhanced chemical vapor deposition
  • Figures 1A-1G show a TFT 100 at various stages of production according to one embodiment.
  • the substrate 102 may comprise a semiconductor substrate.
  • the substrate 102 may comprise a silicon substrate.
  • the substrate 102 may comprise germanium.
  • a thermal oxide layer that serves as an insulating material may be present over the substrate.
  • the thermal oxide layer may be about 10,000 angstroms thick.
  • a gate electrode 104 is formed over the substrate (and thermal oxide layer).
  • the gate electrode 104 is formed by depositing a layer, forming a mask thereover, etching the layer and removing the mask to leave the gate electrode 104.
  • the gate electrode 104 may comprise a metal.
  • the gate electrode 104 may comprise a metal selected from the group consisting of chromium, molybdenum, copper, titanium, tungsten, aluminum, and combinations thereof.
  • the layer for producing the gate electrode 104 may be deposited by physical vapor deposition (PVD).
  • the layer for producing the gate electrode 104 may be deposited by evaporation.
  • the layer for producing the gate electrode 104 may be deposited by electroplating. It is to be understood that other deposition methods may be used to deposit the layer for producing the gate electrode 104.
  • the gate electrode 104 may have a thickness of between about 2000 Angstroms to about 3000 Angstroms.
  • a gate dielectric layer 106 is formed over the gate electrode 104.
  • the gate dielectric layer 106 may be deposited by PECVD.
  • the gate dielectric layer 106 may be deposited by other chemical vapor deposition (CVD) methods. It is to be understood that other deposition methods may be utilized to deposit the gate dielectric layer 106.
  • the gate dielectric layer 106 may comprise an insulating material.
  • the gate dielectric layer 106 may comprise silicon nitride.
  • the gate dielectric layer 106 may comprise silicon oxynitride.
  • the gate dielectric layer 106 may comprise silicon oxide.
  • the gate dielectric layer 106 may comprise silicon dioxide. In one embodiment, the gate dielectric layer 106 may have a thickness of between about 1000 Angstroms to about 6000 Angstroms. In another embodiment, the thickness of the gate dielectric layer 106 may be between about 2000 Angstroms and about 4000 Angstroms. In one embodiment, the gate dielectric layer 106 may comprise multiple layers. When multiple layers are used for the gate dielectric layer 106, one of the layers may be a high deposition rate material, such as silicon nitride with poor quality, and another of the layers may comprise a low deposition rate material, such as silicon nitride with high quality, to gain the throughput and the interface quality desired.
  • a microcrystalline silicon layer 108 may be deposited.
  • the microcrystalline silicon layer 108 may be deposited by PECVD. It is to be understood that the microcrystalline silicon layer 108 may be deposited by other deposition methods as well.
  • the microcrystalline silicon layer 108 may have a thickness of between about 300 Angstroms to about 3000 Angstroms.
  • the TFT will likely have a high subthreshold slope because of the etching of the etch stop layer.
  • the subthreshold slope may be lowered.
  • an amorphous silicon layer 110 may be deposited over the microcrystalline silicon layer 108.
  • the amorphous silicon layer 110 may be deposited by PECVD. It is to be understood that the amorphous silicon layer 110 may be deposited by other deposition methods as well.
  • the amorphous silicon layer 110 may have a thickness of between about 300 Angstroms to about 1000 Angstroms.
  • the amorphous silicon layer 110 significantly reduces the subthreshold slope and simultaneously improves the electrical performance of the TFT. Because the amorphous silicon layer 110 prevents the microcrystalline silicon layer 108 from exposure to the wet etching solution, damage to the microcrystalline silicon layer 108 is prevented.
  • an etch stop material layer 112 may be deposited thereover.
  • the etch stop material layer 112 may be formed by blanket depositing, followed by photoresist depositing, followed by pattern developing.
  • the etch stop material layer 112 may be patterned by wet etching to form an etch stop structure 114. It is to be understood that the etch stop material layer 112 may be etched by other etching methods such as dry or plasma etching.
  • the etch stop material layer 112 may comprise silicon nitride.
  • the etch stop material layer 112 may comprise silicon oxynitride.
  • the etch stop material layer 112 may comprise silicon oxide.
  • a doped amorphous silicon layer 1 6 may be deposited thereover.
  • a metal contact layer 118 may be deposited.
  • the metal contact layer 118 may comprise tungsten, molybdenum, titanium, chromium, aluminum, alloys thereof and combinations thereof.
  • the metal contact layer 18 may be deposited by well known deposition methods such as PVD.
  • the metal contact layer 118 is then patterned by forming a mask thereover, etching and removing the mask to leave a source electrode 122A and a drain electrode 122B.
  • the doped amorphous silicon layer 116 may be etched to form a first ohmic contact 120A and a second ohmic contact 120B.
  • FIG. 2 is a schematic cross sectional view of a TFT 200 according to another embodiment.
  • the TFT 200 includes a substrate 202, gate electrode 204, gate dielectric layer 206, microcrystalline silicon layer 210, amorphous silicon layer 212, etch stop structure 214, first ohmic contact 216A, second ohmic contact 216B, source electrode 218A, and drain electrode 218B.
  • the TFT 200 of Figure 2 may be formed in a similar manner to the TFT 100 discussed above and may comprise the same materials for the various layers as discussed above in reference to Figures 1A-1G.
  • the TFT 200 of Figure 2 has a second microcrystalline silicon layer 208.
  • the second microcrystalline silicon layer 208 is the interface microcrystalline silicon layer with general characteristics of no incubation layer and a column structure with high crystalline fraction.
  • Microcrystalline silicon layer 210 is the bulk microcrystalline silicon layer with no specific structure and low crystalline fraction.
  • FIG. 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs: single layer microcrystalline silicon without amorphous silicon, single layer microcrystalline silicon with amorphous silicon, multi-layer microcrystalline silicon without amorphous silicon, and multi-layer microcrystalline silicon with amorphous silicon.
  • Figure 3 when an amorphous silicon layer is used, the subthreshold slope is improved. Adding the amorphous silicon controls the damage on the contact areas and significantly reduces the subthreshold slope. The amorphous silicon also improves the electrical performance of the TFT. Table I below shows the values of the subthreshold slope, l off current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 3. TABLE I
  • Another problem that occurs in microcrystalline silicon based TFTs is a low field effect mobility.
  • a low resistivity (less than 1 ohm-cm) doped amorphous silicon layer may be used for the ohmic contact layer as opposed to one with a higher resistivity ( ⁇ 50 ohm- cm).
  • the average field effect mobility may be increased from 1.0 cm 2 /V-s to 2.1 cm 2 /V-s, for example.
  • a PECVD deposition method may be used whereby SiH 4 , H2, and PH3 may be delivered to the chamber while applying RF power to ignite a plasma.
  • the SiH 4 may be flowed at a rate of between about 10 seem and about 45 seem
  • the H 2 may be flowed at between about 2000 seem and about 3500 seem
  • the PH 3 may be flowed at between about 50 seem and about 85 seem into a chamber having a volume of greater than about 100000 cm 3 .
  • the substrate may be spaced between about 500 mils and about 600 mils from the showerhead.
  • the chamber may be maintained at a pressure of between about 2000 mTorr and about 3500 mTorr and the substrate may be maintained at between about 300 degrees Celsius and about 359 degrees Celsius.
  • the SiH 4 may be flowed at a rate of 30 seem, the H 2 may be flowed at 3000 seem and the PH 3 may be flowed at 70 seem into a chamber having a volume of greater than about 100000 cm 3 .
  • the substrate may be spaced 550 mils from the showerhead.
  • the chamber may be maintained at a pressure of 3000 mTorr and the substrate may be maintained at 325 degrees Celsius.
  • Figure 4 shows the improvement of the microcrystalline silicon TFT with doped amorphous silicon layer that has a resistivity of less than 1 ohm-cm relative to one with a resistivity of about 50 ohm-cm.
  • the relative low mobility of the microcrystalline silicon TFT is improved by using the low resistivity doped amorphous silicon film as the ohmic contact layer.
  • the low resistivity improves the overall source-drain contact resistance of the TFT.
  • Table II shows values of the subthreshold slope, l off current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 4.
  • the deposition rate for the doped amorphous silicon layer can simply be lowered. However, lowering the deposition rate will affect the substrate throughput.
  • Dual layer or multi-layer doped amorphous silicon may be used. The layer that contacts the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) may be deposited at a high rate and thus have a high resistivity while the layer that is in contact with the source and drain electrodes may be deposited at a low rate to have a low resistivity.
  • the dual or multi-layer doped amorphous silicon has the advantage of making a nice ohmic contact from the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) to the source and drain electrodes.
  • Another method to improve the microcrystalline silicon TFT is to use an H 2 or N 2 plasma pretreatment before the etch stop layer is deposited. Doing so will improve the l 0 ff, subthreshold slope, field effect mobility and threshold voltage. For example, the l 0 ff may be decreased by greater than 30 percent, the subthreshold slope may be decreased by greater than 10 percent, the threshold voltage may be decreased by -2V and the field effect mobility may be improved by greater than 10 percent.
  • the amorphous silicon layer that overlies the topmost microcrystalline silicon layer may be exposed to the plasma.
  • Figure 5 shows the improvement of the drain current versus gate voltage for three scenarios: no plasma treatment of the topmost silicon layer, exposure of the topmost silicon layer to an H 2 plasma, and exposure of the topmost silicon layer to N 2 plasma. Further electrical properties improvement can be achieved by the plasma treatment before the etch stop material layer deposition. The plasma is believed to improve the interface of the contact area between the active layers and the doped amorphous silicon layer used for the ohmic contact.
  • Table III shows the values of the subthreshold slope, l 0 f current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 5.
  • the H 2 gas may be flowed to the chamber at a rate of between about 5000 seem and about 7000 seem while between about 400 W and about 600 W are applied to the showerhead.
  • the chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr.
  • the substrate may be spaced between about 500 mils and about 700 mils from the showerhead and be exposed to the plasma for between about 40 seconds and about 75 seconds.
  • the H 2 gas may be flowed to the chamber at a rate of 6000 seem while 500 W is applied to the showerhead.
  • the chamber may be maintained at a pressure of 1500 mTorr.
  • the substrate may be spaced 700 mils from the showerhead and be exposed to the plasma for 60 seconds.
  • the chamber may have a volume of about 100000 cm 3 or more.
  • the N 2 gas may be flowed to the chamber at a rate of between about 2000 seem and about 3000 seem while between about 500 W and about 750 W are applied to the showerhead.
  • the chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr.
  • the substrate may be spaced between about 800 mils and about 1000 mils from the showerhead and be exposed to the plasma for between about 45 seconds and about 75 seconds.
  • the N 2 gas may be flowed to the chamber at a rate of 2500 seem while 700 W is applied to the showerhead.
  • the chamber may be maintained at a pressure of 1500 mTorr.
  • the substrate may be spaced 900 mils from the showerhead and be exposed to the plasma for 60 seconds.
  • the chamber may have a volume of about 100000 cm 3 or more.
  • the disclosure herein has described numerous techniques to advantageously improve microcrystalline silicon based etch stop TFTs.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the improved performance includes not only the mobility, but also the subthreshold slope.

Abstract

The present invention generally relates to a thin film transistor (TFT) and methods for its fabrication. Some TFTs have an etch stop structure formed thereon in the active channel. The etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.

Description

ETCH STOP MICROCRYSTALLINE THIN FILM TRANSISTOR
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] Embodiments of the present invention generally relate to a thin film transistor (TFT) and methods for its fabrication.
Description of the Related Art
[0002] Liquid Crystal Displays (LCDs) are highly utilized in the flat panel display industry. In an LCD, two glass plates are joined together with a layer of liquid crystal material sandwiched therebetween. The substrates are connected to a power source to change the orientation of the liquid crystal material. TFTs have been used to separately address the pixels of the LCD at very fast rates. In the modern display panel, there are millions of pixels which each are separately addressed by a corresponding TFT.
[0003] One of the types of TFTs that is used in LCD manufacturing is a bottom gate TFT. A bottom gate TFT contains a gate electrode formed over a substrate, a gate dielectric layer formed over the gate electrode, an active material layer such as microcrystalline silicon, a doped amorphous silicon layer as the ohmic contact, and source and drain electrodes. The active material permits the current to pass from the source to the drain electrode whenever the gate electrode is turned on. Once the current passes to the drain electrode, the pixel is addressed.
[0004] The bottom gate TFT oftentimes has an etch stop structure over the active channel between the source and drain electrodes. The etch stop structure is formed by depositing an etch stop material layer over the active material layer and then etching the etch stop material layer. When the etch stop material layer is etched, the underlying microcrystalline silicon layer may be damaged. The damage to the microcrystalline silicon layer may result in a high subthreshold slope for the TFT. [0005] Therefore, there is a need in the art for a bottom gate TFT having an etch stop structure that has a lower subthreshold slope.
SUMMARY OF THE INVENTION
[0006] The present invention generally relates to a TFT and methods for its fabrication. Some TFTs have an etch stop structure formed thereon in the active channel. The etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.
[0007] In one embodiment, a TFT fabrication method is disclosed that includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and depositing an etch stop layer over the amorphous silicon layer. The method also includes etching the etch stop layer to form an etch stop structure and expose at least a portion of the amorphous silicon layer. The method also includes depositing a doped amorphous silicon layer over the amorphous silicon layer and the etch stop structure. In another embodiment, a metal contact layer may be deposited over the doped amorphous silicon layer, the metal contact layer may be etched to form a source electrode and a drain electrode and the doped amorphous silicon layer may be etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure. In another embodiment, a gate electrode may be formed over a substrate and a gate dielectric layer may be deposited over the gate electrode and the substrate.
[0008] In another embodiment, a TFT fabrication method is disclosed that includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an etch stop layer over the first microcrystalline silicon layer, and etching the etch stop layer to form an etch stop structure. The method also includes depositing a doped amorphous silicon layer over the first microcrystalline silicon layer and the etch stop structure. The doped amorphous silicon layer has a resistivity of less than 1 ohm-cm. In another embodiment, a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure. In another embodiment, a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
[0009] In another embodiment, a TFT fabrication method is disclosed that includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and exposing the amorphous silicon layer to a plasma containing an element selected from the group consisting of hydrogen, nitrogen, and combinations thereof. The method also includes depositing an etch stop layer over the first microcrystalline silicon layer, etching the etch stop layer to form an etch stop structure, and depositing a doped amorphous silicon layer over the etch stop structure. In another embodiment, a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure. In another embodiment, a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0011] Figures 1A-1G show a TFT 100 at various stages of production according to one embodiment.
[0012] Figure 2 is a schematic cross sectional view of a TFT 200 according to another embodiment.
[0013] Figure 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs.
[0014] Figure 4 is a graph showing the drain current compared to the gate voltage applied for two separate TFTs that have ohmic contact layers with different resistivities.
[0015] Figure 5 is a graph showing the drain current compared to the gate voltage applied for three separate TFTs having different plasma treatments.
DETAILED DESCRIPTION
[0016] The present invention generally relates to a TFT and methods for its fabrication. Some TFTs have an etch stop structure formed thereon in the active channel. The etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT. [0017] The embodiments discussed herein may be practiced in numerous chambers such as a plasma enhanced chemical vapor deposition (PECVD) chamber manufactured and sold by AKT America, Inc., a subsidiary of Applied Materials, Inc., Santa Clara, CA. It is to be understood that the embodiments discussed herein may be practiced in other chambers, including those sold by other manufacturers.
[0018] Figures 1A-1G show a TFT 100 at various stages of production according to one embodiment. In one embodiment, the substrate 102 may comprise a semiconductor substrate. In another embodiment, the substrate 102 may comprise a silicon substrate. In another embodiment, the substrate 102 may comprise germanium. While not shown, a thermal oxide layer that serves as an insulating material may be present over the substrate. In one embodiment, the thermal oxide layer may be about 10,000 angstroms thick. Over the substrate (and thermal oxide layer), a gate electrode 104 is formed. The gate electrode 104 is formed by depositing a layer, forming a mask thereover, etching the layer and removing the mask to leave the gate electrode 104. In one embodiment, the gate electrode 104 may comprise a metal. In another embodiment, the gate electrode 104 may comprise a metal selected from the group consisting of chromium, molybdenum, copper, titanium, tungsten, aluminum, and combinations thereof. In one embodiment, the layer for producing the gate electrode 104 may be deposited by physical vapor deposition (PVD). In another embodiment, the layer for producing the gate electrode 104 may be deposited by evaporation. In another embodiment, the layer for producing the gate electrode 104 may be deposited by electroplating. It is to be understood that other deposition methods may be used to deposit the layer for producing the gate electrode 104. In one embodiment, the gate electrode 104 may have a thickness of between about 2000 Angstroms to about 3000 Angstroms. It is to be understood that the thickness of the gate electrode 104 may be adjusted to suit the device requirements. [0019] Over the gate electrode 104, a gate dielectric layer 106 is formed. In one embodiment, the gate dielectric layer 106 may be deposited by PECVD. In another embodiment, the gate dielectric layer 106 may be deposited by other chemical vapor deposition (CVD) methods. It is to be understood that other deposition methods may be utilized to deposit the gate dielectric layer 106. In one embodiment, the gate dielectric layer 106 may comprise an insulating material. In another embodiment, the gate dielectric layer 106 may comprise silicon nitride. In another embodiment, the gate dielectric layer 106 may comprise silicon oxynitride. In another embodiment, the gate dielectric layer 106 may comprise silicon oxide. In another embodiment, the gate dielectric layer 106 may comprise silicon dioxide. In one embodiment, the gate dielectric layer 106 may have a thickness of between about 1000 Angstroms to about 6000 Angstroms. In another embodiment, the thickness of the gate dielectric layer 106 may be between about 2000 Angstroms and about 4000 Angstroms. In one embodiment, the gate dielectric layer 106 may comprise multiple layers. When multiple layers are used for the gate dielectric layer 106, one of the layers may be a high deposition rate material, such as silicon nitride with poor quality, and another of the layers may comprise a low deposition rate material, such as silicon nitride with high quality, to gain the throughput and the interface quality desired.
[0020] Once the gate dielectric layer 106 has been deposited, a microcrystalline silicon layer 108 may be deposited. In one embodiment, the microcrystalline silicon layer 108 may be deposited by PECVD. It is to be understood that the microcrystalline silicon layer 108 may be deposited by other deposition methods as well. In one embodiment, the microcrystalline silicon layer 108 may have a thickness of between about 300 Angstroms to about 3000 Angstroms.
[0021] If simply the microcrystalline silicon layer 108 is used as the active material, the TFT will likely have a high subthreshold slope because of the etching of the etch stop layer. By controlling the contact area damage of the microcrystalline silicon layer 108 during the wet etching of the etch stop layer, the subthreshold slope may be lowered. In order to control the damage, an amorphous silicon layer 110 may be deposited over the microcrystalline silicon layer 108. In one embodiment, the amorphous silicon layer 110 may be deposited by PECVD. It is to be understood that the amorphous silicon layer 110 may be deposited by other deposition methods as well. In one embodiment, the amorphous silicon layer 110 may have a thickness of between about 300 Angstroms to about 1000 Angstroms. The amorphous silicon layer 110 significantly reduces the subthreshold slope and simultaneously improves the electrical performance of the TFT. Because the amorphous silicon layer 110 prevents the microcrystalline silicon layer 108 from exposure to the wet etching solution, damage to the microcrystalline silicon layer 108 is prevented.
[0022] After the amorphous silicon layer 110 has been deposited, an etch stop material layer 112 may be deposited thereover. In one embodiment, the etch stop material layer 112 may be formed by blanket depositing, followed by photoresist depositing, followed by pattern developing. The etch stop material layer 112 may be patterned by wet etching to form an etch stop structure 114. It is to be understood that the etch stop material layer 112 may be etched by other etching methods such as dry or plasma etching. In one embodiment, the etch stop material layer 112 may comprise silicon nitride. In another embodiment, the etch stop material layer 112 may comprise silicon oxynitride. In still another embodiment, the etch stop material layer 112 may comprise silicon oxide.
[0023] After the etch stop structure 11 has been formed, a doped amorphous silicon layer 1 6 may be deposited thereover. Over the doped amorphous silicon layer 116, a metal contact layer 118 may be deposited. In one embodiment, the metal contact layer 118 may comprise tungsten, molybdenum, titanium, chromium, aluminum, alloys thereof and combinations thereof. The metal contact layer 18 may be deposited by well known deposition methods such as PVD. The metal contact layer 118 is then patterned by forming a mask thereover, etching and removing the mask to leave a source electrode 122A and a drain electrode 122B. The doped amorphous silicon layer 116 may be etched to form a first ohmic contact 120A and a second ohmic contact 120B.
[0024] Figure 2 is a schematic cross sectional view of a TFT 200 according to another embodiment. The TFT 200 includes a substrate 202, gate electrode 204, gate dielectric layer 206, microcrystalline silicon layer 210, amorphous silicon layer 212, etch stop structure 214, first ohmic contact 216A, second ohmic contact 216B, source electrode 218A, and drain electrode 218B. The TFT 200 of Figure 2 may be formed in a similar manner to the TFT 100 discussed above and may comprise the same materials for the various layers as discussed above in reference to Figures 1A-1G. The TFT 200 of Figure 2, however, has a second microcrystalline silicon layer 208. The second microcrystalline silicon layer 208 is the interface microcrystalline silicon layer with general characteristics of no incubation layer and a column structure with high crystalline fraction. Microcrystalline silicon layer 210, however is the bulk microcrystalline silicon layer with no specific structure and low crystalline fraction.
[0025] In both TFT 100 and TFT 200, the subthreshold slope is improved by use of an amorphous silicon layer between the topmost microcrystalline silicon layer and the etch stop material layer. Figure 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs: single layer microcrystalline silicon without amorphous silicon, single layer microcrystalline silicon with amorphous silicon, multi-layer microcrystalline silicon without amorphous silicon, and multi-layer microcrystalline silicon with amorphous silicon. As shown in Figure 3, when an amorphous silicon layer is used, the subthreshold slope is improved. Adding the amorphous silicon controls the damage on the contact areas and significantly reduces the subthreshold slope. The amorphous silicon also improves the electrical performance of the TFT. Table I below shows the values of the subthreshold slope, loff current, lon current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 3. TABLE I
Figure imgf000011_0001
[0026] Another problem that occurs in microcrystalline silicon based TFTs is a low field effect mobility. To solve the low field effect mobility problem, a low resistivity (less than 1 ohm-cm) doped amorphous silicon layer may be used for the ohmic contact layer as opposed to one with a higher resistivity (~ 50 ohm- cm). By using a lower resistivity doped amorphous silicon layer for the ohmic contact layer, the average field effect mobility may be increased from 1.0 cm2/V-s to 2.1 cm2/V-s, for example. To deposit the doped amorphous silicon layer, a PECVD deposition method may be used whereby SiH4, H2, and PH3 may be delivered to the chamber while applying RF power to ignite a plasma. In one embodiment, the SiH4 may be flowed at a rate of between about 10 seem and about 45 seem, the H2 may be flowed at between about 2000 seem and about 3500 seem and the PH3 may be flowed at between about 50 seem and about 85 seem into a chamber having a volume of greater than about 100000 cm3. The substrate may be spaced between about 500 mils and about 600 mils from the showerhead. The chamber may be maintained at a pressure of between about 2000 mTorr and about 3500 mTorr and the substrate may be maintained at between about 300 degrees Celsius and about 359 degrees Celsius. In one embodiment, the SiH4 may be flowed at a rate of 30 seem, the H2 may be flowed at 3000 seem and the PH3 may be flowed at 70 seem into a chamber having a volume of greater than about 100000 cm3. The substrate may be spaced 550 mils from the showerhead. The chamber may be maintained at a pressure of 3000 mTorr and the substrate may be maintained at 325 degrees Celsius.
[0027] Figure 4 shows the improvement of the microcrystalline silicon TFT with doped amorphous silicon layer that has a resistivity of less than 1 ohm-cm relative to one with a resistivity of about 50 ohm-cm. The relative low mobility of the microcrystalline silicon TFT is improved by using the low resistivity doped amorphous silicon film as the ohmic contact layer. The low resistivity improves the overall source-drain contact resistance of the TFT. Table II shows values of the subthreshold slope, loff current, lon current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 4.
TABLE II
Figure imgf000012_0001
[0028] To lower the resistivity, the deposition rate for the doped amorphous silicon layer can simply be lowered. However, lowering the deposition rate will affect the substrate throughput. Dual layer or multi-layer doped amorphous silicon may be used. The layer that contacts the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) may be deposited at a high rate and thus have a high resistivity while the layer that is in contact with the source and drain electrodes may be deposited at a low rate to have a low resistivity. Thus, the dual or multi-layer doped amorphous silicon has the advantage of making a nice ohmic contact from the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) to the source and drain electrodes.
[0029] Another method to improve the microcrystalline silicon TFT is to use an H2 or N2 plasma pretreatment before the etch stop layer is deposited. Doing so will improve the l0ff, subthreshold slope, field effect mobility and threshold voltage. For example, the l0ff may be decreased by greater than 30 percent, the subthreshold slope may be decreased by greater than 10 percent, the threshold voltage may be decreased by -2V and the field effect mobility may be improved by greater than 10 percent. The amorphous silicon layer that overlies the topmost microcrystalline silicon layer may be exposed to the plasma. [0030] Figure 5 shows the improvement of the drain current versus gate voltage for three scenarios: no plasma treatment of the topmost silicon layer, exposure of the topmost silicon layer to an H2 plasma, and exposure of the topmost silicon layer to N2 plasma. Further electrical properties improvement can be achieved by the plasma treatment before the etch stop material layer deposition. The plasma is believed to improve the interface of the contact area between the active layers and the doped amorphous silicon layer used for the ohmic contact. Table III shows the values of the subthreshold slope, l0 f current, lon current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 5.
[0031] For H2 plasma exposure, the H2 gas may be flowed to the chamber at a rate of between about 5000 seem and about 7000 seem while between about 400 W and about 600 W are applied to the showerhead. The chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr. The substrate may be spaced between about 500 mils and about 700 mils from the showerhead and be exposed to the plasma for between about 40 seconds and about 75 seconds. In one embodiment, the H2 gas may be flowed to the chamber at a rate of 6000 seem while 500 W is applied to the showerhead. The chamber may be maintained at a pressure of 1500 mTorr. The substrate may be spaced 700 mils from the showerhead and be exposed to the plasma for 60 seconds. The chamber may have a volume of about 100000 cm3 or more.
[0032] For N2 plasma exposure, the N2 gas may be flowed to the chamber at a rate of between about 2000 seem and about 3000 seem while between about 500 W and about 750 W are applied to the showerhead. The chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr. The substrate may be spaced between about 800 mils and about 1000 mils from the showerhead and be exposed to the plasma for between about 45 seconds and about 75 seconds. In one embodiment, the N2 gas may be flowed to the chamber at a rate of 2500 seem while 700 W is applied to the showerhead. The chamber may be maintained at a pressure of 1500 mTorr. The substrate may be spaced 900 mils from the showerhead and be exposed to the plasma for 60 seconds. The chamber may have a volume of about 100000 cm3 or more.
TABLE III
Figure imgf000014_0001
[0033] The disclosure herein has described numerous techniques to advantageously improve microcrystalline silicon based etch stop TFTs. By utilizing an amorphous silicon layer between the microcrystalline silicon layer and the etch stop material layer in the TFT fabrication process, the microcrystalline silicon TFT may have improved performance. Additionally, by lowering the resistivity of the ohmic contact layer, the microcrystalline silicon TFT may have improved performance. Also, by exposing the microcrystalline silicon layer to a hydrogen or nitrogen plasma, the microcrystalline silicon TFT may have improved performance. The improved performance includes not only the mobility, but also the subthreshold slope.
[0034] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A thin film transistor fabrication method, comprising:
depositing a first microcrystalline silicon layer over a gate dielectric layer; depositing an amorphous silicon layer over the first microcrystalline silicon layer;
depositing an etch stop layer over the amorphous silicon layer;
etching the etch stop layer to form an etch stop structure and expose at least a portion of the amorphous silicon layer; and
depositing a doped amorphous silicon layer over the amorphous silicon layer and the etch stop structure.
2. The method of claim 1 , further comprising depositing a second microcrystalline silicon layer over the gate dielectric layer prior to depositing the first microcrystalline silicon layer.
3. The method of claim 2, wherein the first microcrystalline silicon layer has a first crystalline fraction and wherein the second microcrystalline silicon layer has a second crystalline fraction that is higher than the first crystalline fraction and wherein the first microcrystalline silicon layer has no specific structure and the second microcrystalline silicon layer has a columnar structure.
4. The method of claim 1 , further comprising exposing the amorphous silicon layer to a plasma containing a element selected from the group consisting of nitrogen, hydrogen and combinations thereof.
5. The method of claim 4, wherein the doped amorphous silicon layer has a resistivity of less than 1 ohm-cm, wherein the amorphous silicon layer has a thickness of between 300 Angstroms and 1000 Angstroms, and wherein etching the etch stop layer comprises wet etching.
6. A thin film transistor fabrication method, comprising:
depositing a first microcrystalline silicon layer over a gate dielectric layer; depositing an amorphous silicon layer over the first microcrystalline silicon layer;
depositing an etch stop layer over the amorphous silicon layer;
etching the etch stop layer to form an etch stop structure; and
depositing a doped amorphous silicon layer over the amorphous silicon layer and the etch stop structure, the doped amorphous silicon layer having a resistivity of less than 1 ohm-cm.
7. The method of claim 6, wherein the thin film transistor has an average field effect mobility of 2.1 cm2/V-s or more.
8. The method of claim 6, further comprising depositing a second microcrystalline silicon layer over the gate dielectric layer prior to depositing the first microcrystalline silicon layer.
9. The method of claim 8, wherein the first microcrystalline silicon layer has a first crystalline fraction and wherein the second microcrystalline silicon layer has a second crystalline fraction that is higher than the first crystalline fraction.
10. The method of claim 9, wherein the first microcrystalline silicon layer has no specific structure and the second microcrystalline silicon layer has a columnar structure.
11. The method of claim 6, further comprising exposing the amorphous silicon layer to a hydrogen or nitrogen plasma, wherein etching the etch stop layer comprises wet etching.
12. A thin film transistor fabrication method, comprising:
depositing a first microcrystalline silicon layer over a gate dielectric layer; depositing an amorphous silicon layer over the first microcrystalline silicon layer;
exposing the amorphous silicon layer to a plasma containing an element selected from the group consisting of hydrogen, nitrogen, and combinations thereof;
depositing an etch stop layer over the amorphous silicon layer;
etching the etch stop layer to form an etch stop structure; and
depositing a doped amorphous silicon layer over the etch stop structure.
13. The method of claim 12, wherein the plasma is formed from h .
14. The method of claim 12, wherein the plasma is formed from N2.
15. The method of claim 12, further comprising depositing a second microcrystalline silicon layer over the gate dielectric layer prior to depositing the first microcrystalline silicon layer, wherein the doped amorphous silicon layer has a resistivity of less than 1 ohm-cm.
PCT/US2010/021323 2010-01-18 2010-01-18 Etch stop microcrystalline thin film transistor WO2011087514A1 (en)

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Citations (4)

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US6387740B1 (en) * 1999-08-12 2002-05-14 Hannstar Display Corp. Tri-layer process for forming TFT matrix of LCD with reduced masking steps
KR20070105012A (en) * 2006-04-24 2007-10-30 삼성전자주식회사 Thin film transistor array panel for display and manufacturing method of the same
KR20080106148A (en) * 2008-10-23 2008-12-04 삼성전자주식회사 Thin film transistor
US20090236597A1 (en) * 2008-03-20 2009-09-24 Applied Materials, Inc. Process to make metal oxide thin film transistor array with etch stopping layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387740B1 (en) * 1999-08-12 2002-05-14 Hannstar Display Corp. Tri-layer process for forming TFT matrix of LCD with reduced masking steps
KR20070105012A (en) * 2006-04-24 2007-10-30 삼성전자주식회사 Thin film transistor array panel for display and manufacturing method of the same
US20090236597A1 (en) * 2008-03-20 2009-09-24 Applied Materials, Inc. Process to make metal oxide thin film transistor array with etch stopping layer
KR20080106148A (en) * 2008-10-23 2008-12-04 삼성전자주식회사 Thin film transistor

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