WO2011078650A2

WO2011078650A2 - Method for fabricating nanofluidic channels

Info

Publication number: WO2011078650A2
Application number: PCT/MY2010/000316
Authority: WO
Inventors: Chia Sheng Daniel Bien
Original assignee: Mimos Berhad
Priority date: 2009-12-22
Filing date: 2010-12-13
Publication date: 2011-06-30
Also published as: MY168162A; WO2011078650A3

Abstract

The present invention provides the method for fabricating nanofluidic channels (23) with a combination of the formation of silicon (22B) or oxide nanowires (22) on a handle substrate (20), layered with or without an insulating material together with wafer planarization techniques. The process provides a simple and practical solution for low cost fabrication of nanofluidic channel with well controlled dimensions where the resolution of the channels is dependent on the resolution of the nanowires instead of on the lithographic tool or type of resist used. This method is compatible with standard CMOS process allowing easy integration on the same platform with other nanofluidic devices and systems fabricated using similar methods.

Description

Title of Invention: METHOD FOR FABRICATING

NANOFLUIDIC CHANNELS

Technical Field

The present invention relates to a method to fabricate nanofluidic flow channels where a combination of silicon and oxide based nanowires and wafer planarization techniques are utilized to form the required channels.

Background

Nanofluidic flow channel has increasing application demands in the area of biomedical analysis and environmental monitoring. These nanoscale channels are important for nanobiology where by miniaturizing the flow channels; researchers could facilitate the detection of individual DNA molecules and proteins by passing one through the channel. Nanofluidic channels also serve as useful tools for chemical analysis systems.

There are several methods to produce nanofluidic flow channels. Presently, these channels are fabricated via conventional microfabrication methods such as masking and etching which rely on resolution of lithographic tools or complicated lithographic methods.

A prior art includes a method of forming nanofluidic enclosed channels by providing a first substrate having a layer of a first material disposed thereon. A plurality of nanoscale slots is formed along a second substrate using nanolithography, etching or other disclosed techniques. The first substrate is then bonded to the second substrate such that the layer of the first material on the first substrate is adjacent to the plurality of slots on the second substrate to define a plurality of enclosed nanofluidic channels there-through. This method uses a combination of nanoimprint lithography and reactive ion etching and requires a mold to be made in polymer for pattern transfer. The method also requires the use of thermal plastic material (PMMA). The channel dimension is dependant on Uthographic resolution while the surface properties are dependant on the type of polymer material used.

Another prior art listed a method of direct fabrication of micro or nano fluidic channels by electron beam lithography. This method requires the use of electron beam lithography which has to be conducted in a two steps lithography process. The resolution of the channels is also dependent on the resolution of the lithographic tool and type of resist used. The type of resist to be used is of non-standard type resist.

Although the methods to produce nanofluidic channels highlighted above are precise and rehable, the techniques rely highly on the high resolution Uthographic equipments such as deep ultraviolet (DUV), extreme ultraviolet (EUV), electron beam hthography, x-ray lithography or nano-imprint lithography. Therefore, the fabrication process can be very costly.

The present invention is made in view of the prior arts described above where the process does not require high end lithographic tool and therefore able to provide a simple and practical solution for low cost fabrication of nanofluidic channel. The method is a single lithography process which uses nanowires to form the required channels and the resolution of the channels is dependent on the nanowires resolution and not on the lithographic tool or type of resist used. This method is also compatible with standard CMOS process which makes it easy to be integrated on the same platform as other nanofluidic devices and systems fabricated using similar methods.

It is a very cost effective method to produce final high resolution final structures with extremely good alignment without the requirement of state-of-art equipment and does not have any hthography imposed limitations. Through this present invention, a method of manufacturing low cost nanoelectromechanical (NEM) devices for biomedical applications has been discovered. This invention also brings about the improvement of current technology from microelectromechamcal (MEMS) based devices to NEM devices.

Summary

The present invention relates to a method to fabricate nanofluidic channels where a combination of silicon and oxide based nanowires and wafer planarization techniques are utilized to form the required channels. The process provides a simple and practical solution for low cost fabrication of nanofluidic channel with well controlled dimensions. The method is a single lithography process which uses nanowires to form the required channels and the resolution of the channels is dependent on the resolution of the nanowires instead of on the lithographic tool or type of resist used as required in the prior art methods. This is a very cost effective method to produce final high resolution final structures with extremely good alignment which is also compatible with standard CMOS process allowing easy integration on the same platform with other nanofluidic devices and systems fabricated using similar methods.

Description of Drawings

Fig. 1 is a flow chart showing the fabrication process of nanofluidic channels as described according to the method of this invention.

] Fig. 2A is a cross-sectional drawing of nitride layer deposition on to substrate.

] Fig. 2B is a cross-sectional drawing of lithographically pattern etching of nitride layer on substrate.

] Fig. 2C is a cross-sectional drawing of oxide layer deposition on to substrate. [14] Fig. 2D is a cross-sectional drawing of oxide spacer formation.

[15] Fig. 2E is a cross-sectional drawing of oxide nanowire formation.

[16] Fig. 2F is a cross-sectional drawing of polysilicon layer deposition on to entire

substrate surface.

[17] Fig. 2G is a cross-sectional drawing of polysilicon layer planarization to form a planar layer with the oxide nanowires.

[18] Fig. 2H is a cross-sectional drawing of nano-channels formation.

[19] Fig. 21 is a cross-sectional drawing of channel encapsulation completing the embodiment of nano-channels utilizing oxide nanowires.

[20] Fig. 3A is a cross-sectional drawing of oxide layer deposition on to substrate.

[21] Fig. 3B is a cross-sectional drawing of lithographically pattern etching of oxide layer on substrate.

[22] Fig. 3C is a cross-sectional drawing of polysilicon layer deposition on to substrate.

[23] Fig. 3D is a cross-sectional drawing of polysilicon spacer formation.

[24] Fig. 3E is a cross-sectional drawing of polysilicon nanowire formation.

[25] Fig. 3F is a cross-sectional drawing of oxide layer deposition on to entire substrate surface.

[26] Fig. 3G is a cross-sectional drawing of oxide layer planarization to form a planar layer with the polysilicon nanowires.

[27] Fig. 3H is a cross-sectional drawing of nano-channels formation.

[28] Fig. 31 is a cross-sectional drawing of channel encapsulation completing the embodiment of nano-channels utilizing polysilicon nanowires.

[29] Fig. 4A is a cross-sectional drawing of nitride layer deposition on to substrate.

[30] Fig. 4B is a cross-sectional drawing of polysilicon layer deposition on to nitride layer.

[31] Fig. 4C is a cross-sectional drawing of lithographically pattern etching of polysilicon layer.

[32] Fig. 4D is a cross-sectional drawing of oxide layer deposition on to substrate.

[33] Fig. 4E is a cross-sectional drawing of oxide spacer formation.

[34] Fig. 4F is a cross-sectional drawing of oxide nanowire formation.

[35] Fig. 4G is a cross-sectional drawing of polysilicon layer deposition on to entire nitride layer surface.

[36] Fig. 4H is a cross-sectional drawing of polysilicon layer planarization to form a planar layer with the oxide nanowires.

[37] Fig. 41 is a cross-sectional drawing of nano-channels formation.

[38] Fig. 4J is a cross-sectional drawing of channel encapsulation completing the embodiment of nano-channels on nitride insulator utilizing oxide nanowires.

Description of Embodiments [39] Hereinafter, the present invention is described in detail.

[40] The invention involves a method to greatly simplify the fabrication of nanofluidic channels with well controlled dimensions. The key process is the ability to integrate a CMOS based nanowire offering a high throughput and cheaper solution compared to other methods.

[41] The main feature of the method is the utilization of nanowires to form the channels and the dimension of the wires dictates the final dimensions of the channels. In the proposed process, silicon or oxide based nanowires can be used to produce the channel structures. Resolution of nanowires is defined by thin film deposition process and not by high end lithographic tools. The nano-channels can also be fabricated directly on the substrate [20] or on an intermediate insulating layer.

[42] A typical process flow chart is presented in Fig. 1. The fabrication process is split into 3 stages comprising of nanowire formation [22], nano-fluidic channel structure formation [23] and finally channel encapsulation [25].

[43] Fig. 2A to Fig. 21 shows a typical fabrication process of the nanofluidic channels directly on silicon or glass substrates [20] utilizing oxide nanowires [22]. With this method, only a single lithographic mask is required. In stage 1, oxide nanowires are formed within 5 steps. Firsdy, a layer of insulator such as nitride [24] is deposited on to the substrate [20]. This is followed by lithographic patterning and etching of the nitride layer [24]. The mask leaves a pattern where nanowires or nanofluidic channels are to be located. Then, a thin layer of oxide [26] is deposited. The thickness of the oxide layer [26] will determine the final channel dimensions. The next step is to dry etch the oxide to form spacer type structures, oxide spacer [28] and lastly the removal of nitride in phosphoric acid, leaving only oxide nanowires [22] structures.

[44] This is followed with stage 2, formation of nanofluidic channel, achieved within three steps. Firstly, a thick layer of polysilicon [30] is deposited to cover the entire substrate [20] surface. Then the polysilicon [30] is planarized to form a planar layer with the oxide nanowires [22]. Planarization is achieved through either an etch-back type process or by chemical mechanical polishing (CMP). Lastly, the nano-channels [23] are formed by selectively removing or etching of the oxide nanowires [22].

[45] The last stage completes the fabrication of nanofluidic channel of this invention. In stage 3, channel encapsulation is conducted by bonding another substrate [20] or polymer film on to the nanofluidic channel substrate. Hence, nanofluidic channel [23] is encapsulated between both structures [20].

[46] In this invention, through the same method, the described process can be modified to use silicon based nanowires [22B] to form the final nano-channels as illustrated from Fig. 3A to Fig. 31. The process steps within the 3 stages are similar with only structures modification. [47] In stage 1, polysilicon nanowires are formed within 5 steps. Firstly, a layer of oxide [26] is deposited on to the substrate [20]. This is followed by lithographic patterning and etching of the oxide layer [26]. The mask leaves a pattern where nanowires are to be located. Then, a thin layer of polysilicon [30] is deposited. The thickness of the polysilicon layer [30] will determine the final channel dimensions. The next step is to dry etch the polysilicon to form spacer type structures, polysilicon spacer [34] and lastly the removal of oxide in phosphoric acid, leaving only polysilicon nanowires [22B] structures.

[48] This is followed with stage 2, formation of nanofluidic channel, achieved within three steps. Firstly, a thick layer of oxide [26] is deposited to cover the entire substrate [20] surface. Then the oxide layer [26] is planarized to form a planar layer with the polysilicon nanowires [22B]. Planarization is achieved through either an etch-back type process or by chemical mechanical polishing (CMP). Lastly, the nano-channels [23] are formed by selectively removing or etching of the polysilicon nanowires [22B].

[49] The last stage completes the fabrication of nanofluidic channel of this invention. In stage 3, channel encapsulation is conducted by bonding another substrate [20] or polymer film on to the channel substrate. Hence, nanofluidic channel [23] is created between both structures [20].

[50] At times where a test fluid is conductive, it is preferred that the nano-fluidic channels are not formed directly onto a silicon substrate [20]. Therefore, an insulating layer such as nitride [24] is required as an interim material between the fluid and substrate.

Hence, the process flow is modified to include an additional step in stage 1 which is the inclusion of the required nitride passivation layer [24] as shown in Fig. 4B. Fig. 4 A to Fig. 4J shows the typical fabrication process of the nanofluidic channels on nitride insulator [24] utilizing oxide nanowires [22].

[51] Using this method, typically any combination of nanowires and materials can be used to form the desired channels.

[52] Accordingly, the invention disclosed a method to fabricate nanofluidic channel. It is the combination of the above features and its technical advantages give rise to the uniqueness of such invention. Although the descriptions above contain much specificity, these should not be construed as limiting the scope of the embodiment but as merely providing illustrations of some of the presently preferred embodiments.

Claims

A method for fabricating nanofluidic channels [23] which comprises, formation of nanowires [22] on a handle substrate [20], with or without an insulating material, characterized with using wafer planarization techniques over the nanowires, and removing the nanowires to form nanofluidic channels [23].

A method according to claim 1, further comprising forming channel encapsulation [25] over the nanofluidic channels [23].

A method according to claim 1, wherein the type of nanowires formed is oxide nanowires [22] or polysilicon nanowires [22B].

A method according to claim 1, wherein the handle substrate [20] can be silicon, glass or polymer.

A method according to claim 1, wherein the insulating material on the substrate is nitride layer [24].

A method according to claim 1, wherein the wafer planarization techniques is etch-back type process or chemical mechanical polishing. A method according to claim 3, wherein the formation of oxide nanowires [22] comprises:

depositing a layer of nitride [24] on the substrate [20];

lithographically patterning and etching the nitride layer, said pattern forms the basis of where nanowires are to be located;

depositing a thin layer of oxide [26];

dry etching oxide to form spacer type structures, oxide spacer [28]; and removing the nitride layer.

A method according to claim 3, wherein the formation of nanofluidic channels utilizing oxide nanowires comprises:

depositing a thick layer of polysilicon [30] to cover the entire substrate [20] surface;

planarizing the polysilicon [30] to form a planar layer with oxide nanowires [22]; and

removing or etching of the oxide nanowires [22].

A method according to claim 3, wherein the formation of polysilicon nanowires [32] comprises:

depositing a layer of oxide [26] on to the substrate [20];

lithographically patterning and etching the oxide layer, said pattern forms the basis of where nanowires are to be located;

depositing a thin layer of polysilicon [30]; dry etching polysilicon to form spacer type structures, polysilicon spacer [34]; and

removing the oxide layer.

[Claim 10] A method according to claim 3, wherein the formation of nanofluidic channels utilizing polysilicon nanowires comprises:

depositing a thick layer of oxide [26] to cover the entire substrate [20] surface;

planarizing the oxide [26] to form a planar layer with polysilicon nanowires [32];

forming nano-channels [23] by selectively removing or etching of the polysilicon nanowires [32].

[Claim 11] A method according to claim 2, wherein the channel encapsulation is performed by bonding another substrate [20] or polymer film on to the channel substrate.