WO2011061043A2 - Grid-line-free contact for a photovoltaic cell - Google Patents
Grid-line-free contact for a photovoltaic cell Download PDFInfo
- Publication number
- WO2011061043A2 WO2011061043A2 PCT/EP2010/066149 EP2010066149W WO2011061043A2 WO 2011061043 A2 WO2011061043 A2 WO 2011061043A2 EP 2010066149 W EP2010066149 W EP 2010066149W WO 2011061043 A2 WO2011061043 A2 WO 2011061043A2
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- WIPO (PCT)
- Prior art keywords
- substrate
- conductive
- photovoltaic cell
- laterally
- metal wiring
- Prior art date
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- 229910045601 alloy Inorganic materials 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 2
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- 239000002178 crystalline material Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
- H01L31/02245—Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0687—Multiple junction or tandem solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention generally relates to structures that provide electrical contacts only from a backside of a multi-junction photovoltaic cell in order to increase an effective area of the photovoltaic cell, and methods of manufacturing the same.
- a photovoltaic cell is a device that converts light directly into electricity by the photovoltaic effect. Assemblies of photovoltaic cells are used to make solar panels, solar modules, or photovoltaic arrays.
- a photovoltaic cell can be formed by providing a large area p-n junction in a semiconductor material.
- a space charge region is formed around a p-n junction in a photovoltaic cell. Photons that impinge on the space charge region generate at least one electron-hole pair if absorbed by the semiconductor material in the space charge region. The electrons and holes diffuse in opposite directions, thereby accumulating positive charges in the bulk portion of the p-doped material and accumulating negative charges in the bulk portion of the n-doped material.
- Conventional photovoltaic cells are configured to provide a p-doped region on one side of the cell and an n-doped region on the opposite side of the cell.
- the front side of the cell can be the p-doped region and the back surface of the cell can be the n-doped region, or vice versa.
- First electrical contacts are made to one node of the photovoltaic cell from the front side
- second electrical contacts are made to the other node of the photovoltaic cell from the back surface. Because the electrical contacts on the front side need to be wired together, a one dimensional array of metal lines is provided on the front side of conventional photovoltaic cells. Such metal lines are called "grid lines" on a photovoltaic cell.
- gird lines block a significant portion of the front side of the photovoltaic cell, thereby reducing the effective area of the photovoltaic cell.
- the width of grid lines on the front side cannot exceed a threshold width in order to limit the reduction of the effective area of the photovoltaic cell.
- the resistance of the grid lines on the front side of the photovoltaic cell is significant, and the efficiency of the photovoltaic cell is reduced through resistive heating of the grid lines during operation.
- a photovoltaic cell that does not employ a wiring structure on the front side. Absence of a wiring structure on the front side increases effective area of the photovoltaic cell. Electrical contact to the front side of the photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell.
- a dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell.
- a conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.
- a photovoltaic cell structure comprises a substrate, at least one laterally-insulated through- substrate contact structure, a first contiguous metal wiring structure, and a second contiguous metal wiring structure.
- the substrate comprises a photovoltaic material that generates a nonzero electric potential across a front surface and a back surface of the substrate upon irradiation by electromagnetic radiation.
- the at least one laterally-insulated through- substrate contact structure is embedded in the substrate.
- Each of the at least one laterally- insulated through-substrate contact structure comprises a dielectric liner and a conductive through-substrate via, which is conductively connected to a surface portion of the substrate located at the front surface and electrically isolated from the back surface.
- the first contiguous metal wiring structure is spaced from the back surface, and is in contact with at least one conductive through-substrate via in the at least one laterally- insulated through- substrate contact structure.
- the second contiguous metal wiring structure is in contact with the back surface of the substrate. The non-zero electric potential is provided across the first and second contiguous metal wiring structures.
- a method of forming a photovoltaic cell structure is provided.
- a dielectric layer is formed on a back surface of a substrate, which comprises a photovoltaic material that generates a non-zero electric potential between a front surface and the back surface of the substrate upon irradiation by electromagnetic radiation.
- At least one through-substrate trench is formed in the substrate.
- At least one laterally- insulated through-substrate contact structure is formed in the substrate by filling the at least one through-substrate trench.
- a first contiguous metal wiring structure is formed on at least one conductive through-substrate via in the at least one laterally- insulated through- substrate contact structure. The first contiguous metal wiring structure is spaced from the back surface by the dielectric layer.
- a second contiguous metal wiring structure is formed directly on the back surface of the substrate.
- FIGS. 1 - 3 and figures with a suffix "B” are vertical cross-sectional views.
- a B - B' plane in a figure with a numeric label and the suffix "A” is the plane of the vertical cross-sectional view for the figure with the same numeric label and the suffix "B.”
- FIGS. 1- 3 and 4A - 9B are views of a first exemplary photovoltaic cell structure at various stages of a manufacturing process according to a first embodiment of the present invention
- FIGS. 10A - 12B are views of a second exemplary photovoltaic cell structure at various stages of a manufacturing process according to a second embodiment of the present invention
- FIGS. 13A - 14B are views of a third exemplary photovoltaic cell structure at various stages of a manufacturing process according to a third embodiment of the present invention.
- FIGS. 15A and 15B are views of a fourth exemplary photovoltaic cell structure according to a fourth embodiment of the present invention.
- the present invention relates to structures that provide electrical contacts only from a backside of a multi-junction photovoltaic cell in order to increase an effective area of the photovoltaic cell, and methods of manufacturing the same, which are now described in detail with accompanying figures.
- the same reference numerals or letters are used to designate like or equivalent elements.
- the drawings are not necessarily drawn to scale.
- a "photovoltaic material” refers to any material that generates a voltage difference between two terminals upon irradiation by electromagnetic radiation.
- the electromagnetic radiation can comprise the visible spectrum, the ultraviolet range, and the infrared range.
- a first element is "conductively connected" to a second element if there is a conduction path between the first and second elements that allow passing of an electrical current.
- proximal surface of an element that is located on a substrate refers to the surface of that element that is closest to the substrate.
- a distal surface of an element that is located on a substrate refers to the surface of that element this is farthest away from the substrate.
- a first element is "directly adjoined to" a second element if the first and second elements make a physical contact at a point, at a one-dimensional curve, or at a two- dimensional surface.
- a "laterally-insulated through-substrate contact structure” is a structure including a conductive element and an insulating element, in which the conductive element conductively connects a first element located on one side of a substrate and a second element located on the opposite side of the substrate, and the insulting element electrically isolates the conductive element from the substrate.
- a first exemplary photovoltaic cell structure according to a first preferred embodiment of the present invention comprises a substrate 10 and an anti- reflective layer 20 located on the front surface 17 of the substrate 10.
- the substrate 10 comprises a photovoltaic material that generates a non-zero electric potential between the front surface 17 and the back surface 19 of the substrate 10 upon irradiation by
- the electromagnetic radiation can be in the visible spectrum, ultraviolet range, and/or infrared range.
- the photovoltaic material can be a crystalline material or an amorphous material.
- the crystalline material can be single crystalline silicon, poly crystalline silicon, germanium, gallium indium, and/or gallium arsenide (GaAs).
- the amorphous and multicrystalline material can be amorphous silicon, cadmium telluride (CdTe), and/or copper indium diselenide (CuInSe 2 , or CIS).
- the photovoltaic material can be in the form of a block, or can be in the form of a thin film
- the photovoltaic material is a semiconductor material
- the photovoltaic material can have a built-in p-n junction 15 in the substrate 10.
- the substrate comprises a p- doped semiconductor material and an n-doped semiconductor material that collectively form the p-n junction 15 at a surface between the front surface 17 and the back surface 19 of the substrate 10.
- any type of photovoltaic material can be employed in the substrate 10 for the purposes of preferred embodiment of the present invention.
- the substrate 10 comprises a "surface portion" 39, which is a portion of the substrate 10 directly beneath the front surface 17 of the substrate 10. Electrical charges of one type accumulate in the surface region 39 of the substrate 10 when the photovoltaic material in the substrate 10 is exposed to electromagnetic radiation.
- the surface region 39 is a front surface portion of the photovoltaic material that is located on the front side on the substrate 10 and is spaced from the p-n junction 15. Electrical charges of the opposite type accumulate in a back surface region 38 of the substrate 10 this is located directly on the back surface 19 of the substrate 10. If the substrate 10 is flipped upside down, the back surface region 38 of the substrate 10 is located directly underneath the back surface 19 of the substrate 10.
- the anti-reflective layer 20 is located directly on the front surface 17 of the substrate 10.
- the anti-reflective layer 20 can be a dielectric material, a semiconducting material, or a conductive material.
- the anti-reflective layer 20 minimizes reflection of the electromagnetic radiation in the wavelength range that the photosensitive material in the substrate 10 absorbs.
- the thickness of the anti-reflective layer 20 can be optimized to minimize the reflection of the electromagnetic radiation.
- the thickness of the anti-reflective layer 20 can be from 5 nm to 100 nm, although lesser and greater thickness can be employed.
- the conductive material of the anti-reflective layer 20 has a low absorption coefficient for electromagnetic radiation in the wavelength range that the photosensitive material in the substrate 10 absorbs.
- the anti- reflective layer 20 can have a homogeneous composition, or can comprise a plurality of layers having different compositions. Any other anti-reflective material can be employed for the anti-reflective layer 20 of the first preferred embodiment of the present invention.
- the substrate 10 can be flipped upside down so that the back surface 19 of the substrate 10 faces up and the anti-reflective layer 20 faces down.
- a dielectric layer 30 is formed on the back surface 19 of the substrate 10.
- the dielectric layer 30 can be formed, for example, by chemical vapor deposition (CVD) of a dielectric material.
- the dielectric material for the dielectric layer 30 can be silicon oxide, silicon nitride, a dielectric metallic oxide, a dielectric metallic nitride, or a combination thereof.
- the thickness of the dielectric layer 30, as measured between a proximal surface 31 of the dielectric layer 30 that contacts the back surface of the substrate 10 and a distal surface 33 of the dielectric layer 30 that is exposed, can be from 10 nm to 10,000 nm, and preferably from 100 nm to 1,000 nm, although lesser and greater thicknesses can be employed.
- At least one through-substrate trench 11 is formed in the dielectric layer 30 and the substrate 10.
- a first photoresist 37 can be applied over the exposed upper surface of the dielectric layer 30, and lithographically patterned to form at least one opening.
- the at least one opening in the photoresist 37 can be a plurality of openings.
- the plurality of openings in the photoresist 37 can be, for example, a one-dimensional array of openings or a two-dimensional array of openings.
- the pattern in the at least one opening in the photoresist 37 is transferred into the dielectric layer 30 and the substrate 10 to form the at least one through- substrate trench 11, which extends from the distal surface 33 of the dielectric layer 30 to a depth within the surface region 39 of the substrate 10.
- An anisotropic etch such as a reactive ion etch (RIE), can be employed to etch the material of the dielectric layer 30 and the substrate 10 selective to the photoresist 37.
- RIE reactive ion etch
- the horizontal cross-sectional area of the at least one through- substrate trench 11 can be substantially constant as a function of depth within the at least one through- substrate trench 11, or alternately, the horizontal cross-sectional area of the at least one through-substrate trench 11 can decrease as a function of depth due to a taper in the sidewalls of the at least one through-substrate trench 11.
- the anisotropic etch employed to form the at least one through-substrate trench 11 can be timed to stop when at least one bottom surface of the at least one through-substrate trench 11 is within the surface region 39 of the substrate 10.
- the anisotropic etch stops before the at least one bottom surface of the at least one through-substrate trench 11 reaches the anti- reflective layer 20.
- the at least one bottom surface of the at least one through-substrate trench 11 exposes a surface at which electrical charges accumulate when the photovoltaic material of the substrate 10 is illuminated by electromagnetic radiation.
- the first photoresist 37 is subsequently removed, for example, by ashing. Referring to FIGS.
- At least one dielectric liner 12 is formed on the sidewalls of the at least one through- substrate trench 11.
- the at least one dielectric liner 12 can be formed by depositing a dielectric material layer and anisotropically etching the horizontal portions of the dielectric material layer.
- the remaining vertical portions of the dielectric material layer on the sidewalls of the at least one through-substrate trench 11 constitute the at least one dielectric liner 12.
- the top portion of the at least one dielectric liner 12 can be substantially coplanar with the distal surface 33 of the dielectric layer 30.
- the at least one dielectric liner 12 protrudes out of the back surface of the substrate and contacts a sidewall of the dielectric layer 30.
- the at least one through-substrate trench 11 is filled with a conductive material to form at least one conductive through- substrate via 40.
- the conductive material can be, for example, W, Al, Cu, Ag, Au, WN, TaN, TiN, a conducting doped semiconductor material, a conductive metal semiconductor alloy, or a combination thereof.
- the conductive material can be deposited by electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof.
- the excess material on the distal surface 33 of the dielectric layer 30 can be removed, for example, by chemical mechanical planarization, a recess etch, or a combination thereof.
- the at least one dielectric liner 12 and the at least one conductive through- substrate via 40 collectively constitute at least one laterally-insulated through-substrate contact structure (12, 40), which is embedded in the substrate 10 and provides a vertical conductive path that is electrically isolated in the lateral direction.
- the at least one conductive through- substrate via 40 is conductively connected only to the surface region 39 of the substrate 10, but is not conductively connected to any other portion of the substrate 10.
- the conductive through- substrate via 40 is electrically isolated from the back surface 19 of the substrate 10.
- a backside end surface of the at least one conductive through-substrate via 40 can be substantially coplanar with the distal surface 33 of the dielectric layer 30.
- Each of the at least one laterally-insulated through-substrate contact structure (12, 40) comprises a dielectric liner 12 and a conductive through- substrate via 40 that is conductively connected to the surface region 39 of the substrate 10 and is electrically isolated from the back surface 19 of the substrate 10. A portion of the at least one conductive through- substrate via 40 protrudes out of the back surface 19 of the substrate 10.
- the at least one laterally- insulated through-substrate contact structure (12, 40) can be a plurality of laterally- insulated through-substrate contact structures (12, 40), and can be a one-dimensional array or a two-dimensional array of laterally- insulated through-substrate contact structures (12, 40).
- a second photoresist 47 is applied on the distal surface 33 of the dielectric layer 30.
- the second photoresist 47 is lithographically patterned so that all of the at least one conductive through-substrate via 40 is covered by the second photoresist 47, while the distal surface 33 of the dielectric layer 30 is exposed in areas between the at least one conductive through- substrate via 40.
- the location of the at least one conductive through-substrate via 40 is shown in dotted lines in FIG. 6A.
- the sidewalls of the second photoresist 47 after lithographic patterning can be a contiguous surface overlying a contiguous line on the distal surface 33 of the dielectric layer 30, in which the contiguous line separates a contiguous area including the areas of all of the at least one conductive through-substrate via 40 from a complementary area.
- the pattern in the second photoresist 47 is transferred into the dielectric layer 30 to form a patterned dielectric layer 30', which is a remaining portion of the dielectric layer 30 after the transfer of the pattern in the second photoresist 47.
- a contiguous portion of the back surface 19 of the substrate 10 is exposed after the formation of the patterned dielectric layer 30'.
- the second photoresist 47 is subsequently removed.
- the removal of the second photoresist 47 is selective to the substrate 10 and the patterned dielectric layer 30'.
- a conductive material layer 50L is deposited on the back surface 19 of the substrate 10 and the exposed surface(s), i.e., the backside end surface(s), of at least one conductive through- substrate via 40.
- the conductive material layer 50L has a conductive material such as W, Al, Cu, Ag, Au, WN, TaN, TiN, a conducting doped semiconductor material, a conductive metal semiconductor alloy, or a combination thereof.
- the conductive material of the conductive material layer 50L is a metallic material.
- the conductive material layer 50L can be formed, for example, by electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof.
- the thickness of the conductive material layer 50L can be from 100 nm to 10,000 nm, and typically from 300 nm to 3,000 nm, although lesser and greater thicknesses can also be employed.
- the conductive material layer 50L can comprise a non-recessed region 3 and a recessed region 5. The non-recessed region 3 is located over the patterned dielectric layer 30' and the at least one conductive through- substrate via 40.
- the recessed region 5 is located over a portion of the back surface 19 of the substrate 10 that does not contact the patterned dielectric layer 30'.
- the conductive material layer 50L can have substantially vertical sidewalls between an exposed surface of the non-recessed region 3 and an exposed surface of the recessed region 5.
- a third photoresist 57 is applied over the conductive material layer 50L and lithographically patterned into two contiguous photoresist portions that are separated from each other.
- a first contiguous region 57A of the third photoresist 57 overlies all of the at least one conductive through- substrate via 40.
- the area covered by the first contiguous region 57A of the third photoresist 57 is less than the area covered by the second photoresist 47 (See FIG. 6A) after lithographic patterning.
- the second contiguous region 57B of the third photoresist 57 overlies all of the recessed region 5 (See FIGS. 7A and 7B) of the conductive material layer 50L.
- the sidewalls of the second contiguous region 57B of the third photoresist 57 overlie the patterned dielectric layer 30'.
- the pattern in the third photoresist 57 is transferred into the conductive material layer 50L, for example, by an anisotropic etch.
- a first remaining portion of the conductive material layer 50L is formed under the first contiguous potion 57A of the third photoresist 57, and a second remaining portion of the conductive material layer 50L is formed under the second contiguous region 57B of the third photoresist 57.
- the first remaining portion of the conductive material layer 50L is derived from the portion of the conductive material layer 50L in the non-recessed region 3 (See FIGS. 7 A and 7B).
- the second remaining portion of the conductive material layer 50L comprises the portion of the conductive material layer 50L in the recessed region 5 (See FIGS. 7A and 7B).
- the first remaining portion of the conductive material layer 50L constitutes a contiguous metal wiring structure 5 OA
- the second remaining portion of the conductive material layer 50L constitutes a second contiguous metal wiring structure 5 OB.
- the first contiguous metal wiring structure 50A and the second contiguous metal wiring structure 5 OB are laterally separated from each other by a contiguous space.
- the first contiguous metal wiring structure 50A is formed on at least one conductive through-substrate via 40 in the at least one laterally-insulated through-substrate contact structure (12, 40).
- the first contiguous metal wiring structure 50A is vertically spaced from the back surface 19 of the substrate 10 by the patterned dielectric layer 30'.
- the second contiguous metal wiring structure 50B is formed directly on the back surface 19 of the substrate 10.
- the third photoresist 57 are subsequently removed, for example, by ashing.
- the patterned dielectric layer 30' can have a distal surface 33 that is substantially coplanar with an end surface of the at least one conductive through- substrate via 40.
- the patterned dielectric layer 30' can have a proximal surface 31 that contacts a portion of the back surface
- the patterned dielectric layer 30' can have a vertical surface 35 that contacts outer sidewalls of the at least one dielectric liner 12.
- a proximal surface 51 of the first contiguous metal wiring structure 50A is in contact with the distal surface 33 of the patterned dielectric layer 30'. The entirety of a proximal surface
- first contiguous metal wiring structure 50A can be coplanar with the distal surface 33 of the patterned dielectric layer 30'. All vertical sidewalls 56 of the first contiguous metal wiring structure 50A can be directly adjoined to the distal surface 33 of the patterned dielectric layer 30'. Some vertical sidewalls 58 of the second contiguous metal wiring structure 50B can be directly adjoined to the distal surface 33 of the patterned dielectric layer
- the distal surface 59 of the second contiguous metal wiring structure 50B can be coplanar with a distal surface 53 of the first contiguous metal wiring structure 50A.
- the first contiguous metal wiring structure 50A functions as one node of the first exemplary photovoltaic cell
- the second contiguous metal wiring structure 5 OB functions as the other node of the first exemplary photovoltaic cell.
- the first contiguous metal wiring structure 50A makes an electrical contact with the surface region 39 through the at least one conductive through- substrate via 40.
- the second contiguous metal wiring structure 5 OB makes physical contact and electrical contact with the back surface 19 of the substrate 10, thereby making electrical contact with a backside surface region 38 of the substrate 10.
- Conductive wiring structure can be absent on the front side of the first exemplary photovoltaic cell structure because all conductive wiring structures (5 OA, 50B) are provided on the backside of the substrate 10.
- the entirety of the front surface of the first exemplary photovoltaic cell structure can be covered by the anti-reflective layer 20 that is contiguous and does not contain any hole.
- the first exemplary photovoltaic cell structure provides enhanced area utilization over prior art photovoltaic cell structures that require a set of conductive wiring structures on the front side.
- the enhanced area utilization in the first exemplary photovoltaic cell structure increases the efficiency and/or compactness over prior art structures.
- the loss in the effective area for photogeneration of electric charges in the first exemplary photovoltaic cell structure is due to the area occupied by the at least one laterally- insulated through-substrate contact structures (12, 40), which can be less than 2 % of the area of the substrate 10. This contrasts with areal loss over 10 % due to the presence of metal lines on the front side of prior art photovoltaic cell structures.
- the first exemplary photovoltaic cell structure provides greater efficiency by utilizing more fraction of the area provided by the substrate 10 for photogeneration of electricity.
- the at least one conductive through-substrate via 40 provides an effective and short conductive path to the backside of the substrate 10, and the first contiguous metal wiring structures 50A can utilize a significant fraction, e.g., 40 % or more, of the area of the substrate 10 to form a conductive path, thereby reducing the resistivity of the first contiguous metal wiring structures 5 OA.
- a second exemplary photovoltaic cell structure according to a second preferred embodiment of the present invention is derived from the first exemplary photovoltaic cell structure of FIG. 3 by employing a conductive material for the anti-reflective layer 20 and extending the anisotropic etch during the formation of the at least one through-substrate trench 11.
- the anisotropic etch employed to form the at least one through-substrate trench 11 is extended to etch through all of the surface region 39 in the substrate 10.
- the anisotropic etch can employ an endpoint scheme to stop at the proximal surface 21 of the anti-reflective layer 20.
- the etch chemistry for the anisotropic etch can be selected to be selective to the material of the anti-reflective layer 20, i.e., to etch only the photosensitive material of the substrate 10 and not to etch the material of the anti-reflective layer 20.
- the anti-reflective layer 20 can be partially etched so that a bottom surface of the at least one through-substrate trench 11 is located within a portion of the anti-reflective layer 20.
- At least one dielectric liner 12 is formed on the sidewalls of the at least one through- substrate trench 11 as in the first embodiment.
- the at least one dielectric liner 12 can have the same composition as, and can be formed by the same methods as, in the first embodiment
- the at least one dielectric liner 12 of the second embodiment contacts the anti- reflective layer 20.
- the at least one dielectric liner 12 of the second embodiment extends from the distal surface 33 of the dielectric layer 30, through the dielectric layer 30 and the substrate 10, and to the anti-reflective layer 20.
- the at least one through-substrate trench 11 is filled with a conductive material to form at least one conductive through- substrate via 40 as in the first embodiment.
- the conductive material can have the same composition as, and can be formed by the same methods as, in the first embodiment.
- the at least one dielectric liner 12 and the at least one conductive through-substrate via 40 collectively constitute at least one laterally- insulated through-substrate contact structure (12, 40), which is embedded in the substrate 10, and provides a vertical conductive path that is electrically isolated in the lateral direction.
- the at least one conductive through-substrate via 40 is conductively connected to the surface region 39 of the substrate 10 through the anti-reflective layer 20, but is not conductively connected to any other portion of the substrate 10. Particularly, the conductive through- substrate via 40 is electrically isolated from the back surface 19 of the substrate 10.
- FIGS. 6 A - 9B are performed in the same manner as in the first embodiment to provide the second exemplary photovoltaic cell structure shown in FIGS. 12A and 12B.
- the first contiguous metal wiring structure 50A functions as one node of the first exemplary photovoltaic cell
- the second contiguous metal wiring structure 50B functions as the other node of the first exemplary photovoltaic cell.
- the first contiguous metal wiring structure 50A makes an electrical contact with the surface region 39 through the at least one conductive through- substrate via 40 and the anti- reflective layer 20 that comprise a conductive material.
- a third exemplary photovoltaic cell structure according to a third preferred embodiment of the present invention can be derived from the first exemplary photovoltaic cell structure of FIGS. 9 A and 9B or from the second exemplary photovoltaic cell structure of FIGS. 12A and 12B by recessing at least one portion of the substrate 10 from the front side.
- a fourth photoresist 67 can be applied on a distal surface 23 of the anti-reflective layer 20 and lithographically patterned to form at least one opening therein.
- the at least one opening in the fourth photoresist 67 is aligned to the at least one conductive through- substrate via 40 located within the substrate 10.
- the pattern in the at least one opening in the fourth photoresist 67 is transferred through the anti-reflective layer 20 and into the surface region 39 of the substrate 10 by an etch.
- the etch may be an anisotropic etch that employs the fourth photoresist 67 as the etch mask.
- the etch forms at least one recessed region 61 on the front side of the substrate 10, i.e., on the side of the substrate 10 that comprises the surface region 39.
- the front side is located on the opposite side of the first and second contiguous metal wiring structures (5 OA, 50B).
- An end surface of the at least one conductive through-substrate via 40 is exposed in each of the at least one recessed region 61.
- the depth of the at least one recessed region 61 is controlled so that the bottom surface of each recessed region 61 is located within the surface region 39 of the substrate 10.
- the fourth photoresist 67 is subsequently removed selective to the at least one conductive through- substrate via 40.
- the anti-reflective layer 20 can be a dielectric material, a semiconducting material, or a conductive material. If the at least one conductive through- substrate via 40 is a one-dimensional array or a two-dimensional array of a plurality of conductive through-substrate vias 40, the at least one recessed region 61 can be a one- dimensional array or a two-dimensional array of a plurality of recessed regions 61.
- the front side of the first exemplary photovoltaic cell structure can have no conductive wiring structure because all conductive wiring structures (5 OA, 50B) are provided on the backside of the substrate 10.
- the second exemplary photovoltaic cell structure increases the efficiency and/or compactness over prior art structures.
- At least one conductive plug 60 can be formed by depositing a conductive material in the at least one recessed region 61 and planarizing the conductive material.
- the planarization may be effected, for example, by chemical mechanical polishing, a recess etch, or a combination thereof.
- a top surface of the at least one conductive plug 60 can be coplanar with the distal surface 23 of the anti-reflective layer 20.
- the at least one conductive plug 60 contacts the at least one conductive through- substrate via 40 and the surface portion 10 of the substrate 10 that comprises the
- the at least one conductive plug 60 laterally contacts sidewalls of the anti-reflective layer 20.
- the at least one conductive through-substrate via 40 is a one-dimensional array or a two- dimensional array of a plurality of conductive through-substrate vias 40
- the at least one conductive plug 60 can be a one-dimensional array or a two-dimensional array of a plurality of conductive plugs 60.
- Each of the plurality of conductive plugs 60 does not contact any other of the plurality of conductive plugs 60.
- the lateral dimensions of at least one conductive plug 60 can be greater, equal to, or lesser than the lateral dimensions of the at least one conductive through- substrate via 40.
- the area covered by the at least one conductive plug can be greater, equal to, or lesser than a horizontal cross-sectional area of the at least one conductive through- substrate via 40.
- the sidewalls of the at least one conductive plug 60 contacts sidewalls of the surface region 39 of the substrate 10.
- a bottom surface of the at least one conductive plug 60 contacts the end surface of an underlying conductive through-substrate via 40, and can contact a horizontal surface of the surface region 39 depending on the lateral extent of the at least one conductive plug 60.
- the front side of the third exemplary photovoltaic structure is studded with the at least one conductive plug 60.
- Each of at least one conductive plug 16 is not connected to another of the least one conductive plug 60 on the front side.
- a conductive line is not present on the front side of the third exemplary photovoltaic structure.
- the area covered by the at least one conductive plug 60 can be minimized to a level lesser than prior art structures enable. For example, metal lines on the front surface of prior art photovoltaic cells cover over 10 % of the area of a substrate.
- the at least one conductive plug 60 in the third preferred embodiment of the present invention can be employed to cover less than 2 % of the area of the substrate 10 without degradation in performance because the at least one conductive plug 60 and the at least one conductive through-substrate via 40 provides an effective and short conductive path to the backside of the substrate 10, and the first contiguous metal wiring structures 50A can utilize a significant fraction, e.g., 40 % or more, of the area of the substrate to form a conductive path.
- a fourth exemplary photovoltaic cell structure according to a fourth preferred embodiment of the present invention can be derived from the second exemplary photovoltaic cell structure of FIGS. 12A and 12B by recessing at least one portion of the anti-reflective layer 20.
- the anti-reflective layer 20 can be a dielectric material, a semiconducting material, or a conductive material.
- a fourth photoresist (not shown) can be applied on a distal surface 23 of the anti-reflective layer 20 and lithographically patterned to form at least one opening therein.
- the at least one opening in the fourth photoresist is aligned to the at least one conductive through- substrate via 40 located within the substrate 10.
- the pattern in the at least one opening in the fourth photoresist is transferred through the anti-reflective layer 20.
- the pattern in the fourth photoresist is transferred is not transferred into the substrate 10.
- a conductive material layer is deposited and lithographically patterned to form at least one conductive plug 60.
- the at least one conductive plug 60 contacts end surface(s) of the at least one conductive through-substrate via 40 and the front surface 17 of the substrate 10 that comprises the photovoltaic material.
- the at least one conductive plug 60 laterally contacts sidewalls of the anti-reflective layer 20.
- the at least one conductive through-substrate via 40 is a one-dimensional array or a two- dimensional array of a plurality of conductive through-substrate vias 40
- the at least one conductive plug 60 can be a one-dimensional array or a two-dimensional array of a plurality of conductive plugs 60.
- Each of the plurality of conductive plugs 60 does not contact any other of the plurality of conductive plugs 60.
Abstract
Description
Claims
Priority Applications (3)
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CN201080052233.6A CN102906883B (en) | 2009-11-19 | 2010-10-26 | Contacting without grid line for photovoltaic cell |
DE112010004501.1T DE112010004501B4 (en) | 2009-11-19 | 2010-10-26 | Contact without grid lines for a photovoltaic cell |
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US12/621,685 US8115097B2 (en) | 2009-11-19 | 2009-11-19 | Grid-line-free contact for a photovoltaic cell |
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KR100997113B1 (en) * | 2008-08-01 | 2010-11-30 | 엘지전자 주식회사 | Solar Cell and Method for Manufacturing thereof |
DE102009005168A1 (en) | 2009-01-14 | 2010-07-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Solar cell and method for producing a solar cell from a silicon substrate |
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2009
- 2009-11-19 US US12/621,685 patent/US8115097B2/en not_active Expired - Fee Related
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2010
- 2010-10-26 DE DE112010004501.1T patent/DE112010004501B4/en active Active
- 2010-10-26 GB GB1202928.6A patent/GB2488421B/en not_active Expired - Fee Related
- 2010-10-26 WO PCT/EP2010/066149 patent/WO2011061043A2/en active Application Filing
- 2010-10-26 CN CN201080052233.6A patent/CN102906883B/en not_active Expired - Fee Related
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2012
- 2012-02-01 US US13/364,171 patent/US8669466B2/en not_active Expired - Fee Related
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10775426B2 (en) | 2010-02-16 | 2020-09-15 | Stmicroelectronics S.R.L. | System and method for electrical testing of through silicon vias (TSVs) |
US9966318B1 (en) * | 2017-01-31 | 2018-05-08 | Stmicroelectronics S.R.L. | System for electrical testing of through silicon vias (TSVs) |
Also Published As
Publication number | Publication date |
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DE112010004501B4 (en) | 2019-05-16 |
CN102906883B (en) | 2015-12-16 |
WO2011061043A3 (en) | 2011-10-27 |
GB2488421A (en) | 2012-08-29 |
GB2488421B (en) | 2013-11-20 |
US8669466B2 (en) | 2014-03-11 |
CN102906883A (en) | 2013-01-30 |
DE112010004501T5 (en) | 2012-10-31 |
US20100218816A1 (en) | 2010-09-02 |
GB201202928D0 (en) | 2012-04-04 |
US20120125433A1 (en) | 2012-05-24 |
US8115097B2 (en) | 2012-02-14 |
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