WO2011009332A1 - 一种数据缓存的处理方法和装置 - Google Patents
一种数据缓存的处理方法和装置 Download PDFInfo
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- WO2011009332A1 WO2011009332A1 PCT/CN2010/073072 CN2010073072W WO2011009332A1 WO 2011009332 A1 WO2011009332 A1 WO 2011009332A1 CN 2010073072 W CN2010073072 W CN 2010073072W WO 2011009332 A1 WO2011009332 A1 WO 2011009332A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
Definitions
- the present invention relates to the field of network communication technologies, and in particular, to a method and an apparatus for processing a data buffer.
- the data cache control module 101 when the data is cached, as shown in FIG. 1, the data cache control module 101 generally splits the data packet into a plurality of data pieces according to a certain rule and stores them in the memory 102. When the data packet is output, The plurality of pieces of data that are split are combined to be restored to the original data package.
- the data slice length of the packet split should be related to factors such as the minimum packet length, internal packet processing speed, and memory data bit width.
- Queue storage usually uses different queue storage areas to dynamically save. Under the condition of considering the bandwidth utilization of dynamic storage, any free area can be put into the queue data that needs to be cached at any time.
- the present invention provides a data cache processing apparatus, including a data cache control module connected to the memory, where the data cache control module is configured to: The received data is cached in the memory, and after the buffer is finished, the data buffered in the memory is read out, the device further includes a data detecting module connected to the data buffer control module; the data cache control The module is further configured to: provide the data detection module with cache data to be written and a memory space address in the memory for storing the cache data before writing the cache data in the memory; After the storage space address reads the cached data, the data detection module is provided with the read cache data; and is further configured to: learn from the data detection module, a normal or abnormal state of the storage space in the memory, And storing the subsequent cache data only in the normal storage
- the data output control unit is configured to: acquire the memory from the storage unit Normal or abnormal state is stored in this cache data storage space, this storage status notification to the data cache control module.
- the data detection module includes a data input control unit, a storage unit, and a data output control unit that are sequentially connected; the data input control unit is configured to: acquire the to-be-waited from the data cache control module The cached data is stored and stored in the storage unit; and is further configured to: after the read cached data is obtained from the data cache control module, compare the read cached data and the stored write to be written When the cached data is the same, it is determined that the storage space for storing the cached data in the memory is normal; when the read cached data is different from the stored cached data to be written, the memory is determined a storage space exception for storing the cached data, and storing a normal or abnormal state of the storage space in the memory for storing the cached data in the storage unit; the data output control unit is configured to:
- the data detection module includes a data input control unit, a storage unit, and a data output control unit connected in sequence; the data input control unit is configured to: obtain the cache to be written from the data cache control module After the data, generating first verification data according to the cache data to be written and saving to the storage unit; the data output control unit is configured to: acquire the readout from the data cache control module After the data is buffered, the second check data is generated according to the read buffer data, and the first check data is obtained from the storage unit, and when the first check data and the second check data are determined to be the same Determining that the storage space for storing the cached data in the memory is normal; determining that the first check data and the second check data are different, determining a storage space in the memory for storing the cached data Abnormally storing a normal or abnormal state of the storage space in the memory for storing the cached data in the storage unit; According to the cache control module is further configured to: by reading the memory cell, normal or abnormal status known stored in the memory space.
- the data detection module includes a data input control unit, a storage unit, and a data output control unit connected in sequence; the data input control unit is configured to: obtain the cache to be written from the data cache control module After the data, the first verification data is generated according to the cached data to be written and sent to the data cache control module; The data output control unit is configured to: obtain the read cache data and the corresponding first check data from the data cache control module, and generate second check data according to the read cache data.
- the control module is further configured to: receive the first verification data sent by the data input control unit, store the cache data to be written and the first verification data in a memory; and, by reading the storage The unit learns the normal or abnormal state of the storage space in the memory.
- the present invention provides a data cache processing method, including: storing cache data in a memory; after reading the cache data from a storage space address in which the cache data is stored in the memory, determining the Whether the cached data that has been read is the same as the cached data to be written before being stored, if the same, it is determined that the storage space for storing the cached data in the memory is normal; when not identical, determining that the memory is used for The storage space for storing this cached data is abnormal; When the cache data is stored in the subsequent data cache process, only the cache data is stored in the storage space in the normal state in the memory.
- the method before storing the cached data in the memory, the method further includes: generating first check data according to the cached data to be written before performing storage; and storing the cached data in the memory comprises: The written cache data and the first check data are both stored in the memory; in the step of reading the cache data, the cache data and the corresponding first check data are read out; After the data is cached, the method further includes: generating second check data according to the read cache data; determining whether the read cache data is the same as the cache data to be written before performing storage In the step, by determining whether the first check data and the second check data are the same, it is determined whether the read cache data is the same as the cache data to be written before being stored.
- the method further includes: storing a normal or abnormal state of the storage space of the cached data; wherein, by maintaining a memory mapping table, recording a state of the storage space in the memory,
- the constituent elements of the memory map correspond to the storage space segment of the memory, and each component element represents the state of the corresponding storage space segment; and the state of the storage space segment is determined to be written into the memory mapping table.
- the space occupied by the constituent elements of the memory mapping table is one bit, and the capacity of the storage space segment corresponding to each component element of the memory mapping table is the same.
- the present invention can be implemented by simple code migration, and can be directly applied to existing devices for data buffering, to detect whether there is unsafe storage space in the memory, and to improve data.
- the reliability of the cache is a requirement that can be implemented by simple code migration, and can be directly applied to existing devices for data buffering, to detect whether there is unsafe storage space in the memory, and to improve data.
- the data cache processing device includes a data cache control module 101 and a memory 102 connected to the data cache control module 101, and a data detection module 103 connected to the data cache control module 101.
- the data cache control module 101 The method is configured to: cache the received data in the memory 102, and read out the data buffered in the memory after the buffer is finished, and further set to: before the buffer data is written in the memory, to the data detection module.
- the buffer data that has been read out is provided; and is further configured to: learn from the data detection module whether the storage space in the memory is normal or abnormal, and only store the cache data in the normal storage space, and isolate the abnormal storage space.
- the data detecting module 103 is configured to: determine the cached data that has been read out and the to-be-written Whether the cached data is the same, if it is the same, it is determined that the storage space for storing the cached data in the memory is normal; when not the same, determining that the storage space for storing the cached data in the memory is abnormal, and
- the data storage control module is configured to include the data input control unit 201, the storage unit 202
- the input control unit 201 is configured to: after acquiring the cached data to be written from the data cache control module, generate first check data according to the cached data to be written, and store the check data After obtaining the read cache data from the data cache control module, generating second check data according to the read cache data; determining the first check data and When the second check data is the same, determining that the storage space for storing the cache data in the memory is normal; When the verification data and the second verification data are different, determining a storage space abnormality in the memory for storing the cached data, and
- the data output control unit 203 is configured to: acquire a normal or abnormal state of the storage space in the memory for storing the cached data from the storage unit, and notify the data cache control module of the state of the storage space.
- the storage unit 202 is configured to: maintain a memory mapping table, the constituent elements of the memory mapping table correspond to the storage space segment of the memory, and the space occupied by the constituent elements of the memory mapping table is one bit (for example, when the bit value is 1) Indicates that the storage space segment corresponding to the component is normal. When the bit value is 0, the storage space segment corresponding to the component is normal.
- the storage space segment corresponding to each component of the memory mapping table has the same or different capacity. Easy to implement, generally set the storage space segment with the same capacity (for example, both 1K bits).
- the storage unit 202 is set At boot time, the memory map is initialized, and each memory address space in the default memory is normal.
- the data input control unit 201 determines the state of the storage space segment, writes the state of the storage space segment to the memory mapping table; the data output control unit 203 provides the memory mapping table to the data cache control module 101, and the data cache When the control module 101 stores the new cached data, it queries the memory map to store the data only in the storage space segment identified as normal.
- the foregoing technical solution may be implemented in the following manners: after the data input control unit 201 acquires the cached data to be written from the data cache control module 101, according to the cached data to be written Generating the first check data, and sending the data to the data cache control module 101, the data cache control module 101 storing the cache data to be written and the first check data in the memory 102; After acquiring the read cache data and the first check data from the data cache control module 101, the second check data is generated according to the read cache data, and the first school is determined.
- the verification data and the second verification data are the same, determining that the storage space for storing the cache data in the memory is normal; determining that the first verification data and the second verification data are different, determining the memory a storage space exception for storing the cached data, and storing a normal or abnormal state of the storage space in the memory for storing the cached data in the storage list
- the data input control unit 201 acquires the cached data to be written from the data cache control module 101
- the first check data is generated according to the cached data to be written and saved to the
- the data output control unit 203 obtains the read cache data from the data cache control module 101
- the second check data is generated according to the read cache data.
- the storage unit 202 obtains the first verification data, and determines that the first verification data and the second verification data are the same, determining that the storage space for storing the cached data in the memory is normal; When the first check data and the second check data are different, determining a storage space abnormality in the memory for storing the cached data, and using a normal or abnormal storage space in the memory for storing the cached data.
- the state is stored in the storage unit 202; or, the data input control unit 201 acquires the cached data to be written from the data cache control module 101, and then saves To the storage unit 202; after the data output control unit 203 acquires the read cache data from the data cache control module 101, compare the read cache data and the stored cache to be written When the cached data is the same, the storage is determined
- the storage space for storing the cached data in the storage is normal; when the read cached data is different from the stored cached data to be written, the storage space for storing the cached data in the storage is determined.
- the first check data is generated according to the cached data to be written and saved to the storage unit 202; and is acquired by the data output control unit 203 from the data cache control module 101.
- the cache control module 101 can be configured to: by reading the storage unit 202, learn the normal or abnormal state of the storage space in the memory.
- the method of the embodiment of the present invention includes: storing cache data in a memory; after reading the cache data from a storage space address in which the cache data is stored in the memory, determining the cached data that has been read and waiting for storage Whether the written cache data is the same, if the same, it is determined that the storage space for storing the cache data in the memory is normal; when not identical, the memory is determined The storage space used to store this cached data is abnormal; when the cached data is stored in the subsequent data cache process, only the cached data is stored in the storage space in the normal state in the memory.
- the method for improving the reliability of the memory data cache by using the apparatus shown in FIG. 2 and FIG. 3 may include the following steps: Step 1: The device is started after power-on or reset; Step 2, the data input control module 201 automatically initializes the mapping list. The value is written into the mapping table and stored in the storage unit 202.
- Step 4 Before the data cache control module 101 writes the cache data to the memory 102, the data input control module 201 learns from the data cache control module 101 the cache data to be written and the storage space address in the memory for storing the cache data, and Generating the first verification data according to the cache data to be written and saving to the storage unit 202; in this step, the present invention does not limit the method for generating the verification data according to the cache data to be written, and those skilled in the art It is possible to use the method of generating the test data that it knows. Step 5: The data cache control module 101 stores the cache data in the memory 102. Step 6.
- the data output control module 203 is from the data cache control module 101.
- the data input control module 201 determines that the storage space address corresponds to the first Whether the check data and the second check data are the same, if different, the value of the component element corresponding to the storage space address storing the cache data in the memory map is 0, indicating that the storage space is abnormal, and the updated
- the memory map table is notified to the data cache control module 101; if the same, the memory map is not identified; in step 8, the data cache control module 101 only stores the memory in subsequent data cache operations.
- the data is stored in the storage space address indicated by the constituent elements having a value of 1 in the shot table.
- the generated first verification data may be stored in an external memory (because the external memory data width is generally slightly larger than the data slice data), and the generated second verification data is directly connected to the memory.
- the first check data read out is compared, that is, after the first check data is generated, the cache data to be written and the corresponding first check data are stored in the memory; when the data is read, the cache is read Reading data and corresponding first check data, generating second check data according to the read buffer data, and determining whether the first check data and the second check data are the same, to determine the read cache Whether the data is the same as the cached data to be written before being stored.
- the data input control module 201 generates the first check data according to the cache data to be written, and sends the first check data to the data cache control module 101.
- the data cache control module 101 is in the memory 102. Storing the cache data and the first check data; in step 6, the data output control module 203 obtains the read cache data, the corresponding first check data, and the memory for storing the cache from the data cache control module 101. The storage address of the data is generated, and the second verification data is generated according to the read buffer data.
- the data output control module 203 determines whether the first verification data and the second verification data corresponding to the storage space address are the same. If it is different, the value of the component element corresponding to the storage space address storing the cached data in the memory mapping table is 0, indicating that the storage space is abnormal; if the same, the memory mapping table is not identified.
- the other steps are the same as described above.
- the above method can conveniently detect whether there is unsafe storage space in the memory, and further improve the reliability of the data cache.
- the present invention is applicable to a large amount of data dynamic cache, and a hardware device having data cache reliability requirements for data segmentation processing, and is generally applicable to a route switching device.
- the present invention provides a data cache processing method and apparatus, which can be implemented by simple code migration, and can be directly applied to existing devices for data caching to detect whether there is unsafe storage space in the memory and improve data. The reliability of the cache.
Abstract
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US13/383,498 US20120117325A1 (en) | 2009-07-24 | 2010-05-21 | Method and device for processing data caching |
BR112012001458A BR112012001458B1 (pt) | 2009-07-24 | 2010-05-21 | método e dispositivo para processamento de armazenamento em cache de dados |
EP10801892.0A EP2458504B1 (en) | 2009-07-24 | 2010-05-21 | Method and device for processing data caching |
Applications Claiming Priority (2)
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CN200910161519.7 | 2009-07-24 | ||
CN2009101615197A CN101615145B (zh) | 2009-07-24 | 2009-07-24 | 一种提高存储器数据缓存可靠性的方法和装置 |
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WO2011009332A1 true WO2011009332A1 (zh) | 2011-01-27 |
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PCT/CN2010/073072 WO2011009332A1 (zh) | 2009-07-24 | 2010-05-21 | 一种数据缓存的处理方法和装置 |
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US (1) | US20120117325A1 (zh) |
EP (1) | EP2458504B1 (zh) |
CN (1) | CN101615145B (zh) |
BR (1) | BR112012001458B1 (zh) |
WO (1) | WO2011009332A1 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101615145B (zh) * | 2009-07-24 | 2011-12-07 | 中兴通讯股份有限公司 | 一种提高存储器数据缓存可靠性的方法和装置 |
CN102567133B (zh) * | 2011-12-31 | 2015-03-04 | 广州视声电子科技有限公司 | 一种通过中断实现通信方法、i2c器件及i2c系统 |
JP5971547B2 (ja) * | 2012-02-15 | 2016-08-17 | 国立大学法人 東京大学 | メモリコントローラ,データ記憶装置およびメモリの制御方法 |
US9116628B2 (en) * | 2012-03-23 | 2015-08-25 | Polycore Software, Inc. | Apparatus and method for providing a multicore programming platform |
CN104359519A (zh) * | 2014-11-28 | 2015-02-18 | 成都千嘉科技有限公司 | 一种用于流量计的参数存储方法 |
CN104359520A (zh) * | 2014-11-28 | 2015-02-18 | 成都千嘉科技有限公司 | 一种用于流量计的参数存储系统 |
CN104580398B (zh) * | 2014-12-22 | 2018-06-01 | 北京像素软件科技股份有限公司 | 一种网络内容推送方法、装置和网络内容展示客户端 |
CN108934187B (zh) | 2017-03-29 | 2020-08-25 | 华为技术有限公司 | 分布式存储系统的访问方法和相关装置和相关系统 |
US10581762B2 (en) * | 2017-12-06 | 2020-03-03 | Mellanox Technologies Tlv Ltd. | Packet scheduling in a switch for reducing cache-miss rate at a destination network node |
CN109165115B (zh) * | 2018-06-26 | 2021-11-09 | 北京中电华大电子设计有限责任公司 | 一种增强flash存储器可靠性的方法 |
CN109636300A (zh) * | 2018-10-16 | 2019-04-16 | 深圳壹账通智能科技有限公司 | 账单的检测方法、装置、终端及计算机可读存储介质 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10269148A (ja) * | 1997-03-27 | 1998-10-09 | Mitsubishi Electric Corp | 回路構成要素診断装置 |
CN1315732A (zh) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | 随机存储器的自动检测方法及其检测电路 |
CN101359512A (zh) * | 2008-09-02 | 2009-02-04 | 中兴通讯股份有限公司 | 一种外部存储器的检测方法和装置 |
CN101615145A (zh) * | 2009-07-24 | 2009-12-30 | 中兴通讯股份有限公司 | 一种提高存储器数据缓存可靠性的方法和装置 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5200959A (en) * | 1989-10-17 | 1993-04-06 | Sundisk Corporation | Device and method for defect handling in semi-conductor memory |
AU4798793A (en) * | 1992-08-10 | 1994-03-03 | Monolithic System Technology, Inc. | Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration |
JP2665718B2 (ja) * | 1993-11-10 | 1997-10-22 | 日本電気エンジニアリング株式会社 | 情報処理装置のキャッシュメモリテスト方法 |
US5893152A (en) * | 1996-03-08 | 1999-04-06 | Sun Microsystems, Inc. | Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory |
US6134684A (en) * | 1998-02-25 | 2000-10-17 | International Business Machines Corporation | Method and system for error detection in test units utilizing pseudo-random data |
US6349369B1 (en) * | 1999-11-09 | 2002-02-19 | International Business Machines Corporation | Protocol for transferring modified-unsolicited state during data intervention |
JP4165990B2 (ja) * | 1999-12-20 | 2008-10-15 | Tdk株式会社 | メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びに、フラッシュメモリへのデータの書き込み方法 |
DE19963689A1 (de) * | 1999-12-29 | 2001-07-12 | Infineon Technologies Ag | Schaltungsanordnung eines integrierten Halbleiterspeichers zum Speichern von Adressen fehlerhafter Speicherzellen |
US6658592B1 (en) * | 2000-07-20 | 2003-12-02 | Emc Corporation | Error detection in disk storage systems |
JP2002074999A (ja) * | 2000-08-23 | 2002-03-15 | Sharp Corp | 不揮発性半導体記憶装置 |
US6700398B1 (en) * | 2000-11-28 | 2004-03-02 | Kingston Technology Company | In-line D.C. testing of multiple memory modules in a panel before panel separation |
JP4049297B2 (ja) * | 2001-06-11 | 2008-02-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US20030014687A1 (en) * | 2001-07-10 | 2003-01-16 | Grandex International Corporation | Nonvolatile memory unit comprising a control circuit and a plurality of partially defective flash memory devices |
JP3822081B2 (ja) * | 2001-09-28 | 2006-09-13 | 東京エレクトロンデバイス株式会社 | データ書込装置、データ書込制御方法及びプログラム |
US20040015762A1 (en) * | 2002-07-22 | 2004-01-22 | Finisar Corporation | Scalable system testing tools |
US7634614B2 (en) * | 2003-01-13 | 2009-12-15 | Sierra Logic | Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves and that support virtual disk formatting |
WO2004114116A1 (ja) * | 2003-06-19 | 2004-12-29 | Fujitsu Limited | キャッシュ二重化方式におけるミラーキャッシュからの書き戻し方法 |
JP4141940B2 (ja) * | 2003-11-28 | 2008-08-27 | 株式会社東芝 | ディスク装置及びディスク再生方法 |
US7389465B2 (en) * | 2004-01-30 | 2008-06-17 | Micron Technology, Inc. | Error detection and correction scheme for a memory device |
JP4411602B2 (ja) * | 2004-12-16 | 2010-02-10 | 日本電気株式会社 | フォールトトレラント・コンピュータシステム |
WO2007010829A1 (ja) * | 2005-07-15 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | 不揮発性記憶装置、メモリコントローラ及び不良領域検出方法 |
US20070097817A1 (en) * | 2005-10-27 | 2007-05-03 | Mediatek Inc. | Method and system for recording data with data verifying process |
KR100805840B1 (ko) * | 2006-09-01 | 2008-02-21 | 삼성전자주식회사 | 캐시를 이용한 플래시 메모리 장치 및 그것의 프로그램방법 |
US8812931B2 (en) * | 2006-11-21 | 2014-08-19 | Freescale Semiconductor, Inc. | Memory system with ECC-unit and further processing arrangement |
US7642105B2 (en) * | 2007-11-23 | 2010-01-05 | Kingston Technology Corp. | Manufacturing method for partially-good memory modules with defect table in EEPROM |
JP5127491B2 (ja) * | 2008-02-08 | 2013-01-23 | 株式会社日立製作所 | ストレージサブシステム及びこれの制御方法 |
JP4542163B2 (ja) * | 2008-02-27 | 2010-09-08 | 富士通株式会社 | ディスクアレイ装置、ディスクアレイ制御方法及びディスクアレイ制御装置 |
JP5286956B2 (ja) * | 2008-06-13 | 2013-09-11 | 富士通株式会社 | 制御方法、ディスクアレイ装置 |
CN101290628B (zh) * | 2008-06-17 | 2010-06-16 | 中兴通讯股份有限公司 | 一种数据文件更新存储方法 |
CN101645846B (zh) * | 2009-09-02 | 2011-10-26 | 中兴通讯股份有限公司 | 一种路由交换设备及其数据缓存的方法 |
GB0915598D0 (en) * | 2009-09-07 | 2009-10-07 | St Microelectronics Res & Dev | Error detection |
-
2009
- 2009-07-24 CN CN2009101615197A patent/CN101615145B/zh not_active Expired - Fee Related
-
2010
- 2010-05-21 US US13/383,498 patent/US20120117325A1/en not_active Abandoned
- 2010-05-21 BR BR112012001458A patent/BR112012001458B1/pt not_active IP Right Cessation
- 2010-05-21 EP EP10801892.0A patent/EP2458504B1/en not_active Not-in-force
- 2010-05-21 WO PCT/CN2010/073072 patent/WO2011009332A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10269148A (ja) * | 1997-03-27 | 1998-10-09 | Mitsubishi Electric Corp | 回路構成要素診断装置 |
CN1315732A (zh) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | 随机存储器的自动检测方法及其检测电路 |
CN101359512A (zh) * | 2008-09-02 | 2009-02-04 | 中兴通讯股份有限公司 | 一种外部存储器的检测方法和装置 |
CN101615145A (zh) * | 2009-07-24 | 2009-12-30 | 中兴通讯股份有限公司 | 一种提高存储器数据缓存可靠性的方法和装置 |
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EP2458504A1 (en) | 2012-05-30 |
BR112012001458A2 (pt) | 2016-12-13 |
CN101615145B (zh) | 2011-12-07 |
US20120117325A1 (en) | 2012-05-10 |
EP2458504A4 (en) | 2014-12-24 |
EP2458504B1 (en) | 2019-05-01 |
BR112012001458B1 (pt) | 2020-02-04 |
CN101615145A (zh) | 2009-12-30 |
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