WO2010101167A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2010101167A1
WO2010101167A1 PCT/JP2010/053391 JP2010053391W WO2010101167A1 WO 2010101167 A1 WO2010101167 A1 WO 2010101167A1 JP 2010053391 W JP2010053391 W JP 2010053391W WO 2010101167 A1 WO2010101167 A1 WO 2010101167A1
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WIPO (PCT)
Prior art keywords
insulating layer
semiconductor device
wiring
layer
forming
Prior art date
Application number
PCT/JP2010/053391
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French (fr)
Japanese (ja)
Inventor
菊池　克
中島　嘉樹
山道　新太郎
森　健太郎
Original Assignee
日本電気株式会社
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Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2011502772A priority Critical patent/JPWO2010101167A1/en
Publication of WO2010101167A1 publication Critical patent/WO2010101167A1/en

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2009-052716 (filed on Mar. 5, 2009), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • the present invention relates to a semiconductor device in which a semiconductor element is built in a wiring board and a manufacturing method thereof.
  • Patent Document 1 discloses a component built-in module including a core layer made of an electrical insulating material, and an electrical insulating layer and a plurality of wiring patterns on at least one side of the core layer.
  • the electrical insulating material of the core layer is formed from a mixture containing at least an inorganic filler and a thermosetting resin, and at least one active component and / or passive component is built in the core layer.
  • Elastic modulus at room temperature of an electrical insulating material wherein the core layer has a plurality of wiring patterns and a plurality of inner vias made of a conductive resin, and the core layer is made of a mixture containing at least an inorganic filler and a thermosetting resin. Is in the range of 0.6 to 10 GPa.
  • Patent Document 2 a plurality of substrates on which semiconductor elements are mounted are bonded with a thermosetting resin composition containing at least a thermosetting resin, and an inner via provided inside the thermosetting resin composition is used.
  • the substrate is electrically connected, and the peripheral portion except the mounting surface of the semiconductor element with the substrate is sealed with a low elastic modulus material having a lower elastic modulus than the thermosetting resin composition,
  • a technique is disclosed in which a semiconductor element is built inside a plurality of substrates.
  • Patent Document 3 in a multilayer substrate for a semiconductor device in which an electronic component such as a semiconductor element or a passive component is embedded in a composite material layer forming a part of a support substrate, the electronic component is mounted on a core substrate.
  • a technique of using a die bond material as a low elastic modulus material is disclosed.
  • the buffering effect of the low-modulus material layer which is a die bond material, alleviates the stress received from the composite material layer during the press molding of the support substrate, thereby preventing the occurrence of defects.
  • Patent Document 4 it is possible to suppress warpage and reduce the thickness of a wiring board with a built-in semiconductor chip by embedding a reinforcing structure that reinforces the insulating layer in the insulating layer in which the semiconductor chip is embedded. ,Are listed.
  • Patent Documents 5 to 7 describe a method for manufacturing a printed wiring board by a subtractive method, a semi-additive method, and a full additive method, respectively.
  • JP 2002-261449 A JP 2006-120935 A JP 2006-332327 A JP 2006-261246 A JP-A-10-51105 JP-A-9-64493 JP-A-6-334334
  • Patent Document 1 material properties of 0.6 to 10 GPa are specified, and 0.6 to 1.0 GPa is considered a low elastic modulus material. Under the condition of this low elastic modulus material, stress concentration tends to occur at the connection portion.
  • Patent Document 1 describes a method using a conductive adhesive and a method using a solder material in the connection portion. In any material, the connection portion is easily broken by the stress generated when connecting to another component or another substrate as a substrate.
  • the wiring on both sides of the core layer is embedded in the core layer, the direction of expansion and contraction in the surface due to the difference in thermal expansion coefficient between the insulating material and the wiring material occurs, the semiconductor element is built in, and one side As a result, the stress balance cannot be realized and the entire warp is greatly generated.
  • the warpage is significantly increased.
  • the stress relaxation is expected by covering the periphery of the semiconductor device with a low elastic modulus material.
  • a high elastic modulus material is used for the connection surface of the semiconductor element, the stress relaxation structure on the entire surface. Since stress is not taken, the targeted stress relaxation cannot be obtained. Further, since the substrate material having a high elastic modulus covers the periphery of the low elastic modulus material, deformation necessary for stress relaxation cannot occur in the low elastic modulus material, and a stress relaxation effect cannot be expected.
  • Patent Document 3 even if only one side of a built-in semiconductor element is made of a low elastic modulus material, the deformation required for stress relaxation cannot be secured. In particular, since the periphery is covered with a high elastic modulus material as in Patent Document 2, a stress relaxation effect cannot be expected.
  • the present invention has been made in view of such problems, and provides a semiconductor device that realizes a thin and low warpage structure by controlling overall warpage in a semiconductor device in which a semiconductor element is embedded in a wiring board. With the goal.
  • an object is to provide a semiconductor device having a total thickness of less than 200 ⁇ m with two-layer wiring.
  • a semiconductor device includes a semiconductor element, a first insulating layer that covers both front and back surfaces of the semiconductor element, a second insulating layer that covers both front and back surfaces of the first insulating layer, and the second insulating layer.
  • the elastic modulus is smaller than the elastic modulus of the second insulating layer.
  • a method of manufacturing a semiconductor device comprising: forming a wiring layer on a support; and forming a first insulating layer so as to cover the wiring layer and to be embedded in the wiring layer A step of placing a semiconductor element on the first insulating layer, a step of forming a first insulating layer again so as to cover the semiconductor element and the support, and a wiring on the first insulating layer Forming a layer; removing the support; providing a second insulating layer on both sides of the first insulating layer; and forming a wiring layer and an electrode on the surface of the second insulating layer on both sides And a process.
  • a method of manufacturing a semiconductor device includes a step of forming a second insulating layer on a support, a step of forming a wiring layer on the second insulating layer, and the wiring layer.
  • the first insulating layer has a lower elastic modulus than that of the second insulating layer, the physical property difference from the semiconductor element having a low thermal expansion coefficient can be absorbed, and effective stress relaxation can be achieved even in a thin semiconductor device. Low warpage can be realized.
  • Example 1 of this invention It is a fragmentary sectional view of the semiconductor device by Example 1 of this invention. It is a fragmentary sectional view of the semiconductor device by Example 2 of this invention. It is a fragmentary sectional view of the semiconductor device by Example 3 of this invention. It is a fragmentary sectional view of the semiconductor device by Example 4 of this invention. It is a fragmentary sectional view of the semiconductor device by Example 5 of this invention. It is a fragmentary sectional view of the semiconductor device by Example 6 of this invention. It is a manufacturing process figure of the semiconductor device by Example 7 of this invention. It is a continuation of the manufacturing-process figure of the semiconductor device by Example 7 of this invention. It is a manufacturing process figure of the semiconductor device by Example 8 of this invention.
  • the first insulating layer has a lower elastic modulus than the second insulating layer, so that the physical property difference from the semiconductor element having a low thermal expansion coefficient can be absorbed, and effective stress relaxation and low warpage can be achieved even in a thin semiconductor device. Can be realized.
  • the semiconductor element 11 includes the connection portion 12 on the surface, and the first insulating layer 13 and the second insulating layer 19 are provided.
  • the plurality of electrodes (20, 21) are connected to the connection portions 12 of the semiconductor element and the vias (17, 18) and / or wiring layers (15, 16), respectively. / Or connected to another electrode (20, 21). That is, the electrodes provided on both surfaces of the semiconductor device are connected to vias (including built-in layer vias), one or more of the wiring layers, connection portions of the semiconductor elements, electrodes on the opposite surface, and other electrodes on the same surface. At least one of them is connected.
  • the reinforcing material 14 is provided in the first insulating layer 13, and the reinforcing material 14 is provided.
  • the front and back sides are covered with the first insulating layer 13.
  • the reinforcing material 14 the rigidity of the entire semiconductor device can be ensured, and lower warpage and reliability can be ensured. A high semiconductor device can be realized.
  • the elastic modulus of the reinforcing material 14 at room temperature is equal to or higher than the elastic modulus of the second insulating layer. is there. That is, the rigidity of the entire semiconductor device is ensured by making the elastic modulus of the second insulating layer larger than the elastic modulus of the first insulating layer and making the elastic modulus of the reinforcing material 14 equal to or higher than the elastic modulus of the second insulating layer.
  • the elastic modulus of the reinforcing material 14 at room temperature is equal to or higher than the elastic modulus of the second insulating layer.
  • the semiconductor devices 10a to 10f according to the embodiment of the present invention include, as shown in FIGS. 1 to 6, for example, a wiring layer 16 provided between the first insulating layer 13 and the second insulating layer 19 on the back surface. (Second wiring) is embedded in the first insulating layer 13 on the back surface.
  • the wiring layer 16 provided on the back surface (opposite surface of the connection portion) of the semiconductor element is not embedded in the first insulating layer, the first insulating layer has a large amount of contraction on the opposite surface of the built-in layer, and warpage occurs. Will occur.
  • By embedding the wiring layer on the back surface of the semiconductor element in the first insulating layer it is possible to reduce the amount of shrinkage and to control the warpage more accurately as a whole.
  • connection portion of the semiconductor element may not contain a solder material and a resin component.
  • the connection part is formed by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electroplating, etc., it does not contain solder material or resin component. Part. If the connecting portion of the semiconductor element does not contain a solder material or a resin material, the reliability of the connecting portion can be increased, and high reliability can be realized.
  • the first insulating layer has a tensile elastic modulus at room temperature of 1.0 MPa or more and less than 1.0 GPa and an elongation at break of 30% or more. High stress relaxation is achieved by the above.
  • the first insulating layer 13 is exposed on at least a part of the side surfaces of the semiconductor devices 10a to 10f. As a result, further deformation is facilitated, and further stress relaxation and low warpage can be realized.
  • the reinforcing material 14 or the first insulating layer 13 is exposed on at least a part of the side surfaces of the semiconductor devices 10a to 10f. It is not limited to the case where the first insulating layer is exposed. Even if the reinforcing material is exposed, further deformation is facilitated, and further stress relaxation and low warpage can be realized.
  • the diameter of the connecting portion 12 is smaller than the diameter of the via (17, 18).
  • the via 17 and the built-in layer via 18 are preferably large in diameter to stabilize the power supply from the first wiring 15 and the second wiring 16, and the connection portion 12 needs to have a large number of connection pins of the semiconductor element 11. Because there may be.
  • the semiconductor devices 10a to 10f include, for example, a plurality of electrodes (20, 21) provided on the front and back surfaces of the second insulating layer 19 as shown in FIGS.
  • a solder resist 22 is provided on the surface of the second insulating layer 19 so that the surface is exposed.
  • the semiconductor device 10e further includes an electronic component 23 in addition to the semiconductor element 11, as shown in FIG.
  • an electronic component 23 By further mounting a capacitor, a resistor, an inductor, a semiconductor element, a MEMS, an optical component, a sensor, and the like, it is possible to realize a semiconductor device capable of function expansion and more stable operation.
  • a semiconductor device 10f may be a semiconductor device 10f in which two or more of the semiconductor devices 10a to 10f are stacked as shown in FIG. 6, for example.
  • a semiconductor device capable of function expansion and stable operation can be realized with a higher degree of design freedom.
  • a method for manufacturing a semiconductor device includes a step of forming a wiring layer 16 on a support (FIG. 7A), as shown in FIGS.
  • a step of forming the first insulating layer 13 so that the layer 16 is embedded therein (FIG. 7B), and a step of placing the semiconductor element 11 on the first insulating layer 13 (FIG. 7C).
  • a step of forming the first insulating layer 13 again so as to cover the semiconductor element 11 and the support 26 (FIG. 7D), and a step of forming the wiring layer 15 on the first insulating layer 13 (FIG. 7).
  • the step of removing the support 26 and providing the second insulating layer 19 on both front and back surfaces of the first insulating layer 13 is performed after removing the support 26 and removing the support 26 as shown in FIGS.
  • the second insulating layer 19 may be formed on both sides, or the support 26 is removed after the second insulating layer is formed on the surface as shown in FIGS. Then, a second insulating layer may be formed on the back surface.
  • a step of forming a second insulating layer 19 on a support 26 (FIGS. 10A and 12B). 15 (b)), the step of forming the wiring layer 16 on the second insulating layer 19 (FIG. 10 (a), FIG. 12 (c), FIG. 15 (c)), and the wiring layer 16 A step of forming the first insulating layer 13 so that the covering wiring layer 16 is embedded therein (FIG. 10B, FIG. 12D, FIG. 15D), and a semiconductor on the first insulating layer 13 A step of placing the element 11 (FIGS.
  • the wiring layer 15 may be formed after the second insulating layer 19 is formed on the support. In both cases, the basic process is the same.
  • the step of forming the second insulating layer 19 on the support is the step of forming the wiring layer 16 (FIG. 12). (A), FIG.15 (a)), and the process (FIG.12 (b), FIG.15 (b)) of forming the 2nd insulating layer 19 which covers the wiring layer 16 is included.
  • the step of forming the second insulating layer 19 on at least the surface of the first insulating layer 13 removes the support 26. Thereafter, a step of forming the second insulating layer 19 on the back surface after the support 26 is removed (FIGS. 13G and 14D) is included.
  • a method for manufacturing a semiconductor device includes, for example, as shown in FIGS. 7 (e), 11 (e), 12 (d), and 15 (d), the semiconductor element is connected to the surface. 12, the step of forming the wiring layer 15 on the first insulating layer 13, the step of connecting to the wiring layer 15 forming the connection portion 12 of the semiconductor element, and the wiring layer 16 embedded in the first insulating layer; Forming vias 18 to be connected.
  • a method of manufacturing a semiconductor device according to an embodiment of the present invention is performed on the first insulating layer 13 as shown in FIGS. 7D, 10D, 12D, and 15D, for example.
  • the step of placing the semiconductor element 11 includes the step of placing a reinforcing material around the semiconductor element on the first insulating layer 13.
  • a method for manufacturing a semiconductor device includes a wiring layer (15, 16) on the surface of the second insulating layer 19 on both the front and back sides, as shown in FIGS. 8 (i) and 13 (i), for example.
  • the step of providing the electrodes (20, 21) includes a step of forming a solder resist 22 on the surface of the second insulating layer so that the surface of the electrode is exposed.
  • the method for manufacturing a semiconductor device further includes a step of stacking a plurality of semiconductor devices manufactured by the above manufacturing method.
  • a plurality of layers can be stacked in the final step.
  • the connection can be made by using a solder material, a conductive paste, an anisotropic conductive material, a stud bump, indium, or the like.
  • FIG. 1 is a partial sectional view showing a semiconductor device according to the first embodiment.
  • a built-in layer including a semiconductor element 11, a first insulating layer 13, and a reinforcing material 14 is provided, and vias 17 and built-in layer vias are formed on both sides of the built-in layer.
  • a first wiring 15 and a second wiring 16 that are electrically connected by a second wiring 18; a second insulating layer 19; and a wiring structure portion in which a first electrode 20 and a second electrode 21 are provided on both sides.
  • the connection surface 12 is provided on the circuit surface 11 and is connected to the first wiring 15.
  • the present invention is not limited to this, and a plurality of semiconductor elements and other electronic components may be incorporated in the built-in layer. It is good also as a structure which exists in the built-in layer from which the built-in of a semiconductor element and another electronic component differs by producing. Furthermore, although shown as four-layer wiring, the number of wiring layers is not limited to this and may be configured.
  • the semiconductor element 11 is connected to the first wiring 15 through the connection portion 12.
  • the connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion.
  • the connecting portion 12 is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, or the like.
  • a desired film thickness can be obtained by an electrolytic plating method or an electroless plating method.
  • any material can be used as long as the resin component disappears or a material that sublimes the resin component when being brought close to the sintered body by applying temperature.
  • the connecting portion 12 is preferably configured with a smaller diameter than the via 17 and the built-in layer via 18.
  • the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a.
  • the thickness is 300 ⁇ m or less, preferably 150 ⁇ m or less, and more preferably 100 ⁇ m or less.
  • the thinner the better but the semiconductor element needs to have a thickness of at least 1 ⁇ m from the viewpoint of maintaining the function.
  • the thickness is less than 1 ⁇ m, impurities, particularly heavy metals, cannot be prevented from entering the diffusion layer of the transistor, and the transistor does not operate.
  • the first insulating layer 13 and the second insulating layer 19 are formed of, for example, an organic material.
  • an organic material for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole) and polynorbornene resin.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the organic material may be either photosensitive or non-photosensitive.
  • openings used for the via 17 and the built-in layer via 18 are formed by a photolithography method or the like.
  • the opening is formed by laser, dry etching, blasting, or the like.
  • the tensile elastic modulus at room temperature (25 ° C.) of the material of the first insulating layer 13 is, for example, less than 1.0 GPa, preferably less than 0.5 GPa, and more preferably less than 0.3 GPa. Further, it is sufficient that the lower limit value of the tensile elastic modulus is 1 MPa or more. Furthermore, the elongation at break is, for example, desirably 30% or more, preferably 50% or more, and more preferably 100% or more.
  • the first insulating layer 13 is exposed in at least a part or all of the end of the semiconductor device 10a.
  • the elongation and elastic modulus of the first insulating layer can be used for deformation more effectively, realizing stress relaxation and warpage control at the same time as thinning. Can do.
  • the second insulating layer 19 since the second insulating layer 19 is responsible for the outermost layer as a semiconductor device, the second insulating layer 19 needs to have resistance to shape maintenance and impact, and is a material having a higher elastic modulus than the first insulating layer 13. .
  • the elastic modulus at 25 ° C. is, for example, 1.0 to 15 GPa.
  • the elastic modulus of the second insulating layer 19 is preferably 1.0 to 10 GPa.
  • the semiconductor element 11 has a structure embedded in the first insulating layer 13. In order to realize stable embedding, it is preferable that the semiconductor element 11 is bonded onto the first insulating layer 13 of the first layer and the embedding is performed with the further first insulating layer 13. In the bonding of the semiconductor element 11, if a desired bonding function exists in the first insulating layer 13 before the first insulating layer 13 is cured, the bonding may be performed as it is. When the first insulating layer 13 does not have a bonding function or when the bonding function is unstable, a liquid or sheet-like adhesive may be used.
  • the adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like.
  • the reinforcing material 14 is used to increase the overall rigidity of the semiconductor device 10a, and a stable shape can be maintained even if it is thin.
  • metal material ceramic, glass, silicon, printed circuit board, woven fabric or nonwoven fabric made of glass cloth or the like can be used.
  • metal material materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used.
  • the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring.
  • the elastic modulus of the first insulating layer 13, the reinforcing material 14, and the second insulating layer 19 is (elastic modulus of the first insulating layer 13) ⁇ (elastic modulus of the second insulating layer 19) ⁇ (elasticity of the reinforcing material 14). Rate). That is, the first insulating layer 13 has a low elastic modulus to effectively release internal stress, and the second insulating layer 19 has a higher elastic modulus than the first insulating layer to support external stress as a surface.
  • the semiconductor device 10a can be protected from impact. And the reinforcement material 14 can raise the intensity
  • the first wiring 15 and the second wiring 16 are made of copper, for example, and have a thickness of 10 ⁇ m.
  • the first wiring 15 and the second wiring 16 are formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method.
  • a subtractive method for example, as disclosed in Patent Document 5, a resist in which a copper foil provided on a substrate or resin is formed in a desired pattern is used as an etching mask, and the resist is removed after etching. This is a method for obtaining a desired wiring pattern.
  • a resist having a desired pattern is formed, and the resist opening is formed.
  • electrolytic plating is deposited on the substrate, the resist is removed, and the power feeding layer is etched to obtain a desired wiring pattern.
  • an electroless plating catalyst is adsorbed on the surface of a substrate or resin, a pattern is formed with a resist, and the catalyst is left while leaving the resist as an insulating layer. This is a method for obtaining a desired wiring pattern by activating and depositing metal in the opening of the insulating layer by electroless plating.
  • the first wiring 15, the first electrode 20, the second wiring 16, and the second electrode 21 may have an adhesion layer with respect to the first insulating layer 13 and the second insulating layer 19.
  • the adhesion layer is a material having adhesion to the material of the first insulating layer 13 or the second insulating layer 19, such as titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, and alloys thereof. Of these, titanium, tungsten, tantalum, chromium, molybdenum and alloys thereof are preferable, and titanium, tungsten and alloys thereof are most preferable.
  • the surface of the first insulating layer 13 or the second insulating layer 19 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Furthermore, it is preferable to form by means of sputtering as a means for increasing the adhesion.
  • the thickness of the first wiring 15 is, for example, 3 to 25 ⁇ m, and 5 to 20 ⁇ m is particularly suitable.
  • the thickness is less than 3 ⁇ m, there is a drawback that the wiring resistance becomes high and the electrical characteristics in the power supply circuit of the semiconductor device are deteriorated.
  • a wiring layer having a thickness exceeding 25 ⁇ m generates a large undulation reflecting the irregularities of the wiring layer on the surface of the insulating layer covering the wiring layer, thereby limiting the number of layers, increasing the thickness of the semiconductor device 10a itself, and increasing the thickness of the semiconductor layer.
  • warpage of the entire apparatus becomes large and that it is difficult to form due to process restrictions.
  • the connection between the plurality of first wirings 15 and / or the first electrode 20 is performed. Further, the connection between the plurality of second wirings 16 and / or the second electrode 21 is similarly performed via the vias 17. Further, the first wiring 15 and the second wiring 16 are connected by a built-in layer via 18.
  • the via 17 and the built-in layer via 18 may be formed simultaneously with the formation of the wiring after providing the via opening as described above, and the via opening is made conductive by an electrolytic plating method, an electroless plating method, a printing method, or the like.
  • the wiring may be formed after filling with the material.
  • a metal post is formed in a portion to be the via 17 and the built-in layer via 18, and after forming the first insulating layer 13 and the second insulating layer 19, the metal post is exposed by polishing to form the via 17 and the built-in layer via. 18 may be used.
  • the wiring of the first wiring 15 and the second wiring 16 is made of at least one metal selected from the group consisting of copper, aluminum, nickel, gold and silver, for example.
  • copper is preferable from the viewpoint of electrical resistance value and cost.
  • nickel can prevent an interface reaction with other materials such as an insulating material, and can be used as an inductor or a resistance wiring utilizing characteristics as a magnetic material.
  • the first wiring 15 is installed above the built-in layer and the second wiring 16 is buried in the first insulating layer 13 with respect to the built-in layer composed of the first insulating layer 13 and the reinforcing material 14. This is because the amount of contraction of the opposite surface of the built-in layer is smaller when the second wiring 16 is not provided so as to be embedded than the surface of the built-in layer where the first wiring 15 to which the semiconductor element 11 is connected by the connection portion 12 is provided. It becomes larger and warpage occurs. For this reason, the amount of shrinkage can be reduced by embedding the second wiring 16 in the first insulating layer 13, and the warpage can be controlled with higher accuracy in the state of the two wiring layers.
  • the first external terminals 20 and 21 may have the structure shown in FIG. 1, or may have a structure called a relief in which the opening of the solder resist 22 is larger than the first electrode 20 and the second electrode 21, Alternatively, a structure in which an electrode is newly formed on a solder resist may be used.
  • the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21.
  • the solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component.
  • the solder material can also flow into the side wall portions of the first electrode 20 and the second electrode 21 to form a connection surface. Reliability can be increased. Further, in the structure in which the electrodes are newly provided, the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized.
  • the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers.
  • the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials.
  • the first electrode 20 and the second electrode 21 are, for example, a nickel layer and a gold layer that are sequentially laminated on a copper layer, and the gold layer is the surface.
  • the thickness of the nickel layer is 3 ⁇ m
  • the thickness of the gold layer is 1 ⁇ m.
  • the first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure.
  • the first electrode 20 and the second electrode 21 may be different in the number and arrangement of external terminals in order to effectively use external terminals on both sides. This makes it possible to increase the degree of freedom in connection when mounting electronic components and semiconductor devices with different external sizes, or when the structure is sandwiched between a mounting substrate and another semiconductor device, and stable connection reliability. Can be secured.
  • the solder resist 22 is formed of, for example, an organic material.
  • an organic material for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
  • the difference in physical properties with the semiconductor element 11 can be absorbed, and even in the thin semiconductor device 10a, effective stress relaxation and low warpage are realized, and high single reliability and reliability after being connected to other components and substrates. Can be realized.
  • the rigidity of the entire semiconductor device can be ensured by using the reinforcing material 14, and a highly reliable semiconductor device with lower warpage can be realized.
  • the room temperature elastic modulus of the first insulating layer 13 is less than 1.0 GPa, the elongation at break is 30% or more, and the built-in layer is exposed at the end of the semiconductor device. Since further deformation can be facilitated, further stress relaxation and low warpage can be realized. Furthermore, since the amount of expansion / contraction on both sides of the built-in layer can be controlled by embedding the wiring 16 on one side of the built-in layer in the built-in layer, it is possible to realize warpage control in the built-in layer that requires countermeasures as the lowest warp. it can. Furthermore, the connection between the semiconductor element 11 and the first wiring 15 does not include a solder material or a resin component. For example, by using a plating method, the reliability of the connection portion can be increased and high reliability is realized. I can do it. Furthermore, the electrodes on both sides can be effectively utilized through the built-in layer via 18.
  • FIG. 2 is a partial cross-sectional view showing a semiconductor device 10b according to the second embodiment.
  • the semiconductor device 10a according to the first embodiment is different from the semiconductor device 10a in that no reinforcing material is provided.
  • parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment.
  • the first electrode 20 and the second electrode 21 in FIG. 2 have the same structure as that in FIG. 1, but can be modified as in the first embodiment.
  • the structure of FIG. 2 is a more effective structure when the semiconductor element 11 is made thinner than 50 ⁇ m and further thinning is performed.
  • the thickness of the reinforcing member 14 that can ensure the rigidity of the semiconductor device according to the first embodiment using the reinforcing member 14 is effective, but the thickness that cannot ensure the substantial rigidity, specifically, less than 40 ⁇ m, Is less than 25 ⁇ m, it is not necessary to use the reinforcing material 14.
  • the cost can be reduced.
  • the built-in layer constituted by the first insulating layer 13 can be made thin, it is possible to reduce the diameter and the pitch of the built-in layer via 18.
  • the semiconductor device according to the second embodiment configured as described above, the following effects can be obtained.
  • a thinner and lower-cost semiconductor device can be realized.
  • FIG. 3 is a partial sectional view showing a semiconductor device according to the third embodiment.
  • the semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in the structure in which the second wiring 16 is embedded on the surface opposite to the surface in contact with the first insulating layer in the second insulating layer 19 on the inner layer side.
  • the first electrode 20 and the second electrode 21 in FIG. 3 have the same structure as that in FIG. 1, but can be modified as described in the first embodiment.
  • the same built-in layer structure as that of the semiconductor device according to the second embodiment may be used.
  • the wiring is described as six-layer wiring, but is not limited thereto, and may be four-layer, five-layer, or a structure having seven-layer or more wiring.
  • the warp control capability can be further enhanced by adopting a structure in which the second wiring 16 is embedded in the second insulating layer 19.
  • the first insulating layer 13 is made of a material having a very low elastic modulus, the effect of the second wiring 16 embedded in the first insulating layer 13 is reduced. It is necessary to provide a second wiring 16 embedded in the second insulating layer 19 to perform warpage control.
  • the second wiring 16 embedded in the second insulating layer 19 is shown as one layer, but the present invention is not limited to this, and it may be formed by the number of layers necessary for warpage control.
  • the semiconductor device according to the third embodiment configured as described above, in addition to the effects of the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment, it is possible to realize a semiconductor device with higher warpage control capability. .
  • FIG. 4 is a partial sectional view showing a semiconductor device according to the fourth embodiment.
  • the first insulating layer 13 has a plurality of layers, and the second wiring 16 is embedded in all the layers of the first insulating layer 13 on the back surface side of the semiconductor element 11. Is different.
  • parts different from the semiconductor device according to the third embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment or the semiconductor device according to the third embodiment.
  • the first electrode 20 and the second electrode 21 in FIG. 4 have the same structure as in FIG. 1, but may be modified in the same manner as in the first embodiment.
  • the same built-in layer structure as that of the semiconductor device according to the second embodiment may be used.
  • FIG. 4 although described as 6-layer wiring, it is not limited to this, and it may be 4 layers, 5 layers, or a structure having 7 or more layers of wiring.
  • the first insulating layer 13 By making the first insulating layer 13 a plurality of layers, a greater stress relaxation effect can be obtained. However, since the entire surface of the second wiring 16 embedded in the inner first insulating layer 13 is surrounded by the first insulating layer 13, the function of warpage control is weakened. For this reason, it is necessary to ensure warpage control capability by embedding the second wiring 16 in the plurality of existing first insulating layers 13.
  • the second wiring 16 embedded in the first insulating layer 13 is shown as two layers, but the present invention is not limited to this, and it may be formed by the number of layers necessary for warpage control.
  • the semiconductor device according to the fourth embodiment configured as described above, in addition to the effects of the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment, and the semiconductor device according to the third embodiment, higher stress relaxation.
  • a semiconductor device with improved function and warpage control capability can be realized.
  • FIG. 5 is a partial sectional view showing a semiconductor device according to the fifth embodiment.
  • the semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in that an electronic component 23 is mounted on the semiconductor device 10a.
  • parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment.
  • the first electrode 20 and the second electrode 21 in FIG. 5 have the same structure as that in FIG. 1, but can be modified in the same manner as in the first embodiment.
  • the semiconductor device 10a according to the first embodiment is described as an example of the semiconductor device, the semiconductor device 10b according to the second embodiment, the semiconductor device 10c according to the third embodiment, and the semiconductor device 10d according to the fourth embodiment may be used.
  • the structure corresponding to the contents described in each embodiment may be used for the number of wiring layers and the combination of insulating layers.
  • the electronic component 23 is connected to the first electrode 20 through a connection portion 24 such as a solder material, a conductive paste, an anisotropic conductive material, wire bonding, ribbon bonding, or tape bonding.
  • a connection portion 24 such as a solder material, a conductive paste, an anisotropic conductive material, wire bonding, ribbon bonding, or tape bonding.
  • the electronic component is connected to the first electrode 20, but the electronic component may be connected to the second electrode 21, and the electronic component is connected to both the first electrode 20 and the second electrode 21. It doesn't matter.
  • the electronic component 23 is a capacitor, resistor, inductor, semiconductor element, MEMS, optical component, sensor, or the like.
  • a semiconductor device capable of function expansion and more stable operation can be realized.
  • FIG. 6 is a partial sectional view showing a semiconductor device according to the sixth embodiment.
  • the semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device 10a according to the first embodiment and the semiconductor device 10c according to the third embodiment are stacked and connected.
  • parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment.
  • the first electrode 20 and the second electrode 21 in FIG. 6 have the same structure as in FIG. 1, but may be modified in the same manner as in the first embodiment.
  • the semiconductor device 10a according to the first embodiment and the semiconductor device 10c according to the third embodiment are described as examples of the semiconductor device.
  • the device 10c and the semiconductor device 10d according to the fourth embodiment may be used as necessary.
  • a structure corresponding to the contents described in each embodiment may be used for the number of wiring layers and the combination of insulating layers.
  • FIG. 6 shows an example of stacking two semiconductor devices, but the present invention is not limited to this, and a desired number of stacks may be stacked.
  • a connecting portion 25 is formed and stacked between the first electrode 20 and the second electrode 21 that oppose the two semiconductor devices 10a and 10c.
  • the connection portion 25 is connected using a solder material, a conductive paste, an anisotropic conductive material, a stud bump, indium, or the like.
  • the electrodes to be connected are not limited to the first electrode 20 and the second electrode 21, and the first electrode 20 and the first electrode 20, or the second electrode 21 and the second electrode 21, as necessary. You can use different connections.
  • the electronic component 23 may be connected as in the semiconductor device according to the fifth embodiment.
  • the semiconductor device according to the sixth embodiment configured as described above, the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment, the semiconductor device according to the third embodiment, the semiconductor device according to the fourth embodiment, and the semiconductor according to the fifth embodiment.
  • the circuit is placed at a desired position of the laminated circuit including the semiconductor element 11, the reinforcing material 14, the first wiring 15, the second wiring 16, the first electrode 20, and the second electrode 21.
  • a capacitor that plays the role of a noise filter or decoupling may be provided.
  • the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2, or Nb 2 O 5 , BST (Ba x Sr 1-x TiO 3).
  • PZT PbZr x Ti 1-x O 3
  • PLZT Pb 1-y La y Zr x Ti 1-x O 3
  • perovskite material SrBi 2 Ta Bi-based layered compounds such as 2 O 9, such as Preferably there is.
  • an organic material mixed with an inorganic material or a magnetic material may be used as a dielectric material constituting the capacitor.
  • one or more layers of the first insulating layer 13 and the second insulating layer 19 are made of a material having a dielectric constant of 9 or more, and a counter electrode is formed at a desired position on the upper and lower wiring layers to form a circuit.
  • a noise filter or a capacitor that plays the role of decoupling may be provided.
  • the dielectric material constituting the capacitor Al 2 O 3, ZrO 2 , HfO 2 or Nb 2 O metal oxide such as 5, BST (Ba x Sr 1 -x TiO 3), PZT (PbZr x Ti 1- x O 3 ) or a perovskite material such as PLZT (Pb 1-y La y Zr x Ti 1-x O 3 ) or a Bi-based layered compound such as SrBi 2 Ta 2 O 9 is preferable.
  • BST Ba x Sr 1 -x TiO 3
  • PZT PbZr x Ti 1- x O 3
  • a perovskite material such as PLZT (Pb 1-y La y Zr x Ti 1-x O 3 ) or a Bi-based layered compound such as SrBi 2 Ta 2 O 9 is preferable.
  • an organic material mixed with an inorganic material or a magnetic material may
  • FIGS. 7 and 8 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the seventh embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
  • the second wiring 16 is formed on the support 26.
  • the support 26 is subjected to treatment such as wet cleaning, dry cleaning, flattening, and roughening of the surface, if necessary.
  • the support 26 is preferably made of a conductive material or a material having a conductive film formed on the surface thereof and has an appropriate rigidity.
  • Specific examples of the support material include semiconductor wafer materials such as silicon, sapphire, and GaAs, metals, quartz, glass, ceramics, and printed boards.
  • the conductive material is formed of one or more of a metal, a semiconductor material, and an organic material having a desired electrical conductivity.
  • a copper plate having a thickness of 0.25 mm was used as the support substrate.
  • the second wiring 16 is made of, for example, copper and has a thickness of 10 ⁇ m.
  • the second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method.
  • the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like.
  • a copper plate was used as a power feeding layer, a dry film resist was used, and Ni and Cu were laminated in this order by electrolytic plating. Ni was 3 ⁇ m thick and Cu was 10 ⁇ m thick.
  • the first insulating layer 13 is formed so as to cover the second wiring 16.
  • the first insulating layer 13 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the first insulating layer 13 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like. Here, lamination was performed by a vacuum laminator using a low elastic modulus sheet-like epoxy resin having a thickness of 20 ⁇ m.
  • the semiconductor element 11 is placed on the first insulating layer 13.
  • the bonding may be performed as it is.
  • a sheet-like adhesive may be used.
  • the adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like.
  • the semiconductor element 11 may be provided with a connection portion 12.
  • connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion. Specifically, it is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, and the like. Examples of the manufacturing method include a semi-additive method in which a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc., and a desired film thickness is obtained by an electrolytic plating method or an electroless plating method. Can be formed. However, in the paste material made of nanoparticles, any material can be used as long as the resin component disappears or a material that sublimes the resin component when the temperature is approached to the sintered body.
  • the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a.
  • the thickness is 300 ⁇ m or less, preferably 150 ⁇ m or less, and more preferably 100 ⁇ m or less.
  • a semiconductor element 11 having a thickness of 50 ⁇ m provided with a copper post having a height of 20 ⁇ m as the connection part 12 is placed on the first insulating layer 13 and bonded by a curing process of the first insulating layer 13. It was.
  • the reinforcing material 14 is laminated, and the first insulating layer 13 is further laminated thereon.
  • a material of the reinforcing material 14 a woven fabric or a non-woven fabric made of a metal material, ceramic, glass, silicon, a printed board, glass cloth, or the like can be used.
  • the metal material materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used.
  • the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring.
  • the reinforcing material 14 may be bonded as long as a desired bonding function exists before the first insulating layer 13 is cured.
  • a liquid or sheet-like adhesive may be used for adhesion.
  • the material itself of the reinforcing material 14 has adhesiveness, it may be used as it is.
  • the first insulating layer 13 is laminated by a vacuum laminator using a sheet-like epoxy resin having a low elastic modulus with a thickness of 20 ⁇ m, and the heat treatment in the curing process is performed by combining the prepreg material and the first insulating layer 13. Carried out.
  • the built-in layer via 18 and the first wiring 15 are formed.
  • the built-in layer via 18 has an opening formed by laser, dry etching, blasting, etc., and is formed in the process of the first wiring 15, or the via opening is made conductive by electrolytic plating, electroless plating, printing, etc.
  • the wiring may be formed after filling with the material.
  • a metal post is formed in a portion to become the internal layer via 18 by a plating method or a printing method, and after the first insulating layer 13 and the reinforcing material 14 are formed, buff polishing, dry etching method, CMP method, grinding method, The first insulating layer 13 on the surface of the metal post may be removed by a lapping method or the like, and the metal post may be exposed to form the built-in layer via 18.
  • FIG. 7 shows the opening of the built-in layer via 18 as a vertical wall, but a taper angle may be provided.
  • connection portion 12 is formed with a connection portion.
  • buffing, dry etching, CMP The connecting portion 12 is exposed before the first wiring 15 is formed by a grinding method, a lapping method, or the like.
  • the connecting portion 12 is thinner than the first insulating layer 13, the opening is formed by laser, dry etching, blasting, or the like, and connected in the process of the first wiring 15.
  • the first wiring 15 is formed by a wiring technique as described in FIG.
  • the built-in layer via 18 is formed with an opening by a laser, and the inside of the opening is filled with copper plating by supplying power from the copper plate of the support.
  • the connection portion 12 formed a copper post having a height of 30 ⁇ m, and the connection point was exposed by polishing the surface of the first insulating layer by buffing.
  • the first wiring 15 was formed with a film thickness of 10 ⁇ m using a semi-additive method using a sputtered film as a power feeding layer.
  • the support 26 is removed.
  • the support 26 is removed by any one of wet etching, dry etching, polishing, or a combination thereof. Further, if the support 26 is provided with a portion with low adhesion that can be easily peeled off, peeling may be performed. After the peeling, any one of wet etching, dry etching, polishing, or a combination thereof may be used. Processing may be performed.
  • the copper plate was removed by wet etching. At that time, Ni is used as an etching barrier when etching the copper plate. Finally, Ni was removed by wet etching.
  • the second insulating layer 19 is formed.
  • the formation method the method described in FIG. 7B is used, and heat treatment is performed after stacking to form an insulating layer. Both sides may be laminated simultaneously, or each side may be laminated alternately.
  • a sheet-like epoxy resin having a thickness of 50 ⁇ m was laminated at the same time by a vacuum laminator.
  • the via 17, the first wiring 15, and the second wiring 16 are formed.
  • the via 17 becomes the via 17 after being formed by a spin coating method, a laminating method, a pressing method, and a printing method.
  • the opening is formed by a photolithography method or the like.
  • the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like.
  • a metal post is formed on the portion to become the via 17 by a plating method or a printing method, and after forming the second insulating layer 19, it is removed by a dry etching method, a CMP method, a grinding method, a lapping method, etc.
  • a method of forming the via 17 by exposing the post may be used.
  • FIG. 8 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided.
  • a solder resist 22 is formed on the outermost surface.
  • the solder resist 22 is formed by opening portions that become the first electrode 20 and the second electrode 21.
  • the solder material on the side wall portions of the first electrode 20 and the second electrode 21 can also be used as a connection surface, thereby improving connection reliability. be able to.
  • the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized.
  • the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers.
  • the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials.
  • the first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure.
  • the solder resist 22 is formed of, for example, an organic material.
  • an organic material for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
  • the structure of the electrode may be the structure shown in FIG. 8, or may be a structure called relief where the opening of the solder resist 22 is larger than the first electrode 20 or the second electrode 21, and further, the electrode is formed on the solder resist. It is good also as a structure which produces again.
  • the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21.
  • the solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component.
  • the Ni layer is formed on the Cu layer so that the Au layer becomes the surface by electroless plating as the first electrode 20 and the second electrode 21.
  • Gold layers were laminated in order.
  • the thickness of the Ni layer is 3 ⁇ m, and the thickness of the Au layer is 1 ⁇ m.
  • the semiconductor device manufacturing method of the seventh embodiment the semiconductor device according to the first embodiment can be efficiently manufactured. If the reinforcing member 14 is not attached, the semiconductor device according to the second embodiment can be efficiently manufactured. In addition, by mounting electronic components and stacking semiconductor devices, the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment can be efficiently manufactured.
  • FIGS. 7 and 8 are shown as partial sectional views of individual pieces, a process in which a plurality of semiconductor devices are manufactured at once and separated into individual pieces by dicing or cutting may be performed. Furthermore, in FIGS. 7A to 7E, semiconductor devices may be formed on both sides of the support to increase productivity.
  • FIG. 8 is a manufacturing process diagram showing a method of manufacturing a semiconductor device according to the eighth embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
  • the manufacturing method according to Example 7 is different in that the second insulating layer 19 is formed before the support 26 is removed.
  • FIG. 9A is in the same state as FIG. 7E, and the process up to FIG.
  • FIG. 9B the second insulating layer 19 is laminated.
  • FIG. 9C the support 26 is removed.
  • FIG. 9D the second insulating layer 19 is laminated on the surface where the first insulating layer 13 is exposed.
  • the first insulating layer 19 is formed first, so that the first wiring 15 is damaged in the removal process of the support 26. As a result, the defect occurrence rate can be reduced. Moreover, since the rigidity after removing the support body 26 becomes higher than that of the seventh embodiment, handling properties can be improved.
  • Example 9 which is a second modification of Example 7
  • 10 and 11 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the ninth embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
  • the seventh embodiment is different from the seventh embodiment in that the second insulating layer 19 is formed on the support 26 and that the support 26 is removed after the second insulating layer 19 is formed so as to cover the first wiring 15. .
  • parts different from the seventh embodiment will be described. Parts not specifically described are the same as those in the manufacturing process of Example 7.
  • the second insulating layer 19 is formed on the support 26.
  • the first wiring 15 is formed on the second insulating layer 19.
  • the first insulating layer 13 is formed so as to cover the second wiring 16.
  • the semiconductor element 11 is bonded onto the first insulating layer 13.
  • the reinforcing material 14 is formed so as to cover the first insulating layer 13.
  • the built-in layer via 18 and the first wiring 15 are formed.
  • the 1st wiring 15 and the connection part 12 are connected.
  • a second insulating layer 19 is formed so as to cover the first wiring 15.
  • the support 26 is removed. After this, the process after FIG. 8H of Example 7 will be advanced.
  • the second insulating layers 19 on both sides are formed before the support is removed, so that the first wiring 15 and the second wiring
  • the wiring 16 is not damaged in the removal process of the support 26, and the defect occurrence rate can be reduced as compared with the eighth embodiment.
  • the handling property can be improved as compared with the seventh and eighth embodiments.
  • 12 and 13 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the tenth embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
  • the second wiring 16 is formed on the support 26.
  • the support 26 is subjected to treatment such as wet cleaning, dry cleaning, flattening, and roughening of the surface, if necessary.
  • the support 26 is a conductive material or a material having a conductive film formed on the surface thereof and preferably has an appropriate rigidity
  • a semiconductor wafer material such as silicon, sapphire, and GaAs
  • a metal Quartz, glass, ceramic, and printed board can be used.
  • the conductive material is formed of one or more of a metal, a semiconductor material, and an organic material having a desired electrical conductivity.
  • a copper plate having a thickness of 0.25 mm was used as the support substrate.
  • the second wiring 16 is made of, for example, copper and has a thickness of 10 ⁇ m.
  • the second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method.
  • the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like.
  • a copper plate was used as a power feeding layer, a dry film resist was used, and Ni and Cu were laminated in this order by electrolytic plating. Ni was 3 ⁇ m thick and Cu was 10 ⁇ m thick.
  • a second insulating layer 19 is formed so as to cover the second wiring 16.
  • the second insulating layer 19 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the second insulating layer 19 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like. Here, lamination was performed by a vacuum laminator using a sheet-like epoxy resin having a thickness of 20 ⁇ m.
  • the via 17 and the second wiring 16 are formed.
  • the via 17 is formed by a spin coating method, a laminating method, a pressing method, and a printing method, and then an opening that becomes the via 17 has a photolithography method or the like. It is formed by.
  • the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like.
  • a metal post is formed on the portion to be the via 17 by a plating method or a printing method, and after the second insulating layer 19 is formed, the second insulating layer is formed by a dry etching method, a CMP method, a grinding method, a lapping method, or the like.
  • the via 17 may be used by removing a part of the metal post and exposing the metal post.
  • FIG. 12 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided.
  • the second wiring 16 is made of, for example, copper and has a thickness of 10 ⁇ m.
  • the second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method.
  • the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like.
  • the via 17 is opened by laser, and a copper wiring having a thickness of 10 ⁇ m is formed by electrolytic plating using a dry film resist with the sputtered film as a power feeding layer.
  • the semiconductor element 11 is placed on the first insulating layer 13, and the lamination of the reinforcing material 14 and the first insulating layer 13, the built-in layer via 18, and the first wiring 15. Form.
  • the bonding may be performed as it is.
  • a sheet-like adhesive may be used.
  • the adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like.
  • connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion. Specifically, it is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, and the like.
  • Examples of the manufacturing method include a semi-additive method in which a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc., and a desired film thickness is obtained by an electrolytic plating method or an electroless plating method. Can be formed.
  • a semi-additive method in which a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc.
  • a desired film thickness is obtained by an electrolytic plating method or an electroless plating method.
  • any material can be used as long as the resin component disappears or a material that sublimes the resin component when being brought close to the sintered body by applying temperature.
  • the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a.
  • the thickness is 300 ⁇ m or less, preferably 150 ⁇ m or less, and more preferably 100 ⁇ m or less.
  • a semiconductor element 11 having a thickness of 50 ⁇ m provided with a copper post having a height of 20 ⁇ m as a connection portion 12 by electrolytic plating is placed on the first insulating layer 13 and bonded by a curing process of the first insulating layer 13. It was.
  • the reinforcing material 14 is laminated, and the first insulating layer 13 is further laminated thereon.
  • a material of the reinforcing material 14 a woven fabric or a non-woven fabric made of a metal material, ceramic, glass, silicon, a printed board, glass cloth, or the like can be used.
  • the metal material materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used.
  • the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring.
  • the reinforcing material 14 may be bonded as long as a desired bonding function exists before the first insulating layer 13 is cured.
  • a liquid or sheet adhesive may be used.
  • the material itself of the reinforcing material 14 has adhesiveness, it may be used as it is.
  • the lamination of the first insulating layer 13 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like. .
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the first insulating layer 13 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like.
  • a 50 ⁇ m-thick prepreg material in which a glass cloth was impregnated with an epoxy resin was used as the reinforcing material 14, and lamination was performed using a vacuum laminator.
  • the first insulating layer 13 is laminated by a vacuum laminator using a sheet-like epoxy resin having a low elastic modulus with a thickness of 20 ⁇ m, and the heat treatment in the curing process is performed by combining the prepreg material and the first insulating layer 13. Carried out.
  • the built-in layer via 18 and the first wiring 15 are formed.
  • the built-in layer via 18 has an opening formed by laser, dry etching, blasting, etc., and is formed in the process of the first wiring 15, or the via opening is made conductive by electrolytic plating, electroless plating, printing, etc.
  • the wiring may be formed after filling with the material.
  • a metal post is formed in a portion to become the internal layer via 18 by a plating method or a printing method, and after the first insulating layer 13 and the reinforcing material 14 are formed, buff polishing, dry etching method, CMP method, grinding method,
  • the internal layer via 18 may be formed by removing the surface by a lapping method or the like and exposing the metal post.
  • connection portion 12 shows the opening of the built-in layer via 18 with a vertical wall, but a taper angle may be provided. Further, the first wiring 15 and the connecting portion 12 are connected. As described above, the connection portion 12 is formed with a connection portion. When the connection portion 12 is thicker than the finished film thickness of the first insulating layer 13, buffing, dry etching, CMP, grinding, lapping The connecting portion 12 is exposed before the first wiring 15 is formed by a method or the like. When the connecting portion 12 is thinner than the first insulating layer 13, the opening is formed by laser, dry etching, blasting, or the like, and connected in the process of the first wiring 15. The first wiring 15 is formed by a wiring technique as described in FIG.
  • the built-in layer via 18 was formed with an opening by a laser, and the inside of the opening was filled with copper plating by supplying power from the copper plate of the support. Further, as described above, the connection portion 12 formed a copper post having a height of 30 ⁇ m, and the connection point was exposed by polishing the surface of the first insulating layer by buffing. Further, the first wiring 15 was formed with a film thickness of 10 ⁇ m using a semi-additive method using a sputtered film as a power feeding layer.
  • the second insulating layer 19 and the first wiring 15 are formed.
  • the second insulating layer 19 is formed using the method shown in FIG. 12B, and the via 17 and the first wiring 15 are formed using the method shown in FIG.
  • the support 26 is removed.
  • the support 26 is removed by any one of wet etching, dry etching, polishing, or a combination thereof. Further, as long as a portion with low adhesion and easy peeling can be provided in the support 26, it may be performed by peeling. After the peeling, any one of wet etching method, dry etching method, polishing method, or a combination of these may be used. You may perform the process by. Here, the copper plate was removed by wet etching. At that time, Ni is used as an etching barrier when etching the copper plate. Finally, Ni was removed by wet etching.
  • the second insulating layer 19 is formed.
  • the formation method the method described in FIG. 13B is used, and heat treatment is performed after stacking to form an insulating layer. Both sides may be laminated simultaneously, or each side may be laminated alternately.
  • a sheet-like epoxy resin having a thickness of 50 ⁇ m is simultaneously laminated on both sides by a vacuum laminator.
  • the via 17, the first wiring 15, and the second wiring 16 are formed.
  • the via 17 is formed by a spin coating method, a laminating method, a pressing method, and a printing method, and then an opening that becomes the via 17 has a photolithography method or the like. It is formed by.
  • the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like.
  • a metal post is formed on the portion to be the via 17 by a plating method or a printing method, and after the second insulating layer 19 is formed, the second insulating layer is formed by a dry etching method, a CMP method, a grinding method, a lapping method, or the like.
  • the via 19 may be used by removing the surface 19 and exposing the metal post.
  • FIG. 13 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided.
  • solder resist 22 is formed on the outermost surface.
  • the solder resist 22 is formed by opening portions that become the first electrode 20 and the second electrode 21.
  • the solder material on the side wall portions of the first electrode 20 and the second electrode 21 can also be used as a connection surface, thereby improving connection reliability. be able to.
  • the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized.
  • the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers.
  • the wettability of solder balls formed on the surfaces of the first electrode 20 and the second electrode 21 and bonding wires In consideration of connectivity, the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials.
  • the first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure.
  • the solder resist 22 is formed of, for example, an organic material.
  • an organic material for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with.
  • polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained.
  • the organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
  • the first electrode 20 and the second electrode 21 may have the structure shown in FIG. 13, or may have a structure called escape where the opening of the solder resist 22 is larger than the first electrode 20 and the second electrode 21, Alternatively, a structure in which an electrode is newly formed on a solder resist may be used. In the structure shown in FIG. 13, when connecting using a solder material, the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21.
  • the solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component.
  • the Ni layer is formed on the Cu layer so that the Au layer becomes the surface by electroless plating as the first electrode 20 and the second electrode 21.
  • Gold layers were laminated in order.
  • the thickness of the Ni layer is 3 ⁇ m, and the thickness of the Au layer is 1 ⁇ m.
  • the semiconductor device according to the fourth embodiment can be efficiently formed by changing the ratio of the semiconductor device according to the third embodiment and the first insulating layer 13 and the second insulating layer 19. Can do. If the reinforcing member 14 is not attached, the effect of the semiconductor device according to the second embodiment can be added.
  • the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment can be efficiently formed.
  • FIGS. 12 and 13 are shown as partial sectional views of individual pieces, a process in which a plurality of semiconductor devices are manufactured at once and separated into individual pieces by dicing or cutting may be performed.
  • semiconductor devices may be formed on both sides of the support to increase productivity.
  • FIG. 14 is a manufacturing process diagram illustrating a method of manufacturing a semiconductor device according to Example 11. In each step, cleaning or heat treatment may be performed as appropriate.
  • Example 11 is different from Example 10 in that the second insulating layer 19 is formed before the support 26 is removed.
  • parts different from the tenth embodiment will be described. Portions not specifically described are the same as those in the tenth embodiment.
  • FIG. 14A is in the same state as FIG. 12E, and up to FIG. 12E is formed with the same content as in the tenth embodiment.
  • the second insulating layer 19 is laminated.
  • the support 26 is removed.
  • the second insulating layer 19 is laminated on the surface where the second wiring 16 is embedded in the second insulating layer 19. Thereafter, the processes after FIG.
  • the first insulating layer 19 is formed first, so that the first wiring 15 is damaged in the removal process of the support 26.
  • the occurrence rate of defects can be reduced.
  • the rigidity after removing the support body 26 is higher than that of the tenth embodiment, the handling property can be improved.
  • Example 12 which is a second modification of Example 10
  • 15 and 16 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the twelfth embodiment. In each step, cleaning or heat treatment may be performed as appropriate. The difference from Example 10 is that the second insulating layer 19 is formed on the support 26 and that the support 26 is removed after the second insulating layer 19 is formed so as to cover the first wiring 15. .
  • parts different from the tenth embodiment will be described. Portions not specifically described are the same as in the manufacturing method of Example 10.
  • the second insulating layer 19 is formed on the support 26.
  • the first wiring 15 is formed on the second insulating layer 19.
  • a second insulating layer 19 is formed so as to cover the second wiring 16.
  • vias 17 and second wirings 16 are formed in the second insulating layer 19.
  • the first insulating layer 13 is formed so as to cover the second wiring 16, and the semiconductor element 11 is installed. Further, after forming the reinforcing material 14 so as to cover the first insulating layer 13, the built-in layer via 18 and the first wiring 15 are formed. The 1st wiring 15 and the connection part 12 are connected.
  • the second insulating layer 19 is formed so as to cover the first wiring 15, and then the via 17 and the first wiring 15 are formed.
  • the second insulating layer 19 is formed so as to cover the first wiring 15.
  • the support 26 is removed as shown in FIG. Thereafter, similarly to the tenth embodiment, the processes after FIG.
  • the first wiring 15 and the second wiring 15 are formed by forming the second insulating layers 19 on both sides before removing the support.
  • the wiring 16 is not damaged in the step of removing the support 26, and the defect occurrence rate can be reduced as compared with the eleventh embodiment.
  • the rigidity after removing the support 26 is higher than those in Examples 7 to 11, handling properties can be improved as compared with Examples 7 to 11.

Abstract

Disclosed is a semiconductor device comprising a semiconductor element built in a wiring board, wherein the stress is relaxed and warping is reduced. Also disclosed is a method for manufacturing the semiconductor device. The semiconductor device comprises a semiconductor element, first insulating layers covering both the front and back surfaces of the semiconductor element, second insulating layers covering both the front and back surfaces of the first insulating layers, a plurality of electrodes provided on both the front and back surfaces of the second insulating layers, and a plurality of wiring layers respectively arranged between the front/back first insulating layer and the front/back second insulating layer. The elastic modulus of the first insulating layers at room temperature is smaller than the elastic modulus of the second insulating layers. The stress acting on the semiconductor element is relaxed by the first insulating layers, while deformation is prevented by the second insulating layers.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　（関連出願についての記載）
　本発明は、日本国特許出願：特願２００９－０５２７１６号（２００９年３月５日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
　本発明は、半導体装置及びその製造方法に関する。特に、配線基板の内部に半導体素子を内蔵した半導体装置及びその製造方法関する。 (Description of related applications)
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2009-052716 (filed on Mar. 5, 2009), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which a semiconductor element is built in a wiring board and a manufacturing method thereof.
　近年、電子機器の急激な小型化、薄型化、高密度化の要求と、半導体素子の高速化、高機能化に伴う端子数増加とにより、半導体装置において、特に薄型化と高密度化が必要となってきている。特に薄型化、小型化に対しては、従来配線基板表面に実装されてきた部品を、配線基板の内部に埋設することが注目され、検討が進められている。 In recent years, due to the rapid demand for electronic devices that are becoming smaller, thinner, and higher in density, and the increase in the number of terminals associated with higher speed and higher functionality of semiconductor elements, semiconductor devices need to be particularly thinner and higher in density. It has become. In particular, for thinning and miniaturization, attention has been paid to the embedding of components that have been conventionally mounted on the surface of a wiring board in the wiring board.
　特許文献１では、電気絶縁材からなるコア層と、前記コア層の少なくとも片面に電気絶縁層と複数の配線パターンとを備えた部品内蔵モジュールが開示されている。部品内蔵モジュールは、前記コア層の電気絶縁材が少なくとも無機質フィラーと熱硬化性樹脂を含む混合物から形成され、前記コア層の内部に少なくとも１つ以上の能動部品及び／又は受動部品を内蔵し、前記コア層が複数の配線パターンと導電性樹脂からなる複数のインナービアを有し、且つ前記コア層の少なくとも無機質フィラーと熱硬化性樹脂を含む混合物からなる電気絶縁材の室温に於ける弾性率が０．６～１０ＧＰａの範囲にあることが記載されている。 Patent Document 1 discloses a component built-in module including a core layer made of an electrical insulating material, and an electrical insulating layer and a plurality of wiring patterns on at least one side of the core layer. In the component built-in module, the electrical insulating material of the core layer is formed from a mixture containing at least an inorganic filler and a thermosetting resin, and at least one active component and / or passive component is built in the core layer. Elastic modulus at room temperature of an electrical insulating material, wherein the core layer has a plurality of wiring patterns and a plurality of inner vias made of a conductive resin, and the core layer is made of a mixture containing at least an inorganic filler and a thermosetting resin. Is in the range of 0.6 to 10 GPa.
　特許文献２では、半導体素子が実装された複数の基板が、熱硬化性樹脂を少なくとも含む熱硬化性樹脂組成物で接着されており、熱硬化性樹脂組成物の内部に設けたインナービアを介して前記基板間が電気的に接続されており、半導体素子の基板との実装面を除く周囲部分が熱硬化性樹脂組成物よりも低い弾性率である低弾性率材料で封止されており、複数の基板で挟まれた内部に半導体素子が内蔵されている技術が開示されている。 In Patent Document 2, a plurality of substrates on which semiconductor elements are mounted are bonded with a thermosetting resin composition containing at least a thermosetting resin, and an inner via provided inside the thermosetting resin composition is used. The substrate is electrically connected, and the peripheral portion except the mounting surface of the semiconductor element with the substrate is sealed with a low elastic modulus material having a lower elastic modulus than the thermosetting resin composition, A technique is disclosed in which a semiconductor element is built inside a plurality of substrates.
　特許文献３では、半導体素子や受動部品などの電子部品が支持基板の一部を成すコンポジット材料層中に埋込まれて成る半導体装置用の多層基板において、電子部品をコア基板に装着するにあたって、ダイボンド材を低弾性率の材料とする技術が開示されている。ダイボンド材である低弾性率材料層の緩衝効果によって、支持基板のプレス成型時に前記コンポジット材料層から受けるストレスを緩和して不具合の発生を未然に防止することができるとしている。 In Patent Document 3, in a multilayer substrate for a semiconductor device in which an electronic component such as a semiconductor element or a passive component is embedded in a composite material layer forming a part of a support substrate, the electronic component is mounted on a core substrate. A technique of using a die bond material as a low elastic modulus material is disclosed. The buffering effect of the low-modulus material layer, which is a die bond material, alleviates the stress received from the composite material layer during the press molding of the support substrate, thereby preventing the occurrence of defects.
　特許文献４には、半導体チップが埋設される絶縁層に絶縁層を補強する補強構造体を埋設することにより半導体チップが内蔵された配線基板において、反りを抑制すると共に薄型化が可能であると、記載されている。 According to Patent Document 4, it is possible to suppress warpage and reduce the thickness of a wiring board with a built-in semiconductor chip by embedding a reinforcing structure that reinforces the insulating layer in the insulating layer in which the semiconductor chip is embedded. ,Are listed.
　さらに、特許文献５～７には、それぞれ、サブトラクティブ法、セミアディティブ法、フルアディティブ法によるプリント配線基板の製造方法が記載されている。 Further, Patent Documents 5 to 7 describe a method for manufacturing a printed wiring board by a subtractive method, a semi-additive method, and a full additive method, respectively.
特開２００２－２６１４４９号公報JP 2002-261449 A 特開２００６－１２０９３５号公報JP 2006-120935 A 特開２００６－３３２３２７号公報JP 2006-332327 A 特開２００６－２６１２４６号公報JP 2006-261246 A 特開平１０－５１１０５号公報JP-A-10-51105 特開平９－６４４９３号公報JP-A-9-64493 特開平６－３３４３３４号公報JP-A-6-334334
　なお、上記の特許文献の開示を、本書に引用をもって繰り込むものとする。
　以下の分析は本発明において与えられる。上述の従来の技術には、以下に示すような問題点がある。 The disclosure of the above patent document is incorporated herein by reference.
The following analysis is given in the present invention. The conventional techniques described above have the following problems.
　特許文献１においては、０．６～１０ＧＰａの材料物性が指定され、０．６～１．０ＧＰａが低弾性率材料と考えられる。この低弾性率材料の状況下においては、接続部分への応力集中が発生しやすくなるが、特許文献１では接続部分に導電性接着剤を用いる方法とハンダ材料を用いる方法とが記載されており、いずれの材料においても基板として別部品や別基板への接続を行った際に生じる応力に対して接続部分が破断しやすい構造となっている。さらに、コア層の両側の配線がコア層内部へ埋設されており、絶縁材料と配線材料との熱膨張係数差による面における伸縮の方向性が発生することと、半導体素子を内蔵して且つ片面が接続されていることから、応力バランスが実現出来ず、全体反りが大きく発生する構造となっている。特に２層配線で半導体装置全体の厚さが２００μｍを下回る配線基板とする場合には、反りが顕著に大きくなる。 In Patent Document 1, material properties of 0.6 to 10 GPa are specified, and 0.6 to 1.0 GPa is considered a low elastic modulus material. Under the condition of this low elastic modulus material, stress concentration tends to occur at the connection portion. However, Patent Document 1 describes a method using a conductive adhesive and a method using a solder material in the connection portion. In any material, the connection portion is easily broken by the stress generated when connecting to another component or another substrate as a substrate. In addition, the wiring on both sides of the core layer is embedded in the core layer, the direction of expansion and contraction in the surface due to the difference in thermal expansion coefficient between the insulating material and the wiring material occurs, the semiconductor element is built in, and one side As a result, the stress balance cannot be realized and the entire warp is greatly generated. In particular, when a wiring board having a thickness of the whole semiconductor device of less than 200 μm with two-layer wiring is used, the warpage is significantly increased.
　特許文献２においては、半導体装置周囲を低弾性率材料で覆うことによる応力緩和を期待しているが、半導体素子の接続面には高弾性率な材料が用いられているため全面における応力緩和構造が取られていないため、狙いとする応力緩和は得られない。さらに、低弾性率材料の周囲を高弾性率の基板材料が覆っているため、応力緩和に必要となる変形が低弾性率材料に発生出来ず、応力緩和効果は期待出来ない。 In Patent Document 2, the stress relaxation is expected by covering the periphery of the semiconductor device with a low elastic modulus material. However, since a high elastic modulus material is used for the connection surface of the semiconductor element, the stress relaxation structure on the entire surface. Since stress is not taken, the targeted stress relaxation cannot be obtained. Further, since the substrate material having a high elastic modulus covers the periphery of the low elastic modulus material, deformation necessary for stress relaxation cannot occur in the low elastic modulus material, and a stress relaxation effect cannot be expected.
　特許文献３においては、内蔵される半導体素子の片面のみを低弾性率材料としても、応力緩和に必要とされる変形が確保出来ない。特に、特許文献２と同様に周囲を高弾性率材料で覆ってしまっていることから、応力緩和効果が期待出来ない。 In Patent Document 3, even if only one side of a built-in semiconductor element is made of a low elastic modulus material, the deformation required for stress relaxation cannot be secured. In particular, since the periphery is covered with a high elastic modulus material as in Patent Document 2, a stress relaxation effect cannot be expected.
　また、特許文献４のように、補強材を用いただけでは、十分な応力緩和ができない。 In addition, as in Patent Document 4, sufficient stress relaxation cannot be achieved only by using a reinforcing material.
　本発明はかかる問題点に鑑みてなされたものであって、半導体素子を配線基板内に内蔵した半導体装置における全体反りを制御し、薄型で且つ低反りな構造を実現した半導体装置を提供することを目的とする。特に、２層配線で全体の厚さが２００μｍを下回る半導体装置を提供することを目的とする。 The present invention has been made in view of such problems, and provides a semiconductor device that realizes a thin and low warpage structure by controlling overall warpage in a semiconductor device in which a semiconductor element is embedded in a wiring board. With the goal. In particular, an object is to provide a semiconductor device having a total thickness of less than 200 μm with two-layer wiring.
　本発明の１つの側面による半導体装置は、半導体素子と、前記半導体素子の表裏両面を覆う第１絶縁層と、前記第１絶縁層の表裏両面を覆う第２絶縁層と、前記第２絶縁層の表裏両面の表面に設けられた複数の電極と、前記表裏の第１絶縁層と第２絶縁層との間に設けられた複数の配線層と、を含み、前記第１絶縁層の室温における弾性率が前記第２絶縁層の弾性率より小さい。 A semiconductor device according to one aspect of the present invention includes a semiconductor element, a first insulating layer that covers both front and back surfaces of the semiconductor element, a second insulating layer that covers both front and back surfaces of the first insulating layer, and the second insulating layer. A plurality of electrodes provided on both front and back surfaces, and a plurality of wiring layers provided between the front and back first insulating layers and the second insulating layer, the first insulating layer at room temperature The elastic modulus is smaller than the elastic modulus of the second insulating layer.
　また、本発明の他の側面による半導体装置の製造方法は、支持体上に配線層を形成する工程と、前記配線層を覆い前記配線層が中に埋設されるように第１絶縁層を形成する工程と、前記第１絶縁層上に半導体素子を載置する工程と、前記半導体素子と前記支持体を覆う様に再度第１絶縁層を形成する工程と、前記第１絶縁層上に配線層を形成する工程と、前記支持体を除去し、前記第１絶縁層の表裏両面に第２絶縁層を設ける工程と、表裏両面の第２絶縁層の表面に配線層と電極とを形成する工程と、を含む。 According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a wiring layer on a support; and forming a first insulating layer so as to cover the wiring layer and to be embedded in the wiring layer A step of placing a semiconductor element on the first insulating layer, a step of forming a first insulating layer again so as to cover the semiconductor element and the support, and a wiring on the first insulating layer Forming a layer; removing the support; providing a second insulating layer on both sides of the first insulating layer; and forming a wiring layer and an electrode on the surface of the second insulating layer on both sides And a process.
　本発明のさらに他の側面による半導体装置の製造方法は、支持体の上に第２絶縁層を形成する工程と、前記第２絶縁層の上に配線層を形成する工程と、前記配線層を覆い前記配線層が中に埋設されるように第１絶縁層を形成する工程と、前記第１絶縁層上に半導体素子を載置する工程と、前記半導体素子と前記支持体を覆う様に再度第１絶縁層を形成する工程と、前記第１絶縁層上に配線層を形成する工程と、前記支持体を除去し、前記第１絶縁層の少なくとも表面に第２絶縁層を形成する工程と、表裏両面の第２絶縁層の表面に配線層と電極とを形成する工程と、を含む。 A method of manufacturing a semiconductor device according to still another aspect of the present invention includes a step of forming a second insulating layer on a support, a step of forming a wiring layer on the second insulating layer, and the wiring layer. A step of forming a first insulating layer so that the wiring layer is embedded therein; a step of placing a semiconductor element on the first insulating layer; and again so as to cover the semiconductor element and the support. Forming a first insulating layer; forming a wiring layer on the first insulating layer; removing the support; and forming a second insulating layer on at least a surface of the first insulating layer; Forming a wiring layer and an electrode on the surface of the second insulating layer on both the front and back surfaces.
　本発明によれば、第１絶縁層が第２絶縁層より低弾性率となることで低熱膨張率である半導体素子との物性差を吸収でき、薄型の半導体装置においても効果的な応力緩和と低反りを実現出来る。 According to the present invention, since the first insulating layer has a lower elastic modulus than that of the second insulating layer, the physical property difference from the semiconductor element having a low thermal expansion coefficient can be absorbed, and effective stress relaxation can be achieved even in a thin semiconductor device. Low warpage can be realized.
本発明の実施例１による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 1 of this invention. 本発明の実施例２による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 2 of this invention. 本発明の実施例３による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 3 of this invention. 本発明の実施例４による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 4 of this invention. 本発明の実施例５による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 5 of this invention. 本発明の実施例６による半導体装置の部分断面図である。It is a fragmentary sectional view of the semiconductor device by Example 6 of this invention. 本発明の実施例７による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 7 of this invention. 本発明の実施例７による半導体装置の製造工程図の続きである。It is a continuation of the manufacturing-process figure of the semiconductor device by Example 7 of this invention. 本発明の実施例８による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 8 of this invention. 本発明の実施例９による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 9 of this invention. 本発明の実施例９による半導体装置の製造工程図の続きである。It is a continuation of the manufacturing-process figure of the semiconductor device by Example 9 of this invention. 本発明の実施例１０による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 10 of this invention. 本発明の実施例１０による半導体装置の製造工程図の続きである。It is a continuation of the manufacturing-process figure of the semiconductor device by Example 10 of this invention. 本発明の実施例１１による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 11 of this invention. 本発明の実施例１２による半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device by Example 12 of this invention. 本発明の実施例１２による半導体装置の製造工程図の続きである。It is a continuation of the manufacturing-process figure of the semiconductor device by Example 12 of this invention.
　本発明の実施形態について、必要に応じて図面を参照して説明する。なお、実施形態の説明において引用する図面及び図面の符号は実施形態の一例として示すものであり、それにより本発明による実施形態のバリエーションを制限するものではない。 Embodiments of the present invention will be described with reference to the drawings as necessary. In addition, drawing quoted in description of embodiment and the code | symbol of drawing are shown as an example of embodiment, and, thereby, the variation of embodiment by this invention is not restrict | limited.
　本発明の一実施形態による半導体装置１０ａ～１０ｆは、例えば図１～図６に示すように、半導体素子１１と、半導体素子１１の表裏両面を覆う第１絶縁層１３と、第１絶縁層１３の表裏両面を覆う第２絶縁層１９と、第２絶縁層１９の表裏両面の表面に設けられた複数の電極（２０、２１）と、表裏の第１絶縁層１３と第２絶縁層１９との間に設けられた複数の配線層（１５、１６）と、を含み、第１絶縁層１３の室温における弾性率が第２絶縁層１９の弾性率より小さい。上記構成により、第１絶縁層が第２絶縁層より低弾性率となることで低熱膨張率である半導体素子との物性差を吸収でき、薄型の半導体装置においても効果的な応力緩和と低反りを実現出来る。 As shown in FIGS. 1 to 6, for example, the semiconductor devices 10a to 10f according to the embodiment of the present invention include a semiconductor element 11, a first insulating layer 13 that covers both front and back surfaces of the semiconductor element 11, and a first insulating layer 13 as shown in FIG. A second insulating layer 19 that covers both front and back surfaces, a plurality of electrodes (20, 21) provided on the front and back surfaces of the second insulating layer 19, the first insulating layer 13 and the second insulating layer 19 on the front and back surfaces, A plurality of wiring layers (15, 16) provided between the first insulating layer 13 and the elastic modulus of the first insulating layer 13 at room temperature is smaller than the elastic modulus of the second insulating layer 19. With the above configuration, the first insulating layer has a lower elastic modulus than the second insulating layer, so that the physical property difference from the semiconductor element having a low thermal expansion coefficient can be absorbed, and effective stress relaxation and low warpage can be achieved even in a thin semiconductor device. Can be realized.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、例えば図１～図６に示すように、半導体素子１１は表面に接続部１２を備え、第１絶縁層１３、第２絶縁層１９にはそれぞれビア（１７、１８）が設けられ、複数の電極（２０、２１）は、それぞれビア（１７、１８）及び／又は配線層（１５、１６）を介して半導体素子の接続部１２及び／又は他の電極（２０、２１）に接続されている。すなわち、半導体装置の両面に設けられた電極は、ビア（内蔵層ビアを含む）、配線層の一つ以上を経由して半導体素子の接続部、反対面の電極、同一面の他の電極のうち、少なくとも一つに接続されている。 Further, in the semiconductor devices 10a to 10f according to the embodiment of the present invention, for example, as shown in FIGS. 1 to 6, the semiconductor element 11 includes the connection portion 12 on the surface, and the first insulating layer 13 and the second insulating layer 19 are provided. Are provided with vias (17, 18), and the plurality of electrodes (20, 21) are connected to the connection portions 12 of the semiconductor element and the vias (17, 18) and / or wiring layers (15, 16), respectively. / Or connected to another electrode (20, 21). That is, the electrodes provided on both surfaces of the semiconductor device are connected to vias (including built-in layer vias), one or more of the wiring layers, connection portions of the semiconductor elements, electrodes on the opposite surface, and other electrodes on the same surface. At least one of them is connected.
　また、本発明の一実施形態による半導体装置１０ａ、１０ｃ～１０ｆは、例えば図１、図３～図６に示すように、第１絶縁層１３の中に補強材１４が設けられ補強材１４の表裏が第１絶縁層１３で覆われている。第１絶縁層の弾性率を第２絶縁層の弾性率より小さくすることに加えて、補強材１４を設けることにより、半導体装置全体の剛性を確保することができ、より低反りで信頼性の高い半導体装置を実現出来る。 Further, in the semiconductor devices 10a, 10c to 10f according to the embodiment of the present invention, for example, as shown in FIGS. 1 and 3 to 6, the reinforcing material 14 is provided in the first insulating layer 13, and the reinforcing material 14 is provided. The front and back sides are covered with the first insulating layer 13. In addition to making the elastic modulus of the first insulating layer smaller than the elastic modulus of the second insulating layer, by providing the reinforcing material 14, the rigidity of the entire semiconductor device can be ensured, and lower warpage and reliability can be ensured. A high semiconductor device can be realized.
　また、本発明の一実施形態による半導体装置１０ａ、１０ｃ～１０ｆは、例えば図１、図３～図６に示すように、補強材１４の室温における弾性率が第２絶縁層の弾性率以上である。すなわち、第１絶縁層の弾性率より第２絶縁層の弾性率を大きく、さらに、補強材１４の弾性率を第２絶縁層の弾性率以上とすることにより、半導体装置全体の剛性を確保することができ、より低反りで信頼性の高い半導体装置を実現出来る。 In addition, in the semiconductor devices 10a, 10c to 10f according to the embodiment of the present invention, as shown in FIGS. 1 and 3 to 6, for example, the elastic modulus of the reinforcing material 14 at room temperature is equal to or higher than the elastic modulus of the second insulating layer. is there. That is, the rigidity of the entire semiconductor device is ensured by making the elastic modulus of the second insulating layer larger than the elastic modulus of the first insulating layer and making the elastic modulus of the reinforcing material 14 equal to or higher than the elastic modulus of the second insulating layer. Thus, a semiconductor device with lower warpage and higher reliability can be realized.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、例えば図１～図６に示すように、裏面の第１絶縁層１３と第２絶縁層１９との間に設けられた配線層１６（第２配線）が裏面の第１絶縁層１３に埋設されている。半導体素子の裏面（接続部の反対面）に設けた配線層１６が第１絶縁層に埋設されていない場合は、第１絶縁層は、内蔵層の反対面の収縮量が大きくなり、反りが発生してしまう。半導体素子裏面の配線層を第１絶縁層に埋設させることにより収縮量を低減させ、全体として反りをより精度良く制御することが実現出来る。 In addition, the semiconductor devices 10a to 10f according to the embodiment of the present invention include, as shown in FIGS. 1 to 6, for example, a wiring layer 16 provided between the first insulating layer 13 and the second insulating layer 19 on the back surface. (Second wiring) is embedded in the first insulating layer 13 on the back surface. When the wiring layer 16 provided on the back surface (opposite surface of the connection portion) of the semiconductor element is not embedded in the first insulating layer, the first insulating layer has a large amount of contraction on the opposite surface of the built-in layer, and warpage occurs. Will occur. By embedding the wiring layer on the back surface of the semiconductor element in the first insulating layer, it is possible to reduce the amount of shrinkage and to control the warpage more accurately as a whole.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、半導体素子の接続部に、ハンダ材料及び樹脂成分が含まれていないこととすることができる。たとえば、蒸着法、スパッタ法、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、無電解めっき法、電解めっき法などで接続部を形成すれば、ハンダ材料、樹脂成分を含まない接続部とすることができる。半導体素子の接続部にハンダ材料や樹脂材料を含んでいなければ、接続部の信頼性を高めることができ、高信頼性を実現出来る。 In addition, in the semiconductor devices 10a to 10f according to one embodiment of the present invention, the connection portion of the semiconductor element may not contain a solder material and a resin component. For example, if the connection part is formed by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electroplating, etc., it does not contain solder material or resin component. Part. If the connecting portion of the semiconductor element does not contain a solder material or a resin material, the reliability of the connecting portion can be increased, and high reliability can be realized.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、第１絶縁層の室温における引っ張り弾性率が１．０ＭＰａ以上１．０ＧＰａ未満であり、破断伸び率が３０％以上である。上記により高い応力緩和が達成される。 In addition, in the semiconductor devices 10a to 10f according to an embodiment of the present invention, the first insulating layer has a tensile elastic modulus at room temperature of 1.0 MPa or more and less than 1.0 GPa and an elongation at break of 30% or more. High stress relaxation is achieved by the above.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、第１絶縁層１３が半導体装置１０ａ～１０ｆの側面の少なくとも一部で露出している。これにより、更なる変形が容易となり、より一層の応力緩和と低反りが実現出来る。 Further, in the semiconductor devices 10a to 10f according to the embodiment of the present invention, the first insulating layer 13 is exposed on at least a part of the side surfaces of the semiconductor devices 10a to 10f. As a result, further deformation is facilitated, and further stress relaxation and low warpage can be realized.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、補強材１４又は第１絶縁層１３が半導体装置１０ａ～１０ｆの側面の少なくとも一部で露出している。第１絶縁層が露出している場合に限られず、補強材が露出していても、更なる変形が容易となり、より一層の応力緩和と低反りが実現出来る。 Further, in the semiconductor devices 10a to 10f according to the embodiment of the present invention, the reinforcing material 14 or the first insulating layer 13 is exposed on at least a part of the side surfaces of the semiconductor devices 10a to 10f. It is not limited to the case where the first insulating layer is exposed. Even if the reinforcing material is exposed, further deformation is facilitated, and further stress relaxation and low warpage can be realized.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、例えば図１～図６に示すように、接続部１２の径がビア（１７、１８）の径より小さい。ビア１７や内蔵層ビア１８は第１配線１５や第２配線１６からの電力供給を安定化させるためにある程度径が大きいことが好ましく、接続部１２は半導体素子１１の接続ピン数を多くとる必要がある場合があるからである。 Further, in the semiconductor devices 10a to 10f according to the embodiment of the present invention, for example, as shown in FIGS. 1 to 6, the diameter of the connecting portion 12 is smaller than the diameter of the via (17, 18). The via 17 and the built-in layer via 18 are preferably large in diameter to stabilize the power supply from the first wiring 15 and the second wiring 16, and the connection portion 12 needs to have a large number of connection pins of the semiconductor element 11. Because there may be.
　また、本発明の一実施形態による半導体装置１０ａ～１０ｆは、例えば図１～図６に示すように、第２絶縁層１９の表裏両面の表面に設けられた複数の電極（２０、２１）の表面が露出するように第２絶縁層１９の表面に設けられたソルダーレジスト２２を有する。 The semiconductor devices 10a to 10f according to the embodiment of the present invention include, for example, a plurality of electrodes (20, 21) provided on the front and back surfaces of the second insulating layer 19 as shown in FIGS. A solder resist 22 is provided on the surface of the second insulating layer 19 so that the surface is exposed.
　また、本発明の一実施形態による半導体装置１０ｅは、例えば図５に示すように、半導体素子１１に加えて電子部品２３がさらに搭載されている。コンデンサ、抵抗、インダクタ、半導体素子、ＭＥＭＳ、光学部品、センサなどをさらに搭載することにより、機能拡張やより安定動作となる半導体装置を実現することができる。 In addition, the semiconductor device 10e according to the embodiment of the present invention further includes an electronic component 23 in addition to the semiconductor element 11, as shown in FIG. By further mounting a capacitor, a resistor, an inductor, a semiconductor element, a MEMS, an optical component, a sensor, and the like, it is possible to realize a semiconductor device capable of function expansion and more stable operation.
　また、本発明の一実施形態による半導体装置１０ｆは、例えば図６に示すように、上記半導体装置１０ａ～１０ｆが２以上積層された半導体装置１０ｆとすることができる。より設計自由度を高めた形で機能拡張や安定動作となる半導体装置を実現することができる。 Further, a semiconductor device 10f according to an embodiment of the present invention may be a semiconductor device 10f in which two or more of the semiconductor devices 10a to 10f are stacked as shown in FIG. 6, for example. A semiconductor device capable of function expansion and stable operation can be realized with a higher degree of design freedom.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図７～９に示すように、支持体上に配線層１６を形成する工程（図７（ａ））と、配線層１６を覆い配線層１６が中に埋設されるように第１絶縁層１３を形成する工程（図７（ｂ））と、第１絶縁層１３上に半導体素子１１を載置する工程（図７（ｃ））と、半導体素子１１と支持体２６を覆う様に再度第１絶縁層１３を形成する工程と（図７（ｄ））と、第１絶縁層１３上に配線層１５を形成する工程（図７（ｅ））と、支持体２６を除去し第１絶縁層１３の表裏両面に第２絶縁層１９を設ける工程（図８（ｇ）、図９（ｄ））と、表裏両面の第２絶縁層の表面に配線層（１５、１６）と電極（２０、２１）とを形成する工程（図８（ｉ））と、を含む。上記工程により、第１絶縁層に半導体素子と配線層１６が埋め込まれ、第１絶縁層の表裏を第２絶縁層で覆い、表裏の第２絶縁層に配線層と電極を形成した半導体装置を製造することができる。なお、支持体２６を除去し第１絶縁層１３の表裏両面に第２絶縁層１９を設ける工程は、図８（ｆ）、（ｇ）のように、支持体２６を除去してから、表裏両面に第２絶縁層１９を形成してもよいし、図９（ｂ）、（ｃ）、（ｄ）のように、表面に第２絶縁層を形成してから、支持体２６を除去し、それから裏面に第２絶縁層を形成してもよい。 A method for manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming a wiring layer 16 on a support (FIG. 7A), as shown in FIGS. A step of forming the first insulating layer 13 so that the layer 16 is embedded therein (FIG. 7B), and a step of placing the semiconductor element 11 on the first insulating layer 13 (FIG. 7C). A step of forming the first insulating layer 13 again so as to cover the semiconductor element 11 and the support 26 (FIG. 7D), and a step of forming the wiring layer 15 on the first insulating layer 13 (FIG. 7). (E)), the step of removing the support 26 and providing the second insulating layer 19 on both the front and back surfaces of the first insulating layer 13 (FIGS. 8G and 9D), and the second insulation on both the front and back surfaces. Forming a wiring layer (15, 16) and an electrode (20, 21) on the surface of the layer (FIG. 8 (i)). A semiconductor device in which the semiconductor element and the wiring layer 16 are embedded in the first insulating layer by the above process, the front and back surfaces of the first insulating layer are covered with the second insulating layer, and the wiring layers and electrodes are formed on the second insulating layer on the front and back surfaces. Can be manufactured. The step of removing the support 26 and providing the second insulating layer 19 on both front and back surfaces of the first insulating layer 13 is performed after removing the support 26 and removing the support 26 as shown in FIGS. The second insulating layer 19 may be formed on both sides, or the support 26 is removed after the second insulating layer is formed on the surface as shown in FIGS. Then, a second insulating layer may be formed on the back surface.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図１０～１６に示すように、支持体２６の上に第２絶縁層１９を形成する工程（図１０（ａ）、図１２（ｂ）、図１５（ｂ））と、第２絶縁層１９の上に配線層１６を形成する工程（図１０（ａ）、図１２（ｃ）、図１５（ｃ））と、配線層１６を覆い配線層１６が中に埋設されるように第１絶縁層１３を形成する工程（図１０（ｂ）、図１２（ｄ）、図１５（ｄ））と、第１絶縁層１３上に半導体素子１１を載置する工程（図１０（ｃ）、図１２（ｄ）、図１５（ｄ））と、半導体素子１１と支持体２６を覆う様に再度第１絶縁層１３を形成する工程（図１０（ｄ）、図１２（ｄ）、図１５（ｄ））と、第１絶縁層１３上に配線層１５を形成する工程（図１１（ｅ）、図１２（ｄ）、図１５（ｄ））と、支持体２６を除去し、第１絶縁層１３の少なくとも表面に第２絶縁層１９を形成する工程（図１１（ｇ）、図１３（ｆ）、図１６（ｇ））と、表裏両面の第２絶縁層１９の表面に配線層（１５、１６）と電極（２０、２１）とを形成する工程（図８（ｉ）、図１３（ｉ））と、を含む。上述したように、支持体の上に直接配線層１５を形成する代わりに、支持体の上に第２絶縁層１９を形成してから配線層１５を形成してもよい。どちらも基本的な工程は同一である。 In the method for manufacturing a semiconductor device according to an embodiment of the present invention, for example, as shown in FIGS. 10 to 16, a step of forming a second insulating layer 19 on a support 26 (FIGS. 10A and 12B). 15 (b)), the step of forming the wiring layer 16 on the second insulating layer 19 (FIG. 10 (a), FIG. 12 (c), FIG. 15 (c)), and the wiring layer 16 A step of forming the first insulating layer 13 so that the covering wiring layer 16 is embedded therein (FIG. 10B, FIG. 12D, FIG. 15D), and a semiconductor on the first insulating layer 13 A step of placing the element 11 (FIGS. 10C, 12D, and 15D), and a step of forming the first insulating layer 13 again so as to cover the semiconductor element 11 and the support 26 ( 10D, 12D, and 15D) and a step of forming the wiring layer 15 on the first insulating layer 13 (FIGS. 11E and 12). d), FIG. 15D), and the step of removing the support 26 and forming the second insulating layer 19 on at least the surface of the first insulating layer 13 (FIG. 11G, FIG. 13F, FIG. 16 (g)) and a step of forming wiring layers (15, 16) and electrodes (20, 21) on the surface of the second insulating layer 19 on both the front and back surfaces (FIGS. 8 (i) and 13 (i)). And including. As described above, instead of forming the wiring layer 15 directly on the support, the wiring layer 15 may be formed after the second insulating layer 19 is formed on the support. In both cases, the basic process is the same.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図１２～１６に示すように、支持体の上に第２絶縁層１９を形成する工程が、配線層１６を形成する工程（図１２（ａ）、図１５（ａ））と、配線層１６を覆う第２絶縁層１９を形成する工程（図１２（ｂ）、図１５（ｂ））と、を含む。 In the method for manufacturing a semiconductor device according to an embodiment of the present invention, for example, as shown in FIGS. 12 to 16, the step of forming the second insulating layer 19 on the support is the step of forming the wiring layer 16 (FIG. 12). (A), FIG.15 (a)), and the process (FIG.12 (b), FIG.15 (b)) of forming the 2nd insulating layer 19 which covers the wiring layer 16 is included.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図１２～１４に示すように、第１絶縁層１３の少なくとも表面に第２絶縁層１９を形成する工程が、支持体２６を除去した後、支持体２６が除去された後の裏面にも第２絶縁層１９を形成する工程（図１３（ｇ）、図１４（ｄ））を含む。 In the method for manufacturing a semiconductor device according to an embodiment of the present invention, for example, as shown in FIGS. 12 to 14, the step of forming the second insulating layer 19 on at least the surface of the first insulating layer 13 removes the support 26. Thereafter, a step of forming the second insulating layer 19 on the back surface after the support 26 is removed (FIGS. 13G and 14D) is included.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図７（ｅ）、図１１（ｅ）、図１２（ｄ）、図１５（ｄ）に示すように、半導体素子は表面に接続部１２を備え、第１絶縁層１３上に配線層１５を形成する工程が、半導体素子の接続部１２を形成する配線層１５に接続する工程と、第１絶縁層に埋設された配線層１６と接続するビア１８を形成する工程と、を含む。 A method for manufacturing a semiconductor device according to an embodiment of the present invention includes, for example, as shown in FIGS. 7 (e), 11 (e), 12 (d), and 15 (d), the semiconductor element is connected to the surface. 12, the step of forming the wiring layer 15 on the first insulating layer 13, the step of connecting to the wiring layer 15 forming the connection portion 12 of the semiconductor element, and the wiring layer 16 embedded in the first insulating layer; Forming vias 18 to be connected.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図７（ｄ）、図１０（ｄ）、図１２（ｄ）、図１５（ｄ）に示すように、第１絶縁層１３上に半導体素子１１を載置する工程が、第１絶縁層１３上の半導体素子周辺に補強材を載置する工程を含む。 A method of manufacturing a semiconductor device according to an embodiment of the present invention is performed on the first insulating layer 13 as shown in FIGS. 7D, 10D, 12D, and 15D, for example. The step of placing the semiconductor element 11 includes the step of placing a reinforcing material around the semiconductor element on the first insulating layer 13.
　本発明の一実施形態による半導体装置の製造方法は、たとえば図８（ｉ）、図１３（ｉ）に示すように、表裏両面の第２絶縁層１９の表面に配線層（１５、１６）と電極（２０、２１）とを設ける工程において、電極の表面が露出するように第２絶縁層の表面にソルダーレジスト２２を形成する工程を含む。 A method for manufacturing a semiconductor device according to an embodiment of the present invention includes a wiring layer (15, 16) on the surface of the second insulating layer 19 on both the front and back sides, as shown in FIGS. 8 (i) and 13 (i), for example. The step of providing the electrodes (20, 21) includes a step of forming a solder resist 22 on the surface of the second insulating layer so that the surface of the electrode is exposed.
　本発明の一実施形態による半導体装置の製造方法は、上記製造方法により製造した半導体装置を複数積層する工程をさらに含む。最終工程で、複数積層することができる。図６の接続部２５のように、ハンダ材料、導電性ペースト、異方性導電材料、スタッドバンプ、インジウムなどを用いて接続することができる。以下、実施例について、図面を参照して詳しく説明する。 The method for manufacturing a semiconductor device according to an embodiment of the present invention further includes a step of stacking a plurality of semiconductor devices manufactured by the above manufacturing method. A plurality of layers can be stacked in the final step. As in the connection portion 25 in FIG. 6, the connection can be made by using a solder material, a conductive paste, an anisotropic conductive material, a stud bump, indium, or the like. Hereinafter, embodiments will be described in detail with reference to the drawings.
　図１は実施例１による半導体装置を示す部分断面図である。図１に示す様に、実施例１による半導体装置１０ａにおいては、半導体素子１１、第１絶縁層１３、補強材１４からなる内蔵層が設けられ、この内蔵層の両面にビア１７と内蔵層ビア１８により電気的に接続される第１配線１５及び第２配線１６と、第２絶縁層１９、さらには第１電極２０と第２電極２１が両面に設けた配線構造部分を有し、半導体素子１１の回路面には接続部１２が設けられ第１配線１５と接続した構造となる。図１では半導体素子１１を一つ内蔵した例を示しているが、これに限定されることなく複数の半導体素子や他の電子部品が内蔵層に内蔵されていても構わず、内蔵層を複数作製することで半導体素子や他の電子部品の内蔵が異なる内蔵層に存在する構成としても良い。さらに、４層の配線として示しているが、これに限らず、それ以上の配線の層数を構成しても構わない。 FIG. 1 is a partial sectional view showing a semiconductor device according to the first embodiment. As shown in FIG. 1, in the semiconductor device 10a according to the first embodiment, a built-in layer including a semiconductor element 11, a first insulating layer 13, and a reinforcing material 14 is provided, and vias 17 and built-in layer vias are formed on both sides of the built-in layer. A first wiring 15 and a second wiring 16 that are electrically connected by a second wiring 18; a second insulating layer 19; and a wiring structure portion in which a first electrode 20 and a second electrode 21 are provided on both sides. The connection surface 12 is provided on the circuit surface 11 and is connected to the first wiring 15. Although FIG. 1 shows an example in which one semiconductor element 11 is incorporated, the present invention is not limited to this, and a plurality of semiconductor elements and other electronic components may be incorporated in the built-in layer. It is good also as a structure which exists in the built-in layer from which the built-in of a semiconductor element and another electronic component differs by producing. Furthermore, although shown as four-layer wiring, the number of wiring layers is not limited to this and may be configured.
　半導体素子１１は、接続部１２を介して第１配線１５に接続されている。接続部１２にはハンダ材料や樹脂成分、つまり、ペースト材料や異方性導電材料による接続は実施されておらず、安定して剛性のある接続部分が設けられる。具体的には、蒸着法、スパッタ法、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、無電解めっき法、電解めっき法などで接続部１２が設けられる。製造方法の例としては、蒸着法、スパッタ法、ＣＶＤ法、ＡＬＤ法、無電解めっき法などで給電層を設けた後に電解めっき法や無電解めっき法により所望の膜厚とすることができる。ただし、ナノ粒子によるペースト材料において、樹脂成分が無くなる場合や、温度をかけて焼結体に近づける際に樹脂成分が昇華する材料であれば使用可能である。接続部１２は、ビア１７や内蔵層ビア１８よりも小さな径にて構成されることが好ましい。これは、接続部１２においては半導体素子１１の接続ピン数が多くなった場合に対応できることと、ビア１７や内蔵層ビア１８においては第１配線１５や第２配線１６からの電力供給を安定化させるためにある程度の径が必要だからである。 The semiconductor element 11 is connected to the first wiring 15 through the connection portion 12. The connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion. Specifically, the connecting portion 12 is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, or the like. As an example of the manufacturing method, after a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method or the like, a desired film thickness can be obtained by an electrolytic plating method or an electroless plating method. However, in the paste material made of nanoparticles, any material can be used as long as the resin component disappears or a material that sublimes the resin component when being brought close to the sintered body by applying temperature. The connecting portion 12 is preferably configured with a smaller diameter than the via 17 and the built-in layer via 18. This can cope with the case where the number of connection pins of the semiconductor element 11 is increased in the connection portion 12, and the power supply from the first wiring 15 and the second wiring 16 is stabilized in the via 17 and the built-in layer via 18. This is because a certain amount of diameter is necessary for the purpose.
　また、半導体素子１１は、半導体装置１０ａの薄型化のために薄く仕上がっていることが望ましい。具体的には、３００μｍ以下の厚み、好ましくは１５０μｍ以下の厚み、より好ましくは１００μｍ以下の厚みである。なお、薄型化のためには、薄ければ薄いほどよいが、半導体素子として、機能維持の観点から少なくとも１μｍ以上の厚みは必要である。１μｍ未満の厚さではトランジスタの拡散層への不純物、特に重金属の進入が防げなくなり、動作しなくなる。 Further, it is desirable that the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a. Specifically, the thickness is 300 μm or less, preferably 150 μm or less, and more preferably 100 μm or less. In order to reduce the thickness, the thinner the better, but the semiconductor element needs to have a thickness of at least 1 μm from the viewpoint of maintaining the function. When the thickness is less than 1 μm, impurities, particularly heavy metals, cannot be prevented from entering the diffusion layer of the transistor, and the transistor does not operate.
　第１絶縁層１３、第２絶縁層１９は、例えば有機材料で形成されており、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。有機材料は、感光性、非感光性のいずれを用いても構わない。感光性の有機材料を用いた場合、フォトリソグラフィー法などによりビア１７や内蔵層ビア１８に用いられる開口部を形成する。非感光性や感光性でパターン解像度が低い有機材料を用いた場合、開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。第１絶縁層１３及び第２絶縁層１９に有機材料を用いることで、半導体装置に別部品の搭載や別基板への接続の際に第１電極２０や第２電極２１から半導体装置にかかる応力を、緩和することができる。第１絶縁層１３の材料の室温（２５℃）における引っ張り弾性率は、例えば１．０ＧＰａ未満であり、好ましくは０．５ＧＰａ未満であり、より好ましくは０．３ＧＰａ未満である。また、引っ張り弾性率の下限値は、１ＭＰａ以上あれば十分である。さらに、破断伸び率は、例えば３０％以上であることが望ましく、好ましくは５０％以上であり、より好ましくは１００％以上となる。これら弾性率と伸び率を保有する材料とすることで、効果的に応力を材料自体の変形で吸収することができ、半導体装置単体の信頼性と他の部品や基板に接続した状態での信頼性を高めるばかりか低反りを実現出来る。 The first insulating layer 13 and the second insulating layer 19 are formed of, for example, an organic material. For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole) and polynorbornene resin. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The organic material may be either photosensitive or non-photosensitive. When a photosensitive organic material is used, openings used for the via 17 and the built-in layer via 18 are formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like. By using an organic material for the first insulating layer 13 and the second insulating layer 19, stress applied to the semiconductor device from the first electrode 20 or the second electrode 21 when another component is mounted on the semiconductor device or connected to another substrate. Can be relaxed. The tensile elastic modulus at room temperature (25 ° C.) of the material of the first insulating layer 13 is, for example, less than 1.0 GPa, preferably less than 0.5 GPa, and more preferably less than 0.3 GPa. Further, it is sufficient that the lower limit value of the tensile elastic modulus is 1 MPa or more. Furthermore, the elongation at break is, for example, desirably 30% or more, preferably 50% or more, and more preferably 100% or more. By using materials with these elastic moduli and elongation rates, stress can be effectively absorbed by deformation of the material itself, and the reliability of the semiconductor device alone and the reliability when connected to other components and substrates In addition to improving the properties, low warpage can be realized.
　また、第１絶縁層１３は、半導体装置１０ａの端部の少なくとも一部、もしくは全てにおいて露出させる。一つの層として端部まで形成することにより、第１絶縁層の伸び率や弾性率をより効果的に変形に使用することができ、薄型化と同時に応力緩和、さらには反り制御を実現することができる。一方、第２絶縁層１９は、半導体装置としての最外層を受け持つため、形状維持や衝撃に対しての耐性を有している必要があり、第１絶縁層１３より高弾性率な材料である。２５℃における弾性率は、例えば１．０乃至１５ＧＰａである。弾性率が１．０ＧＰａ未満の場合には、第２絶縁層１９が面で応力を受けることができず、第１配線１５や第２配線１６に応力の殆どが印加されることとなり、第１配線１５及び第２配線１６の断線及び第１配線１５／ビア１７や第２配線１６／ビア１７、さらには接続部１２や内蔵層ビア１８の界面等での破壊が発生し易いという欠点が発生する。弾性率が１５ＧＰａを超える場合、第２絶縁層１９の変形量が乏しくなり第１配線１５や第２配線１６における応力緩和が不十分となり、半導体装置１０ａ全体において層間剥離及び絶縁膜破壊等が生じやすいという欠点が発生する。従って、第２絶縁層１９の弾性率は１．０乃至１０ＧＰａが好ましい。 Further, the first insulating layer 13 is exposed in at least a part or all of the end of the semiconductor device 10a. By forming up to the end as one layer, the elongation and elastic modulus of the first insulating layer can be used for deformation more effectively, realizing stress relaxation and warpage control at the same time as thinning. Can do. On the other hand, since the second insulating layer 19 is responsible for the outermost layer as a semiconductor device, the second insulating layer 19 needs to have resistance to shape maintenance and impact, and is a material having a higher elastic modulus than the first insulating layer 13. . The elastic modulus at 25 ° C. is, for example, 1.0 to 15 GPa. When the elastic modulus is less than 1.0 GPa, the second insulating layer 19 cannot receive stress on the surface, and most of the stress is applied to the first wiring 15 and the second wiring 16. The disconnection of the wiring 15 and the second wiring 16 and the defect that the first wiring 15 / via 17 and the second wiring 16 / via 17 and also the interface of the connecting portion 12 and the built-in layer via 18 are likely to be broken. To do. When the elastic modulus exceeds 15 GPa, the amount of deformation of the second insulating layer 19 becomes small, and the stress relaxation in the first wiring 15 and the second wiring 16 becomes insufficient, resulting in delamination and insulation film breakdown in the entire semiconductor device 10a. The drawback is easy. Therefore, the elastic modulus of the second insulating layer 19 is preferably 1.0 to 10 GPa.
　半導体素子１１は、第１絶縁層１３に埋設される構造となる。安定した埋設を実現するために、半導体素子１１を一層目の第１絶縁層１３上に接着させ、さらにもう一層の第１絶縁層１３にて埋設を実施することが好ましい。半導体素子１１の接着では、第１絶縁層１３を硬化させる前などで第１絶縁層１３に所望の接着機能が存在していれば、そのまま接着を実施すれば良い。第１絶縁層１３に接着機能が特にない場合や接着機能が不安定である場合は、液状やシート状の接着剤を用いても良い。接着剤は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂などで形成されている。 The semiconductor element 11 has a structure embedded in the first insulating layer 13. In order to realize stable embedding, it is preferable that the semiconductor element 11 is bonded onto the first insulating layer 13 of the first layer and the embedding is performed with the further first insulating layer 13. In the bonding of the semiconductor element 11, if a desired bonding function exists in the first insulating layer 13 before the first insulating layer 13 is cured, the bonding may be performed as it is. When the first insulating layer 13 does not have a bonding function or when the bonding function is unstable, a liquid or sheet-like adhesive may be used. The adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like.
　補強材１４は、半導体装置１０ａの全体剛性を高めるために使用し、薄型でも安定した形状維持が実現出来る。材料としては、金属材料、セラミック、ガラス、シリコン、プリント基板、ガラスクロス等による織布や不織布を用いることができる。金属材料としては、銅、ニッケル、コバルト、鉄、ステンレス、アルミニウム、モリブデン、マンガンを主とする材料や合金を用いることができる。補強材が導電性を有する場合は、第１配線や第２配線と接続して、電源やグランド回路としても良い。また、補強材自体に配線が設けられていても構わない。 The reinforcing material 14 is used to increase the overall rigidity of the semiconductor device 10a, and a stable shape can be maintained even if it is thin. As the material, metal material, ceramic, glass, silicon, printed circuit board, woven fabric or nonwoven fabric made of glass cloth or the like can be used. As the metal material, materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used. When the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring.
　また、第１絶縁層１３、補強材１４、第２絶縁層１９の弾性率は、（第１絶縁層１３の弾性率）＜（第２絶縁層１９の弾性率）≦（補強材１４の弾性率）の関係にあることが望ましい。つまり、第１絶縁層１３が低弾性率であることで内部応力を効果的に解放し、第２絶縁層１９が第１絶縁層より高弾性率とすることで外部応力を面として支えるだけでなく、衝撃から半導体装置１０ａを保護出来る。そして、補強材１４は、少なくとも第１絶縁層１３より高弾性率とすることで、半導体装置１０ａの強度を高め、ハンドリング性や生産性を向上させることができる。 The elastic modulus of the first insulating layer 13, the reinforcing material 14, and the second insulating layer 19 is (elastic modulus of the first insulating layer 13) <(elastic modulus of the second insulating layer 19) ≦ (elasticity of the reinforcing material 14). Rate). That is, the first insulating layer 13 has a low elastic modulus to effectively release internal stress, and the second insulating layer 19 has a higher elastic modulus than the first insulating layer to support external stress as a surface. The semiconductor device 10a can be protected from impact. And the reinforcement material 14 can raise the intensity | strength of the semiconductor device 10a by making it a higher elasticity modulus than the 1st insulating layer 13, and can improve handling property and productivity.
　第１配線１５と第２配線１６は、例えば銅により構成されており、その厚さは１０μｍである。第１配線１５と第２配線１６は、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等の配線形成法により形成する。サブトラクティブ法は、例えば特許文献５に開示されているように、基板又は樹脂上に設けられた銅箔を所望のパターンで形成したレジストをエッチングマスクとし、エッチングを行った後にレジストを除去して所望の配線パターンを得る方法である。セミアディティブ法は、例えば特許文献６に開示されているように、無電解めっき、スパッタ法、ＣＶＤ法等で給電層を形成した後、所望のパターンに開口されたレジストを形成し、レジスト開口部内に電解めっきを析出させ、レジストを除去後に給電層をエッチングして所望の配線パターンを得る方法である。フルアディティブ法は、例えば特許文献７に開示されているように、基板又は樹脂の表面に無電解めっき触媒を吸着させた後にレジストでパターンを形成し、このレジストを絶縁層として残したまま触媒を活性化して無電解めっき法により絶縁層の開口部に金属を析出させることで所望の配線パターンを得る方法である。 The first wiring 15 and the second wiring 16 are made of copper, for example, and have a thickness of 10 μm. The first wiring 15 and the second wiring 16 are formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method. In the subtractive method, for example, as disclosed in Patent Document 5, a resist in which a copper foil provided on a substrate or resin is formed in a desired pattern is used as an etching mask, and the resist is removed after etching. This is a method for obtaining a desired wiring pattern. In the semi-additive method, for example, as disclosed in Patent Document 6, after a power feeding layer is formed by electroless plating, sputtering, CVD, or the like, a resist having a desired pattern is formed, and the resist opening is formed. In this method, electrolytic plating is deposited on the substrate, the resist is removed, and the power feeding layer is etched to obtain a desired wiring pattern. In the full additive method, for example, as disclosed in Patent Document 7, an electroless plating catalyst is adsorbed on the surface of a substrate or resin, a pattern is formed with a resist, and the catalyst is left while leaving the resist as an insulating layer. This is a method for obtaining a desired wiring pattern by activating and depositing metal in the opening of the insulating layer by electroless plating.
　また、第１配線１５、第１電極２０、第２配線１６、第２電極２１は、第１絶縁層１３や第２絶縁層１９に対して密着層を有しても構わない。密着層は、第１絶縁層１３もしくは第２絶縁層１９の材料に対して密着力を有する材料、例としてチタン、タングステン、ニッケル、タンタル、バナジウム、クロム、モリブデン、銅、アルミニウムやこれらの合金等でも良く、中でもチタン、タングステン、タンタル、クロム、モリブデンやこれらの合金が好適であり、さらにはチタン、タングステンやこれらの合金が最も好適である。さらに、第１絶縁層１３もしくは第２絶縁層１９の表面が細かな凹凸を有する粗化面であっても良く、この場合は、銅やアルミニウムでも良好な密着力が得られやすくなる。さらに、より密着力を高める手段として、スパッタ法にて形成されることが好適である。 The first wiring 15, the first electrode 20, the second wiring 16, and the second electrode 21 may have an adhesion layer with respect to the first insulating layer 13 and the second insulating layer 19. The adhesion layer is a material having adhesion to the material of the first insulating layer 13 or the second insulating layer 19, such as titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, and alloys thereof. Of these, titanium, tungsten, tantalum, chromium, molybdenum and alloys thereof are preferable, and titanium, tungsten and alloys thereof are most preferable. Furthermore, the surface of the first insulating layer 13 or the second insulating layer 19 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Furthermore, it is preferable to form by means of sputtering as a means for increasing the adhesion.
　第１配線１５の厚さは、例えば３乃至２５μｍであり、中でも５乃至２０μｍが適している。厚さが３μｍ未満の場合、配線抵抗が高くなり半導体装置の電源回路における電気特性が悪化してしまうという欠点がある。厚さが２５μｍを超える配線層は、配線層を覆う絶縁層の表面に配線層の凹凸を反映した大きなうねりを発生させ積層数に制限が発生すること、半導体装置１０ａ自体の厚みが増加し半導体装置全体の反りが大きくなること、プロセス上の制約から形成することが困難であるという欠点がある。 The thickness of the first wiring 15 is, for example, 3 to 25 μm, and 5 to 20 μm is particularly suitable. When the thickness is less than 3 μm, there is a drawback that the wiring resistance becomes high and the electrical characteristics in the power supply circuit of the semiconductor device are deteriorated. A wiring layer having a thickness exceeding 25 μm generates a large undulation reflecting the irregularities of the wiring layer on the surface of the insulating layer covering the wiring layer, thereby limiting the number of layers, increasing the thickness of the semiconductor device 10a itself, and increasing the thickness of the semiconductor layer. There are disadvantages that warpage of the entire apparatus becomes large and that it is difficult to form due to process restrictions.
　複数の第１配線１５間及び、又は第１電極２０との接続には、ビア１７を介する。また、複数の第２配線１６間及び、又は第２電極２１との接続も同様にビア１７を介する。さらに、第１配線１５と第２配線１６間は、内蔵層ビア１８により接続される。ビア１７と内蔵層ビア１８は、先に記載した通りビア開口部を設けた後、配線形成と同時に形成しても良く、ビア開口部を電解めっき法、無電解めっき法、印刷法等により導電材料で埋めてから配線形成しても良い。さらに、ビア１７と内蔵層ビア１８となる部分に金属ポストを形成しておき、第１絶縁層１３や第２絶縁層１９を形成した後に研磨により金属ポストを露出させてビア１７と内蔵層ビア１８としても構わない。 Via the vias 17, the connection between the plurality of first wirings 15 and / or the first electrode 20 is performed. Further, the connection between the plurality of second wirings 16 and / or the second electrode 21 is similarly performed via the vias 17. Further, the first wiring 15 and the second wiring 16 are connected by a built-in layer via 18. The via 17 and the built-in layer via 18 may be formed simultaneously with the formation of the wiring after providing the via opening as described above, and the via opening is made conductive by an electrolytic plating method, an electroless plating method, a printing method, or the like. The wiring may be formed after filling with the material. Further, a metal post is formed in a portion to be the via 17 and the built-in layer via 18, and after forming the first insulating layer 13 and the second insulating layer 19, the metal post is exposed by polishing to form the via 17 and the built-in layer via. 18 may be used.
　また、第１配線１５、及び第２配線１６の配線は、例えば銅、アルミニウム、ニッケル、金及び銀からなる群から選択された少なくとも一種の金属から構成される。特に、電気抵抗値及びコストの観点から銅が好適である。また、ニッケルは、絶縁材料等の他の材料との界面反応を防止でき、磁性体としての特性を活用したインダクタ又は抵抗配線として使用できる。 Further, the wiring of the first wiring 15 and the second wiring 16 is made of at least one metal selected from the group consisting of copper, aluminum, nickel, gold and silver, for example. In particular, copper is preferable from the viewpoint of electrical resistance value and cost. Further, nickel can prevent an interface reaction with other materials such as an insulating material, and can be used as an inductor or a resistance wiring utilizing characteristics as a magnetic material.
　第１絶縁層１３と補強材１４からなる内蔵層に対して、第１配線１５は内蔵層の上部に設置され、第２配線１６は第１絶縁層１３に埋設される構造とする。これは、半導体素子１１が接続部１２で接続された第１配線１５が設けられる内蔵層の面よりも、埋設させる様に第２配線１６を設けない状態では内蔵層の反対面の収縮量が大きくなり、反りが発生してしまう。このため、第２配線１６を第１絶縁層１３に埋設させることで収縮量を低減させ、配線２層の状態で反りをより精度良く制御することが実現出来る。 The first wiring 15 is installed above the built-in layer and the second wiring 16 is buried in the first insulating layer 13 with respect to the built-in layer composed of the first insulating layer 13 and the reinforcing material 14. This is because the amount of contraction of the opposite surface of the built-in layer is smaller when the second wiring 16 is not provided so as to be embedded than the surface of the built-in layer where the first wiring 15 to which the semiconductor element 11 is connected by the connection portion 12 is provided. It becomes larger and warpage occurs. For this reason, the amount of shrinkage can be reduced by embedding the second wiring 16 in the first insulating layer 13, and the warpage can be controlled with higher accuracy in the state of the two wiring layers.
　また、第１外部端子２０、２１は、図１に示した構造としても良く、ソルダーレジスト２２の開口が第１電極２０や第２電極２１電極より大きくなる逃げと呼ばれる構造としても良く、さらには、ソルダーレジスト上に電極を改めて作製する構造としても良い。図１に示す構造では、ハンダ材料を用いて接続する場合に、第１電極２０や第２電極２１のみにハンダが供給される様にソルダーレジスト２２にて開口を制限している。このソルダーレジスト２２による制限により、ハンダの流れ量が制限されるため、半導体装置を実装基板や別部品と接続する際の取り付け高さを安定化させることが実現出来る。また、ソルダーレジスト２２の開口を第１電極２０や第２電極２１より大きくした場合は、第１電極２０や第２電極２１の側壁部分にもハンダ材料が流れ接続面とすることができ、接続信頼性を高めることができる。また、改めて電極を設ける構造では、ソルダーレジスト２２も応力緩和に用いることができるため、更なる信頼性の向上が実現出来る。 Further, the first external terminals 20 and 21 may have the structure shown in FIG. 1, or may have a structure called a relief in which the opening of the solder resist 22 is larger than the first electrode 20 and the second electrode 21, Alternatively, a structure in which an electrode is newly formed on a solder resist may be used. In the structure shown in FIG. 1, when connecting using a solder material, the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21. The solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component. In addition, when the opening of the solder resist 22 is made larger than the first electrode 20 and the second electrode 21, the solder material can also flow into the side wall portions of the first electrode 20 and the second electrode 21 to form a connection surface. Reliability can be increased. Further, in the structure in which the electrodes are newly provided, the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized.
　第１電極２０や第２電極２１は、例えば複数の層が積層されたものであり、例えば、第１電極２０や第２電極２１の表面に形成されるハンダボールの濡れ性やボンディングワイヤーとの接続性を考慮して、第１電極２０や第２電極２１の表面は、銅、アルミニウム、金、銀及びハンダ材料からなる群から選択された少なくとも一種の金属及び合金が設けられる。第１電極２０や第２電極２１は、例えば銅層上にニッケル層と金層が順に積層され、金層を表面としたものであり、ニッケル層の厚さは３μｍ、金層の厚さは１μｍである。第１電極２０や第２電極２１は、接続に対して効果のある構造を適宜選択すれば良く、必ずしも同じ構造とする必要はない。また、第１電極２０や第２電極２１は、両面の外部端子を有効活用するために、外部端子数や配置が異なっていても良い。これにより、外形サイズの異なる電子部品や半導体装置を搭載する場合や、実装基板と他の半導体装置などに挟まれた構造となる場合において、接続自由度を高めることができ、安定した接続信頼性を確保することができる。 For example, the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers. For example, the wettability of solder balls formed on the surfaces of the first electrode 20 and the second electrode 21 and bonding wires In consideration of connectivity, the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials. The first electrode 20 and the second electrode 21 are, for example, a nickel layer and a gold layer that are sequentially laminated on a copper layer, and the gold layer is the surface. The thickness of the nickel layer is 3 μm, and the thickness of the gold layer is 1 μm. The first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure. The first electrode 20 and the second electrode 21 may be different in the number and arrangement of external terminals in order to effectively use external terminals on both sides. This makes it possible to increase the degree of freedom in connection when mounting electronic components and semiconductor devices with different external sizes, or when the structure is sandwiched between a mounting substrate and another semiconductor device, and stable connection reliability. Can be secured.
　ソルダーレジスト２２は、例えば有機材料で形成されており、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。有機材料は、感光性、非感光性のいずれを用いても構わない。感光性の有機材料を用いた場合、フォトリソグラフィー法などにより開口部を形成する。非感光性や感光性でパターン解像度が低い有機材料を用いた場合、開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。 The solder resist 22 is formed of, for example, an organic material. For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
　次に、上述の如く構成された実施例１による半導体装置によれば、以下の効果が得られる。半導体素子１１を埋設する第１絶縁層１３とさらに外側に第２絶縁層１９の構成とし、第１絶縁層１３が第２絶縁層１９より低弾性率とすることで他の構成部材より低熱膨張率である半導体素子１１との物性差を吸収でき、薄型の半導体装置１０ａにおいても効果的な応力緩和と低反りを実現し、高い単体信頼性と他の部品や基板と接続した後の信頼性を実現出来る。また、補強材１４を用いることで半導体装置全体の剛性を確保することができ、より低反りで信頼性の高い半導体装置を実現出来る。さらに、第１絶縁層１３の室温の弾性率が１．０ＧＰａ未満で、且つ、破断伸び率が３０％以上とすること、さらにまた、内蔵層が半導体装置の端部に露出する構造とすることで更なる変形が容易とできるため、より一層の応力緩和と低反りが実現出来る。さらにまた、内蔵層の片面の配線１６を内蔵層内に埋設することにより内蔵層の両面における伸縮量を制御できるため、最も低反りとして対策が必要な内蔵層での反り制御を実現することができる。さらにまた、半導体素子１１と第１配線１５との接続にハンダ材料や樹脂成分を含めない、たとえば、めっき法による接続とすることで接続部の信頼性を高めることができ、高信頼性を実現出来る。さらにまた、内蔵層ビア１８を介することで両面の電極が有効に活用することができる。 Next, according to the semiconductor device according to the first embodiment configured as described above, the following effects can be obtained. The first insulating layer 13 in which the semiconductor element 11 is embedded and the second insulating layer 19 on the outer side are formed, and the first insulating layer 13 has a lower elastic modulus than the second insulating layer 19 so that it has a lower thermal expansion than other components. The difference in physical properties with the semiconductor element 11 can be absorbed, and even in the thin semiconductor device 10a, effective stress relaxation and low warpage are realized, and high single reliability and reliability after being connected to other components and substrates. Can be realized. In addition, the rigidity of the entire semiconductor device can be ensured by using the reinforcing material 14, and a highly reliable semiconductor device with lower warpage can be realized. Furthermore, the room temperature elastic modulus of the first insulating layer 13 is less than 1.0 GPa, the elongation at break is 30% or more, and the built-in layer is exposed at the end of the semiconductor device. Since further deformation can be facilitated, further stress relaxation and low warpage can be realized. Furthermore, since the amount of expansion / contraction on both sides of the built-in layer can be controlled by embedding the wiring 16 on one side of the built-in layer in the built-in layer, it is possible to realize warpage control in the built-in layer that requires countermeasures as the lowest warp. it can. Furthermore, the connection between the semiconductor element 11 and the first wiring 15 does not include a solder material or a resin component. For example, by using a plating method, the reliability of the connection portion can be increased and high reliability is realized. I can do it. Furthermore, the electrodes on both sides can be effectively utilized through the built-in layer via 18.
　従って、薄型で反り量が少なく、高密度で接続信頼性の高い半導体装置を提供することが可能となる。 Therefore, it is possible to provide a semiconductor device that is thin and has a small amount of warpage, a high density, and high connection reliability.
　次に、実施例２について説明する。図２は実施例２による半導体装置１０ｂを示す部分断面図である。実施例１による半導体装置１０ａとは、補強材を設けていない点が異なっている。以下に、実施例１による半導体装置と異なる部分について説明を行う。特に記載のない部分については、実施例１による半導体装置と同じである。また、図２の第１電極２０や第２電極２１は、図１と同じ構造としたが、実施例１と同様に、変形が可能である。 Next, Example 2 will be described. FIG. 2 is a partial cross-sectional view showing a semiconductor device 10b according to the second embodiment. The semiconductor device 10a according to the first embodiment is different from the semiconductor device 10a in that no reinforcing material is provided. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. The first electrode 20 and the second electrode 21 in FIG. 2 have the same structure as that in FIG. 1, but can be modified as in the first embodiment.
　図２の構造は、半導体素子１１を５０μｍより薄くして更なる薄型化を実施する場合に、より効果的な構造となる。つまり、補強材１４の剛性が確保出来る厚みにおいては、補強材１４を用いる実施例１による半導体装置が効果的であるが、実質的な剛性が確保出来ない厚み、具体的には４０μｍ未満、さらには２５μｍ未満において、補強材１４を用いる必要性が無くなる。補強材１４を無くすことにより、低コスト化も実現出来る。また、あわせて第１絶縁層１３にて構成される内蔵層も薄くできることから、内蔵層ビア１８の小径化や狭ピッチ化を実現することができる。 The structure of FIG. 2 is a more effective structure when the semiconductor element 11 is made thinner than 50 μm and further thinning is performed. In other words, the thickness of the reinforcing member 14 that can ensure the rigidity of the semiconductor device according to the first embodiment using the reinforcing member 14 is effective, but the thickness that cannot ensure the substantial rigidity, specifically, less than 40 μm, Is less than 25 μm, it is not necessary to use the reinforcing material 14. By eliminating the reinforcing material 14, the cost can be reduced. In addition, since the built-in layer constituted by the first insulating layer 13 can be made thin, it is possible to reduce the diameter and the pitch of the built-in layer via 18.
　次に、上述の如く構成された実施例２による半導体装置によれば、以下の効果が得られる。実施例２による半導体装置の補強材１４に関わる部分を除いた効果に加えて、より薄型で且つ低コストな半導体装置を実現することができる。また、半導体装置として実施例１による半導体装置より内蔵層ビア１８のアスペクト比から小径化や狭ピッチ化に対応した高密度化を実現することができる。 Next, according to the semiconductor device according to the second embodiment configured as described above, the following effects can be obtained. In addition to the effect of removing the portion related to the reinforcing member 14 of the semiconductor device according to the second embodiment, a thinner and lower-cost semiconductor device can be realized. Further, as a semiconductor device, it is possible to realize a higher density corresponding to a smaller diameter and a smaller pitch from the aspect ratio of the built-in layer via 18 than the semiconductor device according to the first embodiment.
　次に、本発明の実施例３について説明する。図３は実施例３による半導体装置を示す部分断面図である。実施例１による半導体装置とは、内層側となる第２絶縁層１９においても第２配線１６を第１絶縁層と接している面の反対面で埋設している構造が異なっている。以下に、実施例１による半導体装置と異なる部分について説明を行う。特に記載のない部分については、実施例１による半導体装置と同じである。また、図３の第１電極２０や第２電極２１は、図１と同じ構造としたが、実施例１で説明したように変形することが可能である。さらに、実施例２による半導体装置と同じ内蔵層構造としても良い。図３では、６層の配線として記載しているが、これに限定されることなく４層、５層でも良く、７層以上の配線を持つ構造としても構わない。 Next, Example 3 of the present invention will be described. FIG. 3 is a partial sectional view showing a semiconductor device according to the third embodiment. The semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in the structure in which the second wiring 16 is embedded on the surface opposite to the surface in contact with the first insulating layer in the second insulating layer 19 on the inner layer side. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. Further, the first electrode 20 and the second electrode 21 in FIG. 3 have the same structure as that in FIG. 1, but can be modified as described in the first embodiment. Furthermore, the same built-in layer structure as that of the semiconductor device according to the second embodiment may be used. In FIG. 3, the wiring is described as six-layer wiring, but is not limited thereto, and may be four-layer, five-layer, or a structure having seven-layer or more wiring.
　第２絶縁層１９に対しても第２配線１６を埋設する構造とすることで、さらに反り制御能力を高めることができる。特に、第１絶縁層１３が非常に低弾性率な材料であった場合、第１絶縁層１３に埋設された第２配線１６の効果が少なくなることが発生するため、その外側に配置される第２絶縁層１９に対して埋設された第２配線１６を設けて反り制御を行う必要がある。 The warp control capability can be further enhanced by adopting a structure in which the second wiring 16 is embedded in the second insulating layer 19. In particular, when the first insulating layer 13 is made of a material having a very low elastic modulus, the effect of the second wiring 16 embedded in the first insulating layer 13 is reduced. It is necessary to provide a second wiring 16 embedded in the second insulating layer 19 to perform warpage control.
　図３では、第２絶縁層１９に埋設される第２配線１６を１層として示しているが、これに限定されることはなく、反り制御に必要な層数分形成しても構わない。 In FIG. 3, the second wiring 16 embedded in the second insulating layer 19 is shown as one layer, but the present invention is not limited to this, and it may be formed by the number of layers necessary for warpage control.
　上述の如く構成された実施例３による半導体装置によれば、実施例１による半導体装置と実施例２による半導体装置の効果に加えて、より反り制御能力を高めた半導体装置を実現することができる。 According to the semiconductor device according to the third embodiment configured as described above, in addition to the effects of the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment, it is possible to realize a semiconductor device with higher warpage control capability. .
　次に、実施例４について説明する。図４は実施例４による半導体装置を示す部分断面図である。実施例１による半導体装置及び実施例３による半導体装置とは、第１絶縁層１３が複数層となり、且つ、半導体素子１１の裏面側の第１絶縁層１３全ての層に第２配線１６が埋設されている点が異なっている。以下に、実施例３による半導体装置と異なる部分について説明を行う。特に記載のない部分については、実施例１による半導体装置もしくは実施例３による半導体装置と同じである。また、図４の第１電極２０や第２電極２１は、図１と同じ構造としたが、実施例１と同様に変形してもよい。さらに、実施例２による半導体装置と同じ内蔵層構造としても良い。図４では、６層の配線として記載しているが、これに限定されることなく４層、５層でも良く、７層以上の配線を持つ構造としても構わない。 Next, Example 4 will be described. FIG. 4 is a partial sectional view showing a semiconductor device according to the fourth embodiment. In the semiconductor device according to the first embodiment and the semiconductor device according to the third embodiment, the first insulating layer 13 has a plurality of layers, and the second wiring 16 is embedded in all the layers of the first insulating layer 13 on the back surface side of the semiconductor element 11. Is different. Hereinafter, parts different from the semiconductor device according to the third embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment or the semiconductor device according to the third embodiment. Further, the first electrode 20 and the second electrode 21 in FIG. 4 have the same structure as in FIG. 1, but may be modified in the same manner as in the first embodiment. Furthermore, the same built-in layer structure as that of the semiconductor device according to the second embodiment may be used. In FIG. 4, although described as 6-layer wiring, it is not limited to this, and it may be 4 layers, 5 layers, or a structure having 7 or more layers of wiring.
　第１絶縁層１３を複数層とすることで、より大きな応力緩和効果を得ることができる。ただし、内側の第１絶縁層１３に埋設された第２配線１６に対しては、全面が第１絶縁層１３に囲まれてしまうため、反り制御の機能が弱まってしまう。このため、存在する複数の第１絶縁層１３に対して第２配線１６を埋設することで反り制御能力を確保させることが必要となる。 By making the first insulating layer 13 a plurality of layers, a greater stress relaxation effect can be obtained. However, since the entire surface of the second wiring 16 embedded in the inner first insulating layer 13 is surrounded by the first insulating layer 13, the function of warpage control is weakened. For this reason, it is necessary to ensure warpage control capability by embedding the second wiring 16 in the plurality of existing first insulating layers 13.
　図４では、第１絶縁層１３に埋設される第２配線１６を２層として示しているが、これに限定されることはなく、反り制御に必要な層数分形成しても構わない。 In FIG. 4, the second wiring 16 embedded in the first insulating layer 13 is shown as two layers, but the present invention is not limited to this, and it may be formed by the number of layers necessary for warpage control.
　次に、上述の如く構成された実施例４による半導体装置によれば、実施例１による半導体装置、実施例２による半導体装置、さらに実施例３による半導体装置の効果に加えて、より高い応力緩和機能と反り制御能力を高めた半導体装置を実現することができる。 Next, according to the semiconductor device according to the fourth embodiment configured as described above, in addition to the effects of the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment, and the semiconductor device according to the third embodiment, higher stress relaxation. A semiconductor device with improved function and warpage control capability can be realized.
　次に、実施例５について説明する。図５は実施例５による半導体装置を示す部分断面図である。実施例１による半導体装置とは、半導体装置１０ａに電子部品２３が搭載されている点が異なっている。以下に、実施例１による半導体装置と異なる部分について説明を行う。特に記載のない部分については、実施例１による半導体装置と同じである。また、図５の第１電極２０や第２電極２１は、図１と同じ構造としたが、実施例１と同様に変形することができる。さらに、半導体装置として実施例１による半導体装置１０ａを例として記載しているが、実施例２による半導体装置１０ｂ、実施例３による半導体装置１０ｃ、実施例４による半導体装置１０ｄを用いても構わなく、それぞれの配線層数や絶縁層の組み合わせもそれぞれの実施例に記載された内容に対応する構造を用いても良い。 Next, Example 5 will be described. FIG. 5 is a partial sectional view showing a semiconductor device according to the fifth embodiment. The semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in that an electronic component 23 is mounted on the semiconductor device 10a. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. Further, the first electrode 20 and the second electrode 21 in FIG. 5 have the same structure as that in FIG. 1, but can be modified in the same manner as in the first embodiment. Further, although the semiconductor device 10a according to the first embodiment is described as an example of the semiconductor device, the semiconductor device 10b according to the second embodiment, the semiconductor device 10c according to the third embodiment, and the semiconductor device 10d according to the fourth embodiment may be used. The structure corresponding to the contents described in each embodiment may be used for the number of wiring layers and the combination of insulating layers.
　電子部品２３は、ハンダ材料、導電性ペースト、異方性導電材料、ワイヤボンディング、リボンボンディング、テープボンディングなどの接続部２４にて第１電極２０に接続されている。図５では、第１電極２０に電子部品を接続しているが、第２電極２１に電子部品を接続してもよく、第１電極２０、第２電極２１の両方に電子部品が接続されていても構わない。電子部品２３は、コンデンサや抵抗、インダクタ、半導体素子、ＭＥＭＳ、光学部品、センサなどである。 The electronic component 23 is connected to the first electrode 20 through a connection portion 24 such as a solder material, a conductive paste, an anisotropic conductive material, wire bonding, ribbon bonding, or tape bonding. In FIG. 5, the electronic component is connected to the first electrode 20, but the electronic component may be connected to the second electrode 21, and the electronic component is connected to both the first electrode 20 and the second electrode 21. It doesn't matter. The electronic component 23 is a capacitor, resistor, inductor, semiconductor element, MEMS, optical component, sensor, or the like.
　上述の如く構成された実施例５による半導体装置によれば、実施例１による半導体装置、実施例２による半導体装置、実施例３による半導体装置、さらに実施例４による半導体装置の効果に加えて、機能拡張やより安定動作となる半導体装置を実現することができる。 According to the semiconductor device according to the fifth embodiment configured as described above, in addition to the effects of the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment, the semiconductor device according to the third embodiment, and the semiconductor device according to the fourth embodiment, A semiconductor device capable of function expansion and more stable operation can be realized.
　次に、実施例６について説明する。図６は実施例６による半導体装置を示す部分断面図である。実施例１による半導体装置とは、実施例１による半導体装置１０ａと実施例３による半導体装置１０ｃを積層し、接続させた点が異なっている。以下に、実施例１による半導体装置と異なる部分について説明を行う。特に記載のない部分については、実施例１による半導体装置と同じである。また、図６の第１電極２０や第２電極２１は、図１と同じ構造としたが、実施例１と同様に変形しても良い。さらに、半導体装置として実施例１による半導体装置１０ａと実施例３による半導体装置１０ｃを例として記載しているが、実施例１による半導体装置１０ａ、実施例２による半導体装置１０ｂ、実施例３による半導体装置１０ｃ、実施例４による半導体装置１０ｄを必要にあわせて用いてもよい。それぞれの配線層数や絶縁層の組み合わせもそれぞれの実施例に記載された内容に対応する構造を用いても良い。さらに、図６では二つの半導体装置の積層の例を示しているが、これに限定されることはなく所望の個数分積層して良い。 Next, Example 6 will be described. FIG. 6 is a partial sectional view showing a semiconductor device according to the sixth embodiment. The semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device 10a according to the first embodiment and the semiconductor device 10c according to the third embodiment are stacked and connected. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. Further, the first electrode 20 and the second electrode 21 in FIG. 6 have the same structure as in FIG. 1, but may be modified in the same manner as in the first embodiment. Further, the semiconductor device 10a according to the first embodiment and the semiconductor device 10c according to the third embodiment are described as examples of the semiconductor device. However, the semiconductor device 10a according to the first embodiment, the semiconductor device 10b according to the second embodiment, and the semiconductor according to the third embodiment. The device 10c and the semiconductor device 10d according to the fourth embodiment may be used as necessary. A structure corresponding to the contents described in each embodiment may be used for the number of wiring layers and the combination of insulating layers. Further, FIG. 6 shows an example of stacking two semiconductor devices, but the present invention is not limited to this, and a desired number of stacks may be stacked.
　図６では、二つの半導体装置１０ａと１０ｃを対抗する第１電極２０と第２電極２１間に接続部２５を形成して積層している。接続部２５は、ハンダ材料、導電性ペースト、異方性導電材料、スタッドバンプ、インジウムなどを用いて接続されている。また、接続される電極は、第１電極２０と第２電極２１に限定されることはなく、必要に応じて第１電極２０と第１電極２０や第２電極２１と第２電極２１での接続を使い分けて構わない。さらに、実施例５による半導体装置の様に、電子部品２３を接続しても構わない。 In FIG. 6, a connecting portion 25 is formed and stacked between the first electrode 20 and the second electrode 21 that oppose the two semiconductor devices 10a and 10c. The connection portion 25 is connected using a solder material, a conductive paste, an anisotropic conductive material, a stud bump, indium, or the like. Further, the electrodes to be connected are not limited to the first electrode 20 and the second electrode 21, and the first electrode 20 and the first electrode 20, or the second electrode 21 and the second electrode 21, as necessary. You can use different connections. Further, the electronic component 23 may be connected as in the semiconductor device according to the fifth embodiment.
　上述の如く構成された実施例６による半導体装置によれば、実施例１による半導体装置、実施例２による半導体装置、実施例３による半導体装置、実施例４による半導体装置、さらに実施例５による半導体装置の効果に加えて、より設計自由度を高めた形で機能拡張やより安定動作となる半導体装置を実現することができる。 According to the semiconductor device according to the sixth embodiment configured as described above, the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment, the semiconductor device according to the third embodiment, the semiconductor device according to the fourth embodiment, and the semiconductor according to the fifth embodiment. In addition to the effects of the device, it is possible to realize a semiconductor device that can perform function expansion and more stable operation with a higher degree of design freedom.
　なお、前述の各実施例において、半導体素子１１、補強材１４、第１配線１５、第２配線１６、第１電極２０、第２電極２１で構成される積層回路の所望の位置に、回路のノイズフィルターやデカップリングの役割を果たすコンデンサが設けられていてもよい。コンデンサを構成する誘電体材料としては、酸化チタン、酸化タンタル、Ａｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＨｆＯ２又はＮｂ２Ｏ５等の金属酸化物、ＢＳＴ（ＢａｘＳｒ１－ｘＴｉＯ３）、ＰＺＴ（ＰｂＺｒｘＴｉ１－ｘＯ３）又はＰＬＺＴ（Ｐｂ１－ｙＬａｙＺｒｘＴｉ１－ｘＯ３）等のペロブスカイト系材料若しくはＳｒＢｉ２Ｔａ２Ｏ９等のＢｉ系層状化合物であることが好ましい。但し、０≦ｘ≦１、０＜ｙ＜１である。また、コンデンサを構成する誘電体材料として、無機材料や磁性材料を混合した有機材料等を使用してもよい。 In each of the above-described embodiments, the circuit is placed at a desired position of the laminated circuit including the semiconductor element 11, the reinforcing material 14, the first wiring 15, the second wiring 16, the first electrode 20, and the second electrode 21. A capacitor that plays the role of a noise filter or decoupling may be provided. Examples of the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2, or Nb 2 O 5 , BST (Ba x Sr 1-x TiO 3). ), in PZT (PbZr x Ti 1-x O 3) or PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite material or SrBi 2 Ta Bi-based layered compounds such as 2 O 9, such as Preferably there is. However, 0 ≦ x ≦ 1 and 0 <y <1. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
　更に、第１絶縁層１３や第２絶縁層１９の一層もしくは複数層において、誘電率が９以上となる材料により構成され、その上下の配線層の所望の位置に対向電極を形成することで回路のノイズフィルターやデカップリングの役割を果たすコンデンサを設けても良い。コンデンサを構成する誘電体材料としては、Ａｌ２Ｏ３、ＺｒＯ２、ＨｆＯ２又はＮｂ２Ｏ５等の金属酸化物、ＢＳＴ（ＢａｘＳｒ１－ｘＴｉＯ３）、ＰＺＴ（ＰｂＺｒｘＴｉ１－ｘＯ３）又はＰＬＺＴ（Ｐｂ１－ｙＬａｙＺｒｘＴｉ１－ｘＯ３）等のペロブスカイト系材料若しくはＳｒＢｉ２Ｔａ２Ｏ９等のＢｉ系層状化合物であることが好ましい。但し、０≦ｘ≦１、０＜ｙ＜１である。また、コンデンサを構成する誘電体材料として、無機材料や磁性材料を混合した有機材料等を使用してもよい。 Further, one or more layers of the first insulating layer 13 and the second insulating layer 19 are made of a material having a dielectric constant of 9 or more, and a counter electrode is formed at a desired position on the upper and lower wiring layers to form a circuit. A noise filter or a capacitor that plays the role of decoupling may be provided. The dielectric material constituting the capacitor, Al 2 O 3, ZrO 2 , HfO 2 or Nb 2 O metal oxide such as 5, BST (Ba x Sr 1 -x TiO 3), PZT (PbZr x Ti 1- x O 3 ) or a perovskite material such as PLZT (Pb 1-y La y Zr x Ti 1-x O 3 ) or a Bi-based layered compound such as SrBi 2 Ta 2 O 9 is preferable. However, 0 ≦ x ≦ 1 and 0 <y <1. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.
　以下、本発明による半導体装置の製造方法の実施例について図面を参照して具体的に説明する。先ず、実施例７による半導体装置の製造方法について説明する。図７、図８は実施例７による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。 Hereinafter, embodiments of a method for manufacturing a semiconductor device according to the present invention will be specifically described with reference to the drawings. First, a method for manufacturing a semiconductor device according to Example 7 will be described. 7 and 8 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the seventh embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
　まず、図７（ａ）に示したとおり、支持体２６上に第２配線１６を形成する。支持体２６については、必要であれば表面のウェット洗浄、ドライ洗浄、平坦化、粗化など処理を施す。支持体２６は、導電性の材料、もしくは、表面に導電性の膜が形成された材料で、適度な剛性を有していることが望ましい。具体的な支持体の材料としては、シリコン、サファイア、ＧａＡｓ等の半導体ウエハ材料、金属、石英、ガラス、セラミック、プリント板を用いることができる。導電性の材料は、金属、半導体材料、および所望の電気伝導度を有する有機材料のいずれかもしくは複数により形成される。ここでは、０．２５ｍｍ厚みの銅板を支持基板に用いた。第２配線１６は、例えば銅により構成されており、その厚さは１０μｍである。第２配線１６は、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等の配線形成法により形成する。微細な配線を形成する場合は、セミアディティブ法を選択し、給電層をスパッタ法、無電解めっき法、ＣＶＤ法、エアロゾル法等により形成する。ここでは、銅板を給電層としてドライフィルムレジストを用いて、電解めっきによりＮｉ，Ｃｕの順に積層した。Ｎｉは３μｍ厚み、Ｃｕは１０μｍ厚みとした。 First, as shown in FIG. 7A, the second wiring 16 is formed on the support 26. The support 26 is subjected to treatment such as wet cleaning, dry cleaning, flattening, and roughening of the surface, if necessary. The support 26 is preferably made of a conductive material or a material having a conductive film formed on the surface thereof and has an appropriate rigidity. Specific examples of the support material include semiconductor wafer materials such as silicon, sapphire, and GaAs, metals, quartz, glass, ceramics, and printed boards. The conductive material is formed of one or more of a metal, a semiconductor material, and an organic material having a desired electrical conductivity. Here, a copper plate having a thickness of 0.25 mm was used as the support substrate. The second wiring 16 is made of, for example, copper and has a thickness of 10 μm. The second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method. In the case of forming fine wiring, the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like. Here, a copper plate was used as a power feeding layer, a dry film resist was used, and Ni and Cu were laminated in this order by electrolytic plating. Ni was 3 μm thick and Cu was 10 μm thick.
　次に、図７（ｂ）に示したとおり、第２配線１６を覆う様に第１絶縁層１３を形成する。第１絶縁層１３は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。第１絶縁層１３の形成は、液状の有機材料であれば、スピンコート法、カーテンコート法、ダイコート法、スプレー法、印刷法等により形成される。また、フィルム状の有機材料の場合は、ラミネート法、プレス法やそれぞれに真空状態を付加した製法等により形成される。ここでは、２０μｍ厚みの低弾性率のシート状エポキシ樹脂を用いて、真空ラミネータにより積層を行った。 Next, as shown in FIG. 7B, the first insulating layer 13 is formed so as to cover the second wiring 16. The first insulating layer 13 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The first insulating layer 13 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like. Here, lamination was performed by a vacuum laminator using a low elastic modulus sheet-like epoxy resin having a thickness of 20 μm.
　次に、図７（ｃ）に示したとおり、半導体素子１１を第１絶縁層１３上に設置する。半導体素子１１の接着では、第１絶縁層１３を硬化させる前などで所望の接着機能が存在していれば、そのまま接着を実施すれば良く、特にない場合や不安定である場合は、液状やシート状の接着剤を用いても良い。接着剤は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂などで形成されている。また、半導体素子１１には接続部１２が設けられていても良い。 Next, as shown in FIG. 7C, the semiconductor element 11 is placed on the first insulating layer 13. In the bonding of the semiconductor element 11, if a desired bonding function exists before the first insulating layer 13 is cured, the bonding may be performed as it is. A sheet-like adhesive may be used. The adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like. The semiconductor element 11 may be provided with a connection portion 12.
　接続部１２にはハンダ材料や樹脂成分、つまり、ペースト材料や異方性導電材料による接続は実施されておらず、安定して剛性のある接続部分が設けられる。具体的には、蒸着法、スパッタ法、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、無電解めっき法、電解めっき法などで設けられる。製造方法の例としては、蒸着法、スパッタ法、ＣＶＤ法、ＡＬＤ法、無電解めっき法などで給電層を設けた後に電解めっき法や無電解めっき法により所望の膜厚とするセミアディティブ法により形成することができる。ただし、ナノ粒子によるペースト材料において、樹脂成分が無くなる場合や、温度をかけて焼結体に近づける際に樹脂成分が昇華する材料であれば使用可能である。 The connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion. Specifically, it is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, and the like. Examples of the manufacturing method include a semi-additive method in which a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc., and a desired film thickness is obtained by an electrolytic plating method or an electroless plating method. Can be formed. However, in the paste material made of nanoparticles, any material can be used as long as the resin component disappears or a material that sublimes the resin component when the temperature is approached to the sintered body.
　また、半導体素子１１は、半導体装置１０ａの薄型化のために薄く仕上がっていることが望ましい。具体的には、３００μｍ以下の厚み、好ましくは１５０μｍ以下の厚み、より好ましくは１００μｍ以下の厚みである。ここでは、接続部１２として２０μｍ高さの銅ポストを電解めきにより設けた５０μｍ厚みの半導体素子１１を、第１絶縁層１３上に設置し、第１絶縁層１３のキュア処理にて接着を行った。 Further, it is desirable that the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a. Specifically, the thickness is 300 μm or less, preferably 150 μm or less, and more preferably 100 μm or less. Here, a semiconductor element 11 having a thickness of 50 μm provided with a copper post having a height of 20 μm as the connection part 12 is placed on the first insulating layer 13 and bonded by a curing process of the first insulating layer 13. It was.
　次に、図７（ｄ）に示したとおり、補強材１４を積層し、さらにその上に第１絶縁層１３を積層する。補強材１４の材料としては、金属材料、セラミック、ガラス、シリコン、プリント基板、ガラスクロス等による織布や不織布を用いることができる。金属材料としては、銅、ニッケル、コバルト、鉄、ステンレス、アルミニウム、モリブデン、マンガンを主とする材料や合金を用いることができる。補強材が導電性を有する場合は、第１配線や第２配線と接続して、電源やグランド回路としても良い。また、補強材自体に配線が設けられていても構わない。補強材１４の接着は、半導体素子１１と同様に、第１絶縁層１３を硬化させる前などで所望の接着機能が存在していれば、そのまま接着を実施すれば良い。接着機能が特にない場合や不安定である場合は、液状やシート状の接着剤を用いて接着しても良い。また、補強材１４の材料自体に接着性がある場合は、そのまま使用しても構わない。第１絶縁層１３の積層は、図７（ｂ）で記載した方法を繰り返す。この実施例では、補強材１４としてガラスクロスにエポキシ樹脂を含浸した５０μｍ厚みのプリプレグ材を用い、真空ラミネータにより積層を行った。また、第１絶縁層１３は、２０μｍ厚みの低弾性率のシート状エポキシ樹脂を用いて、真空ラミネータにより積層を実施し、先のプリプレグ材と第１絶縁層１３をあわせてキュア工程の熱処理を実施した。 Next, as shown in FIG. 7D, the reinforcing material 14 is laminated, and the first insulating layer 13 is further laminated thereon. As a material of the reinforcing material 14, a woven fabric or a non-woven fabric made of a metal material, ceramic, glass, silicon, a printed board, glass cloth, or the like can be used. As the metal material, materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used. When the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring. As with the semiconductor element 11, the reinforcing material 14 may be bonded as long as a desired bonding function exists before the first insulating layer 13 is cured. When the adhesive function is not particularly present or unstable, a liquid or sheet-like adhesive may be used for adhesion. Moreover, when the material itself of the reinforcing material 14 has adhesiveness, it may be used as it is. For the lamination of the first insulating layer 13, the method described in FIG. In this example, a 50 μm-thick prepreg material in which a glass cloth was impregnated with an epoxy resin was used as the reinforcing material 14, and lamination was performed using a vacuum laminator. The first insulating layer 13 is laminated by a vacuum laminator using a sheet-like epoxy resin having a low elastic modulus with a thickness of 20 μm, and the heat treatment in the curing process is performed by combining the prepreg material and the first insulating layer 13. Carried out.
　次に、図７（ｅ）に示したとおり、内蔵層ビア１８と第１配線１５を形成する。内蔵層ビア１８は、開口部をレーザ、ドライエッチング法、ブラストなどにより形成し、第１配線１５の工程で形成するか、ビア開口部を電解めっき法、無電解めっき法、印刷法等により導電材料で埋めてから配線形成しても良い。さらに、内蔵層ビア１８となる部分に金属ポストをめっき法や印刷法により形成しておき、第１絶縁層１３や補強材１４を形成した後にバフ研磨、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより金属ポスト表面の第１絶縁層１３を除去し、金属ポストを露出させて内蔵層ビア１８としても構わない。また、図７は、内蔵層ビア１８の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。 Next, as shown in FIG. 7E, the built-in layer via 18 and the first wiring 15 are formed. The built-in layer via 18 has an opening formed by laser, dry etching, blasting, etc., and is formed in the process of the first wiring 15, or the via opening is made conductive by electrolytic plating, electroless plating, printing, etc. The wiring may be formed after filling with the material. Further, a metal post is formed in a portion to become the internal layer via 18 by a plating method or a printing method, and after the first insulating layer 13 and the reinforcing material 14 are formed, buff polishing, dry etching method, CMP method, grinding method, The first insulating layer 13 on the surface of the metal post may be removed by a lapping method or the like, and the metal post may be exposed to form the built-in layer via 18. FIG. 7 shows the opening of the built-in layer via 18 as a vertical wall, but a taper angle may be provided.
　また、第１配線１５と接続部１２は接続する。接続部１２は、図７（ｃ）で記載したとおり接続部分が形成されており、第１絶縁層１３の仕上がり膜厚より厚い接続部１２の場合は、バフ研磨、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより接続部１２を第１配線１５形成前に露出させる。接続部１２が第１絶縁層１３より薄い場合は、開口部をレーザ、ドライエッチング法、ブラストなどにより形成し、第１配線１５の工程で接続する。 Also, the first wiring 15 and the connecting portion 12 are connected. As shown in FIG. 7C, the connection portion 12 is formed with a connection portion. In the case of the connection portion 12 thicker than the finished film thickness of the first insulating layer 13, buffing, dry etching, CMP, The connecting portion 12 is exposed before the first wiring 15 is formed by a grinding method, a lapping method, or the like. When the connecting portion 12 is thinner than the first insulating layer 13, the opening is formed by laser, dry etching, blasting, or the like, and connected in the process of the first wiring 15.
　第１配線１５は、図７（ａ）に記載したとおりの配線技術により形成する。ここでは、内蔵層ビア１８はレーザにより開口を形成し、支持体の銅板から給電を行うことで開口内部を銅メッキで充填した。また、接続部１２は、先に記載した通り、３０μｍ高さの銅ポストを形成しており、第１絶縁層表面をバフ研磨により研磨することで接続点を露出させた。さらに、第１配線１５は、スパッタ膜を給電層としたセミアディティブ法を用い、膜厚１０μｍとして形成した。 The first wiring 15 is formed by a wiring technique as described in FIG. Here, the built-in layer via 18 is formed with an opening by a laser, and the inside of the opening is filled with copper plating by supplying power from the copper plate of the support. Further, as described above, the connection portion 12 formed a copper post having a height of 30 μm, and the connection point was exposed by polishing the surface of the first insulating layer by buffing. Further, the first wiring 15 was formed with a film thickness of 10 μm using a semi-additive method using a sputtered film as a power feeding layer.
　次に、図８（ｆ）に示したとおり、支持体２６を除去する。支持体２６の除去方法は、ウェットエッチング法、ドライエッチング法、及び研磨法などのいずれかもしくはこれらの組み合わせにより行う。また、支持体２６に低密着の剥離が容易な部分を設けていれば、剥離により行っても構わなく、剥離後にウェットエッチング法、ドライエッチング法、及び研磨法などのいずれかもしくはこれらの組み合わせによる処理を行っても良い。ここでは、ウェットエッチングにより銅板を除去した。その際、Ｎｉは銅板エッチング時のエッチングバリアとして使用する。最終的にはＮｉをウェットエッチングにて除去した。 Next, as shown in FIG. 8F, the support 26 is removed. The support 26 is removed by any one of wet etching, dry etching, polishing, or a combination thereof. Further, if the support 26 is provided with a portion with low adhesion that can be easily peeled off, peeling may be performed. After the peeling, any one of wet etching, dry etching, polishing, or a combination thereof may be used. Processing may be performed. Here, the copper plate was removed by wet etching. At that time, Ni is used as an etching barrier when etching the copper plate. Finally, Ni was removed by wet etching.
　次に、図８（ｇ）に示すとおり、第２絶縁層１９を形成する。形成方法は、図７（ｂ）に記載した方法を用い、積層後に熱処理を行って絶縁層とする。両面同時に積層しても良く、片面ずつ交互に積層しても構わない。ここでは、シート状の５０μｍ厚みのエポキシ樹脂を真空ラミネータにより両面同時に積層した。 Next, as shown in FIG. 8G, the second insulating layer 19 is formed. As the formation method, the method described in FIG. 7B is used, and heat treatment is performed after stacking to form an insulating layer. Both sides may be laminated simultaneously, or each side may be laminated alternately. Here, a sheet-like epoxy resin having a thickness of 50 μm was laminated at the same time by a vacuum laminator.
　次に、図８（ｈ）に示すとおり、ビア１７と第１配線１５と第２配線１６を形成する。ビア１７は、感光性の有機材料を第２絶縁層１９に用いた場合は、スピンコート法、ラミネート法、プレス法、及び印刷法により形成した後、ビア１７となる。 Next, as shown in FIG. 8H, the via 17, the first wiring 15, and the second wiring 16 are formed. In the case where a photosensitive organic material is used for the second insulating layer 19, the via 17 becomes the via 17 after being formed by a spin coating method, a laminating method, a pressing method, and a printing method.
　開口部はフォトリソグラフィー法などにより形成される。非感光性や感光性でパターン解像度が低い有機材料を用いた場合は、ビア１７となる開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。さらに、ビア１７となる部分に金属ポストをめっき法や印刷法により形成しておき、第２絶縁層１９を形成した後に、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより除去し、金属ポストを露出させることでビア１７とする方法を用いても構わない。また、図８は、ビア１７の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。 The opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like. Further, a metal post is formed on the portion to become the via 17 by a plating method or a printing method, and after forming the second insulating layer 19, it is removed by a dry etching method, a CMP method, a grinding method, a lapping method, etc. A method of forming the via 17 by exposing the post may be used. FIG. 8 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided.
　次に、図８（ｉ）に示すとおり、最表面にソルダーレジスト２２を形成する。ソルダーレジスト２２は、第１電極２０と第２電極２１となる部分を開口して形成する。ソルダーレジスト２２の開口を第１電極２０や第２電極２１より大きくした場合は、第１電極２０や第２電極２１の側壁部分のハンダ材料も接続面とすることができ、接続信頼性を高めることができる。また、改めて電極を設ける構造では、ソルダーレジスト２２も応力緩和に用いることができるため、更なる信頼性の向上が実現出来る。第１電極２０や第２電極２１は、例えば複数の層が積層されたものであり、例えば、第１電極２０や第２電極２１の表面に形成されるハンダボールの濡れ性やボンディングワイヤーとの接続性を考慮して、第１電極２０や第２電極２１の表面は、銅、アルミニウム、金、銀及びハンダ材料からなる群から選択された少なくとも一種の金属及び合金が設けられる。第１電極２０や第２電極２１は、接続に対して効果のある構造を適宜選択すれば良く、必ずしも同じ構造とする必要はない。 Next, as shown in FIG. 8I, a solder resist 22 is formed on the outermost surface. The solder resist 22 is formed by opening portions that become the first electrode 20 and the second electrode 21. When the opening of the solder resist 22 is made larger than the first electrode 20 and the second electrode 21, the solder material on the side wall portions of the first electrode 20 and the second electrode 21 can also be used as a connection surface, thereby improving connection reliability. be able to. Further, in the structure in which the electrodes are newly provided, the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized. For example, the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers. For example, the wettability of solder balls formed on the surfaces of the first electrode 20 and the second electrode 21 and bonding wires In consideration of connectivity, the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials. The first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure.
　ソルダーレジスト２２は、例えば有機材料で形成されており、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。有機材料は、感光性、非感光性のいずれを用いても構わない。感光性の有機材料を用いた場合、フォトリソグラフィー法などにより開口部を形成する。非感光性や感光性でパターン解像度が低い有機材料を用いた場合、開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。 The solder resist 22 is formed of, for example, an organic material. For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
　電極の構造は、図８に示した構造としても良く、ソルダーレジスト２２の開口が第１電極２０や第２電極２１電極より大きくなる逃げと呼ばれる構造としても良く、さらには、ソルダーレジスト上に電極を改めて作製する構造としても良い。図８に示す構造では、ハンダ材料を用いて接続する場合に、第１電極２０や第２電極２１のみにハンダが供給される様にソルダーレジスト２２にて開口を制限している。このソルダーレジスト２２による制限により、ハンダの流れ量が制限されるため、半導体装置を実装基板や別部品と接続する際の取り付け高さを安定化させることが実現出来る。ここでは、感光性のソルダーレジスト２２を用いて開口部を形成した後に、第１電極２０や第２電極２１として無電解めっきにて、Ａｕ層が表面となる様にＣｕ層上にＮｉ層と金層を順に積層させた。Ｎｉ層の厚さは３μｍ、Ａｕ層の厚さは１μｍである。 The structure of the electrode may be the structure shown in FIG. 8, or may be a structure called relief where the opening of the solder resist 22 is larger than the first electrode 20 or the second electrode 21, and further, the electrode is formed on the solder resist. It is good also as a structure which produces again. In the structure shown in FIG. 8, when connecting using a solder material, the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21. The solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component. Here, after the opening is formed using the photosensitive solder resist 22, the Ni layer is formed on the Cu layer so that the Au layer becomes the surface by electroless plating as the first electrode 20 and the second electrode 21. Gold layers were laminated in order. The thickness of the Ni layer is 3 μm, and the thickness of the Au layer is 1 μm.
　上記実施例７による半導体装置の製造方法によれば、実施例１による半導体装置を効率よく製造することができる。補強材１４を取り付けなければ実施例２による半導体装置を効率よく製造することができる。また、電子部品を搭載することや半導体装置の積層を行うことで、実施例５による半導体装置や実施例６による半導体装置を効率よく製造することができる。さらに、図７、８は個片の部分断面図として示しているが、複数の半導体装置が一度に作製され、ダイシングや裁断により個片化される工程を行っても良い。さらにまた、図７（ａ）から（ｅ）までは、支持体の両面に半導体装置を形成して生産性を高めることを行っても良い。 According to the semiconductor device manufacturing method of the seventh embodiment, the semiconductor device according to the first embodiment can be efficiently manufactured. If the reinforcing member 14 is not attached, the semiconductor device according to the second embodiment can be efficiently manufactured. In addition, by mounting electronic components and stacking semiconductor devices, the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment can be efficiently manufactured. Further, although FIGS. 7 and 8 are shown as partial sectional views of individual pieces, a process in which a plurality of semiconductor devices are manufactured at once and separated into individual pieces by dicing or cutting may be performed. Furthermore, in FIGS. 7A to 7E, semiconductor devices may be formed on both sides of the support to increase productivity.
　次に、実施例７の変形例である実施例８による半導体装置の製造方法について説明する。図８は実施例８による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。実施例７による製造方法とは、第２絶縁層１９を支持体２６除去前に形成する点が異なっている。 Next, a method for manufacturing a semiconductor device according to Example 8, which is a modification of Example 7, will be described. FIG. 8 is a manufacturing process diagram showing a method of manufacturing a semiconductor device according to the eighth embodiment. In each step, cleaning or heat treatment may be performed as appropriate. The manufacturing method according to Example 7 is different in that the second insulating layer 19 is formed before the support 26 is removed.
　以下に、実施例７の製造方法と異なる工程分について説明を行う。特に記載のない部分については、実施例７の製造工程と同じである。まず、図９（ａ）は、図７（ｅ）と同じ状態であり、図７（ｅ）までは実施例７と同一の方法で形成する。次いで、図９（ｂ）に示すとおり、第２絶縁層１９を積層する。次いで、図９（ｃ）に示すとおり、支持体２６を除去する。次いで、図９（ｄ）に示すとおり、第１絶縁層１３が露出している面に第２絶縁層１９を積層する。この後は、実施例７の図８（ｈ）以降の工程を進めることとなる。 Hereinafter, steps different from the manufacturing method of Example 7 will be described. Parts not specifically described are the same as those in the manufacturing process of Example 7. First, FIG. 9A is in the same state as FIG. 7E, and the process up to FIG. Next, as shown in FIG. 9B, the second insulating layer 19 is laminated. Next, as shown in FIG. 9C, the support 26 is removed. Next, as shown in FIG. 9D, the second insulating layer 19 is laminated on the surface where the first insulating layer 13 is exposed. After this, the process after FIG. 8H of Example 7 will be advanced.
　実施例８の製造方法によれば、実施例７と同じ効果に加えて、先に第２絶縁層１９を形成することにより、第１配線１５が支持体２６の除去工程でダメージを受けることが無くなり、不良発生率を少なくすることができる。また、支持体２６を除去した後の剛性が実施例７より高くなるため、ハンドリング性を改善することができる。 According to the manufacturing method of the eighth embodiment, in addition to the same effect as that of the seventh embodiment, the first insulating layer 19 is formed first, so that the first wiring 15 is damaged in the removal process of the support 26. As a result, the defect occurrence rate can be reduced. Moreover, since the rigidity after removing the support body 26 becomes higher than that of the seventh embodiment, handling properties can be improved.
　次に、実施例７の第２の変形例である実施例９による半導体装置の製造方法について説明する。図１０、１１は実施例９による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。実施例７とは、支持体２６上に第２絶縁層１９を形成する点と、第１配線１５を覆う様に第２絶縁層１９を形成してから支持体２６除去する点が異なっている。以下に、実施例７と異なる部分について説明を行う。特に記載のない部分については、実施例７の製造工程と同じである。 Next, a method for manufacturing a semiconductor device according to Example 9 which is a second modification of Example 7 will be described. 10 and 11 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the ninth embodiment. In each step, cleaning or heat treatment may be performed as appropriate. The seventh embodiment is different from the seventh embodiment in that the second insulating layer 19 is formed on the support 26 and that the support 26 is removed after the second insulating layer 19 is formed so as to cover the first wiring 15. . Hereinafter, parts different from the seventh embodiment will be described. Parts not specifically described are the same as those in the manufacturing process of Example 7.
　まず、図１０（ａ）に示すとおり、支持体２６上に第２絶縁層１９を形成する。また、第２絶縁層１９上に第１配線１５を形成する。次いで、図１０（ｂ）に示すとおり、第２配線１６を覆う様に第１絶縁層１３を形成する。次いで、図１０（ｃ）に示すとおり、半導体素子１１を第１絶縁層１３上に接着させる。次いで、図１０（ｄ）に示すとおり、補強材１４を形成し、第１絶縁層１３を覆う様に形成する。次いで、図１１（ｅ）に示すとおり、内蔵層ビア１８と第１配線１５を形成する。第１配線１５と接続部１２は接続されている。次いで、図１１（ｆ）に示すとおり、第１配線１５を覆う様に第２絶縁層１９を形成する。次いで、図１１（ｇ）に示すとおり、支持体２６を除去する。この後は、実施例７の図８（ｈ）以降の工程を進めることとなる。 First, as shown in FIG. 10A, the second insulating layer 19 is formed on the support 26. In addition, the first wiring 15 is formed on the second insulating layer 19. Next, as shown in FIG. 10B, the first insulating layer 13 is formed so as to cover the second wiring 16. Next, as shown in FIG. 10C, the semiconductor element 11 is bonded onto the first insulating layer 13. Next, as shown in FIG. 10D, the reinforcing material 14 is formed so as to cover the first insulating layer 13. Next, as shown in FIG. 11E, the built-in layer via 18 and the first wiring 15 are formed. The 1st wiring 15 and the connection part 12 are connected. Next, as shown in FIG. 11F, a second insulating layer 19 is formed so as to cover the first wiring 15. Next, as shown in FIG. 11G, the support 26 is removed. After this, the process after FIG. 8H of Example 7 will be advanced.
　上記実施例９の半導体装置の製造方法によれば、実施例７と同じ効果に加えて、支持体除去より先に両側の第２絶縁層１９を形成することにより、第１配線１５と第２配線１６が支持体２６の除去工程でダメージを受けることが無くなり、不良発生率を実施例８より少なくすることができる。また、支持体２６を除去した後の剛性が実施例７、８より高くなるため、実施例７、８よりハンドリング性を改善することができる。 According to the manufacturing method of the semiconductor device of the ninth embodiment, in addition to the same effect as that of the seventh embodiment, the second insulating layers 19 on both sides are formed before the support is removed, so that the first wiring 15 and the second wiring The wiring 16 is not damaged in the removal process of the support 26, and the defect occurrence rate can be reduced as compared with the eighth embodiment. In addition, since the rigidity after removing the support 26 is higher than those of the seventh and eighth embodiments, the handling property can be improved as compared with the seventh and eighth embodiments.
　次いで、実施例１０による半導体装置の製造方法について説明する。図１２、１３は実施例１０による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。 Next, a method for manufacturing a semiconductor device according to Example 10 will be described. 12 and 13 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the tenth embodiment. In each step, cleaning or heat treatment may be performed as appropriate.
　まず、図１２（ａ）に示したとおり、支持体２６上に第２配線１６を形成する。支持体２６については、必要であれば表面のウェット洗浄、ドライ洗浄、平坦化、粗化など処理を施す。支持体２６は、導電性の材料、もしくは、表面に導電性の膜が形成された材料で、適度な剛性を有していることが望ましいため、シリコン、サファイア、ＧａＡｓ等の半導体ウエハ材料、金属、石英、ガラス、セラミック、プリント板を用いることができる。導電性の材料は、金属、半導体材料、および所望の電気伝導度を有する有機材料のいずれかもしくは複数により形成される。ここでは、０．２５ｍｍ厚みの銅板を支持基板に用いた。第２配線１６は、例えば銅により構成されており、その厚さは１０μｍである。第２配線１６は、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等の配線形成法により形成する。微細な配線を形成する場合は、セミアディティブ法を選択し、給電層をパッタ法、無電解めっき法、ＣＶＤ法、エアロゾル法等により形成する。ここでは、銅板を給電層としてドライフィルムレジストを用いて、電解めっきによりＮｉ，Ｃｕの順に積層した。Ｎｉは３μｍ厚み、Ｃｕは１０μｍ厚みとした。 First, as shown in FIG. 12A, the second wiring 16 is formed on the support 26. The support 26 is subjected to treatment such as wet cleaning, dry cleaning, flattening, and roughening of the surface, if necessary. Since the support 26 is a conductive material or a material having a conductive film formed on the surface thereof and preferably has an appropriate rigidity, a semiconductor wafer material such as silicon, sapphire, and GaAs, a metal Quartz, glass, ceramic, and printed board can be used. The conductive material is formed of one or more of a metal, a semiconductor material, and an organic material having a desired electrical conductivity. Here, a copper plate having a thickness of 0.25 mm was used as the support substrate. The second wiring 16 is made of, for example, copper and has a thickness of 10 μm. The second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method. In the case of forming fine wiring, the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like. Here, a copper plate was used as a power feeding layer, a dry film resist was used, and Ni and Cu were laminated in this order by electrolytic plating. Ni was 3 μm thick and Cu was 10 μm thick.
　次に、図１２（ｂ）に示したとおり、第２配線１６を覆う様に第２絶縁層１９を形成する。第２絶縁層１９は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。第２絶縁層１９の形成は、液状の有機材料であれば、スピンコート法、カーテンコート法、ダイコート法、スプレー法、印刷法等により形成される。また、フィルム状の有機材料の場合は、ラミネート法、プレス法やそれぞれに真空状態を付加した製法等により形成される。ここでは、２０μｍ厚みのシート状エポキシ樹脂を用いて、真空ラミネータにより積層を行った。 Next, as shown in FIG. 12B, a second insulating layer 19 is formed so as to cover the second wiring 16. The second insulating layer 19 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The second insulating layer 19 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like. Here, lamination was performed by a vacuum laminator using a sheet-like epoxy resin having a thickness of 20 μm.
　次に、図１２（ｃ）に示したとおり、ビア１７と第２配線１６を形成する。ビア１７は、感光性の有機材料を第２絶縁層１９に用いた場合は、スピンコート法、ラミネート法、プレス法、及び印刷法により形成した後、ビア１７となる開口部はフォトリソグラフィー法などにより形成される。非感光性や感光性でパターン解像度が低い有機材料を用いた場合は、ビア１７となる開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。さらに、ビア１７となる部分に金属ポストをめっき法や印刷法により形成しておき、第２絶縁層１９を形成した後に、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより第２絶縁層の一部を除去し、金属ポストを露出させることでビア１７とする方法を用いても構わない。また、図１２は、ビア１７の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。第２配線１６は、例えば銅により構成されており、その厚さは１０μｍである。第２配線１６は、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等の配線形成法により形成する。微細な配線を形成する場合は、セミアディティブ法を選択し、給電層をスパッタ法、無電解めっき法、ＣＶＤ法、エアロゾル法等により形成する。本発明では、ビア１７はレーザによる開口を行い、スパッタ膜を給電層としてドライフィルムレジストを用いて、電解めっきにより１０μｍ厚みの銅配線を形成した。 Next, as shown in FIG. 12C, the via 17 and the second wiring 16 are formed. When a photosensitive organic material is used for the second insulating layer 19, the via 17 is formed by a spin coating method, a laminating method, a pressing method, and a printing method, and then an opening that becomes the via 17 has a photolithography method or the like. It is formed by. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like. Further, a metal post is formed on the portion to be the via 17 by a plating method or a printing method, and after the second insulating layer 19 is formed, the second insulating layer is formed by a dry etching method, a CMP method, a grinding method, a lapping method, or the like. Alternatively, the via 17 may be used by removing a part of the metal post and exposing the metal post. FIG. 12 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided. The second wiring 16 is made of, for example, copper and has a thickness of 10 μm. The second wiring 16 is formed by a wiring formation method such as a subtractive method, a semi-additive method, or a full additive method. In the case of forming fine wiring, the semi-additive method is selected, and the power feeding layer is formed by a sputtering method, an electroless plating method, a CVD method, an aerosol method, or the like. In the present invention, the via 17 is opened by laser, and a copper wiring having a thickness of 10 μm is formed by electrolytic plating using a dry film resist with the sputtered film as a power feeding layer.
　次に、図１２（ｄ）に示したとおり、半導体素子１１を第１絶縁層１３上に設置し、補強材１４と第１絶縁層１３の積層と、内蔵層ビア１８及び第１配線１５の形成を行う。半導体素子１１の接着では、第１絶縁層１３を硬化させる前などで所望の接着機能が存在していれば、そのまま接着を実施すれば良く、特にない場合や不安定である場合は、液状やシート状の接着剤を用いても良い。接着剤は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂などで形成されている。 Next, as shown in FIG. 12D, the semiconductor element 11 is placed on the first insulating layer 13, and the lamination of the reinforcing material 14 and the first insulating layer 13, the built-in layer via 18, and the first wiring 15. Form. In the bonding of the semiconductor element 11, if a desired bonding function exists before the first insulating layer 13 is cured, the bonding may be performed as it is. A sheet-like adhesive may be used. The adhesive is formed of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like.
　また、半導体素子１１には接続部１２が設けられていても良い。接続部１２にはハンダ材料や樹脂成分、つまり、ペースト材料や異方性導電材料による接続は実施されておらず、安定して剛性のある接続部分が設けられる。具体的には、蒸着法、スパッタ法、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、無電解めっき法、電解めっき法などで設けられる。製造方法の例としては、蒸着法、スパッタ法、ＣＶＤ法、ＡＬＤ法、無電解めっき法などで給電層を設けた後に電解めっき法や無電解めっき法により所望の膜厚とするセミアディティブ法により形成することができる。ただし、ナノ粒子によるペースト材料において、樹脂成分が無くなる場合や、温度をかけて焼結体に近づける際に樹脂成分が昇華する材料であれば使用可能である。 Further, the semiconductor element 11 may be provided with a connection portion 12. The connection portion 12 is not connected with a solder material or a resin component, that is, a paste material or an anisotropic conductive material, and is provided with a stable and rigid connection portion. Specifically, it is provided by vapor deposition, sputtering, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, electrolytic plating, and the like. Examples of the manufacturing method include a semi-additive method in which a power supply layer is provided by a vapor deposition method, a sputtering method, a CVD method, an ALD method, an electroless plating method, etc., and a desired film thickness is obtained by an electrolytic plating method or an electroless plating method. Can be formed. However, in the paste material made of nanoparticles, any material can be used as long as the resin component disappears or a material that sublimes the resin component when being brought close to the sintered body by applying temperature.
　また、半導体素子１１は、半導体装置１０ａの薄型化のために薄く仕上がっていることが望ましい。具体的には、３００μｍ以下の厚み、好ましくは１５０μｍ以下の厚み、より好ましくは１００μｍ以下の厚みである。ここでは、接続部１２として２０μｍ高さの銅ポストを電解めっきにより設けた５０μｍ厚みの半導体素子１１を、第１絶縁層１３上に設置し、第１絶縁層１３のキュア処理にて接着を行った。 Further, it is desirable that the semiconductor element 11 is thinly finished in order to reduce the thickness of the semiconductor device 10a. Specifically, the thickness is 300 μm or less, preferably 150 μm or less, and more preferably 100 μm or less. Here, a semiconductor element 11 having a thickness of 50 μm provided with a copper post having a height of 20 μm as a connection portion 12 by electrolytic plating is placed on the first insulating layer 13 and bonded by a curing process of the first insulating layer 13. It was.
　次いで、補強材１４を積層し、さらにその上に第１絶縁層１３を積層する。補強材１４の材料としては、金属材料、セラミック、ガラス、シリコン、プリント基板、ガラスクロス等による織布や不織布を用いることができる。金属材料としては、銅、ニッケル、コバルト、鉄、ステンレス、アルミニウム、モリブデン、マンガンを主とする材料や合金を用いることができる。補強材が導電性を有する場合は、第１配線や第２配線と接続して、電源やグランド回路としても良い。また、補強材自体に配線が設けられていても構わない。補強材１４の接着は、半導体素子１１と同様に、第１絶縁層１３を硬化させる前などで所望の接着機能が存在していれば、そのまま接着を実施すれば良く、特にない場合や不安定である場合は、液状やシート状の接着剤を用いても良い。また、補強材１４の材料自体に接着性がある場合は、そのまま使用しても構わない。 Next, the reinforcing material 14 is laminated, and the first insulating layer 13 is further laminated thereon. As a material of the reinforcing material 14, a woven fabric or a non-woven fabric made of a metal material, ceramic, glass, silicon, a printed board, glass cloth, or the like can be used. As the metal material, materials or alloys mainly containing copper, nickel, cobalt, iron, stainless steel, aluminum, molybdenum, and manganese can be used. When the reinforcing material has conductivity, it may be connected to the first wiring or the second wiring to form a power source or a ground circuit. Further, the reinforcing material itself may be provided with wiring. As in the case of the semiconductor element 11, the reinforcing material 14 may be bonded as long as a desired bonding function exists before the first insulating layer 13 is cured. In this case, a liquid or sheet adhesive may be used. Moreover, when the material itself of the reinforcing material 14 has adhesiveness, it may be used as it is.
　第１絶縁層１３の積層は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。第１絶縁層１３の形成は、液状の有機材料であれば、スピンコート法、カーテンコート法、ダイコート法、スプレー法、印刷法等により形成される。また、フィルム状の有機材料の場合は、ラミネート法、プレス法やそれぞれに真空状態を付加した製法等により形成される。 The lamination of the first insulating layer 13 is made of, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), polynorbornene resin, or the like. . In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The first insulating layer 13 is formed by a spin coating method, a curtain coating method, a die coating method, a spray method, a printing method, or the like if it is a liquid organic material. Further, in the case of a film-like organic material, it is formed by a laminating method, a pressing method, a manufacturing method in which a vacuum state is added to each, or the like.
　ここでは、補強材１４としてガラスクロスにエポキシ樹脂を含浸した５０μｍ厚みのプリプレグ材を用い、真空ラミネータにより積層を行った。また、第１絶縁層１３は、２０μｍ厚みの低弾性率のシート状エポキシ樹脂を用いて、真空ラミネータにより積層を実施し、先のプリプレグ材と第１絶縁層１３をあわせてキュア工程の熱処理を実施した。 Here, a 50 μm-thick prepreg material in which a glass cloth was impregnated with an epoxy resin was used as the reinforcing material 14, and lamination was performed using a vacuum laminator. The first insulating layer 13 is laminated by a vacuum laminator using a sheet-like epoxy resin having a low elastic modulus with a thickness of 20 μm, and the heat treatment in the curing process is performed by combining the prepreg material and the first insulating layer 13. Carried out.
　次いで、内蔵層ビア１８と第１配線１５を形成する。内蔵層ビア１８は、開口部をレーザ、ドライエッチング法、ブラストなどにより形成し、第１配線１５の工程で形成するか、ビア開口部を電解めっき法、無電解めっき法、印刷法等により導電材料で埋めてから配線形成しても良い。さらに、内蔵層ビア１８となる部分に金属ポストをめっき法や印刷法により形成しておき、第１絶縁層１３や補強材１４を形成した後にバフ研磨、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより表面を除去し、金属ポストを露出させて内蔵層ビア１８としても構わない。また、図１２は、内蔵層ビア１８の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。また、第１配線１５と接続部１２は接続する。接続部１２は、先に記載したとおり接続部分が形成されており、第１絶縁層１３の仕上がり膜厚より厚い接続部１２の場合は、バフ研磨、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより接続部１２を第１配線１５形成前に露出させる。接続部１２が第１絶縁層１３より薄い場合は、開口部をレーザ、ドライエッチング法、ブラストなどにより形成し、第１配線１５の工程で接続する。第１配線１５は、図１０（ａ）に記載したとおりの配線技術により形成する。 Next, the built-in layer via 18 and the first wiring 15 are formed. The built-in layer via 18 has an opening formed by laser, dry etching, blasting, etc., and is formed in the process of the first wiring 15, or the via opening is made conductive by electrolytic plating, electroless plating, printing, etc. The wiring may be formed after filling with the material. Further, a metal post is formed in a portion to become the internal layer via 18 by a plating method or a printing method, and after the first insulating layer 13 and the reinforcing material 14 are formed, buff polishing, dry etching method, CMP method, grinding method, The internal layer via 18 may be formed by removing the surface by a lapping method or the like and exposing the metal post. FIG. 12 shows the opening of the built-in layer via 18 with a vertical wall, but a taper angle may be provided. Further, the first wiring 15 and the connecting portion 12 are connected. As described above, the connection portion 12 is formed with a connection portion. When the connection portion 12 is thicker than the finished film thickness of the first insulating layer 13, buffing, dry etching, CMP, grinding, lapping The connecting portion 12 is exposed before the first wiring 15 is formed by a method or the like. When the connecting portion 12 is thinner than the first insulating layer 13, the opening is formed by laser, dry etching, blasting, or the like, and connected in the process of the first wiring 15. The first wiring 15 is formed by a wiring technique as described in FIG.
　ここでは、内蔵層ビア１８はレーザにより開口を形成し、支持体の銅板から給電を行うことで開口内部を銅メッキで充填した。また、接続部１２は、先に記載した通り、３０μｍ高さの銅ポストを形成しており、第１絶縁層表面をバフ研磨により研磨することで接続点を露出させた。さらに、第１配線１５は、スパッタ膜を給電層としたセミアディティブ法を用い、膜厚１０μｍとして形成した。 Here, the built-in layer via 18 was formed with an opening by a laser, and the inside of the opening was filled with copper plating by supplying power from the copper plate of the support. Further, as described above, the connection portion 12 formed a copper post having a height of 30 μm, and the connection point was exposed by polishing the surface of the first insulating layer by buffing. Further, the first wiring 15 was formed with a film thickness of 10 μm using a semi-additive method using a sputtered film as a power feeding layer.
　次に、図１２（ｅ）に示したとおり、第２絶縁層１９と第１配線１５を形成する。第２絶縁層１９は、図１２（ｂ）に記載の方法を、ビア１７と第１配線１５の形成は、図１２（ｃ）に記載した方法を用いて行う。 Next, as shown in FIG. 12E, the second insulating layer 19 and the first wiring 15 are formed. The second insulating layer 19 is formed using the method shown in FIG. 12B, and the via 17 and the first wiring 15 are formed using the method shown in FIG.
　次に、図１３（ｆ）に示したとおり、支持体２６を除去する。支持体２６の除去方法は、ウェットエッチング法、ドライエッチング法、及び研磨法などのいずれかもしくはこれらの組み合わせにより行う。また、支持体２６内に低密着の剥離が容易な部分を設けていれば、剥離により行っても構わなく、剥離後にウェットエッチング法、ドライエッチング法、及び研磨法などのいずれかもしくはこれらの組み合わせによる処理を行っても良い。ここでは、ウェットエッチングにより銅板を除去した。その際、Ｎｉは銅板エッチング時のエッチングバリアとして使用する。最終的にはＮｉをウェットエッチングにて除去した。 Next, as shown in FIG. 13 (f), the support 26 is removed. The support 26 is removed by any one of wet etching, dry etching, polishing, or a combination thereof. Further, as long as a portion with low adhesion and easy peeling can be provided in the support 26, it may be performed by peeling. After the peeling, any one of wet etching method, dry etching method, polishing method, or a combination of these may be used. You may perform the process by. Here, the copper plate was removed by wet etching. At that time, Ni is used as an etching barrier when etching the copper plate. Finally, Ni was removed by wet etching.
　次に、図１３（ｇ）に示すとおり、第２絶縁層１９を形成する。形成方法は、図１３（ｂ）に記載した方法を用い、積層後に熱処理を行って絶縁層とする。両面同時に積層しても良く、片面ずつ交互に積層しても構わない。本発明では、シート状の５０μｍ厚みのエポキシ樹脂を真空ラミネータにより両面同時に積層した。 Next, as shown in FIG. 13G, the second insulating layer 19 is formed. As the formation method, the method described in FIG. 13B is used, and heat treatment is performed after stacking to form an insulating layer. Both sides may be laminated simultaneously, or each side may be laminated alternately. In the present invention, a sheet-like epoxy resin having a thickness of 50 μm is simultaneously laminated on both sides by a vacuum laminator.
　次に、図１３（ｈ）に示すとおり、ビア１７と第１配線１５と第２配線１６を形成する。ビア１７は、感光性の有機材料を第２絶縁層１９に用いた場合は、スピンコート法、ラミネート法、プレス法、及び印刷法により形成した後、ビア１７となる開口部はフォトリソグラフィー法などにより形成される。非感光性や感光性でパターン解像度が低い有機材料を用いた場合は、ビア１７となる開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。さらに、ビア１７となる部分に金属ポストをめっき法や印刷法により形成しておき、第２絶縁層１９を形成した後に、ドライエッチング法、ＣＭＰ法、研削法、ラップ法などにより第２絶縁層１９の表面を除去し、金属ポストを露出させることでビア１７とする方法を用いても構わない。また、図１３は、ビア１７の開口部を垂直な壁で示しているが、テーパ角を付けても構わない。 Next, as shown in FIG. 13H, the via 17, the first wiring 15, and the second wiring 16 are formed. When a photosensitive organic material is used for the second insulating layer 19, the via 17 is formed by a spin coating method, a laminating method, a pressing method, and a printing method, and then an opening that becomes the via 17 has a photolithography method or the like. It is formed by. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening serving as the via 17 is formed by laser, dry etching, blasting, or the like. Further, a metal post is formed on the portion to be the via 17 by a plating method or a printing method, and after the second insulating layer 19 is formed, the second insulating layer is formed by a dry etching method, a CMP method, a grinding method, a lapping method, or the like. Alternatively, the via 19 may be used by removing the surface 19 and exposing the metal post. FIG. 13 shows the opening of the via 17 as a vertical wall, but a taper angle may be provided.
　次に、図１３（ｉ）に示すとおり、最表面にソルダーレジスト２２を形成する。ソルダーレジスト２２は、第１電極２０と第２電極２１となる部分を開口して形成する。ソルダーレジスト２２の開口を第１電極２０や第２電極２１より大きくした場合は、第１電極２０や第２電極２１の側壁部分のハンダ材料も接続面とすることができ、接続信頼性を高めることができる。また、改めて電極を設ける構造では、ソルダーレジスト２２も応力緩和に用いることができるため、更なる信頼性の向上が実現出来る。 Next, as shown in FIG. 13I, a solder resist 22 is formed on the outermost surface. The solder resist 22 is formed by opening portions that become the first electrode 20 and the second electrode 21. When the opening of the solder resist 22 is made larger than the first electrode 20 and the second electrode 21, the solder material on the side wall portions of the first electrode 20 and the second electrode 21 can also be used as a connection surface, thereby improving connection reliability. be able to. Further, in the structure in which the electrodes are newly provided, the solder resist 22 can also be used for stress relaxation, so that further improvement in reliability can be realized.
　第１電極２０や第２電極２１は、例えば複数の層が積層されたものであり、例えば、第１電極２０や第２電極２１の表面に形成されるハンダボールの濡れ性やボンディングワイヤーとの接続性を考慮して、第１電極２０や第２電極２１の表面は、銅、アルミニウム、金、銀及びハンダ材料からなる群から選択された少なくとも一種の金属及び合金が設けられる。第１電極２０や第２電極２１は、接続に対して効果のある構造を適宜選択すれば良く、必ずしも同じ構造とする必要はない。 For example, the first electrode 20 and the second electrode 21 are formed by laminating a plurality of layers. For example, the wettability of solder balls formed on the surfaces of the first electrode 20 and the second electrode 21 and bonding wires In consideration of connectivity, the surfaces of the first electrode 20 and the second electrode 21 are provided with at least one metal and alloy selected from the group consisting of copper, aluminum, gold, silver, and solder materials. The first electrode 20 and the second electrode 21 may be appropriately selected from structures having an effect on connection, and are not necessarily the same structure.
　ソルダーレジスト２２は、例えば有機材料で形成されており、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ＰＢＯ（Ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）及びポリノルボルネン樹脂等で形成されている。特に、ポリイミド樹脂及びＰＢＯは、膜強度、引張弾性率及び破断伸び率等の機械的特性が優れているため、高い信頼性を得ることができる。有機材料は、感光性、非感光性のいずれを用いても構わない。感光性の有機材料を用いた場合、フォトリソグラフィー法などにより開口部を形成する。非感光性や感光性でパターン解像度が低い有機材料を用いた場合、開口部はレーザ、ドライエッチング法、ブラストなどにより形成される。 The solder resist 22 is formed of, for example, an organic material. For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like. It is formed with. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The organic material may be either photosensitive or non-photosensitive. In the case where a photosensitive organic material is used, the opening is formed by a photolithography method or the like. When an organic material that is non-photosensitive or photosensitive and has a low pattern resolution is used, the opening is formed by laser, dry etching, blasting, or the like.
　第１電極２０や第２電極２１は、図１３に示した構造としても良く、ソルダーレジスト２２の開口が第１電極２０や第２電極２１電極より大きくなる逃げと呼ばれる構造としても良く、さらには、ソルダーレジスト上に電極を改めて作製する構造としても良い。図１３に示す構造では、ハンダ材料を用いて接続する場合に、第１電極２０や第２電極２１のみにハンダが供給される様にソルダーレジスト２２にて開口を制限している。このソルダーレジスト２２による制限により、ハンダの流れ量が制限されるため、半導体装置を実装基板や別部品と接続する際の取り付け高さを安定化させることが実現出来る。ここでは、感光性のソルダーレジスト２２を用いて開口部を形成した後に、第１電極２０や第２電極２１として無電解めっきにて、Ａｕ層が表面となる様にＣｕ層上にＮｉ層と金層を順に積層させた。Ｎｉ層の厚さは３μｍ、Ａｕ層の厚さは１μｍである。 The first electrode 20 and the second electrode 21 may have the structure shown in FIG. 13, or may have a structure called escape where the opening of the solder resist 22 is larger than the first electrode 20 and the second electrode 21, Alternatively, a structure in which an electrode is newly formed on a solder resist may be used. In the structure shown in FIG. 13, when connecting using a solder material, the opening is limited by the solder resist 22 so that the solder is supplied only to the first electrode 20 and the second electrode 21. The solder resist 22 limits the amount of solder flow, so that it is possible to stabilize the mounting height when the semiconductor device is connected to a mounting board or another component. Here, after the opening is formed using the photosensitive solder resist 22, the Ni layer is formed on the Cu layer so that the Au layer becomes the surface by electroless plating as the first electrode 20 and the second electrode 21. Gold layers were laminated in order. The thickness of the Ni layer is 3 μm, and the thickness of the Au layer is 1 μm.
　実施例１０による半導体装置の製造方法によれば、実施例３による半導体装置と第１絶縁層１３と第２絶縁層１９の割合を変化させることで実施例４による半導体装置を効率よく形成することができる。補強材１４を取り付けなければ実施例２による半導体装置の効果を追加することができる。また、電子部品を搭載することや半導体装置の積層を行うことで、実施例５による半導体装置や実施例６による半導体装置を効率よく形成することができる。さらに、図１２、１３は個片の部分断面図として示しているが、複数の半導体装置が一度に作製され、ダイシングや裁断により個片化される工程を行っても良い。さらにまた、図１２（ａ）から（ｅ）までは、支持体の両面に半導体装置を形成して生産性を高めることを行っても良い。 According to the method of manufacturing a semiconductor device according to the tenth embodiment, the semiconductor device according to the fourth embodiment can be efficiently formed by changing the ratio of the semiconductor device according to the third embodiment and the first insulating layer 13 and the second insulating layer 19. Can do. If the reinforcing member 14 is not attached, the effect of the semiconductor device according to the second embodiment can be added. In addition, by mounting electronic components or stacking semiconductor devices, the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment can be efficiently formed. Furthermore, although FIGS. 12 and 13 are shown as partial sectional views of individual pieces, a process in which a plurality of semiconductor devices are manufactured at once and separated into individual pieces by dicing or cutting may be performed. Furthermore, in FIGS. 12A to 12E, semiconductor devices may be formed on both sides of the support to increase productivity.
　次に、実施例１０の変形例である実施例１１による半導体装置の製造方法について説明する。図１４は実施例１１による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。実施例１１は実施例１０とは、第２絶縁層１９を支持体２６除去前に形成する点が異なっている。以下に、実施例１０と異なる部分について説明を行う。特に記載のない部分については、実施例１０と同じである。 Next, a method for manufacturing a semiconductor device according to Example 11, which is a modification of Example 10, will be described. FIG. 14 is a manufacturing process diagram illustrating a method of manufacturing a semiconductor device according to Example 11. In each step, cleaning or heat treatment may be performed as appropriate. Example 11 is different from Example 10 in that the second insulating layer 19 is formed before the support 26 is removed. Hereinafter, parts different from the tenth embodiment will be described. Portions not specifically described are the same as those in the tenth embodiment.
　まず、図１４（ａ）は、図１２（ｅ）と同じ状態であり、図１２（ｅ）までは実施例１０と同じ内容にて形成する。次いで、図１４（ｂ）に示すとおり、第２絶縁層１９を積層する。次いで、図１４（ｃ）に示すとおり、支持体２６を除去する。次いで、図１４（ｄ）に示すとおり、第２絶縁層１９に第２配線１６が埋設されている面に第２絶縁層１９を積層する。この後は、図１３（ｈ）以降の工程を進めることとなる。 First, FIG. 14A is in the same state as FIG. 12E, and up to FIG. 12E is formed with the same content as in the tenth embodiment. Next, as shown in FIG. 14B, the second insulating layer 19 is laminated. Next, as shown in FIG. 14C, the support 26 is removed. Next, as shown in FIG. 14D, the second insulating layer 19 is laminated on the surface where the second wiring 16 is embedded in the second insulating layer 19. Thereafter, the processes after FIG.
　実施例１１による半導体装置の製造方法によれば、実施例１０と同じ効果に加えて、先に第２絶縁層１９を形成することにより、第１配線１５が支持体２６の除去工程でダメージを受けることが無くなり、不良発生率を少なくすることができる。また、支持体２６を除去した後の剛性が実施例１０より高くなるため、ハンドリング性を改善することができる。 According to the method for manufacturing a semiconductor device according to the eleventh embodiment, in addition to the same effect as that of the tenth embodiment, the first insulating layer 19 is formed first, so that the first wiring 15 is damaged in the removal process of the support 26. The occurrence rate of defects can be reduced. Moreover, since the rigidity after removing the support body 26 is higher than that of the tenth embodiment, the handling property can be improved.
　次に、実施例１０の第２の変形例である実施例１２による半導体装置の製造方法について説明する。図１５、１６は実施例１２による半導体装置の製造方法を示す製造工程図である。なお、各工程においては適宜洗浄や熱処理を行っても構わない。実施例１０とは、支持体２６上に第２絶縁層１９を形成する点と、第１配線１５を覆う様に第２絶縁層１９を形成してから支持体２６除去する点が異なっている。以下に、実施例１０と異なる部分について説明を行う。特に記載のない部分については、実施例１０の製造方法と同じである。 Next, a method for manufacturing a semiconductor device according to Example 12, which is a second modification of Example 10, will be described. 15 and 16 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the twelfth embodiment. In each step, cleaning or heat treatment may be performed as appropriate. The difference from Example 10 is that the second insulating layer 19 is formed on the support 26 and that the support 26 is removed after the second insulating layer 19 is formed so as to cover the first wiring 15. . Hereinafter, parts different from the tenth embodiment will be described. Portions not specifically described are the same as in the manufacturing method of Example 10.
　まず、図１５（ａ）に示すとおり、支持体２６上に第２絶縁層１９を形成する。また、第２絶縁層１９上に第１配線１５を形成する。次いで、図１５（ｂ）に示すとおり、第２配線１６を覆う様に第２絶縁層１９を形成する。次いで、図１５（ｃ）に示すとおり、第２絶縁層１９にビア１７と第２配線１６を形成する。次いで、図１５（ｄ）に示すとおり、第２配線１６を覆う様に第１絶縁層１３を形成し、半導体素子１１を設置する。さらに、補強材１４を形成し、第１絶縁層１３を覆う様に形成した後、内蔵層ビア１８と第１配線１５を形成する。第１配線１５と接続部１２は接続されている。 First, as shown in FIG. 15A, the second insulating layer 19 is formed on the support 26. In addition, the first wiring 15 is formed on the second insulating layer 19. Next, as shown in FIG. 15B, a second insulating layer 19 is formed so as to cover the second wiring 16. Next, as shown in FIG. 15C, vias 17 and second wirings 16 are formed in the second insulating layer 19. Next, as shown in FIG. 15D, the first insulating layer 13 is formed so as to cover the second wiring 16, and the semiconductor element 11 is installed. Further, after forming the reinforcing material 14 so as to cover the first insulating layer 13, the built-in layer via 18 and the first wiring 15 are formed. The 1st wiring 15 and the connection part 12 are connected.
　次いで、図１６（ｅ）に示すとおり、第２絶縁層１９を第１配線１５を覆う様に形成した後に、ビア１７と第１配線１５を形成する。次いで、図１６（ｆ）に示すとおり、第１配線１５を覆う様に第２絶縁層１９を形成する。次いで、図１６（ｇ）に示すとおり、支持体２６を除去する。この後は、実施例１０と同様に図１３（ｈ）以降の工程を進めることとなる。 Next, as shown in FIG. 16E, the second insulating layer 19 is formed so as to cover the first wiring 15, and then the via 17 and the first wiring 15 are formed. Next, as illustrated in FIG. 16F, the second insulating layer 19 is formed so as to cover the first wiring 15. Next, the support 26 is removed as shown in FIG. Thereafter, similarly to the tenth embodiment, the processes after FIG.
　上記実施例１２による半導体装置の製造方法によれば、実施例１０と同じ効果に加えて、支持体除去より先に両側の第２絶縁層１９を形成することにより、第１配線１５と第２配線１６が支持体２６の除去工程でダメージを受けることが無くなり、不良発生率を実施例１１より少なくすることができる。また、支持体２６を除去した後の剛性が実施例７～１１より高くなるため、実施例７～１１よりハンドリング性を改善することができる。 According to the manufacturing method of the semiconductor device according to the twelfth embodiment, in addition to the same effect as the tenth embodiment, the first wiring 15 and the second wiring 15 are formed by forming the second insulating layers 19 on both sides before removing the support. The wiring 16 is not damaged in the step of removing the support 26, and the defect occurrence rate can be reduced as compared with the eleventh embodiment. In addition, since the rigidity after removing the support 26 is higher than those in Examples 7 to 11, handling properties can be improved as compared with Examples 7 to 11.
　以上、実施例について説明したが、本発明は上記実施例の構成にのみ制限されるものでなく、本発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。 Although the embodiments have been described above, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is.
１０ａ～１０ｆ：半導体装置
１１：半導体素子
１２、２４、２５：接続部
１３：第１絶縁層
１４：補強材
１５：第１配線
１６：第２配線
１７：ビア
１８：内蔵層ビア
１９：第２絶縁層
２０：第１電極
２１：第２電極
２２：ソルダーレジスト
２３：電子部品
２６：支持体 10a to 10f: Semiconductor device 11: Semiconductor elements 12, 24, 25: Connection portion 13: First insulating layer 14: Reinforcing material 15: First wiring 16: Second wiring 17: Via 18: Built-in layer via 19: Second Insulating layer 20: first electrode 21: second electrode 22: solder resist 23: electronic component 26: support

Claims (21)

  1. 　半導体素子と、
    　前記半導体素子の表裏両面を覆う第１絶縁層と、
    　前記第１絶縁層の表裏両面を覆う第２絶縁層と、
    　前記第２絶縁層の表裏両面の表面に設けられた複数の電極と、
    　前記表裏の第１絶縁層と第２絶縁層との間に設けられた複数の配線層と、
    を含み、
    　前記第１絶縁層の室温における弾性率が前記第２絶縁層の弾性率より小さいことを特徴とする半導体装置。     A semiconductor element;
    A first insulating layer covering both front and back surfaces of the semiconductor element;
    A second insulating layer covering both front and back surfaces of the first insulating layer;
    A plurality of electrodes provided on the front and back surfaces of the second insulating layer;
    A plurality of wiring layers provided between the first and second first and second insulating layers;
    Including
    A semiconductor device, wherein the elastic modulus of the first insulating layer at room temperature is smaller than the elastic modulus of the second insulating layer.
  2. 　前記半導体素子は表面に接続部を備え、
    　前記第１絶縁層、第２絶縁層にはそれぞれビアが設けられ、
    　前記複数の電極は、それぞれ前記ビア及び／又は前記配線層を介して前記半導体素子の接続部及び／又は他の前記電極に接続されていることを特徴とする請求項１記載の半導体装置。     The semiconductor element includes a connection portion on a surface,
    Vias are provided in the first insulating layer and the second insulating layer,
    2. The semiconductor device according to claim 1, wherein the plurality of electrodes are connected to a connection portion of the semiconductor element and / or another electrode through the via and / or the wiring layer, respectively.
  3. 　前記第１絶縁層の中に補強材が設けられ前記補強材の表裏が前記第１絶縁層で覆われていることを特徴とする請求項１又は２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a reinforcing material is provided in the first insulating layer, and front and back surfaces of the reinforcing material are covered with the first insulating layer.
  4. 　前記補強材の室温における弾性率が前記第２絶縁層の弾性率以上であることを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein an elastic modulus of the reinforcing material at room temperature is equal to or higher than an elastic modulus of the second insulating layer.
  5. 　前記裏面の第１絶縁層と第２絶縁層との間に設けられた配線層が前記裏面の第１絶縁層に埋設されていることを特徴とする請求項１乃至４いずれか１項記載の半導体装置。 The wiring layer provided between the 1st insulating layer and the 2nd insulating layer of the said back surface is embed | buried under the 1st insulating layer of the said back surface, The Claim 1 thru | or 4 characterized by the above-mentioned. Semiconductor device.
  6. 　前記半導体素子の接続部に、ハンダ材料及び樹脂成分が含まれていないことを特徴とする請求項２記載の半導体装置。 3. A semiconductor device according to claim 2, wherein a solder material and a resin component are not included in the connection portion of the semiconductor element.
  7. 　前記第１絶縁層の室温における引っ張り弾性率が１．０ＭＰａ以上１．０ＧＰａ未満であり、破断伸び率が３０％以上であることを特徴とする請求項１乃至６いずれか１項記載の半導体装置。 7. The semiconductor device according to claim 1, wherein the first insulating layer has a tensile modulus at room temperature of 1.0 MPa or more and less than 1.0 GPa and an elongation at break of 30% or more. .
  8. 　前記第１絶縁層が前記半導体装置の側面の少なくとも一部で露出していることを特徴とする請求項１乃至７いずれか１項記載の半導体装置。 8. The semiconductor device according to claim 1, wherein the first insulating layer is exposed on at least a part of a side surface of the semiconductor device.
  9. 　前記補強材又は前記第１絶縁層が前記半導体装置の側面の少なくとも一部で露出していることを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the reinforcing material or the first insulating layer is exposed on at least a part of a side surface of the semiconductor device.
  10. 　前記接続部の径が前記ビアの径より小さいことを特徴とする請求項２記載の半導体装置。 3. The semiconductor device according to claim 2, wherein a diameter of the connection portion is smaller than a diameter of the via.
  11. 　前記第２絶縁層の表裏両面の表面に設けられた複数の電極の表面が露出するように前記第２絶縁層の表面に設けられたソルダーレジスタを有することを特徴とする請求項１乃至１０いずれか１項記載の半導体装置。 The solder resistor provided on the surface of the second insulating layer so that the surfaces of the plurality of electrodes provided on the front and back surfaces of the second insulating layer are exposed. A semiconductor device according to claim 1.
  12. 　前記半導体素子に加えて電子部品がさらに搭載されていることを特徴とする請求項１乃至１１いずれか１項記載の半導体装置。 12. The semiconductor device according to claim 1, wherein an electronic component is further mounted in addition to the semiconductor element.
  13. 　請求項１乃至１２いずれか１項記載の半導体装置が積層されたことを特徴とする半導体装置。 13. A semiconductor device, wherein the semiconductor device according to claim 1 is stacked.
  14. 　支持体上に配線層を形成する工程と、
    　前記配線層を覆い前記配線層が中に埋設されるように第１絶縁層を形成する工程と、
    　前記第１絶縁層上に半導体素子を載置する工程と、
    　前記半導体素子と前記支持体を覆う様に再度第１絶縁層を形成する工程と、
    　前記第１絶縁層上に配線層を形成する工程と、
    　前記支持体を除去し、前記第１絶縁層の表裏両面に第２絶縁層を設ける工程と、
    　表裏両面の第２絶縁層の表面に配線層と電極とを形成する工程と、
    を含むことを特徴とする半導体装置の製造方法。     Forming a wiring layer on the support;
    Forming a first insulating layer so as to cover the wiring layer and to be embedded in the wiring layer;
    Placing a semiconductor element on the first insulating layer;
    Forming a first insulating layer again so as to cover the semiconductor element and the support;
    Forming a wiring layer on the first insulating layer;
    Removing the support and providing a second insulating layer on both front and back surfaces of the first insulating layer;
    Forming a wiring layer and an electrode on the surface of the second insulating layer on both the front and back surfaces;
    A method for manufacturing a semiconductor device, comprising:
  15. 　支持体の上に第２絶縁層を形成する工程と、
    　前記第２絶縁層の上に配線層を形成する工程と、
    　前記配線層を覆い前記配線層が中に埋設されるように第１絶縁層を形成する工程と、
    　前記第１絶縁層上に半導体素子を載置する工程と、
    　前記半導体素子と前記支持体を覆う様に再度第１絶縁層を形成する工程と、
    　前記第１絶縁層上に配線層を形成する工程と、
    　前記支持体を除去し、前記第１絶縁層の少なくとも表面に第２絶縁層を形成する工程と、
    　表裏両面の第２絶縁層の表面に配線層と電極とを形成する工程と、
    を含むことを特徴とする半導体装置の製造方法。     Forming a second insulating layer on the support;
    Forming a wiring layer on the second insulating layer;
    Forming a first insulating layer so as to cover the wiring layer and to be embedded in the wiring layer;
    Placing a semiconductor element on the first insulating layer;
    Forming a first insulating layer again so as to cover the semiconductor element and the support;
    Forming a wiring layer on the first insulating layer;
    Removing the support and forming a second insulating layer on at least the surface of the first insulating layer;
    Forming a wiring layer and an electrode on the surface of the second insulating layer on both the front and back surfaces;
    A method for manufacturing a semiconductor device, comprising:
  16. 　前記支持体の上に第２絶縁層を形成する工程が、配線層を形成する工程と、前記配線層を覆う第２絶縁層を形成する工程と、を含むことを特徴とする請求項１５記載の半導体装置の製造方法。 16. The step of forming a second insulating layer on the support includes a step of forming a wiring layer and a step of forming a second insulating layer that covers the wiring layer. Semiconductor device manufacturing method.
  17. 　前記第１絶縁層の少なくとも表面に第２絶縁層を形成する工程が、前記支持体を除去した後、前記支持体が除去された後の裏面にも第２絶縁層を形成する工程を含むことを特徴とする請求項１５又は１６記載の半導体装置の製造方法。 The step of forming the second insulating layer on at least the surface of the first insulating layer includes the step of forming the second insulating layer on the back surface after the support is removed after the support is removed. The method of manufacturing a semiconductor device according to claim 15 or 16.
  18. 　前記半導体素子は表面に接続部を備え、
    　前記第１絶縁層上に配線層を形成する工程が、前記半導体素子の接続部を形成する配線層に接続する工程と、前記第１絶縁層に埋設された配線層と接続するビアを形成する工程と、を含むことを特徴とする請求項１４乃至１７いずれか１項記載の半導体装置の製造方法。     The semiconductor element includes a connection portion on a surface,
    The step of forming a wiring layer on the first insulating layer includes a step of connecting to the wiring layer forming the connection portion of the semiconductor element, and a via connecting to the wiring layer embedded in the first insulating layer. 18. The method for manufacturing a semiconductor device according to claim 14, further comprising a step.
  19. 　前記第１絶縁層上に半導体素子を載置する工程が、前記第１絶縁層上の前記半導体素子周辺に補強材を載置する工程を含むことを特徴とする請求項１４乃至１８いずれか１項記載の半導体装置の製造方法。 19. The step of placing a semiconductor element on the first insulating layer includes a step of placing a reinforcing material around the semiconductor element on the first insulating layer. A method for manufacturing a semiconductor device according to item.
  20. 　前記表裏両面の第２絶縁層の表面に配線層と電極とを設ける工程において、前記電極の表面が露出するように前記第２絶縁層の表面にソルダーレジスタを形成する工程を含むことを特徴とする請求項１４乃至１９いずれか１項記載の半導体装置の製造方法。 The step of providing a wiring layer and an electrode on the surface of the second insulating layer on both the front and back surfaces includes a step of forming a solder resistor on the surface of the second insulating layer so that the surface of the electrode is exposed. The method for manufacturing a semiconductor device according to claim 14.
  21. 　前記請求項１４乃至２０いずれか１項によって製造した半導体装置を複数積層する工程をさらに含むことを特徴とする半導体装置の製造方法。 21. A method of manufacturing a semiconductor device, further comprising a step of stacking a plurality of semiconductor devices manufactured according to any one of claims 14 to 20.
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