WO2010101163A1 - 機能素子内蔵基板及びそれを用いた電子デバイス - Google Patents

機能素子内蔵基板及びそれを用いた電子デバイス Download PDF

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Publication number
WO2010101163A1
WO2010101163A1 PCT/JP2010/053382 JP2010053382W WO2010101163A1 WO 2010101163 A1 WO2010101163 A1 WO 2010101163A1 JP 2010053382 W JP2010053382 W JP 2010053382W WO 2010101163 A1 WO2010101163 A1 WO 2010101163A1
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Prior art keywords
functional element
substrate
insulating layer
wiring
layer
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PCT/JP2010/053382
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English (en)
French (fr)
Inventor
山道　新太郎
大輔 大島
菊池　克
森　健太郎
中島　嘉樹
秀哉 村井
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日本電気株式会社
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Priority to JP2011502769A priority Critical patent/JPWO2010101163A1/ja
Publication of WO2010101163A1 publication Critical patent/WO2010101163A1/ja

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the present invention relates to a functional element-embedded substrate having a functional element and an electronic device using the same.
  • the wire bonding connection can be packaged at low cost when the number of pads of the semiconductor element is small. However, it is necessary to reduce the wire diameter as the pitch of the pads of the semiconductor element is narrowed, and the yield reduction in the assembly process such as wire breakage is a problem.
  • Flip chip connection has an advantage that high-speed signal transmission between a semiconductor element and a wiring board is possible compared to wire bonding connection.
  • the connection strength of the solder bumps is weakened, and defects such as the occurrence of cracks at the connection locations frequently occur.
  • Patent Document 1 a package technology in which a functional element such as a semiconductor element is incorporated, that is, a so-called functional element incorporation technology has been proposed (for example, Patent Document 1).
  • This technology realizes higher integration and higher functionality of functional elements such as semiconductor devices, and high-density mounting that realizes thinner packages, lower costs, high frequency compatibility, low stress connection, improved electromigration characteristics, etc. Expected as a technology.
  • a bump is formed on a circuit surface of a semiconductor element to be electrically connected to a semiconductor element built in the insulating substrate, and a first wiring formed on the insulating substrate via the bump.
  • the structure which electrically connects with is disclosed.
  • a second wiring is formed on the back surface of the insulating substrate, and the first wiring and the second wiring are connected to the side of the semiconductor element by a conductive post penetrating the insulating resin substrate.
  • the substrate with a built-in functional element according to an embodiment of the present invention, A functional element; An insulating layer in which the functional element is embedded; A wiring layer disposed on two main surfaces of the insulating layer; In the insulating layer, on the side of the functional element, and having an insulating layer through via for connecting between the wiring layers disposed on the two main surfaces,
  • the functional element has a through-substrate via that penetrates the substrate of the functional element, and at least part of the electrical connection between the wiring layers disposed on the two main surfaces is via the through-substrate via. This is a functional element-embedded substrate.
  • FIG. 3 is a schematic cross-sectional view illustrating an example of a structure of a functional element built-in substrate according to the first embodiment.
  • FIG. 6 is a schematic cross-sectional view illustrating an example of a structure of a functional element built-in substrate according to a second embodiment.
  • A)-(e) Process sectional drawing explaining the manufacture example of the functional element built-in board
  • FIG. FIG. 6 is a schematic cross-sectional view showing an example of the structure of a functional element built-in substrate according to Embodiment 3.
  • FIG. 10 is a schematic cross-sectional view showing an example of the structure of a functional element-embedded substrate according to Embodiment 4.
  • FIG. FIG. 6 is a schematic cross-sectional view showing an example of the structure of an electronic device according to a fifth embodiment.
  • 10 is a schematic cross-sectional view showing an example of the structure of an electronic device according to Embodiment 6.
  • FIG. (A)-(e) Process sectional drawing explaining the manufacture example of the functional element built-in board
  • FIG. 10 is a schematic cross-sectional view showing an example of the structure of a functional element-embedded substrate according to Embodiment 9.
  • a technique for reducing the mounting area of an electronic device is known.
  • the entire wiring system is classified into three as shown in FIG.
  • a group A shows a wiring system from the LSI 1001 which is a functional element to the upper package 1003 and a wiring system to a mounting board (not shown) under the functional element built-in substrate 1002, and a group B shows the LSI 1001 and the mounting board.
  • the wiring system C is a wiring system between the upper package 1003 and the mounting substrate.
  • Wiring layers are formed on both main surfaces of the functional element built-in substrate 1002, and are connected to the upper package 1003 by external terminals 1005 such as a ball grid array (hereinafter referred to as BGA). .
  • BGA ball grid array
  • the functional element built-in substrate 1002 and the mounting substrate are connected by an external terminal 1004 such as a BGA.
  • the wiring system of the group B is performed via a DSV (not shown) provided on the side of the LSI 1001. DSV is also required for Group A and Group C.
  • the LSI 1001 becomes multifunctional and the number of external terminals increases (multiple pins), the number of wires in the B group also increases, and the number of DSVs for guiding the B group wiring system to the lower side must be increased.
  • the number of DSVs formed on the functional element built-in substrate 1002 increases. Increasing the area of the functional element-embedded substrate 1002 can meet this requirement, but increases the mounting area. Therefore, in order to increase the number of DSVs without increasing the mounting area, the DSVs must be arranged at a high density.
  • the wiring system of the group B can be dropped directly to the mounting board side.
  • the A group also needs to be connected via the DSV. Therefore, when the number of pins of the LSI 1001 increases and the number of components mounted as the upper package 1003 increases, Similarly, it is necessary to increase the density of the DSV.
  • Such difficulty in securing the wiring system is not limited to the PoP shape, and may also occur when the built-in LSI has a large number of pins or a plurality of functional elements.
  • the present invention provides a highly reliable functional element-embedded substrate and an electronic device including the functional element-embedded substrate that suppresses an increase in mounting area.
  • FIG. 1 is a schematic cross-sectional view of a main part of a functional element-embedded substrate 100 according to Embodiment 1 of the present invention.
  • the functional element-embedded substrate 100 according to the first embodiment is provided on two main surfaces (an upper surface and a back surface) of a functional element 101 such as a semiconductor element typified by an LSI, an insulating layer 102 in which the functional element 101 is embedded, and the insulating layer 102.
  • a first wiring layer 103 and a second wiring layer 108 are provided.
  • the functional element 101 one or a plurality of element through vias 106 including vias penetrating the substrate constituting the functional element are formed.
  • the through-element via 106 is formed with a conductive material and can conduct from the upper surface to the lower surface of the functional element 101.
  • An insulating layer through via 107 is provided in the insulating layer 102 and connects the first wiring layer 103 and the second wiring layer 108.
  • an electronic circuit (not shown) and a pad (not shown) are formed on the upper surface (upward surface shown in the figure) of the functional element 101, and an adhesive layer 105 is formed on the lower surface of the functional element.
  • the element through via 106 also penetrates the adhesive layer 105.
  • a connection portion 104 to the first wiring layer 103 is formed on the upper surface of the functional element 101, and the first wiring layer 103 and the second wiring layer 108 are connected via an element through via 106 formed in the functional element 101. Are also electrically connected.
  • the through-element via 106 may be composed of a single member or a plurality of members.
  • a combination of a through-substrate via that penetrates the substrate constituting the functional element and a post electrode that penetrates a protective layer that protects the semiconductor substrate may be used.
  • the wiring path may be configured by connecting the wiring circuit on the functional element and the through-substrate via.
  • Such a through-substrate via is preferably formed before the functional element is formed.
  • a via hole may be formed after the functional element is formed, and the via hole may be filled with a conductive material.
  • the portion penetrating the substrate is a through-substrate via.
  • the material of the element through via 106 may be any material as long as it has conductivity, but a metal such as Cu or Al, an alloy thereof, or conductive metal oxidation. Or a filler (conductive paste) to which conductive fine particles are added, or a conductive polymer in which the polymer itself is conductive.
  • via holes are formed after the functional elements are formed, and through-element vias are formed by filling with a conductive paste.
  • a copper post was formed in a portion penetrating the adhesive layer 105.
  • the functional element for forming the through-element via it is preferable to select a functional element having a relatively large area among the functional elements.
  • a semiconductor element such as an LSI has a relatively large chip size and is suitable for forming a through-via.
  • an element through via is not provided in an element that affects the function of the element by providing a current path in the substrate such as a coil component.
  • the substrate of the functional element is, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), gallium nitride (GaN), silicon carbide (SiC) to form a semiconductor element.
  • a semiconductor substrate such as zinc oxide (ZnO) can be used. Further, II-VI group compounds, III-V group compounds, diamond, etc. exhibiting semiconductor characteristics may be used.
  • an inorganic substrate such as a silica substrate or a sapphire substrate, or an insulating substrate such as an organic resin may be used. Further, a combination of a semiconductor material such as an SOI substrate and an insulating material may be used. Of course, it is not limited to these.
  • a semiconductor element having a silicon substrate is used as the functional element 100.
  • the number of functional elements 101 incorporated in the functional element-embedded substrate 100 is not limited to one, and a plurality of functional elements 101 can be provided.
  • a plurality of functional elements 101 may be stacked in the Y direction in FIG. 1 in addition to an aspect in which a plurality of functional elements are disposed in the X direction in FIG. Further, when a plurality of functional elements are incorporated in this way, the through-element via 106 and the through-substrate via are not necessarily provided in all the functional elements.
  • the position where the element through via 106 is disposed is not particularly limited, and may be disposed in consideration of the arrangement of the electronic circuit formed in the functional element 101 and the relationship between the first wiring layer 103 and the second wiring layer 108. Well, it is not limited to a strict arrangement.
  • the individual shape of the element through via 106 is not particularly limited, and may be, for example, a polygonal shape such as a circle or a rectangle, a shape surrounded by a curve, or a combination thereof.
  • the diameters of the element through via 106 and the substrate through via are not particularly limited, but can be, for example, about 10 ⁇ m to 100 ⁇ m.
  • the insulating layer 102 can be formed using, for example, a photosensitive or non-photosensitive organic material.
  • the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), and polynorbornene resin.
  • a material obtained by impregnating a woven fabric or a nonwoven fabric formed of glass cloth, aramid fiber, or the like with a resin selected from these resin groups may be used.
  • an epoxy resin is used as the insulating layer 102.
  • the adhesive layer 105 is preferably a semi-cured resin called a die attachment film (DAF), a resin paste such as epoxy resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or silver paste. It is. Of course, it is not limited to these. In the first embodiment, DAF mainly composed of epoxy resin is used.
  • the first wiring layer 103 and the second wiring layer 108 are, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium, or these as main components.
  • An alloy as a component or a conductive resin made of a resin containing a conductive filler is suitable, but is not limited thereto. From the viewpoint of electrical resistance value and cost, it is desirable to form with copper. In Embodiment 1, copper was used.
  • the element connection via 104 is formed by filling a via hole penetrating from the surface of the insulating layer 102 to the pad (not shown) of the functional element 101 with a conductor.
  • the element connection via 104 can be formed simultaneously with the formation of the first wiring layer 103 by forming a via hole in the insulating layer 102 with a laser, for example.
  • a device in which a metal bump or the like is previously formed on the functional element 101 can be suitably applied as the element connection via 104.
  • a via hole can be formed by a photolithography technique.
  • the element connection via 104 may be directly connected to the element through via 106.
  • a via hole is opened using a laser, and copper is filled in the via hole by plating.
  • the number of element connection vias 104 needs to be increased in the conventional functional element built-in substrate.
  • FIG. The number of element connection vias can be reduced by covering part of the wiring system of the A group and the B group described in 11 with the element through vias.
  • the insulating layer through via 107 can be formed without increasing the via density and the aspect ratio even when the number of built-in elements is increased. As a result, the mounting area of the functional element built-in substrate can be increased without increasing the mounting area of the built-in element. Further, when a functional element having the same number of terminals as that in the prior art is incorporated, the number of vias through the insulating layer can be reduced, so that the manufacturing yield can be further improved and the mounting area can be further reduced.
  • the insulating layer through via 107 is configured by a conductor disposed in a via hole penetrating from the first main surface of the insulating layer 102 to the surface of the second wiring layer 108.
  • the formation method can be the same as the element connection via 104, and is preferably formed simultaneously with the element connection via 104.
  • FIG. 1 An example in which a plurality of through-element vias 106 are connected to one wiring of the second wiring layer 108 is shown.
  • This is, for example, a wiring system that can share a ground potential or the like. Suitable for connecting.
  • through-element vias are connected to individual wirings as in the embodiments described later, this is suitable for connection to individual wiring systems such as signal potentials.
  • Such a connection method can be appropriately changed by those skilled in the art.
  • the functional element built-in substrate may be warped or swelled depending on the process of incorporating the functional element and the use environment. By providing this, it is possible to suppress these warpage and undulation and to improve the reliability. In particular, the temperature cycle test characteristics can be improved. Furthermore, since the wiring yield of the built-in substrate is improved due to the low warpage, the loss of discard of non-defective semiconductor elements due to wiring defects can be reduced, and the manufacturing cost can be reduced. Furthermore, the low warpage makes it possible to further miniaturize the wiring of the built-in substrate, and to reduce the cost by reducing the number of wiring layers.
  • the strength of the semiconductor element is not deteriorated, and the entire thickness of the semiconductor element-embedded substrate can be reduced.
  • the handling property when the semiconductor element is thinned can be improved, and the manufacturing yield can be improved.
  • the element through via 106 is disposed in the vicinity of the element peripheral portion which is the stress concentration position. Further, from the viewpoint of dispersing the partial stress concentration in the element substrate, it is preferable that the element substrate is disposed point-symmetrically or line-symmetrically in plan view. Furthermore, the element through via according to the present invention and a substrate opening that suppresses such warpage and undulation (a through hole or a recess formed in the semiconductor substrate, which may be filled with a low elasticity resin or the like). May be combined.
  • the functional element-embedded substrate 200 according to the second embodiment has the same basic configuration as that of the first embodiment except for the following points. That is, in the first embodiment, the adhesive layer 105 is provided below the functional element 101, whereas in the second embodiment, the adhesive layer 105 is not provided, and the upper and lower sides of the functional element-embedded substrate are not provided.
  • the wiring layer is different in that it is formed in multiple layers.
  • the functional element built-in substrate 200 includes a functional element 201 to be incorporated, a first insulating layer 202 in which the functional element is embedded, a first wiring layer 203 and a third wiring layer 212 above the functional element 201.
  • the fifth wiring layer 215 includes a second wiring layer 208, a fourth wiring layer 218, and a sixth wiring layer 221 below the functional element.
  • one or a plurality of through-element vias 206 are formed on the substrate of the functional element 201.
  • the through-element via 206 is formed with a conductive material and can conduct from the upper surface to the lower surface of the functional element.
  • the first insulating layer 202 is provided with a first insulating layer through via 207 to connect the first wiring layer 203 and the second wiring layer 208.
  • the first wiring layer 203 is connected to the third wiring layer 212 by a connection via 211 formed in the second insulating layer 209, and the third wiring layer 212 is connected by a connection via 214 formed in the fourth insulating layer 213.
  • the fifth wiring layer 215 is connected.
  • the second wiring layer 208 is formed in the third insulating layer 210, and the second wiring layer 208 is connected to the fourth wiring layer 218 by connection vias 217 formed in the fifth insulating layer 216.
  • the fourth wiring layer 218 is connected to the sixth wiring layer 221 by connection vias 220 formed in the seventh insulating layer 219.
  • This example shows a case where an electronic circuit (not shown) or a pad (not shown) is formed on the upper surface (upper surface shown in the figure) of the functional element 201, and a plurality of second elements are formed on the lower surface of the functional element.
  • a wiring layer 208 is provided.
  • the through-element vias 206 are connected to individual wirings of the second wiring layer 208, respectively.
  • An element connection via 204 that connects the first wiring layer 203 is formed on the upper surface of the functional element 201, and the first wiring layer 203 and the second wiring layer 208 include an element through via 206 formed in the functional element 201. It is also electrically connected via.
  • Each wiring layer and connection via can be selected from the same materials as in the first embodiment.
  • copper is used for each wiring layer and connection via.
  • the second wiring layer 208 is formed on the main surface of the support body 250. Then, the support body 250 and the second wiring layer 208 are covered with the third insulating layer 210 (see FIG. 3A).
  • the support body 250 any one of resin, metal, glass, semiconductor, ceramic, or a combination thereof can be used. Further, in order to clarify the position where the functional element 201 is mounted, a position mark (not shown) may be appropriately provided on the support body 250.
  • a copper alloy is used as the support body 250. Further, as a position mark for mounting the functional element 201, nickel having a thickness of 5 ⁇ m was provided by electroplating.
  • the second wiring layer 208 can be formed by a method such as a subtractive method, a semi-additive method, or a full additive method.
  • the subtractive method is a method in which a resist having a desired pattern is formed on a metal layer (copper foil) provided on a substrate, an unnecessary metal layer is etched, and then the resist is removed to obtain a desired pattern.
  • a power supply layer is formed by an electroless plating method, a sputtering method, a CVD method, etc., a resist having an opening in a desired pattern is formed, and a metal is deposited in the resist opening by an electrolytic plating method.
  • a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating film.
  • a desired wiring pattern is obtained by depositing metal.
  • copper is used as the second wiring layer 208 and is formed by a semi-additive method and then covered with the third insulating layer 210.
  • a suitable material for the third insulating layer 210 may be the same material as the insulating layer 102 described in the first embodiment.
  • a transfer molding method, a compression molding method, a printing method, a vacuum press method, a vacuum laminating method, a spin coating method, a die coating method, a curtain coating method, a photolithography method, or the like is applied. be able to.
  • the third insulating layer 210 is formed by vacuum lamination using an epoxy resin.
  • the functional element 201 in which the element through via 206 is formed is prepared. Then, the functional element 201 is mounted on the upper layer of the support 250 at a predetermined position so that the second wiring layer 208 and the element through via 206 are connected (see FIG. 3B).
  • a solder material such as tin may be inserted into the joint interface between the element through via 206 and the second wiring layer 208.
  • the first insulating layer 202 is formed so as to cover the third insulating layer 210 and the functional element 201 (see FIG. 3C).
  • the through-element via 206 can be provided at an arbitrary place as long as the mechanical strength of the functional element 201 is not lowered.
  • the substrate material of the functional element for example, the material described in the first embodiment can be suitably applied.
  • a silicon LSI is used as the substrate material of the functional element.
  • the functional element 201 was mounted on the support 250 using a semiconductor mounting machine in a face-up state.
  • the material described in the first embodiment can be preferably applied to the through-element via 206.
  • the element through via 206 is formed by plating after forming a via hole in the functional element 201 using copper.
  • the first insulating layer 202 is formed so as to embed the functional element 201.
  • a material of the first insulating layer 202 for example, the material of the insulating layer 102 described in the first embodiment can be preferably applied.
  • the method for incorporating the functional element 201 is as described in the first embodiment.
  • a via hole 241 penetrating from the surface of the first insulating layer 202 to the surface of the pad (not shown) of the functional element 201 is provided.
  • a via hole 242 that penetrates from the surface of the first insulating layer 202 to the surface of the second wiring layer 208 is formed (see FIG. 3D).
  • the via holes 241 and 242 are formed using a laser processing method.
  • a conductor is formed inside the via holes 241 and 242, and the first wiring layer 203 is formed on the first insulating layer 202 (see FIG. 3E).
  • the element connecting via 204 is formed by filling the via hole 241 with a conductor
  • the first insulating layer through via 207 is formed by filling the via hole 242 with the conductor.
  • Suitable examples of these conductor materials and formation methods are as described in the first embodiment.
  • the material and the method described in the second wiring layer can be suitably applied to the material and the forming method of the first wiring layer 203.
  • copper is used and the first wiring layer 203 is formed by a semi-additive method.
  • the support body 250 is removed (see FIG. 3F).
  • the removal of the support 250 is preferably a wet etching method using a chemical solution, a grinding method using mechanical polishing, a physical peeling method, or the like, but is not limited thereto.
  • the support body 250 which is a copper alloy was removed using alkaline wet etching liquid.
  • a second insulating layer 209 described below may be formed.
  • the second insulating layer 209, the connection via 211, the third wiring layer 212, the fourth insulating layer 216, the connection via 217, and the fourth wiring layer 218 are formed (see FIG. 3G).
  • Suitable materials for the second insulating layer 209 and the fourth insulating layer 216 are as described above.
  • it can form by the method similar to the 3rd insulating layer 210 mentioned above, for example.
  • the second insulating layer 209 and the fourth insulating layer 216 are formed by vacuum lamination using an epoxy resin.
  • a method of forming the connection vias 211 and 217 in the second insulating layer 209 and the fourth insulating layer 216 is not particularly limited, but the same method as the element connection via 204 and the first insulating layer through via 207 is preferably applied. can do.
  • an opening is formed using a laser processing method, and is filled with copper.
  • the third wiring layer 212 and the fourth wiring layer 218 were formed by a semi-additive method using copper.
  • a fifth insulating layer 213, a connection via 214, a fifth wiring layer 215, a sixth insulating layer 219, a connection via 220, and a sixth wiring layer 221 are formed (see FIG. 3H).
  • Suitable materials for the fifth insulating layer 213 and the sixth insulating layer 219 are as described above.
  • it can form by the method similar to the 2nd insulating layer 210 mentioned above, for example.
  • the method for forming the connection vias 214 and 220, the fifth wiring layer 215, and the sixth wiring layer 221 is the same as described above.
  • the first insulating layer penetrating via 207 penetrating only the first insulating layer 202 has been described as the insulating layer penetrating via on the side of the functional element 201.
  • the plural penetrating insulating layers are penetrated.
  • An insulating layer through via may be used.
  • a via penetrating from the fifth insulating layer 213 to the sixth insulating layer 219 may be provided so as to directly connect the fifth wiring layer 215 and the sixth wiring layer 221.
  • the functional element-embedded substrate 300 according to the third embodiment has the same basic configuration as that of the first embodiment except for the following points. That is, as shown in the schematic cross-sectional view of FIG. 4, the adhesive layer 105 is provided below the functional element 101 in the first embodiment, whereas the lower part of the functional element 301 is present in the third embodiment. Is not provided with an adhesive layer 105, and the first wiring layer 303 and the second wiring layer 308 are protected by solder resist layers 332 and 331, and an external terminal 333 connected to an external substrate (not shown) is provided. It is provided in the opening of the solder resist layer 331. In FIG. 4, reference numerals 301 to 308 correspond to reference numerals 101 to 108 in FIG.
  • FIG. 5 shows a schematic cross-sectional view of a functional element-embedded substrate 400 according to the fourth embodiment.
  • the fourth embodiment is the same as the second embodiment except that a solder resist layer 431 and an external terminal 433 are provided below the functional element-embedded substrate 200 of the second embodiment.
  • reference numerals 401 to 421 correspond to reference numerals 201 to 221 in FIG. 2, respectively.
  • solder resist layers 332, 331, and 431 By providing the solder resist layers 332, 331, and 431 in the third and fourth embodiments, the surface circuit of the functional element-embedded substrate can be protected and flame retardancy can be imparted.
  • solder resist layer a photosensitive resist ink was used.
  • the number of wiring layers and insulating layers is only an example, and it goes without saying that the required number of wiring layers and insulating layers can be stacked without being limited to the above embodiment.
  • the functional device when the wiring system of the group B shown in FIG. 11 is increased by increasing the functionality of the functional device (increasing the number of pins), the functional device is penetrated in addition to the insulating layer through via on the side of the functional device. Since it has a wiring system using through-element vias, it is possible to cope with further diversification without requiring high density and high aspect ratio of through-layer vias.
  • the electronic device 500 according to the fifth embodiment has a PoP shape by mounting an upper package 536 on a functional element-embedded substrate.
  • the structure below the second wiring layer 512 is the same as that of the fourth embodiment, and reference numerals 501 to 512, 516 to 521, 531 and 533 in FIG. 6 denote reference numerals 401 to 412 and 416 to 421 in FIG. The same meaning as 431,433 is shown.
  • the second wiring layer 512 is protected by a solder resist layer 532 and is connected to the upper package 536 by an external terminal 534 such as a BGA provided in the upper package 536.
  • the upper package 536 is fixed to the solder resist layer 532 on the functional element-embedded substrate with an adhesive layer 535.
  • the element formation surface of the functional element 501 built in the first insulating layer 502 faces the upper package 536, and the wiring systems of the groups A to C shown in FIG. This is performed through the first insulating layer through via 507 provided on the side of the element 501.
  • a part of the wiring system of the A to C groups is also performed through the element through via 506 provided in the functional element 501. Therefore, when the functional element 501 becomes multifunctional and the number of external terminals increases (multiple pins) and the number of wires in the B group also increases, a path for guiding the wiring system of the B group downward is provided in the first insulating layer.
  • the wiring system can be secured without increasing the mounting area.
  • FIG. 7 A modification of the fifth embodiment will be described as a sixth embodiment.
  • the electronic device 600 according to the sixth embodiment has the functional element built-in substrate turned upside down.
  • Reference numerals 601 to 618 in FIG. 7 have the same meanings as reference numerals 501 to 518 in FIG. 5, and reference numerals 631 to 636 are the same as reference numerals 531 to 536 in FIG.
  • the element formation surface of the functional element 601 faces downward on the mounting substrate (not shown) side, and the group B wiring system shown in FIG. 11 can be dropped directly on the mounting substrate side. it can.
  • the group A can secure two systems of the first insulating layer through via 607 and the element through via 606, increase the number of functional elements 601 and mount as the upper package 636. Even if the number of pins to be used is increased, it can be handled. Further, the wiring system of the group C can be dealt with by two systems of the first insulating layer through via 607 and the element through via 606.
  • a functional element such as an LSI is designed such that an element formation surface is mounted upward in an element for wire bonding, and an element formation surface is mounted downward in an element for flip chip mounting.
  • an element for wire bonding is mounted downward or an element for flip chip mounting is mounted upward, (i) an LSI IP core layout, (ii) a multilayer wiring of an LSI-embedded substrate, (iii) on a mounting substrate (motherboard)
  • a mounting substrate motherboard
  • Embodiment 5, 6 is an example, Comprising: It is not limited to these.
  • another electronic component may be mounted at a desired position.
  • the LCR element which plays the role of the noise filter of a circuit can be provided.
  • a MEMS component, a sensor, an energy device, an optical component, etc. may be mounted or built in as a passive component.
  • various modifications can be made without departing from the spirit of the present invention.
  • the wiring system of these components can be performed not only by the first insulating layer through vias 507 and 607 but also by two systems of the element through vias 506 and 606.
  • FIGS. 8A to 8K illustrate a manufacturing process of the functional element-embedded substrate 700 according to the seventh embodiment, and show a modification of the fourth embodiment.
  • the functional element-embedded substrate 700 according to the seventh embodiment has the same basic configuration as that of the fourth embodiment except for the following points. That is, the sixth wiring layer 421 is formed on the lower surface of the sixth insulating layer 419 in the drawing in the fourth embodiment, whereas in the seventh embodiment, the sixth wiring layer 721 is formed. Is different in that the sixth insulating layer 719 is formed on the upper inner surface side in the drawing. This is based on the difference in manufacturing method.
  • a sixth wiring layer 721 is formed on the main surface of the support 750 (see FIG. 8A). Then, the support 750 and the sixth wiring layer 721 are covered with the sixth insulating layer 719, the connection via 720 and the fourth wiring layer 718 are formed in the same manner as described above, and the sixth insulating film 719 and the fourth wiring layer are formed as the fourth. Cover with an insulating layer 716. Further, a connection via 717 is formed (see FIG. 8B).
  • the support body 750 what was illustrated in the said Embodiment 2 can be used. Further, in order to clarify the position where the functional element 701 is mounted, a position mark (not shown) may be provided as appropriate on the support 750.
  • a copper alloy is used as the support 750.
  • the second wiring layer 708 After forming the second wiring layer 708 on the fourth insulating layer, the second wiring layer 708 is covered with the third insulating layer 710 (see FIG. 8C).
  • a functional element 701 having a through-element via 706 is prepared. Then, the functional element 701 is mounted on the upper layer of the predetermined position of the support 750 so that the second wiring layer 708 and the element through via 706 are connected (see FIG. 8D). After that, the first insulating layer 702 is formed so as to cover the third insulating layer 710 and the functional element 701. The functional element 701 was mounted on the support 750 using a semiconductor mounting machine in a face-up state.
  • the material described in the first embodiment can be suitably applied to the element through via 706.
  • the element through via 706 is formed by plating after forming a via hole in the functional element 701 using copper.
  • the first insulating layer 702 is formed so as to embed the functional element 701.
  • a material of the first insulating layer 702 for example, the material of the insulating layer 102 described in Embodiment 1 can be preferably applied.
  • the method for incorporating the functional element 701 is as described in the first embodiment.
  • a via hole 741 penetrating from the surface of the first insulating layer 702 to the surface of the pad (not shown) of the functional element 701 is provided.
  • a via hole 742 penetrating from the surface of the first insulating layer 702 to the surface of the second wiring layer 708 is formed (see FIG. 8E).
  • the via holes 741 and 742 are formed using a laser processing method.
  • a conductor is formed inside the via holes 741 and 742, and a first wiring layer 703 is formed on the first insulating layer 702 (see FIG. 8F).
  • the via hole 741 With a conductor, the element connection via 704 is formed, and by filling the via hole 742 with a conductor, the first insulating layer through via 707 is formed.
  • Suitable examples of these conductor materials and formation methods are as described in the first embodiment.
  • the materials and methods described in the above wiring layers can be suitably applied to the material and forming method of the first wiring layer 703.
  • copper is used and the first wiring layer 703 is formed by a semi-additive method.
  • first insulating layer 702 and the first wiring layer 703 are covered with the second insulating layer 709, and the connection via 711 and the third wiring layer 712 are similarly formed (see FIG. 8G). Further, the second insulating layer 709 and the third wiring layer 712 are covered with the third insulating layer 713, and the connection via 714 and the fifth wiring layer 715 are similarly formed (see FIG. 8H).
  • the support 750 is removed (see FIG. 8 (i)).
  • the support 750 was removed by removing the support 750, which is a copper alloy, using an alkaline wet etching solution.
  • a solder resist layer 731 having an opening is formed on the sixth wiring layer 721 (see FIG. 8J). Thereafter, an external terminal 733 such as a BGA connected to the sixth wiring layer 721 is formed on the solder resist layer 731 side.
  • the method for manufacturing a functional element-embedded substrate according to the seventh embodiment since all the wiring layers can be formed on the support 750, the warpage during the manufacturing process is small, and the manufacturing yield can be improved. .
  • the functional element-embedded substrate according to the seventh embodiment can obtain the same effects as those of the fourth embodiment.
  • the insulating layer (first insulating layer) that fills the functional element is formed of one type of insulating layer, but the present invention is not limited to this, and is configured of two or more types of insulating layers. It may be.
  • the eighth embodiment will be described with reference to the process cross-sectional view of FIG.
  • the configuration of the functional element-embedded substrate 800 shown in FIG. 9 will be described as a modified example of the first embodiment, but it goes without saying that it can be applied to other embodiments.
  • the second wiring layer 808 is formed on the support 850 (see FIG. 9A).
  • the insulating layer 802 is stacked on the support 850 and the second wiring layer 808.
  • the material exemplified as the insulating layer 102 of the first embodiment can be used, but in the eighth embodiment, a material having higher mechanical strength can be used.
  • an epoxy resin containing an inorganic filler is used.
  • Such an insulating layer with increased mechanical strength can form a via having a large diameter, but it may be difficult to form a fine via. In particular, it is difficult to accurately form fine vias such as element connection vias that connect the functional elements and the wiring layers.
  • an insulating layer that forms an insulating layer through via that connects the first wiring layer and the second wiring layer, and an insulation that forms an element connection via that connects the first wiring layer and the functional element.
  • the layers are composed of different insulating layers.
  • an opening 802A is formed at a position where the functional element of the insulating layer 802 is mounted. Subsequently, a functional element 801 having an element through via 806 is installed in the opening 802A.
  • an adhesive layer 805 such as DAF is provided as in the first embodiment, and the element through via 806 also penetrates the adhesive layer 805.
  • an insulating material 861 is filled in the opening 802A.
  • the insulating material 861 is filled with a material that can be easily processed, such as an epoxy resin that does not contain an inorganic filler. Alternatively, a photosensitive organic material may be filled.
  • via holes 842 for through-layer vias are formed in the insulating layer 802, and via holes 841 for element connection vias are formed in the insulating material 861 (see FIG. 9D).
  • the element connection via 804, the insulating layer through via 807, and the first wiring layer 803 are formed in the same manner as in the first embodiment (see FIG. 9E), and finally the support 850 is removed, A functional element-embedded substrate 800 according to the embodiment is formed (see FIG. 9F).
  • the element mounting portion may be previously punched out of a semi-cured material (glass prepreg) in which a glass cloth or the like is impregnated with a resin, and bonded and then cured.
  • a semi-cured material glass prepreg
  • an insulating layer having high mechanical strength can be adopted, and the overall mechanical strength of the functional element built-in substrate and the electronic device using the same can be increased.
  • the element through via is formed in the functional element, a sufficient wiring path can be secured even if a via having a large diameter is formed in the insulating layer having high mechanical strength. The same effect can be obtained when a skin layer is formed by using a glass prepreg having an opening in the element built-in portion as a core layer and filling a material having good processability around the element and the formation surface of the wiring layer. .
  • the functional element-embedded substrate 900 according to the ninth embodiment describes a case where the plurality of functional elements described in the first embodiment are stacked in the X direction.
  • the case where the circuit forming surfaces of the two functional elements 901a and 901b are stacked to face each other will be described.
  • the present invention is not limited to this, and the circuit forming surface faces the same direction or faces the other direction. Even if it is, it can be applied.
  • the functional elements 901a and 901b are embedded in the first insulating layers 902a and 902b, respectively, and the first insulating layer through vias 907a and 907b are respectively provided on the side of the functional elements.
  • An element connection via 904a and a first wiring layer 903a are formed on the circuit forming surface side of the functional element 901a, and a second wiring layer 908a is formed on the back surface side.
  • an element connection via 904b and a first wiring layer 903b are formed on the circuit forming surface side of the functional element 901b, and a second wiring layer 908b is formed on the back surface side.
  • the functional element 901a has a through-element via 906, and the functional element 901b has no through-element via.
  • Such a functional element-embedded substrate 900 is manufactured by forming the laminated structure indicated by a and b in the drawing in accordance with the manufacturing process of the second embodiment described above, and then forming the circuit of the functional element 901a and the functional element 901b. It can be easily carried out by pasting together so that the surfaces face each other. That is, the laminated structure a can be manufactured by forming the steps shown in FIGS. 3A to 3E and further forming the second insulating layer 909a and the connection via 911a, and the laminated structure b can be produced by the steps shown in FIGS. e) through the process shown in e), and finally the laminated structures a and b are bonded together using the second insulating layer 909b as an adhesive layer.
  • the group A to C wiring systems exist, and the first insulating layer through via 907a provided on the side of the functional element 901a is provided. Will be done through. Further, a part of the wiring system of the groups A to C is also performed through the element through via 906 provided in the functional element 901a.
  • the first route for guiding the B group wiring system to the lower side This can be performed by two systems of the insulating layer through via 907a and the element through via 906, and it is not necessary to increase the density of the first insulating layer through via 907a.
  • the wiring system can be secured without increasing the mounting area.
  • the upper package is mounted on the functional element built-in substrate 900, it is not necessary to increase the density of the first insulating layer through via 907b by providing the functional element 901b with an element through via.
  • the insulating layer through vias are provided in the first insulating layers 902a and 902b, respectively.
  • vias that directly connect the second wiring layers 908b and 908a may be formed.
  • the indications “first”, “second”, and “third” in the present embodiment are for convenience of explanation of the manufacturing method, and include cases that are different from the above-described embodiments. Needless to say.

Abstract

　機能素子と、機能素子を埋設する絶縁層と、絶縁層の２つの主面に配設される配線層と、絶縁層中であって、機能素子の側方に、配線層間を接続する絶縁層貫通ビアとを有し、機能素子は、機能素子の基板を貫通する基板貫通ビアを有し、上記配線層間の電気的接続の少なくとも一部が、基板貫通ビアを介することを特徴とする機能素子内蔵基板を用いることで、機能素子の高機能化しても、機能素子内蔵基板の実装面積を拡大することなく、十分な配線系統を確保できる。

Description

機能素子内蔵基板及びそれを用いた電子デバイス
　本発明は、機能素子を内蔵した機能素子内蔵基板及びそれを用いた電子デバイスに関する。
　電子機器の継続的な軽薄短小化に伴い、半導体素子そのものの微細化や集積化と共に、半導体パッケージにおける高密度実装技術がますます進展している。半導体素子とパッケージの配線基板との接続には、金線等を用いるワイヤーボンディング接続や、半田ボール等を用いるフリップチップ接続が用いられている。
　ワイヤーボンディング接続は、半導体素子のパッド数が少ない場合には、低コストでパッケージングすることができる。しかしながら、半導体素子のパッドの狭ピッチ化に伴って、ワイヤー径を小さくする必要が生じ、ワイヤー切れ等の組立プロセスにおける歩留まり低下が課題となっている。
　フリップチップ接続は、ワイヤーボンディング接続に比べて半導体素子と配線基板間の高速信号伝送が可能であるというメリットがある。しかしながら、半導体素子のパッド数の増加や狭ピッチ化に伴って、半田バンプの接続強度が弱くなり、接続箇所のクラック発生等の不良が多発していた。
　そこで、近年、半導体素子などの機能素子を内蔵するパッケージ技術、いわゆる機能素子内蔵技術が提案されている（例えば、特許文献１）。この技術は、半導体装置などの機能素子のさらなる高集積化及び高機能化を実現し、パッケージの薄型化、低コスト化、高周波対応、低ストレス接続、エレクトロマイグレーション特性改善等を実現する高密度実装技術として期待されている。
　特許文献１においては、絶縁性基板に内蔵された半導体素子に電気的に接続するため、半導体素子の回路面にバンプ形成し、このバンプを介して絶縁性基板上に形成された第１の配線と電気的に接続する構成が開示されている。また、絶縁性基板の裏面に第２の配線が形成されており、半導体素子の側方に絶縁樹脂基板を貫通する導電性ポストにより第１の配線と第２の配線とが接続されている。
特開２００７－１３４５６９号公報
　昨今、半導体素子等の機能素子は日々高機能化されており、機能素子内蔵基板に内蔵される機能素子についても例外ではない。機能素子の高機能化は、例えば、外部端子数の増加（多ピン化）につながり、多ピン化すると機能素子内蔵基板内の配線数も増加する。特許文献１のように上下の配線層間を半導体素子の側方の絶縁層を貫通する貫通ビア（Ｄｉｅ　Ｓｉｄｅ　Ｖｉａ、以下、ＤＳＶと称す）で接続している場合、機能素子の多ピン化に伴い、ＤＳＶの数を増加するなど多様化する必要がある。一方、実装面積を拡大することなくＤＳＶの数を増加するには、ＤＳＶの配置を高密度にするべく、ＤＳＶの径を小さくし、配置ピッチを縮小する必要があるが、機能素子内蔵基板の製造歩留まりが低下し、信頼性において問題があった。結局、ＤＳＶを備える機能素子内蔵基板の信頼性を確保するには、実装面積を大きくせざるを得ない状況にある。
　本発明の一実施形態に係る機能素子内蔵基板は、
　機能素子と、
　該機能素子を埋設する絶縁層と、
　該絶縁層の２つの主面に配設される配線層と、
　前記絶縁層中であって、前記機能素子の側方に、前記２つの主面に配設される配線層間を接続する絶縁層貫通ビアと
を有し、
　前記機能素子は、該機能素子の基板を貫通する基板貫通ビアを有し、前記２つの主面に配設される配線層間の電気的接続の少なくとも一部が、該基板貫通ビアを介することを特徴とする機能素子内蔵基板である。
　本発明によれば、機能素子内蔵基板の実装面積を拡大することなく、内蔵する部品の多ピン化などの多様化に十分に対応できる。
実施形態１に係る機能素子内蔵基板の構造の例を示す模式的断面図。 実施形態２に係る機能素子内蔵基板の構造の例を示す模式的断面図。 （ａ）～（ｅ）：実施形態２に係る機能素子内蔵基板の製造例を説明する工程断面図。 （ｆ）～（ｈ）：実施形態２に係る機能素子内蔵基板の製造例を説明する工程断面図。 実施形態３に係る機能素子内蔵基板の構造の例を示す模式的断面図。 実施形態４に係る機能素子内蔵基板の構造の例を示す模式的断面図。 実施形態５に係る電子デバイスの構造の例を示す模式的断面図。 実施形態６に係る電子デバイスの構造の例を示す模式的断面図。 （ａ）～（ｅ）：実施形態７に係る機能素子内蔵基板の製造例を説明する工程断面図。 （ｆ）～（ｈ）：実施形態７に係る機能素子内蔵基板の製造例を説明する工程断面図。 （ｉ）～（ｋ）：実施形態７に係る機能素子内蔵基板の製造例を説明する工程断面図。 （ａ）～（ｆ）：実施形態８に係る機能素子内蔵基板の製造例を説明する工程断面図。 実施形態９に係る機能素子内蔵基板の構造の例を示す模式的断面図。 本発明の一課題を説明するための概念図。
　ＰｏＰ(Package on Package)形状に代表されるように、電子デバイスの実装面積を縮小する技術が知られている。ＤＳＶを備える機能素子内蔵基板に上パッケージが実装される場合、全体の配線系統は図１１に示すように３つに分類される。ここで、Ａ群は機能素子であるＬＳＩ１００１から、上パッケージ１００３への配線系統及び、機能素子内蔵基板１００２下の実装基板（不図示）への配線系統を示し、Ｂ群はＬＳＩ１００１と実装基板との配線系統、Ｃ群は上パッケージ１００３と実装基板との配線系統である。機能素子内蔵基板１００２の両主面には不図示の配線層が形成されており、上パッケージ１００３とは、ボールグリッドアレイ（Ball Grid Array:以下、ＢＧＡ）などの外部端子１００５で接続されている。また、機能素子内蔵基板１００２と実装基板は、ＢＧＡなどの外部端子１００４で接続される。
　ここで、ＬＳＩ１００１の回路面が上パッケージ１００３方向を向いている場合、Ｂ群の配線系統は、ＬＳＩ１００１の側方に設けたＤＳＶ（不図示）を介して行われることになる。Ａ群及びＣ群にもＤＳＶが必要である。ＬＳＩ１００１が多機能化して外部端子数が増加（多ピン化）するとＢ群の配線数も増加し、Ｂ群の配線系統を下側に導くためのＤＳＶの数も増加させざるを得ない。この結果、機能素子内蔵基板１００２に形成するＤＳＶの数が増大する。機能素子内蔵基板１００２の面積を大きくすればこの要求に応えることはできるが、実装面積の増大になる。したがって、実装面積を増大させることなくＤＳＶの数を増やすためには、ＤＳＶを高密度に配置しなければならない。
　ＤＳＶを高密度に配置するためには、前述の通りＤＳＶの径を小さくし、ＤＳＶの配置ピッチを縮小する必要がある。しかし、これはＤＳＶの高アスペクト化を招き、以下の技術的課題が発生する。
　（１）高アスペクトな開口部を形成する技術、
　（２）高アスペクトな開口部底の残渣を除去する技術、
　（３）高アスペクトな開口部底に銅などの導電体を形成する技術、特にめっき技術。
　これらのプロセスは、いずれも不安定であり、プロセスウィンドウが狭いため、結果的に機能素子内蔵基板の製造歩留まりが低下し、長期信頼性の低下も引き起こす。
　一方、ＬＳＩ１００１の回路面が下向きの場合、Ｂ群の配線系統は直接実装基板側に落とすことができる。この時、Ａ群の配線系統に着目すると、Ａ群もＤＳＶを介する必要があるため、ＬＳＩ１００１の多ピン化、上パッケージ１００３として実装する部品の多ピン化が進むと、Ａ群配線系統のために同様にＤＳＶの高密度化が必要になる。
　このような配線系統の確保の困難さは、ＰｏＰ形状に限定されず、内蔵するＬＳＩが多ピン化する場合や、複数の機能素子を内蔵する場合にも起こりえる。
　このように、従来は信頼性を確保するという観点から、ＤＳＶを備える機能素子内蔵基板の実装面積拡大が避けられない状況にあった。本発明では、実装面積の拡大を抑制し、信頼性の高い機能素子内蔵基板及び該機能素子内蔵基板を含む電子デバイスが提供するものである。
　以下、本発明のより具体的な実施形態について図面を参照しつつ説明する。なお、複数の実施形態において、同一又は類似の要素部材には下２桁に同一の符号を付し、適宜、重複する説明を省略する。
　〔実施形態１〕
　図１に、本発明の実施形態１に係る機能素子内蔵基板１００の要部の模式的断面図を示す。本実施形態１に係る機能素子内蔵基板１００は、ＬＳＩに代表される半導体素子等の機能素子１０１、機能素子１０１を埋設する絶縁層１０２、絶縁層１０２の２つの主面（上面及び裏面）に第１配線層１０３及び第２配線層１０８を備える。機能素子１０１には、機能素子を構成する基板を貫通するビアを含む素子貫通ビア１０６が１個又は複数形成されている。素子貫通ビア１０６には、導電材料が形成されており、機能素子１０１の上面から下面へ導通可能となっている。絶縁層１０２には絶縁層貫通ビア１０７が設けられており、第１配線層１０３と第２配線層１０８を接続している。この例では、機能素子１０１の上面（図示する上方向の面）に電子回路（不図示）やパッド（不図示）が形成される場合を示しており、機能素子の下面には接着層１０５を設けている。素子貫通ビア１０６はこの接着層１０５をも貫通している。機能素子１０１の上面には第１配線層１０３との接続部１０４が形成されており、第１配線層１０３と第２配線層１０８とは、機能素子１０１に形成した素子貫通ビア１０６を介しても電気的に接続されている。
　素子貫通ビア１０６は、一つの部材で構成されていてもよく、また、複数の部材で構成されていても良い。例えば、機能素子を構成する基板を貫通する基板貫通ビアと、半導体基板を保護する保護層を貫通するポスト電極との組み合わせであっても良い。なお、本発明において、機能素子を構成する基板を貫通する基板貫通ビアにより第１配線層と第２配線層との間の配線経路の一部が確保されればよいので、図示する素子貫通ビア１０６に限定されず、例えば、機能素子上の配線回路と基板貫通ビアとが接続されて配線経路を構成してもよい。このような基板貫通ビアは、機能素子形成前に形成することが好ましい。また、素子貫通ビア１０６を一部材で構成する場合、機能素子形成後にビアホールを形成し、このビアホールに導電材料を充填すればよい。この場合も、基板を貫通する部分では基板貫通ビアということになる。なお、以下の説明では簡略のため、断りがない限り「素子貫通ビア」として説明するが、いずれの場合も上記説明を含むものと理解される。
　素子貫通ビア１０６（基板貫通ビアを含む）の材料としては、導電性を有していればどのような材料であってもよいが、Ｃｕ，Ａｌ等の金属やその合金、導電性の金属酸化物、あるいは、導電性の微細粒子が添加された充填材（導電性ペースト）やポリマー自体が導電性を有する導電性ポリマーなどが挙げられる。本実施形態では、機能素子形成後にビアホールを形成し、導電性ペーストを充填して素子貫通ビアを形成した。また、接着層１０５を貫通する部分には銅ポストを形成した。導電性樹脂を使用することで、機能素子１０１に使用される半導体基板などの基板材料と絶縁層１０２との応力歪みを緩和することもできる。
　素子貫通ビアを形成する機能素子としては、機能素子の中でも比較的専有面積の大きな機能素子を選択することが好ましい。一般的に、ＬＳＩ等の半導体素子は、チップサイズが比較的大きく、素子貫通ビアを形成するのに適している。一方、コイル部品等基板内に電流経路を設けることで素子の機能に影響するものには、素子貫通ビアは設けない。
　機能素子の基板は、例えば、半導体素子を構成するために、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ガリウム砒素（ＧａＡｓ）、ガリウム砒素リン（ＧａＡｓＰ）、窒化ガリウム（ＧａＮ）、炭化珪素（ＳｉＣ）、酸化亜鉛（ＺｎＯ）等の半導体基板を適用することができる。また、半導体特性を示すＩＩ－ＶＩ族化合物、ＩＩＩ－Ｖ族化合物や、ダイアモンドなどを用いてもよい。また、機能素子の基板として、シリカ基板、サファイア基板などの無機絶縁物、有機樹脂等の絶縁性基板を用いてもよい。また、ＳＯＩ基板など半導体材料と絶縁性材料との組み合わせであってもよい。勿論、これらに限定されるものではない。本実施形態１では、機能素子１００としてシリコン基板を有する半導体素子を用いた。
　機能素子内蔵基板１００内に内蔵される機能素子１０１の数は、１つに限定されるものではなく、複数配設することができる。複数配設する方法としては、図１中のＸ方向に機能素子を複数配設する態様の他、図１中のＹ方向に機能素子１０１を複数積層するものであってもよい。また、このように複数の機能素子を内蔵する場合、素子貫通ビア１０６や基板貫通ビアは必ずしも全ての機能素子に設ける必要はない。
　素子貫通ビア１０６を配設する位置は、特に限定されず、機能素子１０１に形成する電子回路の配置や、第１配線層１０３及び第２配線層１０８との関係等を考慮して配置すればよく、厳密な配置に限定されるものではない。
　また、素子貫通ビア１０６の個々の形状は、特に限定されるものではなく、例えば、円形、矩形等の多角形状、または曲線で囲まれた形状、若しくはこれらを組み合わせたものであってもよい。素子貫通ビア１０６や基板貫通ビアの径は、特に限定されるものではないが、例えば、１０μｍ～１００μｍ程度とすることができる。
　絶縁層１０２は、例えば、感光性又は非感光性の有機材料を用いて形成することができる。有機材料としては、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ(benzocyclobutene)、ＰＢＯ(polybenzoxazole)、ポリノルボルネン樹脂等を列挙することができる。また、これら樹脂群から選ばれる樹脂等を、ガラスクロスやアラミド繊維などで形成された織布や不織布に含浸させた材料を用いてもよい。また、上記樹脂群から選ばれる樹脂等やケイ素樹脂に、無機フィラーや有機フィラーを含ませたものを用いてもよい。勿論、これらに限定されるものではなく、無機材料を含め、本発明の趣旨を逸脱しない範囲において種々のものを適用することができる。本実施形態１では、絶縁層１０２としてエポキシ樹脂を用いた。
　接着層１０５は、例えば、ダイアタッチメントフィルム（ＤＡＦ；Die Attachment Film）と呼ばれる半硬化樹脂や、エポキシ樹脂、ポリイミド樹脂、ＢＣＢ(benzocyclobutene)、ＰＢＯ(polybenzoxazole)などの樹脂ペースト、あるいは銀ペーストなどが好適である。無論、これらに限定されない。本実施形態１ではエポキシ樹脂を主成分とするＤＡＦを用いた。
　第１配線層１０３及び第２配線層１０８は、例えば、銅、銀、金、ニッケル、アルミニウム、チタン、モリブデン、タングステン、及びパラジウムからなる群から選択された少なくとも１種の金属、若しくはこれらを主成分とする合金、あるいは導電性フィラーを含有する樹脂から成る導電性樹脂などが好適であるが、これらに限定されない。電気抵抗値及びコストの観点からは、銅により形成することが望ましい。本実施形態１では、銅を用いた。
　素子接続ビア１０４は、絶縁層１０２の表面から機能素子１０１のパッド（不図示）まで貫通するビアホールに、導電体が充填されたものである。素子接続ビア１０４は、例えば、レーザにより絶縁層１０２にビアホールを形成し、第１配線層１０３の形成と同時に形成することができる。また、機能素子１０１に予め金属バンプなどを形成したものを素子接続ビア１０４として好適に適用することができる。また、絶縁層材料として感光性の有機材料を用いる場合には、フォトリソグラフィー技術によりビアホールを形成することができる。素子接続ビア１０４は、素子貫通ビア１０６と直接接続されていてもよい。本実施形態１においては、レーザを用いて、ビアホールを開口し、ビアホール内にメッキにより銅を充填した。なお、内蔵する機能素子の多ピン化が進むと、従来の機能素子内蔵基板では素子接続ビア１０４の数も増やす必要があったが、本発明のように素子貫通ビアを設けることで、前記図１１で説明したＡ群及びＢ群の配線系統の一部を素子貫通ビアで賄うことで、素子接続ビアの数を減らすこともできる。
　本発明において、絶縁層貫通ビア１０７は、内蔵する素子の多ピン化が進んでも、ビア密度やアスペクト比を高めることなく形成することができる。この結果、機能素子内蔵基板の実装面積を拡大することがなく、内蔵する素子の多ピン化に対応できる。また、従来同様の端子数の機能素子を内蔵する場合は、絶縁層貫通ビアの数を減らすことができるため、製造歩留まりの更なる向上や、実装面積の更なる縮小も可能となる。絶縁層貫通ビア１０７は、絶縁層１０２の第１主面から、第２配線層１０８の表面まで貫通するビアホール内に配設された導電体により構成される。形成方法は、素子接続ビア１０４と同様の方法で形成でき、好ましくは、素子接続ビア１０４と同時に形成される。
　なお、図１に示す構成では、素子貫通ビア１０６の複数が第２配線層１０８の一つの配線に接続される例を示しているが、これは、例えば、グランド電位等の共通化できる配線系統を接続する場合に適している。後述する実施形態のように、素子貫通ビアが個別の配線に接続される場合には、信号電位等の個別の配線系統に接続する場合に適している。このような接続方法は、当業者が適宜変更できるものである。
　また、機能素子の基板として半導体基板を用いる場合、機能素子を内蔵する工程や使用環境によって機能素子内蔵基板の反り、うねりが発生する場合があったが、本実施形態１のように素子貫通ビアを設けることで、これら反りやうねりを抑制し、信頼性を改善することもできる。特に、温度サイクル試験特性を改善することができる。さらに、低反りによって、内蔵基板の配線歩留まりが改善されるため、配線不良による良品の半導体素子の破棄損失が減少し、製造コストを低減することができる。さらに、低反りによって、内蔵基板の配線をより微細化することも可能となり、配線層数削減によるコスト低減も可能となる。また、半導体素子を薄くしても半導体素子の強度が劣化せず、半導体素子内蔵基板の全体の厚さを小さくすることができる。また半導体素子を薄くしたときのハンドリング性を改善でき、製造歩留まりを向上させることができる。
　このような反り、うねりを抑制する観点からは、素子貫通ビア１０６を応力集中位置である素子周辺部近傍に配置することが好ましい。また、素子基板における部分的な応力集中を分散する観点から、素子基板内において、平面視上、点対称、若しくは線対称に配置することが好ましい。さらに、本発明における素子貫通ビアと、このような反り、うねりを抑制する基板開口部（半導体基板に形成した貫通孔又は凹部であって、空隙でも低弾性の樹脂等を充填しても良い）を組み合わせても良い。
　〔実施形態２〕
　次に、上記実施形態１とは異なる機能素子内蔵基板の一例について説明する。本実施形態２に係る機能素子内蔵基板２００は、以下の点を除く基本的な構成は上記実施形態１と同様である。すなわち、上記実施形態１においては、機能素子１０１の下部に接着層１０５を設けていたのに対し、本実施形態２においては、接着層１０５を設けておらず、また、機能素子内蔵基板の上下の配線層を多層に形成している点において相違する。
　すなわち、本実施形態２に係る機能素子内蔵基板２００は、内蔵される機能素子２０１、機能素子を埋設する第１絶縁層２０２、機能素子２０１の上方に第１配線層２０３、第３配線層２１２、第５配線層２１５が備え、機能素子の下方に第２配線層２０８、第４配線層２１８、第６配線層２２１を備える。機能素子２０１の基板には、実施形態１と同様に１又は複数の素子貫通ビア２０６が形成されている。素子貫通ビア２０６には、導電材料が形成されており、機能素子の上面から下面へ導通可能となっている。第１絶縁層２０２には第１絶縁層貫通ビア２０７が設けられており、第１配線層２０３と第２配線層２０８を接続している。第１配線層２０３は第２絶縁層２０９内に形成した接続ビア２１１で第３配線層２１２に接続されており、第３配線層２１２は第４絶縁層２１３内に形成された接続ビア２１４により第５配線層２１５とが接続されている。第２配線層２０８は、第３絶縁層２１０中に形成されており、第２配線層２０８は第５絶縁層２１６内に形成された接続ビア２１７により第４配線層２１８と接続されており、第４配線層２１８は第７絶縁層２１９内に形成された接続ビア２２０により第６配線層２２１と接続されている。この例では、機能素子２０１の上面（図示する上方向の面）に電子回路（不図示）やパッド（不図示）が形成される場合を示しており、機能素子の下面には複数の第２配線層２０８を設けている。素子貫通ビア２０６はそれぞれ第２配線層２０８の個別の配線に接続されている。機能素子２０１の上面には第１配線層２０３とを接続する素子接続ビア２０４が形成されており、第１配線層２０３と第２配線層２０８とは、機能素子２０１に形成した素子貫通ビア２０６を介しても電気的に接続されている。
　このように、多層配線化することにより、機能素子２０１からのファンアウト（Fun-out）が容易となる。
　各配線層及び接続ビアは、上記実施形態１と同様の材料から選定することができる。本実施形態では、各配線層及び接続ビアとして、銅を用いた。
　次に、本実施形態２に係る機能素子内蔵基板２００の製造方法の一例について図３（ａ）～（ｇ）の製造工程断面図を用いつつ説明する。
　まず、支持体２５０の主面上に第２配線層２０８を形成する。そして支持体２５０、及び第２配線層２０８を第３絶縁層２１０により被覆する（図３（ａ）参照）。支持体２５０は、樹脂、金属、ガラス、半導体、セラミック等のいずれか又はそれらの組み合わせたものを用いることができる。また、機能素子２０１を搭載する位置を明確にするために、支持体２５０上に位置マーク（不図示）を適宜設けてもよい。本実施形態２では、支持体２５０として銅合金を用いた。また、機能素子２０１を搭載するための位置マークとして、電気めっきによる厚さ５μｍのニッケルを設けた。
　第２配線層２０８は、例えば、サブトラクティブ法、セミアディティブ法又はフルアディティブ法等の方法により形成することができる。サブトラクティブ法は、基板上に設けられた金属層（銅箔）上に所望のパターンのレジストを形成し、不要な金属層をエッチングした後に、レジストを剥離して所望のパターンを得る方法である。セミアディティブ法は、無電解めっき法、スパッタ法、ＣＶＤ法等で給電層を形成した後、所望のパターンに開口されたレジストを形成し、レジスト開口部内に電解めっき法による金属を析出させ、レジストを除去した後に給電層をエッチングして所望の配線パターンを得る方法である。フルアディティブ法は、基板上に無電解めっき触媒を吸着させた後に、レジストでパターンを形成し、このレジストを絶縁膜として残したまま触媒を活性化し、無電解めっき法により絶縁膜の開口部に金属を析出させることで所望の配線パターンを得る方法である。本実施形態では、第２配線層２０８として銅を用い、セミアディティブ法で形成した後、第３絶縁層２１０で被覆した。
　第３絶縁層２１０の好適な材料は、上記実施形態１において述べた絶縁層１０２と同様の材料が挙げられる。第３絶縁層２１０の形成方法としては、トランスファーモールディング法、圧縮形成モールド法、印刷法、真空プレス法、真空ラミネート法、スピンコート法、ダイコート法、カーテンコート法、又はフォトリソグラフィー法等を適用することができる。本実施形態２では、エポキシ樹脂を用いて真空ラミネート法により第３絶縁層２１０を形成した。
　次に、素子貫通ビア２０６が形成された機能素子２０１を用意する。そして、支持体２５０の所定の位置の上層に、第２配線層２０８と素子貫通ビア２０６が接続されるように機能素子２０１を搭載する（図３（ｂ）参照）。ここで素子貫通ビア２０６と第２配線層２０８との接合界面に例えば錫のようなはんだ材料(不図示)を挿入しても良い。
　その後、第３絶縁層２１０及び機能素子２０１を被覆するように第１絶縁層２０２を形成する（図３（ｃ）参照）。素子貫通ビア２０６は、機能素子２０１の機械的強度を低下させない範囲において、任意の場所に設けることができる。機能素子の基板材料としては、例えば、上記実施形態１で説明した材料を好適に適用することができる。本実施形態２ではシリコンのＬＳＩを用いた。機能素子２０１の支持体２５０上への搭載は、フェースアップの状態で半導体搭載機を用いて行った。
　素子貫通ビア２０６は、上記実施形態１で説明した材料を好適に適用することができる。本実施形態２では、素子貫通ビア２０６は、銅を用い、機能素子２０１にビアホールを形成した後、めっき法にて形成した。
　第１絶縁層２０２は、機能素子２０１を埋設するように形成する。第１絶縁層２０２の材料としては、例えば、上記実施形態１で説明した絶縁層１０２の材料を好適に適用することができる。機能素子２０１の内蔵方法は、上記実施形態１で述べたとおりである。
　続いて、第１絶縁層２０２の表面から、機能素子２０１のパッド（不図示）の表面まで貫通するビアホール２４１を設ける。同時に、第１絶縁層２０２の表面から、第２配線層２０８の表面まで貫通するビアホール２４２を形成する（図３（ｄ）参照）。本実施形態２では、レーザ加工法を用いてビアホール２４１，２４２を形成した。
　次に、ビアホール２４１及び２４２の内部に導体を形成し、第１絶縁層２０２上に第１配線層２０３を形成する（図３（ｅ）参照）。ビアホール２４１に導体を充填することにより素子接続ビア２０４が、ビアホール２４２に導体を充填することにより第１絶縁層貫通ビア２０７が形成される。これらの導体の材料、及び形成方法の好適な例は、上記実施形態１で述べたとおりである。また、第１配線層２０３の材料、及び形成方法も上記第２配線層で述べた材料や方法を好適に適用することができる。本実施形態２においては、銅を用い、セミアディティブ法により第１配線層２０３を形成した。
　その後、支持体２５０を除去する（図３（ｆ）参照）。支持体２５０の除去は、支持体４５の除去には、薬液によるウェットエッチング法、機械的研磨による研削法、物理的な剥離法等が好適であるが、これらに限定されない。本実施形態２においては、アルカリ性のウェットエッチング液を用いて、銅合金である支持体２５０を除去した。また、第１配線層２０３を保護するため、次に説明する第２絶縁層２０９を形成しておいてもよい。
　次に、第２絶縁層２０９、接続ビア２１１、第３配線層２１２、第４絶縁層２１６、接続ビア２１７、第４配線層２１８を形成する（図３（ｇ）参照）。第２絶縁層２０９、第４絶縁層２１６の好適な材料は、上述したとおりである。また、第２絶縁層２０９、第４絶縁層２０４の形成方法としては、例えば、上述した第３絶縁層２１０と同様の方法により形成することができる。本実施形態２においては、エポキシ樹脂を用いて真空ラミネート法により第２絶縁層２０９、第４絶縁層２１６を形成した。
　第２絶縁層２０９、第４絶縁層２１６に接続ビア２１１、２１７を形成する方法としては、特に限定されないが、上記素子接続ビア２０４、第１絶縁層貫通ビア２０７と同様の方法を好適に適用することができる。本実施形態２においては、レーザ加工法を用いて開口部を形成し、銅を充填して形成した。また、銅を用いセミアディティブ法により第３配線層２１２、及び第４配線層２１８を形成した。
　次に、第５絶縁層２１３、接続ビア２１４、第５配線層２１５、第６絶縁層２１９、接続ビア２２０、第６配線層２２１を形成する（図３（ｈ）参照）。第５絶縁層２１３、第６絶縁層２１９の好適な材料は、上述したとおりである。また、第５絶縁層２１３、第６絶縁層２１９の形成方法としては、例えば、上述した第２絶縁層２１０と同様の方法により形成することができる。接続ビア２１４及び２２０、第５配線層２１５、第６配線層２２１の形成方法も上記と同様である。
　なお、この実施形態２においては、機能素子２０１の側方の絶縁層貫通ビアとして、第１絶縁層２０２のみを貫通する第１絶縁層貫通ビア２０７として説明したが、複数の絶縁層を貫通する絶縁層貫通ビアでもよい。例えば、第５配線層２１５と第６配線層２２１とを直接接続するように、第５絶縁層２１３から第６絶縁層２１９まで貫通するビアを設けてもよい。
　また、本実施形態２のように、機能素子の設置時に接着層を設けない場合、構成材料が少なくなり、材料及び工程数の両面で低コスト化できるという利点もある。
　〔実施形態３〕
　実施形態３では、実施形態１の変形例を示す。本実施形態３に係る機能素子内蔵基板３００は、以下の点を除く基本的な構成は上記実施形態１と同様である。すなわち、図４の模式的断面図に示すように、上記実施形態１においては、機能素子１０１の下部に接着層１０５を設けていたのに対し、本実施形態３においては、機能素子３０１の下部には接着層１０５を設けておらず、また、第１配線層３０３及び第２配線層３０８をソルダーレジスト層３３２、３３１で保護し、さらに、外部基板（不図示）と接続する外部端子３３３をソルダーレジスト層３３１の開口部に設けている。図４において、符号３０１～３０８は、図１の符号１０１～１０８にそれぞれ相当する。
　〔実施形態４〕
　実施形態４では、実施形態２の変形例を示す。図５に実施形態４に係る機能素子内蔵基板４００の概略断面図を示す。本実施形態４では実施形態２の機能素子内蔵基板２００の下部にソルダーレジスト層４３１と外部端子４３３を設けている以外、実施形態２と同様である。図５において、符号４０１～４２１は、図２の符号２０１～２２１にそれぞれ相当する。
　上記実施形態３及び４におけるソルダーレジスト層３３２，３３１、４３１を設けることにより、機能素子内蔵基板の表面回路を保護するとともに、難燃性を付与することができる。ソルダーレジスト層として、感光性レジストインクを用いた。
　なお、配線層や絶縁層の数は、一例であって、上記実施形態に限定されることなく、必要な数だけ配線層や絶縁層を積層することができることは言うまでもない。以上の実施形態では、機能素子の高機能化（多ピン化）により、図１１に示すＢ群の配線系統が増加する場合に、機能素子側面の絶縁層貫通ビアに加えて、機能素子を貫通する素子貫通ビアによる配線系統を有することから、絶縁層貫通ビアの高密度化、高アスペクト化を必要とせず、更なる多様化に対応できる。
　〔実施形態５〕
　次に、本発明の機能素子内蔵基板を用いた電子デバイスの実施形態について説明する。本実施形態５に係る電子デバイス５００は、機能素子内蔵基板上に上パッケージ５３６を搭載してＰｏＰ形状としたものである。第２配線層５１２から下の構造は、上記の実施形態４と同様であり、図６における符号５０１～５１２，５１６～５２１，５３１，５３３は、図５の符号４０１～４１２，４１６～４２１，４３１，４３３と同様の意味を示す。第２配線層５１２は、ソルダーレジスト層５３２で保護されており、上パッケージ５３６に設けたＢＧＡなどの外部端子５３４で上パッケージ５３６と接続されている。また、上パッケージ５３６は機能素子内蔵基板上のソルダーレジスト層５３２に接着剤層５３５で固定されている。
　本実施形態５の電子デバイス５００は、第１絶縁層５０２に内蔵される機能素子５０１の素子形成面が上パッケージ５３６方向を向いており、図１１に示すＡ～Ｃ群の配線系統は、機能素子５０１の側方に設けた第１絶縁層貫通ビア５０７を介して行われることになる。また、Ａ～Ｃ群の一部の配線系統は、機能素子５０１に設けた素子貫通ビア５０６を介しても行われる。そのため、機能素子５０１が多機能化して外部端子数が増加（多ピン化）してＢ群の配線数も増加する場合、Ｂ群の配線系統を下側に導くための経路を第１絶縁層貫通ビア５０７と素子貫通ビア５０６の２系統で行うことができ、第１絶縁層貫通ビア５０７を高密度化する必要がない。この結果、実装面積を増大させることなく、配線系統の確保が可能となる。また、上パッケージ５３６として実装する電子部品の多ピン化などにも対応できる。
　〔実施形態６〕
　実施形態５の変形例を実施形態６として示す。本実施形態６に係る電子デバイス６００は、図７に示すように、機能素子内蔵基板を上下逆転している。図７における符号６０１～６１８は、図５の符号５０１～５１８と同様の意味を示し、符号６３１～６３６は、図６の符号５３１～５３６と同様である。
　本実施形態６に係る電子デバイス６００は、機能素子６０１の素子形成面が実装基板（不図示）側となる下向きであり、図１１に示すＢ群の配線系統は直接実装基板側に落とすことができる。この時、Ａ群の配線系統に着目すると、Ａ群は第１絶縁層貫通ビア６０７と素子貫通ビア６０６の２系統を確保することができ、機能素子６０１の多ピン化、上パッケージ６３６として実装する部品の多ピン化が進んでも、対応することができる。また、Ｃ群の配線系統についても、第１絶縁層貫通ビア６０７と素子貫通ビア６０６の２系統で対応することができる。
　一般的にＬＳＩ等の機能素子は、ワイヤボンディング向けの素子では素子形成面を上向きに、また、フリップチップ実装向けの素子では素子形成面を下向きに実装するように設計されている。ワイヤボンディング向けの素子を下向き、あるいはフリップチップ実装向けの素子を上向きに実装すると、（ｉ）ＬＳＩのＩＰコアレイアウト、（ｉｉ）ＬＳＩ内蔵基板の多層配線、（ｉｉｉ）実装基板（マザーボード）上の部品配置、のいずれかを鏡面反転しなければならず、これは極めてコストアップとなるからである。従来のような絶縁層貫通ビアだけの機能素子内蔵基板でも、ワイヤボンディング向けの素子を下向きに、またはフリップチップ実装向けの素子を上向きに内蔵すると、内蔵配線層で配線レイアウトを左右反転すべき経路が多くなりすぎて、配線層数が増大し、歩留まりが劣化してコストが上がるため、機能素子内蔵基板への機能素子の内蔵は、従来の一般的な設計思想を踏襲して行われていた。これに対し、本発明によれば、絶縁層貫通ビアと素子貫通ビアを有効活用することにより、機能素子の内蔵方向に対する自由度を向上させ、ひいては内蔵配線層のレイアウトを容易にし、配線層数を削減しコストを低減することができる。
　なお、上記実施形態５，６は一例であって、これらに限定されるものではない。本発明の電子デバイスは、所望の位置に、他の電子部品が搭載されていてもよい。電子部品としては、特に限定されないが、例えば、回路のノイズフィルターの役割を果たすＬＣＲ素子を設けることができる。また、受動部品として、ＭＥＭＳ部品、センサ、エネルギーデバイス、光部品などが搭載又は内蔵されていてもよい。このほか、本発明の趣旨を逸脱しない範囲において種々の変形が可能である。これらの部品の配線系統も第１絶縁層貫通ビア５０７、６０７のみならず、素子貫通ビア５０６、６０６の２系統で行うことができる。
　〔実施形態７〕
　その他、本発明の変形例について、製造工程を参照しつつ説明する。図８（ａ）～（ｋ）は本実施形態７に係る機能素子内蔵基板７００の製造工程を説明するもので、実施形態４の変形例を示す。本実施形態７に係る機能素子内蔵基板７００は、以下の点を除く基本的な構成は上記実施形態４と同様である。すなわち、第６配線層４２１が、上記実施形態４においては、第６絶縁層４１９の図中下側の表面上に形成されているのに対し、本実施形態７においては、第６配線層７２１は第６絶縁層７１９の図中上側の内面側に形成されている点において相違する。これは、製造方法の相違に基づくものである。
　まず、支持体７５０の主面上に第６配線層７２１を形成する（図８（ａ）参照）。そして支持体７５０及び第６配線層７２１を第６絶縁層７１９により被覆し、上記と同様に接続ビア７２０、第４配線層７１８を形成し、第６絶縁膜７１９及び第４配線層を第４絶縁層７１６で被覆する。さらに、接続ビア７１７を形成する（図８（ｂ）参照）。支持体７５０としては、上記実施形態２で例示したものを用いることができる。また、機能素子７０１を搭載する位置を明確にするために、支持体７５０上に位置マーク（不図示）を適宜設けてもよい。本実施形態７では、支持体７５０として銅合金を用いた。
　第４絶縁層上に第２配線層７０８を形成した後、第２配線層７０８を第３絶縁層７１０で被覆する（図８（ｃ）参照）。
　次に、素子貫通ビア７０６が形成された機能素子７０１を用意する。そして、支持体７５０の所定の位置の上層に、第２配線層７０８と素子貫通ビア７０６が接続されるように機能素子７０１を搭載する（図８（ｄ）参照）。その後、第３絶縁層７１０及び機能素子７０１を被覆するように第１絶縁層７０２を形成する。機能素子７０１の支持体７５０上への搭載は、フェースアップの状態で半導体搭載機を用いて行った。
　素子貫通ビア７０６は、上記実施形態１で説明した材料を好適に適用することができる。本実施形態７では、素子貫通ビア７０６は、銅を用い、機能素子７０１にビアホールを形成した後、めっき法にて形成した。
　第１絶縁層７０２は、機能素子７０１を埋設するように形成する。第１絶縁層７０２の材料としては、例えば、上記実施形態１で説明した絶縁層１０２の材料を好適に適用することができる。機能素子７０１の内蔵方法は、上記実施形態１で述べたとおりである。
　続いて、第１絶縁層７０２の表面から、機能素子７０１のパッド（不図示）の表面まで貫通するビアホール７４１を設ける。同時に、第１絶縁層７０２の表面から、第２配線層７０８の表面まで貫通するビアホール７４２を形成する（図８（ｅ）参照）。本実施形態７では、レーザ加工法を用いてビアホール７４１，７４２を形成した。
　次に、ビアホール７４１及び７４２の内部に導体を形成し、第１絶縁層７０２上に第１配線層７０３を形成する（図８（ｆ）参照）。ビアホール７４１に導体を充填することにより素子接続ビア７０４が、ビアホール７４２に導体を充填することにより第１絶縁層貫通ビア７０７が形成される。これらの導体の材料、及び形成方法の好適な例は、上記実施形態１で述べたとおりである。また、第１配線層７０３の材料、及び形成方法も上記各配線層で述べた材料や方法を好適に適用することができる。本実施形態７においては、銅を用い、セミアディティブ法により第１配線層７０３を形成した。
　さらに、第１絶縁層７０２及び第１配線層７０３を第２絶縁層７０９で被覆し、接続ビア７１１、第３配線層７１２を同様に形成する（図８（ｇ）参照）。さらに、第２絶縁層７０９及び第３配線層７１２を第３絶縁層７１３で被覆し、接続ビア７１４、第５配線層７１５を同様に形成する（図８（ｈ）参照）。
　その後、支持体７５０を除去する（図８（ｉ）参照）。支持体７５０の除去は、アルカリ性のウェットエッチング液を用いて、銅合金である支持体７５０を除去した。
　次いで、第６配線層７２１上に開口部を有するソルダーレジスト層７３１を形成する（図８（ｊ）参照）。その後、ソルダーレジスト層７３１側において、第６配線層７２１と接続するＢＧＡなどの外部端子７３３を形成する。上記工程等を経て、図８（ｋ）に示す機能素子内蔵基板７００が製造される。
　本実施形態７に係る機能素子内蔵基板の製造方法によれば、支持体７５０上に全ての配線層を作り込むことができるため、製造工程中の反りが小さく、製造歩留まりを向上させることができる。また、本実施形態７に係る機能素子内蔵基板は、上記実施形態４と同様の効果が得られる。
　〔実施形態８〕
　以上の実施形態において、機能素子を埋める絶縁層（第１絶縁層）は、１種の絶縁層で形成しているが、本発明はこれに限定されず、２種以上の絶縁層で構成されていてもよい。本実施形態８として、図９の工程断面図を参照しつつ説明する。図９に示す機能素子内蔵基板８００の構成は、上記実施形態１の変形例として説明するが、その他の実施形態に適用できることはいうまでもない。
　まず、支持体８５０上に第２配線層８０８を形成する（図９（ａ）参照）。次に、絶縁層８０２を支持体８５０及び第２配線層８０８上に積層する。絶縁層８０２としては、実施形態１の絶縁層１０２として例示したものが使用できるが、本実施形態８では、機械的強度をより高めた材料を使用することができる。本実施形態８では、無機フィラーを含有するエポキシ樹脂を用いた。このような機械的強度を高めた絶縁層は、径の大きなビアは形成することができるが、微細なビアを形成するのに困難を要する場合がある。特に機能素子と配線層とを接続する素子接続ビアなどの微細なビアを精度よく形成することが困難になる。そこで、本実施形態８では、第１配線層と第２配線層とを接続する絶縁層貫通ビアを形成する絶縁層と、第１配線層と機能素子とを接続する素子接続ビアを形成する絶縁層とを異なる絶縁層で構成する。
　図９（ｂ）に示すように、絶縁層８０２の機能素子を搭載する位置に開口部８０２Ａを形成する。続いて、開口部８０２Ａ内に、素子貫通ビア８０６を有する機能素子８０１を設置する。この実施形態８では実施形態１と同様にＤＡＦなどの接着層８０５を設けており、素子貫通ビア８０６は接着層８０５も貫通している。
　次に、開口部８０２Ａ内に絶縁材料８６１を充填する。絶縁材料８６１としては、無機フィラーを含有していないエポキシ樹脂など微細加工が容易な材料を充填する。あるいは、感光性の有機材料を充填しても良い。その後は、絶縁層８０２に絶縁層貫通ビア用のビアホール８４２を形成し、絶縁材料８６１に素子接続ビア用のビアホール８４１をそれぞれ形成する（図９（ｄ）参照）。
　その後は、素子接続ビア８０４、絶縁層貫通ビア８０７、第１配線層８０３を上記実施形態１と同様に形成し（図９（ｅ）参照）、最後に支持体８５０を除去することで、本実施形態に係る機能素子内蔵基板８００が形成される（図９（ｆ）参照）。
　絶縁層８０２としては、ガラスクロスなどに樹脂を含浸した半硬化材料（ガラスプリプレグ）に予め素子搭載部を型抜きしておいて、貼り合わせた後硬化させてもよい。
　このように、本実施形態８では機械的強度の高い絶縁層を採用することができ、機能素子内蔵基板及びこれを用いた電子デバイスの全体的な機械的強度を高めることができる。また、機能素子に素子貫通ビアを形成しているため、このような機械的強度の高い絶縁層には径の大きなビアを形成しても、十分な配線経路を確保することができる。また、素子内蔵部に開口部を有するガラスプリプレグ等をコア層とし、素子周辺及び配線層の形成面に加工性の良好な材料を充填してスキン層を形成する場合にも同様の効果を奏する。
　〔実施形態９〕
　本実施形態９に係る機能素子内蔵基板９００は、実施形態１で説明した複数の機能素子をＸ方向に積層する場合を説明するものである。本実施形態では２つの機能素子９０１ａと９０１ｂとの回路形成面を対向させて積層する場合について説明するが、これに限定されず、回路形成面が同方向を向いている場合や他方向を向いている場合であっても適用することができる。
　図９に示すように、機能素子９０１ａと９０１ｂは、それぞれ第１絶縁層９０２ａ、９０２ｂに埋設されており、機能素子の側方には第１絶縁層貫通ビア９０７ａ、９０７ｂがそれぞれ設けられている。機能素子９０１ａの回路形成面側には素子接続ビア９０４ａと第１配線層９０３ａが形成され、裏面側に第２配線層９０８ａが形成されている。他方、機能素子９０１ｂの回路形成面側には素子接続ビア９０４ｂと第１配線層９０３ｂが形成され、裏面側に第２配線層９０８ｂが形成されている。そして、機能素子９０１ａには素子貫通ビア９０６が形成され、機能素子９０１ｂには素子貫通ビアは形成されていない。
　このような機能素子内蔵基板９００の製造は、図中ａ及びｂで示す積層構造を、上記説明した実施形態２の製造工程に準じてそれぞれ形成した後、機能素子９０１ａと機能素子９０１ｂの回路形成面が対向するように貼り合わせることで容易に実施できる。つまり、積層構造ａは図３（ａ）～（ｅ）に示す工程及びさらに第２絶縁層９０９ａ、接続ビア９１１ａを形成して製造することができ、積層構造ｂは図３（ａ）～（ｅ）に示す工程を経て製造し、最後に接着層として第２絶縁層９０９ｂを用いて積層構造ａとｂを貼り合わせる。
　本実施形態９に係る機能素子内蔵基板９００においても、実施形態５で説明したようにＡ～Ｃ群の配線系統が存在し、機能素子９０１ａの側方に設けた第１絶縁層貫通ビア９０７ａを介して行われることになる。また、Ａ～Ｃ群の一部の配線系統は、機能素子９０１ａに設けた素子貫通ビア９０６を介しても行われる。そのため、機能素子９０１ａ又は９０１ｂが多機能化して外部端子数が増加（多ピン化）してＢ群の配線数も増加する場合、Ｂ群の配線系統を下側に導くための経路を第１絶縁層貫通ビア９０７ａと素子貫通ビア９０６の２系統で行うことができ、第１絶縁層貫通ビア９０７ａを高密度化する必要がない。この結果、実装面積を増大させることなく、配線系統の確保が可能となる。さらに、機能素子内蔵基板９００上に上パッケージを実装する場合には、機能素子９０１ｂにも素子貫通ビアを設けることで、第１絶縁層貫通ビア９０７ｂを高密度化する必要がなくなる。
　本実施形態９では、絶縁層貫通ビアを第１絶縁層９０２ａと９０２ｂにそれぞれ設けているが、上述したように、第２配線層９０８ｂと９０８ａを直接接続するビアを形成してもよい。さらに、本実施形態における「第１」、「第２」、「第３」との表示は製造方法を説明するための便宜上のものであって、上記の実施形態とは異なる場合も含まれることはいうまでもない。
　この出願は、２００９年３月４日に出願された日本出願特願２００９－０５０４８８を基礎とする優先権を主張し、その開示の全てをここに取り込む。
１００，２００，３００，４００，７００，８００，９００：機能素子内蔵基板
５００，６００：電子デバイス
１０１，２０１，３０１，４０１，５０１，６０１，７０１，８０１，９０１ａ，９０１ｂ：機能素子
１０２，３０２,８０２：絶縁層
２０２，４０２，５０２，６０２，７０２，９０２ａ，９０２ｂ：第１絶縁層
１０３，２０３，３０３，４０３，５０３，６０３，７０３，８０３，９０３ａ，９０３ｂ：第１配線層
１０４，２０４，３０４，４０４，５０４，６０４，７０４，８０４，９０４ａ，９０４ｂ：素子接続ビア
１０５，８０５，９０５：接着層
１０６，２０６，３０６，４０６，５０６，６０６，７０６，８０６，９０６：素子貫通ビア
１０７，３０７，８０７：絶縁層貫通ビア
２０７，４０７，５０７，６０７，７０７，９０７ａ，９０７ｂ：第１絶縁層貫通ビア
１０８，２０８，３０８，４０８，５０８，６０８，７０８，８０８，９０８ａ，９０８ｂ：第２配線層
２０９，４０９，５０９，６０９，７０９，９０９ａ，９０９ｂ：第２絶縁層
２１０，４１０，５１０，６１０，７１０，９１０ａ，９１０ｂ：第３絶縁層
２１１，４１１，５１１，６１１，７１１：第１－第３配線接続ビア
９１１ｂ：接続ビア
２１２，４１２，５１２，６１２，７１２：第３配線層
２１３，４１３，６１３，７１３：第４絶縁層
２１４，４１４，６１４，７１４：第３－第５配線接続ビア
２１５，４１５，６１５，７１５：第５配線層
２１６，４１６，５１６，６１６，７１６：第５絶縁層
２１７，４１７，５１７，６１７，７１７；第２－第４配線接続ビア
２１８，４１８，５１８，６１８，７１８：第４配線層
２１９，４１９，５１９，７１９：第６絶縁層
２２０，４２０，５２０，７２０：第４－第６配線接続ビア
２２１，４２１，５２１，７２１：第６配線層
３３１，３３２，４３１，５３１，５３２，６３１，６３２，７３１：ソルダーレジスト層
３３３，４３３，５３３，５３４，６３３，６３４，７３３：外部端子（ＢＧＡ）
５３５，６３５：接着剤層
５３６，６３６：上パッケージ
２４１，２４２，７４１，７４２，８４１，８４２：ビアホール
２５０，７５０，８５０：支持体
８６１：絶縁材料

Claims (14)

  1. 　機能素子と、
    　該機能素子を埋設する絶縁層と、
    　該絶縁層の２つの主面に配設される配線層と、
    　前記絶縁層中であって、前記機能素子の側方に、前記２つの主面に配設される配線層間を接続する絶縁層貫通ビアと
    を有し、
    　前記機能素子は、該機能素子の基板を貫通する基板貫通ビアを有し、前記２つの主面に配設される配線層間の電気的接続の少なくとも一部が、該基板貫通ビアを介することを特徴とする機能素子内蔵基板。
  2. 　前記機能素子は、前記基板貫通ビアを含む、機能素子の表面から裏面に貫通する素子貫通ビアを有する請求項１に記載の機能素子内蔵基板。
  3. 　前記機能素子の回路から、前記機能素子の回路の形成面と対向する側に配設された配線層への電気的接続の一部が、前記基板貫通ビアを介することを特徴とする請求項１又は２に記載の機能素子内蔵基板。
  4. 　前記機能素子は、半導体素子である請求項１乃至３のいずれかに記載の機能素子内蔵基板。
  5. 　前記半導体素子は、シリコンを基板とする半導体素子である請求項４に記載の機能素子内蔵基板。
  6. 　前記基板貫通ビアは、導電性の微細粒子が添加された充填材で構成されている請求項１乃至５のいずれか１項に記載の機能素子内蔵基板。
  7. 　前記基板貫通ビアは、金属材料で構成されている請求項１乃至５のいずれか１項に記載の機能素子内蔵基板。
  8. 　前記２つの主面に配設される配線層の少なくとも一方が、多層配線である請求項１乃至７のいずれかに記載の機能素子内蔵基板。
  9. 　前記機能素子の回路が、機能素子の回路面上に設けられた絶縁層を貫通する接続ビアを介して、前記機能素子の回路面上の配線層と電気的に接続されており、前記機能素子の側方に設けられる絶縁層貫通ビアを形成する絶縁層と、前記機能素子の回路面上に設けられた絶縁層とが異なる材料で構成される請求項１乃至８のいずれかに記載の機能素子内蔵基板。
  10. 　機能素子を複数内蔵し、少なくとも１つの機能素子が前記基板貫通ビアを有する機能素子である請求項１乃至９のいずれかに記載の機能素子内蔵基板。
  11. 　少なくとも２つの機能素子が前記機能素子内蔵基板の厚み方向に積層され、隣接する２つの機能素子の回路が両機能素子間の配線層を介して電気的に接続されており、上層の機能素子と下層の機能素子の下に配設される配線層との電気的接続が、前記下層の機能素子の側方に形成された絶縁層貫通ビアと前記下層の機能素子の基板を貫通する基板貫通ビアとの両方を介して行われる請求項１０に記載の機能素子内蔵基板。
  12. 　前記機能素子内蔵基板の外部接続面にソルダーレジスト層を有する請求項１乃至１１に記載の機能素子内蔵基板。
  13. 　前記ソルダーレジスト層は、配線層の一部を露出する開口部を有し、該開口部に外部接続用の端子を有する請求項１２に記載の機能素子内蔵基板。
  14. 　請求項１乃至１３のいずれかに記載の機能素子内蔵基板と、該機能素子内蔵基板の上面に搭載される上パッケージを有する電子デバイスであって、前記上パッケージと、該上パッケージに対して前記機能素子内蔵基板に内蔵される機能素子の下部にあたる配線層とが電気的に接続されており、その一部が、前記機能素子基板を貫通する基板貫通ビアを介して行われることを特徴とする電子デバイス。
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