WO2010101163A1 - Substrat comprenant un élément fonctionnel intégré et dispositif électronique utilisant le substrat - Google Patents

Substrat comprenant un élément fonctionnel intégré et dispositif électronique utilisant le substrat Download PDF

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Publication number
WO2010101163A1
WO2010101163A1 PCT/JP2010/053382 JP2010053382W WO2010101163A1 WO 2010101163 A1 WO2010101163 A1 WO 2010101163A1 JP 2010053382 W JP2010053382 W JP 2010053382W WO 2010101163 A1 WO2010101163 A1 WO 2010101163A1
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Prior art keywords
functional element
substrate
insulating layer
wiring
layer
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PCT/JP2010/053382
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English (en)
Japanese (ja)
Inventor
山道　新太郎
大輔 大島
菊池　克
森　健太郎
中島　嘉樹
秀哉 村井
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日本電気株式会社
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Priority to JP2011502769A priority Critical patent/JPWO2010101163A1/ja
Publication of WO2010101163A1 publication Critical patent/WO2010101163A1/fr

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the present invention relates to a functional element-embedded substrate having a functional element and an electronic device using the same.
  • the wire bonding connection can be packaged at low cost when the number of pads of the semiconductor element is small. However, it is necessary to reduce the wire diameter as the pitch of the pads of the semiconductor element is narrowed, and the yield reduction in the assembly process such as wire breakage is a problem.
  • Flip chip connection has an advantage that high-speed signal transmission between a semiconductor element and a wiring board is possible compared to wire bonding connection.
  • the connection strength of the solder bumps is weakened, and defects such as the occurrence of cracks at the connection locations frequently occur.
  • Patent Document 1 a package technology in which a functional element such as a semiconductor element is incorporated, that is, a so-called functional element incorporation technology has been proposed (for example, Patent Document 1).
  • This technology realizes higher integration and higher functionality of functional elements such as semiconductor devices, and high-density mounting that realizes thinner packages, lower costs, high frequency compatibility, low stress connection, improved electromigration characteristics, etc. Expected as a technology.
  • a bump is formed on a circuit surface of a semiconductor element to be electrically connected to a semiconductor element built in the insulating substrate, and a first wiring formed on the insulating substrate via the bump.
  • the structure which electrically connects with is disclosed.
  • a second wiring is formed on the back surface of the insulating substrate, and the first wiring and the second wiring are connected to the side of the semiconductor element by a conductive post penetrating the insulating resin substrate.
  • the substrate with a built-in functional element according to an embodiment of the present invention, A functional element; An insulating layer in which the functional element is embedded; A wiring layer disposed on two main surfaces of the insulating layer; In the insulating layer, on the side of the functional element, and having an insulating layer through via for connecting between the wiring layers disposed on the two main surfaces,
  • the functional element has a through-substrate via that penetrates the substrate of the functional element, and at least part of the electrical connection between the wiring layers disposed on the two main surfaces is via the through-substrate via. This is a functional element-embedded substrate.
  • FIG. 3 is a schematic cross-sectional view illustrating an example of a structure of a functional element built-in substrate according to the first embodiment.
  • FIG. 6 is a schematic cross-sectional view illustrating an example of a structure of a functional element built-in substrate according to a second embodiment.
  • A)-(e) Process sectional drawing explaining the manufacture example of the functional element built-in board
  • FIG. FIG. 6 is a schematic cross-sectional view showing an example of the structure of a functional element built-in substrate according to Embodiment 3.
  • FIG. 10 is a schematic cross-sectional view showing an example of the structure of a functional element-embedded substrate according to Embodiment 4.
  • FIG. FIG. 6 is a schematic cross-sectional view showing an example of the structure of an electronic device according to a fifth embodiment.
  • 10 is a schematic cross-sectional view showing an example of the structure of an electronic device according to Embodiment 6.
  • FIG. (A)-(e) Process sectional drawing explaining the manufacture example of the functional element built-in board
  • FIG. 10 is a schematic cross-sectional view showing an example of the structure of a functional element-embedded substrate according to Embodiment 9.
  • a technique for reducing the mounting area of an electronic device is known.
  • the entire wiring system is classified into three as shown in FIG.
  • a group A shows a wiring system from the LSI 1001 which is a functional element to the upper package 1003 and a wiring system to a mounting board (not shown) under the functional element built-in substrate 1002, and a group B shows the LSI 1001 and the mounting board.
  • the wiring system C is a wiring system between the upper package 1003 and the mounting substrate.
  • Wiring layers are formed on both main surfaces of the functional element built-in substrate 1002, and are connected to the upper package 1003 by external terminals 1005 such as a ball grid array (hereinafter referred to as BGA). .
  • BGA ball grid array
  • the functional element built-in substrate 1002 and the mounting substrate are connected by an external terminal 1004 such as a BGA.
  • the wiring system of the group B is performed via a DSV (not shown) provided on the side of the LSI 1001. DSV is also required for Group A and Group C.
  • the LSI 1001 becomes multifunctional and the number of external terminals increases (multiple pins), the number of wires in the B group also increases, and the number of DSVs for guiding the B group wiring system to the lower side must be increased.
  • the number of DSVs formed on the functional element built-in substrate 1002 increases. Increasing the area of the functional element-embedded substrate 1002 can meet this requirement, but increases the mounting area. Therefore, in order to increase the number of DSVs without increasing the mounting area, the DSVs must be arranged at a high density.
  • the wiring system of the group B can be dropped directly to the mounting board side.
  • the A group also needs to be connected via the DSV. Therefore, when the number of pins of the LSI 1001 increases and the number of components mounted as the upper package 1003 increases, Similarly, it is necessary to increase the density of the DSV.
  • Such difficulty in securing the wiring system is not limited to the PoP shape, and may also occur when the built-in LSI has a large number of pins or a plurality of functional elements.
  • the present invention provides a highly reliable functional element-embedded substrate and an electronic device including the functional element-embedded substrate that suppresses an increase in mounting area.
  • FIG. 1 is a schematic cross-sectional view of a main part of a functional element-embedded substrate 100 according to Embodiment 1 of the present invention.
  • the functional element-embedded substrate 100 according to the first embodiment is provided on two main surfaces (an upper surface and a back surface) of a functional element 101 such as a semiconductor element typified by an LSI, an insulating layer 102 in which the functional element 101 is embedded, and the insulating layer 102.
  • a first wiring layer 103 and a second wiring layer 108 are provided.
  • the functional element 101 one or a plurality of element through vias 106 including vias penetrating the substrate constituting the functional element are formed.
  • the through-element via 106 is formed with a conductive material and can conduct from the upper surface to the lower surface of the functional element 101.
  • An insulating layer through via 107 is provided in the insulating layer 102 and connects the first wiring layer 103 and the second wiring layer 108.
  • an electronic circuit (not shown) and a pad (not shown) are formed on the upper surface (upward surface shown in the figure) of the functional element 101, and an adhesive layer 105 is formed on the lower surface of the functional element.
  • the element through via 106 also penetrates the adhesive layer 105.
  • a connection portion 104 to the first wiring layer 103 is formed on the upper surface of the functional element 101, and the first wiring layer 103 and the second wiring layer 108 are connected via an element through via 106 formed in the functional element 101. Are also electrically connected.
  • the through-element via 106 may be composed of a single member or a plurality of members.
  • a combination of a through-substrate via that penetrates the substrate constituting the functional element and a post electrode that penetrates a protective layer that protects the semiconductor substrate may be used.
  • the wiring path may be configured by connecting the wiring circuit on the functional element and the through-substrate via.
  • Such a through-substrate via is preferably formed before the functional element is formed.
  • a via hole may be formed after the functional element is formed, and the via hole may be filled with a conductive material.
  • the portion penetrating the substrate is a through-substrate via.
  • the material of the element through via 106 may be any material as long as it has conductivity, but a metal such as Cu or Al, an alloy thereof, or conductive metal oxidation. Or a filler (conductive paste) to which conductive fine particles are added, or a conductive polymer in which the polymer itself is conductive.
  • via holes are formed after the functional elements are formed, and through-element vias are formed by filling with a conductive paste.
  • a copper post was formed in a portion penetrating the adhesive layer 105.
  • the functional element for forming the through-element via it is preferable to select a functional element having a relatively large area among the functional elements.
  • a semiconductor element such as an LSI has a relatively large chip size and is suitable for forming a through-via.
  • an element through via is not provided in an element that affects the function of the element by providing a current path in the substrate such as a coil component.
  • the substrate of the functional element is, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), gallium nitride (GaN), silicon carbide (SiC) to form a semiconductor element.
  • a semiconductor substrate such as zinc oxide (ZnO) can be used. Further, II-VI group compounds, III-V group compounds, diamond, etc. exhibiting semiconductor characteristics may be used.
  • an inorganic substrate such as a silica substrate or a sapphire substrate, or an insulating substrate such as an organic resin may be used. Further, a combination of a semiconductor material such as an SOI substrate and an insulating material may be used. Of course, it is not limited to these.
  • a semiconductor element having a silicon substrate is used as the functional element 100.
  • the number of functional elements 101 incorporated in the functional element-embedded substrate 100 is not limited to one, and a plurality of functional elements 101 can be provided.
  • a plurality of functional elements 101 may be stacked in the Y direction in FIG. 1 in addition to an aspect in which a plurality of functional elements are disposed in the X direction in FIG. Further, when a plurality of functional elements are incorporated in this way, the through-element via 106 and the through-substrate via are not necessarily provided in all the functional elements.
  • the position where the element through via 106 is disposed is not particularly limited, and may be disposed in consideration of the arrangement of the electronic circuit formed in the functional element 101 and the relationship between the first wiring layer 103 and the second wiring layer 108. Well, it is not limited to a strict arrangement.
  • the individual shape of the element through via 106 is not particularly limited, and may be, for example, a polygonal shape such as a circle or a rectangle, a shape surrounded by a curve, or a combination thereof.
  • the diameters of the element through via 106 and the substrate through via are not particularly limited, but can be, for example, about 10 ⁇ m to 100 ⁇ m.
  • the insulating layer 102 can be formed using, for example, a photosensitive or non-photosensitive organic material.
  • the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), and polynorbornene resin.
  • a material obtained by impregnating a woven fabric or a nonwoven fabric formed of glass cloth, aramid fiber, or the like with a resin selected from these resin groups may be used.
  • an epoxy resin is used as the insulating layer 102.
  • the adhesive layer 105 is preferably a semi-cured resin called a die attachment film (DAF), a resin paste such as epoxy resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or silver paste. It is. Of course, it is not limited to these. In the first embodiment, DAF mainly composed of epoxy resin is used.
  • the first wiring layer 103 and the second wiring layer 108 are, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium, or these as main components.
  • An alloy as a component or a conductive resin made of a resin containing a conductive filler is suitable, but is not limited thereto. From the viewpoint of electrical resistance value and cost, it is desirable to form with copper. In Embodiment 1, copper was used.
  • the element connection via 104 is formed by filling a via hole penetrating from the surface of the insulating layer 102 to the pad (not shown) of the functional element 101 with a conductor.
  • the element connection via 104 can be formed simultaneously with the formation of the first wiring layer 103 by forming a via hole in the insulating layer 102 with a laser, for example.
  • a device in which a metal bump or the like is previously formed on the functional element 101 can be suitably applied as the element connection via 104.
  • a via hole can be formed by a photolithography technique.
  • the element connection via 104 may be directly connected to the element through via 106.
  • a via hole is opened using a laser, and copper is filled in the via hole by plating.
  • the number of element connection vias 104 needs to be increased in the conventional functional element built-in substrate.
  • FIG. The number of element connection vias can be reduced by covering part of the wiring system of the A group and the B group described in 11 with the element through vias.
  • the insulating layer through via 107 can be formed without increasing the via density and the aspect ratio even when the number of built-in elements is increased. As a result, the mounting area of the functional element built-in substrate can be increased without increasing the mounting area of the built-in element. Further, when a functional element having the same number of terminals as that in the prior art is incorporated, the number of vias through the insulating layer can be reduced, so that the manufacturing yield can be further improved and the mounting area can be further reduced.
  • the insulating layer through via 107 is configured by a conductor disposed in a via hole penetrating from the first main surface of the insulating layer 102 to the surface of the second wiring layer 108.
  • the formation method can be the same as the element connection via 104, and is preferably formed simultaneously with the element connection via 104.
  • FIG. 1 An example in which a plurality of through-element vias 106 are connected to one wiring of the second wiring layer 108 is shown.
  • This is, for example, a wiring system that can share a ground potential or the like. Suitable for connecting.
  • through-element vias are connected to individual wirings as in the embodiments described later, this is suitable for connection to individual wiring systems such as signal potentials.
  • Such a connection method can be appropriately changed by those skilled in the art.
  • the functional element built-in substrate may be warped or swelled depending on the process of incorporating the functional element and the use environment. By providing this, it is possible to suppress these warpage and undulation and to improve the reliability. In particular, the temperature cycle test characteristics can be improved. Furthermore, since the wiring yield of the built-in substrate is improved due to the low warpage, the loss of discard of non-defective semiconductor elements due to wiring defects can be reduced, and the manufacturing cost can be reduced. Furthermore, the low warpage makes it possible to further miniaturize the wiring of the built-in substrate, and to reduce the cost by reducing the number of wiring layers.
  • the strength of the semiconductor element is not deteriorated, and the entire thickness of the semiconductor element-embedded substrate can be reduced.
  • the handling property when the semiconductor element is thinned can be improved, and the manufacturing yield can be improved.
  • the element through via 106 is disposed in the vicinity of the element peripheral portion which is the stress concentration position. Further, from the viewpoint of dispersing the partial stress concentration in the element substrate, it is preferable that the element substrate is disposed point-symmetrically or line-symmetrically in plan view. Furthermore, the element through via according to the present invention and a substrate opening that suppresses such warpage and undulation (a through hole or a recess formed in the semiconductor substrate, which may be filled with a low elasticity resin or the like). May be combined.
  • the functional element-embedded substrate 200 according to the second embodiment has the same basic configuration as that of the first embodiment except for the following points. That is, in the first embodiment, the adhesive layer 105 is provided below the functional element 101, whereas in the second embodiment, the adhesive layer 105 is not provided, and the upper and lower sides of the functional element-embedded substrate are not provided.
  • the wiring layer is different in that it is formed in multiple layers.
  • the functional element built-in substrate 200 includes a functional element 201 to be incorporated, a first insulating layer 202 in which the functional element is embedded, a first wiring layer 203 and a third wiring layer 212 above the functional element 201.
  • the fifth wiring layer 215 includes a second wiring layer 208, a fourth wiring layer 218, and a sixth wiring layer 221 below the functional element.
  • one or a plurality of through-element vias 206 are formed on the substrate of the functional element 201.
  • the through-element via 206 is formed with a conductive material and can conduct from the upper surface to the lower surface of the functional element.
  • the first insulating layer 202 is provided with a first insulating layer through via 207 to connect the first wiring layer 203 and the second wiring layer 208.
  • the first wiring layer 203 is connected to the third wiring layer 212 by a connection via 211 formed in the second insulating layer 209, and the third wiring layer 212 is connected by a connection via 214 formed in the fourth insulating layer 213.
  • the fifth wiring layer 215 is connected.
  • the second wiring layer 208 is formed in the third insulating layer 210, and the second wiring layer 208 is connected to the fourth wiring layer 218 by connection vias 217 formed in the fifth insulating layer 216.
  • the fourth wiring layer 218 is connected to the sixth wiring layer 221 by connection vias 220 formed in the seventh insulating layer 219.
  • This example shows a case where an electronic circuit (not shown) or a pad (not shown) is formed on the upper surface (upper surface shown in the figure) of the functional element 201, and a plurality of second elements are formed on the lower surface of the functional element.
  • a wiring layer 208 is provided.
  • the through-element vias 206 are connected to individual wirings of the second wiring layer 208, respectively.
  • An element connection via 204 that connects the first wiring layer 203 is formed on the upper surface of the functional element 201, and the first wiring layer 203 and the second wiring layer 208 include an element through via 206 formed in the functional element 201. It is also electrically connected via.
  • Each wiring layer and connection via can be selected from the same materials as in the first embodiment.
  • copper is used for each wiring layer and connection via.
  • the second wiring layer 208 is formed on the main surface of the support body 250. Then, the support body 250 and the second wiring layer 208 are covered with the third insulating layer 210 (see FIG. 3A).
  • the support body 250 any one of resin, metal, glass, semiconductor, ceramic, or a combination thereof can be used. Further, in order to clarify the position where the functional element 201 is mounted, a position mark (not shown) may be appropriately provided on the support body 250.
  • a copper alloy is used as the support body 250. Further, as a position mark for mounting the functional element 201, nickel having a thickness of 5 ⁇ m was provided by electroplating.
  • the second wiring layer 208 can be formed by a method such as a subtractive method, a semi-additive method, or a full additive method.
  • the subtractive method is a method in which a resist having a desired pattern is formed on a metal layer (copper foil) provided on a substrate, an unnecessary metal layer is etched, and then the resist is removed to obtain a desired pattern.
  • a power supply layer is formed by an electroless plating method, a sputtering method, a CVD method, etc., a resist having an opening in a desired pattern is formed, and a metal is deposited in the resist opening by an electrolytic plating method.
  • a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating film.
  • a desired wiring pattern is obtained by depositing metal.
  • copper is used as the second wiring layer 208 and is formed by a semi-additive method and then covered with the third insulating layer 210.
  • a suitable material for the third insulating layer 210 may be the same material as the insulating layer 102 described in the first embodiment.
  • a transfer molding method, a compression molding method, a printing method, a vacuum press method, a vacuum laminating method, a spin coating method, a die coating method, a curtain coating method, a photolithography method, or the like is applied. be able to.
  • the third insulating layer 210 is formed by vacuum lamination using an epoxy resin.
  • the functional element 201 in which the element through via 206 is formed is prepared. Then, the functional element 201 is mounted on the upper layer of the support 250 at a predetermined position so that the second wiring layer 208 and the element through via 206 are connected (see FIG. 3B).
  • a solder material such as tin may be inserted into the joint interface between the element through via 206 and the second wiring layer 208.
  • the first insulating layer 202 is formed so as to cover the third insulating layer 210 and the functional element 201 (see FIG. 3C).
  • the through-element via 206 can be provided at an arbitrary place as long as the mechanical strength of the functional element 201 is not lowered.
  • the substrate material of the functional element for example, the material described in the first embodiment can be suitably applied.
  • a silicon LSI is used as the substrate material of the functional element.
  • the functional element 201 was mounted on the support 250 using a semiconductor mounting machine in a face-up state.
  • the material described in the first embodiment can be preferably applied to the through-element via 206.
  • the element through via 206 is formed by plating after forming a via hole in the functional element 201 using copper.
  • the first insulating layer 202 is formed so as to embed the functional element 201.
  • a material of the first insulating layer 202 for example, the material of the insulating layer 102 described in the first embodiment can be preferably applied.
  • the method for incorporating the functional element 201 is as described in the first embodiment.
  • a via hole 241 penetrating from the surface of the first insulating layer 202 to the surface of the pad (not shown) of the functional element 201 is provided.
  • a via hole 242 that penetrates from the surface of the first insulating layer 202 to the surface of the second wiring layer 208 is formed (see FIG. 3D).
  • the via holes 241 and 242 are formed using a laser processing method.
  • a conductor is formed inside the via holes 241 and 242, and the first wiring layer 203 is formed on the first insulating layer 202 (see FIG. 3E).
  • the element connecting via 204 is formed by filling the via hole 241 with a conductor
  • the first insulating layer through via 207 is formed by filling the via hole 242 with the conductor.
  • Suitable examples of these conductor materials and formation methods are as described in the first embodiment.
  • the material and the method described in the second wiring layer can be suitably applied to the material and the forming method of the first wiring layer 203.
  • copper is used and the first wiring layer 203 is formed by a semi-additive method.
  • the support body 250 is removed (see FIG. 3F).
  • the removal of the support 250 is preferably a wet etching method using a chemical solution, a grinding method using mechanical polishing, a physical peeling method, or the like, but is not limited thereto.
  • the support body 250 which is a copper alloy was removed using alkaline wet etching liquid.
  • a second insulating layer 209 described below may be formed.
  • the second insulating layer 209, the connection via 211, the third wiring layer 212, the fourth insulating layer 216, the connection via 217, and the fourth wiring layer 218 are formed (see FIG. 3G).
  • Suitable materials for the second insulating layer 209 and the fourth insulating layer 216 are as described above.
  • it can form by the method similar to the 3rd insulating layer 210 mentioned above, for example.
  • the second insulating layer 209 and the fourth insulating layer 216 are formed by vacuum lamination using an epoxy resin.
  • a method of forming the connection vias 211 and 217 in the second insulating layer 209 and the fourth insulating layer 216 is not particularly limited, but the same method as the element connection via 204 and the first insulating layer through via 207 is preferably applied. can do.
  • an opening is formed using a laser processing method, and is filled with copper.
  • the third wiring layer 212 and the fourth wiring layer 218 were formed by a semi-additive method using copper.
  • a fifth insulating layer 213, a connection via 214, a fifth wiring layer 215, a sixth insulating layer 219, a connection via 220, and a sixth wiring layer 221 are formed (see FIG. 3H).
  • Suitable materials for the fifth insulating layer 213 and the sixth insulating layer 219 are as described above.
  • it can form by the method similar to the 2nd insulating layer 210 mentioned above, for example.
  • the method for forming the connection vias 214 and 220, the fifth wiring layer 215, and the sixth wiring layer 221 is the same as described above.
  • the first insulating layer penetrating via 207 penetrating only the first insulating layer 202 has been described as the insulating layer penetrating via on the side of the functional element 201.
  • the plural penetrating insulating layers are penetrated.
  • An insulating layer through via may be used.
  • a via penetrating from the fifth insulating layer 213 to the sixth insulating layer 219 may be provided so as to directly connect the fifth wiring layer 215 and the sixth wiring layer 221.
  • the functional element-embedded substrate 300 according to the third embodiment has the same basic configuration as that of the first embodiment except for the following points. That is, as shown in the schematic cross-sectional view of FIG. 4, the adhesive layer 105 is provided below the functional element 101 in the first embodiment, whereas the lower part of the functional element 301 is present in the third embodiment. Is not provided with an adhesive layer 105, and the first wiring layer 303 and the second wiring layer 308 are protected by solder resist layers 332 and 331, and an external terminal 333 connected to an external substrate (not shown) is provided. It is provided in the opening of the solder resist layer 331. In FIG. 4, reference numerals 301 to 308 correspond to reference numerals 101 to 108 in FIG.
  • FIG. 5 shows a schematic cross-sectional view of a functional element-embedded substrate 400 according to the fourth embodiment.
  • the fourth embodiment is the same as the second embodiment except that a solder resist layer 431 and an external terminal 433 are provided below the functional element-embedded substrate 200 of the second embodiment.
  • reference numerals 401 to 421 correspond to reference numerals 201 to 221 in FIG. 2, respectively.
  • solder resist layers 332, 331, and 431 By providing the solder resist layers 332, 331, and 431 in the third and fourth embodiments, the surface circuit of the functional element-embedded substrate can be protected and flame retardancy can be imparted.
  • solder resist layer a photosensitive resist ink was used.
  • the number of wiring layers and insulating layers is only an example, and it goes without saying that the required number of wiring layers and insulating layers can be stacked without being limited to the above embodiment.
  • the functional device when the wiring system of the group B shown in FIG. 11 is increased by increasing the functionality of the functional device (increasing the number of pins), the functional device is penetrated in addition to the insulating layer through via on the side of the functional device. Since it has a wiring system using through-element vias, it is possible to cope with further diversification without requiring high density and high aspect ratio of through-layer vias.
  • the electronic device 500 according to the fifth embodiment has a PoP shape by mounting an upper package 536 on a functional element-embedded substrate.
  • the structure below the second wiring layer 512 is the same as that of the fourth embodiment, and reference numerals 501 to 512, 516 to 521, 531 and 533 in FIG. 6 denote reference numerals 401 to 412 and 416 to 421 in FIG. The same meaning as 431,433 is shown.
  • the second wiring layer 512 is protected by a solder resist layer 532 and is connected to the upper package 536 by an external terminal 534 such as a BGA provided in the upper package 536.
  • the upper package 536 is fixed to the solder resist layer 532 on the functional element-embedded substrate with an adhesive layer 535.
  • the element formation surface of the functional element 501 built in the first insulating layer 502 faces the upper package 536, and the wiring systems of the groups A to C shown in FIG. This is performed through the first insulating layer through via 507 provided on the side of the element 501.
  • a part of the wiring system of the A to C groups is also performed through the element through via 506 provided in the functional element 501. Therefore, when the functional element 501 becomes multifunctional and the number of external terminals increases (multiple pins) and the number of wires in the B group also increases, a path for guiding the wiring system of the B group downward is provided in the first insulating layer.
  • the wiring system can be secured without increasing the mounting area.
  • FIG. 7 A modification of the fifth embodiment will be described as a sixth embodiment.
  • the electronic device 600 according to the sixth embodiment has the functional element built-in substrate turned upside down.
  • Reference numerals 601 to 618 in FIG. 7 have the same meanings as reference numerals 501 to 518 in FIG. 5, and reference numerals 631 to 636 are the same as reference numerals 531 to 536 in FIG.
  • the element formation surface of the functional element 601 faces downward on the mounting substrate (not shown) side, and the group B wiring system shown in FIG. 11 can be dropped directly on the mounting substrate side. it can.
  • the group A can secure two systems of the first insulating layer through via 607 and the element through via 606, increase the number of functional elements 601 and mount as the upper package 636. Even if the number of pins to be used is increased, it can be handled. Further, the wiring system of the group C can be dealt with by two systems of the first insulating layer through via 607 and the element through via 606.
  • a functional element such as an LSI is designed such that an element formation surface is mounted upward in an element for wire bonding, and an element formation surface is mounted downward in an element for flip chip mounting.
  • an element for wire bonding is mounted downward or an element for flip chip mounting is mounted upward, (i) an LSI IP core layout, (ii) a multilayer wiring of an LSI-embedded substrate, (iii) on a mounting substrate (motherboard)
  • a mounting substrate motherboard
  • Embodiment 5, 6 is an example, Comprising: It is not limited to these.
  • another electronic component may be mounted at a desired position.
  • the LCR element which plays the role of the noise filter of a circuit can be provided.
  • a MEMS component, a sensor, an energy device, an optical component, etc. may be mounted or built in as a passive component.
  • various modifications can be made without departing from the spirit of the present invention.
  • the wiring system of these components can be performed not only by the first insulating layer through vias 507 and 607 but also by two systems of the element through vias 506 and 606.
  • FIGS. 8A to 8K illustrate a manufacturing process of the functional element-embedded substrate 700 according to the seventh embodiment, and show a modification of the fourth embodiment.
  • the functional element-embedded substrate 700 according to the seventh embodiment has the same basic configuration as that of the fourth embodiment except for the following points. That is, the sixth wiring layer 421 is formed on the lower surface of the sixth insulating layer 419 in the drawing in the fourth embodiment, whereas in the seventh embodiment, the sixth wiring layer 721 is formed. Is different in that the sixth insulating layer 719 is formed on the upper inner surface side in the drawing. This is based on the difference in manufacturing method.
  • a sixth wiring layer 721 is formed on the main surface of the support 750 (see FIG. 8A). Then, the support 750 and the sixth wiring layer 721 are covered with the sixth insulating layer 719, the connection via 720 and the fourth wiring layer 718 are formed in the same manner as described above, and the sixth insulating film 719 and the fourth wiring layer are formed as the fourth. Cover with an insulating layer 716. Further, a connection via 717 is formed (see FIG. 8B).
  • the support body 750 what was illustrated in the said Embodiment 2 can be used. Further, in order to clarify the position where the functional element 701 is mounted, a position mark (not shown) may be provided as appropriate on the support 750.
  • a copper alloy is used as the support 750.
  • the second wiring layer 708 After forming the second wiring layer 708 on the fourth insulating layer, the second wiring layer 708 is covered with the third insulating layer 710 (see FIG. 8C).
  • a functional element 701 having a through-element via 706 is prepared. Then, the functional element 701 is mounted on the upper layer of the predetermined position of the support 750 so that the second wiring layer 708 and the element through via 706 are connected (see FIG. 8D). After that, the first insulating layer 702 is formed so as to cover the third insulating layer 710 and the functional element 701. The functional element 701 was mounted on the support 750 using a semiconductor mounting machine in a face-up state.
  • the material described in the first embodiment can be suitably applied to the element through via 706.
  • the element through via 706 is formed by plating after forming a via hole in the functional element 701 using copper.
  • the first insulating layer 702 is formed so as to embed the functional element 701.
  • a material of the first insulating layer 702 for example, the material of the insulating layer 102 described in Embodiment 1 can be preferably applied.
  • the method for incorporating the functional element 701 is as described in the first embodiment.
  • a via hole 741 penetrating from the surface of the first insulating layer 702 to the surface of the pad (not shown) of the functional element 701 is provided.
  • a via hole 742 penetrating from the surface of the first insulating layer 702 to the surface of the second wiring layer 708 is formed (see FIG. 8E).
  • the via holes 741 and 742 are formed using a laser processing method.
  • a conductor is formed inside the via holes 741 and 742, and a first wiring layer 703 is formed on the first insulating layer 702 (see FIG. 8F).
  • the via hole 741 With a conductor, the element connection via 704 is formed, and by filling the via hole 742 with a conductor, the first insulating layer through via 707 is formed.
  • Suitable examples of these conductor materials and formation methods are as described in the first embodiment.
  • the materials and methods described in the above wiring layers can be suitably applied to the material and forming method of the first wiring layer 703.
  • copper is used and the first wiring layer 703 is formed by a semi-additive method.
  • first insulating layer 702 and the first wiring layer 703 are covered with the second insulating layer 709, and the connection via 711 and the third wiring layer 712 are similarly formed (see FIG. 8G). Further, the second insulating layer 709 and the third wiring layer 712 are covered with the third insulating layer 713, and the connection via 714 and the fifth wiring layer 715 are similarly formed (see FIG. 8H).
  • the support 750 is removed (see FIG. 8 (i)).
  • the support 750 was removed by removing the support 750, which is a copper alloy, using an alkaline wet etching solution.
  • a solder resist layer 731 having an opening is formed on the sixth wiring layer 721 (see FIG. 8J). Thereafter, an external terminal 733 such as a BGA connected to the sixth wiring layer 721 is formed on the solder resist layer 731 side.
  • the method for manufacturing a functional element-embedded substrate according to the seventh embodiment since all the wiring layers can be formed on the support 750, the warpage during the manufacturing process is small, and the manufacturing yield can be improved. .
  • the functional element-embedded substrate according to the seventh embodiment can obtain the same effects as those of the fourth embodiment.
  • the insulating layer (first insulating layer) that fills the functional element is formed of one type of insulating layer, but the present invention is not limited to this, and is configured of two or more types of insulating layers. It may be.
  • the eighth embodiment will be described with reference to the process cross-sectional view of FIG.
  • the configuration of the functional element-embedded substrate 800 shown in FIG. 9 will be described as a modified example of the first embodiment, but it goes without saying that it can be applied to other embodiments.
  • the second wiring layer 808 is formed on the support 850 (see FIG. 9A).
  • the insulating layer 802 is stacked on the support 850 and the second wiring layer 808.
  • the material exemplified as the insulating layer 102 of the first embodiment can be used, but in the eighth embodiment, a material having higher mechanical strength can be used.
  • an epoxy resin containing an inorganic filler is used.
  • Such an insulating layer with increased mechanical strength can form a via having a large diameter, but it may be difficult to form a fine via. In particular, it is difficult to accurately form fine vias such as element connection vias that connect the functional elements and the wiring layers.
  • an insulating layer that forms an insulating layer through via that connects the first wiring layer and the second wiring layer, and an insulation that forms an element connection via that connects the first wiring layer and the functional element.
  • the layers are composed of different insulating layers.
  • an opening 802A is formed at a position where the functional element of the insulating layer 802 is mounted. Subsequently, a functional element 801 having an element through via 806 is installed in the opening 802A.
  • an adhesive layer 805 such as DAF is provided as in the first embodiment, and the element through via 806 also penetrates the adhesive layer 805.
  • an insulating material 861 is filled in the opening 802A.
  • the insulating material 861 is filled with a material that can be easily processed, such as an epoxy resin that does not contain an inorganic filler. Alternatively, a photosensitive organic material may be filled.
  • via holes 842 for through-layer vias are formed in the insulating layer 802, and via holes 841 for element connection vias are formed in the insulating material 861 (see FIG. 9D).
  • the element connection via 804, the insulating layer through via 807, and the first wiring layer 803 are formed in the same manner as in the first embodiment (see FIG. 9E), and finally the support 850 is removed, A functional element-embedded substrate 800 according to the embodiment is formed (see FIG. 9F).
  • the element mounting portion may be previously punched out of a semi-cured material (glass prepreg) in which a glass cloth or the like is impregnated with a resin, and bonded and then cured.
  • a semi-cured material glass prepreg
  • an insulating layer having high mechanical strength can be adopted, and the overall mechanical strength of the functional element built-in substrate and the electronic device using the same can be increased.
  • the element through via is formed in the functional element, a sufficient wiring path can be secured even if a via having a large diameter is formed in the insulating layer having high mechanical strength. The same effect can be obtained when a skin layer is formed by using a glass prepreg having an opening in the element built-in portion as a core layer and filling a material having good processability around the element and the formation surface of the wiring layer. .
  • the functional element-embedded substrate 900 according to the ninth embodiment describes a case where the plurality of functional elements described in the first embodiment are stacked in the X direction.
  • the case where the circuit forming surfaces of the two functional elements 901a and 901b are stacked to face each other will be described.
  • the present invention is not limited to this, and the circuit forming surface faces the same direction or faces the other direction. Even if it is, it can be applied.
  • the functional elements 901a and 901b are embedded in the first insulating layers 902a and 902b, respectively, and the first insulating layer through vias 907a and 907b are respectively provided on the side of the functional elements.
  • An element connection via 904a and a first wiring layer 903a are formed on the circuit forming surface side of the functional element 901a, and a second wiring layer 908a is formed on the back surface side.
  • an element connection via 904b and a first wiring layer 903b are formed on the circuit forming surface side of the functional element 901b, and a second wiring layer 908b is formed on the back surface side.
  • the functional element 901a has a through-element via 906, and the functional element 901b has no through-element via.
  • Such a functional element-embedded substrate 900 is manufactured by forming the laminated structure indicated by a and b in the drawing in accordance with the manufacturing process of the second embodiment described above, and then forming the circuit of the functional element 901a and the functional element 901b. It can be easily carried out by pasting together so that the surfaces face each other. That is, the laminated structure a can be manufactured by forming the steps shown in FIGS. 3A to 3E and further forming the second insulating layer 909a and the connection via 911a, and the laminated structure b can be produced by the steps shown in FIGS. e) through the process shown in e), and finally the laminated structures a and b are bonded together using the second insulating layer 909b as an adhesive layer.
  • the group A to C wiring systems exist, and the first insulating layer through via 907a provided on the side of the functional element 901a is provided. Will be done through. Further, a part of the wiring system of the groups A to C is also performed through the element through via 906 provided in the functional element 901a.
  • the first route for guiding the B group wiring system to the lower side This can be performed by two systems of the insulating layer through via 907a and the element through via 906, and it is not necessary to increase the density of the first insulating layer through via 907a.
  • the wiring system can be secured without increasing the mounting area.
  • the upper package is mounted on the functional element built-in substrate 900, it is not necessary to increase the density of the first insulating layer through via 907b by providing the functional element 901b with an element through via.
  • the insulating layer through vias are provided in the first insulating layers 902a and 902b, respectively.
  • vias that directly connect the second wiring layers 908b and 908a may be formed.
  • the indications “first”, “second”, and “third” in the present embodiment are for convenience of explanation of the manufacturing method, and include cases that are different from the above-described embodiments. Needless to say.

Abstract

La présente invention concerne un substrat comprenant un élément fonctionnel intégré qui comprend : l'élément fonctionnel ; une couche isolante dans laquelle est intégré l'élément fonctionnel ; des couches d'interconnexion disposées sur les deux faces principales de la couche isolante ; et une couche intermédiaire pénétrant la couche isolante, qui est réalisée sur le côté de l'élément fonctionnel à l'intérieur de la couche isolante et qui établit la connexion entre les couches d'interconnexion. L'élément fonctionnel comprend une couche intermédiaire pénétrant le substrat, qui pénètre le substrat de l'élément fonctionnel, et au moins une partie de la connexion électrique entre les couches d'interconnexion est réalisée via la couche intermédiaire pénétrant le substrat. L'utilisation du substrat comprenant l'élément fonctionnel intégré permet d'obtenir un système de câblage satisfaisant, sans augmenter la zone de montage du substrat même lorsque l'élément fonctionnel est doté de fonctions importantes.
PCT/JP2010/053382 2009-03-04 2010-03-03 Substrat comprenant un élément fonctionnel intégré et dispositif électronique utilisant le substrat WO2010101163A1 (fr)

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