WO2010088465A1

WO2010088465A1 - Improved digital image processing and systems incorporating the same

Info

Publication number: WO2010088465A1
Application number: PCT/US2010/022511
Authority: WO
Inventors: Jeremy C. Andrus; Jon H. Bechtel; Tom B. Sherman
Original assignee: Gentex Corporation
Priority date: 2009-02-02
Filing date: 2010-01-29
Publication date: 2010-08-05
Also published as: US8577169B2; US20100195908A1; US20100195901A1; US9866805B2

Abstract

Algorithms for improving the quality of images tone mapped using a bilateral filter is presented. The algorithms involve a localized operator applied to the tone mapping compression factor which enhances apparent image contrast in the low dynamic range output of the tone mapping. In at least one embodiment, a spectrally mosaiced digital image is provided with missing color data. At least one embodiment of the present invention is related to circuitry configured to perform at least a portion of related calculations.

Description

IMPROVED DIGITAL IMAGE PROCESSING AND SYSTEMS INCORPORATING THE SAME

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of U.S. Provisional Patent Application S/Ns:

61/149,049, filed February 2, 2009; 61/155,691, filed February 26, 2009; 61/181,770, filed May 28, 2009; and 61/222,532, filed July 2, 2009, under 35 U.S.C. 119(e), the entire content of each is incorporated herein by reference.

INTRODUCTION

[0002] It has become desirable to obtain a first series of high dynamic range digital images from high dynamic range digital sources, demosaic the first series of high dynamic range digital images to obtain a second series of digital images having missing color data for each pixel of the first series imputed. It has become desirable to obtain a series of high dynamic range digital images from high dynamic range digital sources, convert said series of high dynamic range digital images to a second series of digital images having a lower dynamic range and display the series of digital images having a lower dynamic range on a display. It should be understood that the second series of digital images having missing color data for each pixel of the first series imputed may constitute the high dynamic range digital image source.

[0003] Commonly assigned U.S. Provisional Patent Applications S/N 60/900,588, S/N

60/902,728 and S/N 61/008,762; U.S. Patent Applications S/N 11/999,623, filed December 6, 2007, S/N 12/082,215, filed April 9, 2008, S/N 12/150,234, filed April 25, 2008, and S/N 12/157,476, filed June 11, 2008; and Taiwanese Patent Application No. 97103404, filed January 30, 2008 describe high dynamic range sources for use with the present invention. The disclosures of each of the above are incorporated in their entireties herein by reference.

[0004] Commonly assigned U.S. Provisional Application No. 60/780,655 filed on March 9,

2006; U.S. Provisional Application No. 60/804,351 filed on June 9, 2006; U.S. Patent Application Publication Number 2008/0068520, filed on March 9, 2007; U.S. Patent Application S/N 12/193,426, filed on August 18, 2008; U.S. Patent Application S/N 12/570,585, filed September 30, 2009; and U.S. Provisional Patent Application S/N 61/286,452, filed December 15, 2009 describe various displays for use with the present invention. The entire disclosures of each of these applications are incorporated herein by reference.

[0005] It should be understood that a source for high dynamic range digital images may be synthetic in nature; a high dynamic range digital image may be synthesized from a series of images of a give scene, where each image is acquired with varying exposures. It also should be understood that any commercially available display may be incorporated. In at least one embodiment, a high dynamic range digital image having 5,000,000-to-l dynamic range is received and a second digital image is produced having a dynamic range of 256-to-l .

BRIEF DESCRIPTION OF THE FIGURES

[0006] Fig. 1 depicts a plan view of a controlled vehicle proximate other vehicles on a roadway;

[0007] Fig. 2 depicts a plan view of a controlled vehicle having various systems;

[0008] Figs. 3a and 3b depict perspective views of a rearview assembly for a controlled vehicle; [0009] Fig. 4 depicts an exploded, perspective, view of a controlled vehicle accessory module;

[0010] Fig. 5 depicts a profile view of a digital camera;

[0011 ] Fig. 6 depicts a digital image compressed using a Durand and Dorsey bilateral tone mapping operator; [0012] Fig. 7 depicts a digital image compressed using the tone mapping algorithm of the present invention; [0013] Fig. 8 depicts equations employed in algorithms of at least one embodiment of the present invention; [0014] Fig. 9 depicts a graph including the global component for various tone mapping equations; [0015] Fig. 10 depicts three rational expressions for a factor in a modified tone mapping expression;

[0016] Fig. 11 depicts a graph of five tone mapping operators;

[0017] Fig. 12 depicts a block diagram of a system incorporating the present invention;

[0018] Fig. 13 depicts an array of pixel values that are used to calculate a bilateral filter value;

[0019] Figs. 14 and 15 depict steps illustrating the layout of a pixel array;

[0020] Fig. 16 depicts a storage array for pixel values used to compute a bilateral tone mapping filter value with a 7 x 7 kernel; [0021] Fig. 17 depicts a 9 x 9 kernel;

[0022] Fig. 18 depicts a 5 x 5 kernel;

[0023] Fig. 19 depicts a storage array for pixel values used to compute a bilateral tone mapping filter value with a 5 x 5 kernel; [0024] Figs. 20A-L represent various examples of pixel patters and their associated keys generated and used by the apparatus of Fig. 22; [0025] Fig. 21 depicts a table of product term multipliers used by selectable interpolation equations to calculate missing color data; [0026] Fig. 22 depicts a simplified schematic of an embodiment of the present invention implementing an averaging based algorithm; [0027] Fig. 23 depicts an extended table of product term multipliers to supplement those of Fig.

21; [0028] Figs. 24A-E depict a direction classifier for multiple fine line features of a digital image; [0029] Fig. 25 depicts classification of pixels near the border of a digital image used to provide missing color data interpolation calculations; [0030] Fig. 26 depicts an example data storage for a system in accordance with the present invention; [0031] Fig. 27 depicts a simplified flow diagram of the operation of a device configured to accept data associated with a digital image having missing color data for each pixel; and [0032] Fig. 28 depicts a simplified schematic of a preferred embodiment of the present invention implementing a multi-pattern based algorithm.

DETAIL DESCRIPTION

[0033] Referring initially to Fig. 1 , for illustrative purposes, an automatic vehicle equipment control system 106 is shown to be installed within a controlled vehicle 105. Although the control system 106 is depicted to be integral with the interior rearview mirror assembly, it should be understood that the control system, or any of the individual components thereof, may be mounted in any suitable location within the interior, or on the exterior, of the controlled vehicle 105. The term "controlled vehicle" is used herein with reference to a vehicle comprising an automatic vehicle exterior light control system. Suitable locations for mounting the associated image sensor are those locations that provide an unobstructed view of the scene generally forward of the controlled vehicle 105 and allow for detection of headlights 116 of oncoming vehicles 115 and taillights 111 of leading vehicles 110 within the glare zone 108 associated with the controlled vehicle. Fig. 2 depicts a controlled vehicle 205 comprising an interior rearview mirror assembly

206 incorporating an automatic vehicle exterior light control system. The processing and control system functions to send configuration data to the imager, receive image data from the imager, to process the images and to generate exterior light control signals. Detailed descriptions of such automatic vehicle exterior light control systems are contained in commonly assigned U.S. Patent numbers 5,837,994, 5,990,469, 6,008,486, 6,130,448, 6,130,421, 6,049,171, 6,465,963, 6,403,942, 6,587,573, 6,611,610, 6,621,616, 6,631,316 and U.S. Patent application serial numbers 10/208,142, 09/799,310, 60/404,879, 60/394,583, 10/235,476, 10/783,431, 10/777,468 and 09/800,460; the disclosures of which are incorporated herein in their entireties by reference. The controlled vehicle is also depicted to include a driver's side outside rearview mirror assembly 210a, a passenger's side outside rearview mirror assembly 210b, a center high mounted stop light (CHMSL) 245, A-pillars 250a, 250b, B-pillars 255a, 255b and C-pillars 260a, 260b; it should be understood that any of these locations may provide alternate locations for an image sensor, image sensors or related processing and, or, control components. It should be understood that any, or all, of the rearview mirrors may be automatic dimming electro-optic mirrors. The controlled vehicle is depicted to include a host of exterior lights including head- lights 220a, 220b, foil weather lights 230a, 230b, front turn indicator/hazard lights 235a, 235b, tail lights 225a, 225b, rear turn indicator lights 226a, 226b, rear hazard lights 227a, 227b and backup lights 240a, 240b. It should be understood that additional exterior lights may be provided, such as, separate low beam and high beam headlights, integrated lights that comprise multipurpose lighting, etc. It should also be understood that any of the exterior lights may be provided with positioners (not shown) to adjust the associated primary optical axis of the given exterior light. It should be understood that the controlled vehicle of Fig. 2 is generally for illustrative purposes and that suitable automatic vehicle exterior light control systems, such as those disclosed in the patents and patent applications incorporated herein by reference, may be employed along with other features described herein and within disclosures incorporated herein by reference. In at least one embodiment, a plurality of imaging devices are incorporated in a vehicle vision system along with at least one display configured to provide the driver with a "bird's eye" view of the area surrounding the controlled vehicle. For example, a first imaging device is integrated into an interior rearview mirror assembly viewing generally forward of the controlled vehicle, a second imaging device is integrated into a CHMSL assembly viewing generally rearward of the controlled vehicle, a third imaging device is mounted proximate the driver's side of the controlled vehicle and a fourth imaging device is mounted proximate the passenger's side of the controlled vehicle. In at least one related embodiment, a digital image processing algorithm is implemented to synthetically "stitch" the individual images into one contiguous image for display to the driver. Any given imaging device, combination of imaging devices or sub-combination of imaging devices may then be employed for additional automatic control/warning tasks, such as; automatic high-beam assist, lane departure, accident reconstruction, collision avoidance, tunnel detection, pedestrian detection, sign recognition, fog light control, etc.

[0036] Turning now to Figs. 3a and 3b, an embodiment of an interior rearview mirror assembly

300a, 300b is shown. The mirror assembly includes a stationary accessory assembly enclosed within a front housing 385a, 385b and a rear housing 390a, 390b. The front housing comprises an aperture 386b defining an image sensor visual opening. The stationary accessory assembly along with a rearview mirror are carried by an attachment member 355a, 355b. The rearview mirror comprises a mirror housing 360a, 360b, a bezel 361a, 361b and a mirror element 362a. A wire cover 394a, 394b is included to conceal related wiring 315b. The rearview mirror assembly 300a, 300b also incorporates an ambient light sensor 365b, at least one microphone 366b, a glare light sensor 365a, operator interfaces 363a, indicators 364a and at least one information display 370.

[0037] Turning now to Fig. 4, there is shown an exploded, perspective, view of an accessory and rearview mirror mount assembly 405. In a preferred embodiment, the accessory and rearview mirror mount assembly provides a rigid structure for mounting a repositionably mounted interior rearview mirror along with a precisely aligned image sensor either stationarily mounted as described in more detail within commonly assigned U.S. Patent application serial number 10/783,273 (7606) or automatically repositioning as described in commonly assigned U.S. Patent application serial number 10/645,801, both of which are hereby incorporated in their entireties herein by reference. A preferred accessory and rearview mirror mount assembly facilitates ease of assembly as well as provides for repeatable, reliable and precise alignment of the related components. In at least one embodiment, the associated imager is used for automatic exterior vehicle light control for which precision alignment of the image sensor is preferred. It should be understood that the present invention has broad application to light sensing optics generally, in addition to, automotive and consumer electronics applications. Imager board 410 is provided with an image sensor with lens 411. In a preferred embodiment, the imager board will also include an image sensor control logic and timing circuit, communication line drivers and wire harness receptacle 413. Optionally, the imager board may comprise a processor for receiving and, at least partially, processing images obtained from the image sensor. In a preferred embodiment, the image sensor and at least one other device selected from the group comprising; 1) an image sensor control logic; 2) an A/D converter; 3) a low voltage differential signal line driver; 4) a temperature sensor; 5) a control output; 6) a voltage regulator; 7) a second image sensor; 8) a microprocessor; 9) a moisture sensor and 10) a compass are integrated in a common ASIC, most preferably on a common silicon wafer. In at least one embodiment, the image sensor with lens 911 includes lens cover snap portions 412 for engaging a lens cover 420 snap clips 421. The lens cover has an aperture 422 for alignment with the optical axis of the image sensor and lens. Various suitable optical systems, such as those depicted and described in commonly assigned U.S. Patents 5,990,469; 6,008,486; 6,130,421; 6,130,448; 6,049,171; and 6,403,942 and U.S. Patent Application serial number 60/495,906 (2880); the disclosures of which are incorporated herein in their entireties by reference; may be employed. It should be understood that optics in accordance with the present invention may obviate the need for a lens cover 420 as described in detail herein. It should be understood that the lens cover snap portions, the lens optical cover and snap clips may be eliminated with use of optical elements in accordance with the present invention. In at least one embodiment, the "lens cover" is formed on a molded organic material optics element using a laser as described in detail herein. [0039] An imager board wiring harness (not shown) is preferably provided with plugs on either end thereof. The imager board is preferably provided with a male receptacle 413 for receiving one of the plugs of the imager board wiring harness (not shown).

[0040] Fig. 5 depicts a profile view of a digital camera 506 in accordance with the present invention having an imager with lens 511. It should be understood that optics in accordance with the present invention may be incorporated into a host of assemblies included, but not limited to, light sensing, image acquisition, moisture sensing, rear-vision systems, lane departure detection systems, adaptive cruise control systems, occupancy detection systems, security systems, vision systems, color measurement systems, head lamp control systems, variable reflectance rearview mirror control systems, digital video recorders and digital cameras.

[0041] Operations and algorithms which map high dynamic range sources onto low dynamic range output displays, or tone mapping operators, have become an important part of a modern digital image processing work flow and will become even more important as high dynamic range imaging sources become more readily available. Tone mapping operators can be divided into two main categories, global operators which use a single transform for every pixel, and local operators which separately transform groups of spatially proximate pixels. In general, global operators are simple to implement, but tend to wash-out image detail or distort local contrast throughout the image. Local operators have the ability to preserve image detail (high spatial frequencies) throughout the range of input intensities at the cost of higher algorithmic complexity. The tone mapping operator proposed by Durand and Dorsey is based on the bilateral filter which is a local operator. In contrast to many existing local operators (Fattal, et al; Mantiuk, et al; Ledda et al.) the bilateral filter is straightforward to implement, does not require image decomposition into multiple layers or scales (thus requiring multiple copies of the image in memory), and works consistently across a wide variety of input images with only minor adjustments to the operator parameters. The bilateral tone mapping process based on the bilateral filter also treats image noise in an even-handed way (i.e., there is no specific noise reduction provision, but there is also no noise enhancement across the entire input space). While Durand and Dorsey's tone mapping operator elegantly reduces the entire input dynamic range into an arbitrary output dynamic range, it unfortunately tends to under-utilize the output dynamic range. Extremely low luminance input values get mapped into mid-scale output luminance values due to the exponential nature of the compression. This exponential mapping results in "flat" images which, while completely mapping input luminance and detail to the output space, lack photographic and visual appeal. This result has been confirmed by a recent study done at the University of Bristol, "Evaluation of Tone Mapping Operators using a High Dynamic Range Display," Ledda et al. ACM Transactions on Graphics, Volume 24 Issue 3, July 2005, where several tone mapping operators were compared over a set of images. The bilateral tone mapping operator was consistently ranked much lower than several more sophisticated and complex tone mapping algorithms. The proposed modifications to the bilateral tone mapping operator enhance the apparent contrast of the resulting low dynamic range output by better utilizing the entire output dynamic range. A method to automatically adjust the tone mapping operator input parameters in order to optimize the visual and photographic appeal of the still image or image stream (video) output is also presented. Better utilization of the output dynamic range is accomplished by applying a proposed new local operator to the compression factor generated by the Durand/Dorsey tone mapping operator. This proposed local operator can optionally take advantage of the noise reduction properties of the bilateral filter while preserving as much image information as possible in the low dynamic range output by only operating on the compression factor. [0043] The bilateral tone mapping process, as proposed by Durand and Dorsey, can be summarized as follows:

BASE = bilatcral(log₁₀ Y, σ_s , σ_τ ) DETAIL = logio Y - BASE

L = BASE • c + DETAIL

CF = ψ where

Y — input pixel luminance σs — spatial filter support σj — intensity (log-luminance) filter support c = compression ratio

CF = compression factor (pixel multiplier)

[0044] An input image is first separated into luminance and color channels. The tone mapping process then uses the log₁₀ of the luminance channel, Y, as the input to a bilateral filter. The output of the bilateral filter is labeled the BASE layer, and is then used to compute a DETAIL layer. A compression factor, CF, is calculated by reducing the contrast of the BASE layer by some input compression ratio c, adding the DETAIL layer to the reduced contrast BASE layer, and then exponentiating and scaling by the original input luminance. The compression factor, CF, is multiplied against the R, G and B color channels of the input image (or just the luminance channel of a grayscale image) to produce the tone mapped, low dynamic range output image. From this formulation, two key aspects of the bilateral tone mapping operator are apparent: the operator is indifferent to input noise, and the calculated compression factor, CF, is an exponential function which tends to reduce and shift the output range into which low luminance input values (shadows, dark areas) are mapped. [0045] The DETAIL layer, generated by subtracting the bilateral filter output from the log- luminance channel, necessarily contains all of the high-frequency noise components present in the input image. This layer is directly added to the final compression factor which effectively retains all of the noise of the input image in the output (the compression ratio, c, is used only to compress the BASE layer). In this way the Durand/Dorsey tone mapping operator passes substantially all of the noise in the input image through to the output image without leveraging the noise reduction properties of the bilateral filter. [0046] In order to more clearly see the mechanism by which the bilateral tone mapping operator misrepresents shadowed or dark regions of an image, it is useful to reformulate the equation for the compression factor, CF, as follows:

_Cp ₌ Λ₀(BASE.c + DETAIL) W _γ

₌ λ_o(BASE.c + log_{] 0}Y - BASE)W_y = L(BASE-(C - l) + log₁₀y) W _r

_{= 10}(BASE.(c - l))

[0047] The original luminance, Y, drops out of the equation and the simple exponential compression factor (similar to a gamma correction) becomes apparent. The value of the input compression ratio, c, is intended to be between 0 and 1 which creates an inverse relationship and quickly maps input shadows into output mid-range values forcing the output image values into a range smaller than the actual output space. There is no provision in the original tone mapping formulation for adjustment of the image black-point (artificial mapping of an intensity level within the image to a zero intensity value), and thus images output from the Durand / Dorsey tone mapping algorithm generally lack shadowed regions, or regions with a very low average luminance value. While cleverly preserving contrast ratios across many orders of magnitude, the lack of low luminance values in output images leads to lackluster visual appeal and "flat" images.

[0048] The current invention builds on the bilateral tone mapping operator, adding an additional local operator to the contrast compression factor which intentionally re-shapes the compression. The addition of this component better utilizes the output data space while simultaneously increasing apparent contrast and photographic appeal of the output image. This operator is preferably based on the output of the bilateral filter and applied directly to the compression factor, CF, thus not only enhancing the visual appeal of the output image, but also leveraging the edge-preserving noise reduction inherent to the bilateral filter. Applying this operator directly to the compression factor has the added benefit of altering the compression before it has been applied to the original image. This ensures that a maximal amount of usable data will be retained in the output image for possible post-processing operations.

[0049] An exemplary operator that has the re-shaping characteristics just described can be formulated as a rational expression using the output of the bilateral filter as follows:

CF- * + ^Grange

where

CF = Durand/Dorsey compression factor β_maχ = max (bilateral(log₁₀ Y, σ_s, σ_/)) B_miτι = inin (bilateral (log₁₀ Y, σ_s, σ_/))

-δrailge ^~ ^max — ^rnin e — black-point adjustment parameter

[0050] This particular formulation modulates the Durand/Dorsey compression factor, CF, in a manner similar to the local dodging and burning operator used by Reinhard, et al., in their paper, "Photographic Tone Reproduction for Digital Images," ACM Transactions on Graphics, 2002. At low input intensity values, the exemplary rational expression, involving BASE, divides the original compression factor by approximately the square of B_range. As input intensity values increase, the rational expression smoothly transitions to a factor of approximately 1 thereby stretching (lowering) the compression only for low input intensities. The epsilon input parameter allows the equation to be tuned to any arbitrary input space, and also provides a method of control over the resulting image black point by adjusting the point at which the rational expression transitions to a factor of approximately 1. Using this new compression factor, CF_e, to compress the R, G, and B input channels has the effect of compressing low luminance values less than they would previously have been compressed while smoothly transitioning to the original exponential compression factor for high luminance values. The use of the BASE layer in the exemplary rational expression adds a measure of smoothing to the new compression factor due to the Gaussian nature of the BASE layer formulation. A similar formulation of an exemplary rational expression replacing BASE with log-luminance (logioY), B_min with min (logioY) and B_max with max (logioY) can perform the same contrast stretching described above, but without introducing additional smoothing or noise reduction in the final output image. Depending on image content, either approach may be desirable. In order to decrease the sensitivity of this new operator to extremes in the image, the

Bmax and B_min parameters can be replaced with percentile values (e.g. 90% and 10%), time- averaged values, statistical or histogram-based values, or a combination of all three. This can be especially useful for compressing streams of images from an HDR source where changing extremes in the image could lead to a visual "flicker" in the overall brightness or appearance of the compressed output. [0052] Additionally, it should be understood that the exemplary operator described above can be replaced with any arbitrary rational expression provided the rational expression modulates the Durand / Dorsey compression factor, CF, in a manner substantially similar to the exemplary operator presented above. For example, hardware implementations of the present invention may desire to avoid division, which is costly in hardware, and thus replace the exemplary rational expression with some other equivalent function more conducive to hardware implementation.

[0053] For comparison, two tone mapped images are presented in Figs. 6 and 7. The scene in both is of the Stanford memorial chapel and has been used extensively as a tone mapping benchmark. The image depicted in Fig. 6 has been compressed using Durand and Dorsey's bilateral tone mapping operator. The image depicted in Fig. 7 has been compressed with the proposed modifications to the bilateral tone mapping operator. Notice the difference in apparent contrast and the increased visual appeal of the image compressed using the new operator. Most of the increased visual appeal of the output of the proposed operator stems from the addition of low-luminance data to the output image. The exponential compression of the original bilateral tone mapping operator has effectively compressed low luminance values into mid-range luminance values.

[0054] In addition to the modified compression technique presented above, the current invention includes a method for automatically determining the compression ratio, c, input parameter to the bilateral tone mapping operator based on key scene parameters derived from either the original input image, the bilateral filter or some other substantially similar image processing technique. The bilateral tone mapping compression ratio, c, is used to scale the BASE layer that was generated by running the bilateral filter over the log-luminance channel of the original image. The current invention provides a mechanism to automatically derive a reasonable value for this ratio, but also provides a new input parameter to optionally adjust the automatic calculation if necessary.

[0055] Before defining the method for automatically deriving the compression ratio, it is helpful to draw an analogy between modern digital imaging and Ansel Adams' Zone System [Adams, The Camera, 1980; The Negative, 1981; The Print, 1983]. In the zone system numbers are assigned to different brightness levels (0 - 10), each brightness level is labeled as a zone and the brightness of each zone differs from its adjacent zones by a factor of 2. The metering and exposure of a scene using the zone system can be done in several different ways - in fact the system is designed to give a systematic method for precisely defining the relationships between the way a scene is perceived and the final print. One method of using the zone system is to choose a key point in the scene that should map to a mid-range luminance value and assign this key to Zone 5. This helps to ensure that as much scene detail, both shadows and highlights, are properly exposed. The absolute luminance of the scene's key element can vary from scene to scene. A scene with a key element that has high luminance value can be said to be a high-key scene. Correspondingly, a scene with a key element that has a low luminance value can be said to be a low-key scene.

[0056] To make the analogy to digital photography and the present invention, a high-key scene is subjectively bright and would map to a digital image which has pixel values dominated by high digital values. A low-key scene is subjectively dark and would map to a digital image having pixel values dominated by low luminance values. Historically, this analogy has been imperfect due to traditional digital imaging exposure compensation issues (e.g., a high-key scene can be captured with an exposure time which is too short resulting in mid- to low-range luminance values of the digital pixels), but when dealing with high dynamic range data (especially data generated from a high dynamic range source) the analogy holds fairly well. Using this analogy, the process of choosing a compression ratio becomes analogous to choosing a middle grey mapping in Adams' Zone System. In order to perform this mapping the digital key value of an image needs to be computed. [0057] One simple way to compute an image's digital key value is to take the ratio of the arithmetic average of the bilateral filter output (the BASE layer) to the range of values present in the BASE layer:

[0058] Because the BASE layer is in the logarithmic domain, the arithmetic average of the

BASE layer is equivalent to the geometric mean of the input pixel values. Humans perceive light in a logarithmic manner, thus using the geometric mean of the set of input luminance values to calculate a scene's key value makes intuitive sense. However, because the input high dynamic range image contains a huge range of luminance values, any sort of mean or average is quickly distorted by high intensity regions - even very small ones. This distortion, or weighting, results in digital key values that are skewed towards high-key scenes even when the overall scene may be subjectively much lower-key.

[0059] In order to further refine the calculation of the digital key value, and to address the short-comings of the use of an average calculation, the present invention proposes to use histogram statistics to characterize the key of a scene. By analyzing the shape of the histogram, the scene's digital key value can be calculated in a more robust way. The proposed algorithm for calculating the digital key value of an image is as follows: First, calculate an image histogram. This histogram is preferably calculated on the output of the bilateral filter, the BASE layer, in order to take advantage of the noise suppressing characteristics of the filter in the digital key value calculation. The BASE layer values are in log space, and are preferably quantized into a finite number of bins in order to make the histogram calculation tractable.

[0060] Next, a histogram minimum bin, H_mm, is calculated by locating the first histogram bin whose count is above some given count threshold, H_thres_h, and whose neighboring bin counts also exceed H t_hres_h- A histogram maximum bin, H_max, is calculated by locating the last bin whose count is greater than H_th_resh, and whose neighboring bin counts also exceed H_th_resh-

[0061 ] Finally, a rolling window of size N^_n is passed over bins between H_min and H_max and an arbitrary bin of the window with the largest total bin count is labelled as the histogram peak bin, H_pea_k. The histogram bins H_min, H_max, and H_peak&XQ then referred back to their corresponding BASE layer values (or other image-referred values on which the histogram was calculated) to generate B hmin, Bhmax and Bh_peak- These values are then used in place oiB_min, B_max and B_avg to compute the digital key value.

[0062] This histogram method of calculating the digital key value rejects outlier pixels and outlier image content (which can be defined as luminance values which do not affect the key of a scene, are substantially disparate from the bulk of the histogram, and whose luminance values do not spread over more than two histogram bins). Rejection of these types of image content is critical in calculating a digital key value which corresponds to Ansel Adams' key value, and which corresponds to a more intuitively appropriate key value. The H_th_resh value can be used to adjust these rejection characteristics.

[0063] Once calculated, the digital key value is then used to automatically adjust the compression ratio, c, in a manner substantially similar to the following:

[0064] The compression ratio calculated for image scenes with a low-key value will approach the maximum compression ratio, c_max, which will result in a compression factor, CF, calculation which maximizes the (c-1) term (as it approaches 0) and thus compresses the image less. Similarly, the compression ratio calculated for image scenes with a high-key value will approach the minimum compression ratio, c_mι_n, which will result in a compression factor, CF, calculation which minimizes the (c-1) term (as it diverges from 0) and thus compresses the image more.

[0065] As in the proposed formulation of the new compression factor, the values extracted from the image to calculate the digital key value can be replaced with time averaged values to smoothly transition between extremes in subsequent frames of a high dynamic range image stream. Without time averaging of digital key value input parameters, the digital key value calculation could potentially change dramatically from image-to-image which would result in an apparent "flicker" of the output low dynamic range images due to the drastically different compression ratios calculated from the digital key value. [0066] The present invention also provides a mechanism for dealing with extremes in input image data that would cause the automatic calculation of the compression ratio, and possibly the modulation of the compression factor, to produce undesirable results. Specifically, when the input image data has a sufficiently low dynamic range the exemplary compression factor rational expression will too quickly transition to a factor of 1 (losing the visual enhancement property of the equation), and the automatic calculation of the compression ratio will become overly sensitive to image noise. Treating low dynamic range input data as a special case and fixing all tone mapping operator parameters for optimal image output simultaneously overcome these problems. It may also be desirable to manipulate the automatic calculation of the compression ratio and the compression factor rational expression to smoothly transition into the low dynamic range input mode.

[0067] The automatic generation of a compression ratio, described above, used in combination with the proposed enhancement to the compression factor calculation can provide an incredibly robust and visually appealing method of performing bilateral tone mapping. Deriving most of the key tone mapping operator parameters from the original image, the proposed tone mapping algorithm creates consistent, visually appealing low dynamic range images from wide range of high dynamic (and low dynamic) range input sources.

[0068] To better understand the bilateral tone mapping algorithm as proposed by Durand and

Dorsey, the algorithm may be separated into two factors. The first factor is a local operator based on the detail layer and directly related to the application of the bilateral filter and the second factor is a global operator that may be expressed as the luminance of the pixel raised to a power. This separation is outlined below and for convenience the first component will be re- ferred to as the original local tone mapping factor and the second as the original global tone mapping factor.

[0069] For very uniform areas of an image or for very small values for σs in combination with very large values for σi, the value BASE which is defined as bilateral (logioY, σs, σi) approaches logioY in value so

C v_Fr_NS « - 1i πv^{logi«Y*(c~1)} - -

[0070] CF_NS denotes a compression factor calculated using the bilateral tone mapping algorithm but without the smoothing effect of the bilateral filter. Multiplication of the pixel value by CF_NS results in a new luminance value for the pixel that is approximately equal to CF_NS times Y where Y is the original luminance of the pixel. For the special case above, the luminance Y of the pixel before tone mapping cancels the luminance Y in the denominator of the expression for CF_NS leaving Y^c as the new pixel luminance after tone mapping. In this expression, c is the compression ratio used for the bilateral tone mapping operation. As an example, for a compression ratio of c equal to 0.5, small contrast ratios are reduced by a factor of c (0.5) and large contrast ratios of 10,000 to 1, for example, are reduced by a far larger factor of 0.01 from the initial ratio of 10,000 to 1 to a resulting ratio of 100 to 1. In general, a contrast ratio of R is reduced to resulting contrast ratio of R^c.

[0071] For the more general case where the filtering or smoothing effects of BASE are significant:

CF = io^BASE*(c~υ [0072]

Now let Y_NS represent the luminance of pixel Y after applying the CF_NS compression factor without the smoothing effect and Ys represent the luminance of the same pixel Y after application of the CF for which smoothing effects are present. Now let:

ExpBASE = 10^BASE Then:

Y^ - Y^_d Ys - ExpBASE^ - Y

Then:

(O- 1 )

Y_s ExpBASE^{(c i)} - Y [ExpBASE ^"T

Y Y^c Y i

Then rearranging and substituting the value for DETAIL from the tone mapping equa¬

tions:

_ I QDETAIL'(I-C)

Further, since Ys and Y_NS are obtained by multiplying CF and CF_Ns, respectively, by Y:

CF

C ^F¹ NS Y ^rNS

Therefore:

_{CF =} J₀DETAIl -U-C) . _Cp_{Ns =} J₀DBTAILHl-C) . Y^

[0073] Here the factor io^DETAIL(1~c) is designated as the original local tone mapping factor and factor Y7Y is designated as the original global tone mapping factor. The original local tone mapping factor has the advantage that its value may, for example, be computed for a given in- dividual pixel location using arrays of pixel values as small as 5x5 or 7x7 with the given pixel at the center to compute the bilateral filter value, BASE, associated with the given pixel location. This necessitates retaining only 5 to 7 rows of pixels in memory at any given time to provide pixel values required for the computation. Thus when, for example, an image is acquired pixel by pixel for each row and row by row for each frame, only 5 to 7 rows of image data need to be buffered to provide the data for the computation of the BASE value of the bilateral filter associated with each pixel of the image and if the computation is arranged to keep up with the pixel input rate, the image output needs to be delayed by little more than the time required to acquire 5 to 7 rows of image data in order to provide the tone mapped output. This is a very important feature for tone mapping of images for real time display where safety critical decisions or the ability to use visual feedback to control a vehicle or other operation may be needed and additionally the modest buffering requirement reduces memory needed to perform the filter operation. The original local tone mapping factor has low frequency components removed and serves primarily to enhance contrast in neighboring features of the image which are initially low in contrast and which lack visibility and visual appeal when contrast is not enhanced in the tone mapping operation. The original global tone mapping factor achieves the contrast compression using the pixel luminance raised to a predetermined exponential power. This is very similar to the gamma function used to pre-process images for display and has the advantages of compressing large contrast ratios much more than small ones and operating in a mathematically uniform manner over arbitrarily large ranges in luminance. A further advantage is that simple adjustment of the exponent based on the compression ratio that is needed provides for setting the compression to meet requirements that may range from provision of contrast expansion to provision of extreme contrast compression. In exemplary embodiments in this invention, this adjustment is utilized for its original tone mapping function and further extended to provide the proper amount of compression (or compression ratio) to compensate for the combined effects on the overall compression ratio of the compression or expansion introduced by factors added to modify the tone mapping algorithm along with the provision of compression to map the image from the dynamic range of the input image to the desired dynamic range of the tone mapped image. As illustrated in Fig. 11 , the original global tone mapping factor appears as a straight line 1101 on the log-log scale used in Fig. 11. The exponent determines the slope of the plot but the line remains straight allowing only flexibility to change its slope or to multiply by a constant scaling factor that shifts its vertical position on the log-log graph in Fig. 11. One or more additional, non-constant terms are needed in the compression factor of the tone mapping algorithm to provide flexibility to shape or characterize the transfer characteristic of the compression factor to provide a more pleasing and intelligible image which makes better use of the dynamic range used to display the tone mapped image. Such flexibility is provided in one example by the addition of bFactor (805 of Fig. 8). bFactor is included as a product term in the compression factor Yns bl mod norm (811 of Fig. 8). The plots in Fig. 11 are of equations listed in Fig. 8. As an approximation, the plots in Fig. 11 are depicted as global tone mapping curves from which averaging or smoothing effects of the bilateral filter have been removed as indicated by the designation ns for no smoothing. Straight line plot 1101 represents the prior art bilateral filter and plots 1102, 1103, 1104 and 1105 depict plots using various parameters in the compression factor Yns bl mod norm introduced as an example which incorporates aspects of this invention. The curves in the illustration are generated by addition of non-constant rational factors or product terms to the originally proposed bilateral tone mapping equation that in its normalized form with the smoothing effects of the bilateral filter removed is designated as Yns bl mod norm. These additional factors or product terms are preferably expressed in terms of either log luminance of the associated pixel and/or of BASE (the bilateral filtered log luminance value associated with the pixel). In the example, calculations for BASE and for the compression factor are performed using the logarithm of the luminance of the pixel values and the original compression factor may be expressed as 10 raised to the power BASE (c-1) indicating that conversion from the logarithmic space or domain back to the linear space or domain has taken place for the compression factor value CF in the original bilateral filter equations. In the examples, the additional factor is expressed optionally using the variable BASE and/or the variable log(Y) both of which are still in the log luminance domain. Thus, for the example, the new compression factor is created by combining the compression factor from the prior art bilateral filter compression factor expressed in the linear domain with a modifying factor or product term that preferably includes a rational expression that includes a variable or variables that are in the log luminance domain. This rational expression is preferably included as a direct multiplier of the exponential compression factor (in the linear domain) from the original bilateral filter equation. The compression ratio c in the original bilateral filter equation is preferably adjusted to provide the desired overall image compression with the additional factor included in the expression for the new compression factor taken into account. It has been observed that the numerator of the rational expression which is added as a product term works well when it is of degree 2 and that desired results are particularly sensitive to the choice of zeros for the expression relative to the minimum value of the BASE for the image. It has also been observed that the results when appropriately scaled are relatively insensitive to the polynomial expression in the denominator of the rational expression so long as it does not have zeros close to values of BASE or log(Y) which occurs in the image. It has been additionally observed that for a range of expressions that provide desirable tone mapping characteristics, nearly equivalent results may be obtained when the degree of the polynomial in the denominator of the rational expression is 0, 1, or 2 provided that compensating adjustments are made in the scale factor and in the compression ratio c used in the portion of the expression from the original bilateral filter and in coefficients in the polynomial term which remains in the numerator. Thus, choosing degree 0 for the polynomial expression in the denominator of the rational expression and providing only a numerator which may, for example, be a polynomial of degree 2 and which may even a polynomial of degree 1 is a desirable simplification which may reduce computational overhead considerably in some implementations. The compression factor CF in the versions of the tone mapping equation as proposed by

Durand and Dorsey may be expressed in terms of BASE without log(Y). Following this lead, for best utilization of the smoothing effects and halo reducing effects of the bilateral filter, it is preferable to give some preference to the use of BASE as opposed to log(Y) as a variable in the terms used in the modified tone mapping equation. However, use of log(Y) or of a mix of variables and even inclusion of other variables such as Y in its non-logarithmic form remains options in embodiments of this invention. Use of log(Y) in some implementations increases both apparent sharpness and noise as opposed to use of BASE as a variable in the product term added to the original tone mapping equation. Use of one or more intermediate variables such as DETAIL is convenient in explanation but is likely to be unnecessary and even counterproductive in calculations. The grouping and the intermediate variables have been used above for ex- planation and derivation and not to imply that such choices are optimal for calculation in the implementation.

[0077] Tone mapping algorithms classed as global contain no local terms and many tone mapping operators classed as local ones are not as amenable to partition into global and local tone mapping components as the original bilateral filter. It is not a requirement that such a partition exist but when it does, it may be used as above to provide insight about characteristics of the tone mapping operation. Above, the criterion was to consider the global component of the tone mapping algorithm to be the limiting case when smoothing effects of the bilateral filter were removed. The use of BASE in terms used to modify the original filter certainly adds both local and global components and may cloud the original distinction between global and local. This does not invalidate use of such terms in the modified bilateral filter.

[0078] The plot 900 in Fig. 9 depicts the global component for various tone mapping equations including a linear one, the original Durand Dorsey one, and several examples of tone mapping equations of this invention. All are normalized to output a value of 1 for the highest luminance value that they are intended to map. Fig. 8 lists supporting equations and minimum and maximum values used in the plot. In Fig. 8 Bmin 801 is the general minimum value of BASE or log(Y) intended to be handled in tone mapping of the frame and Bmax 802 is the maximum value. These values may be based on any of a number of criteria including the minimum and maximum values of BASE and or log(Y) for the present image or for a previous image or images in a video or multi-frame sequence. Brange 803 is the difference between Bmax and Bmin. Ymin 814, Ymax 815, and Ymax/Ymin 816 are corresponding values in linear space. The values listed are ones used in equations for the plots in Fig. 9 and the values of Y for which points are plotted extend over the range from Ymin to Ymax. Note that the ratio of Ymax/Ymin 816 is slightly greater than 5 million which is a huge range compared to a dynamic range of 256 which is representative of many existing display technologies. CF 804 is the compression factor proposed by Durand and Dorsey and bF actor 805 is a modifying product term that serves as an example of the application of principles of this invention. The equation 806 expresses the factor in the form presented earlier and the form 807 depicts the same expression after reorganization to show that it is a rational expression. In this specification an expression that after possible reorganization may be expressed as a quotient of polynomial expressions is considered to be a rational expression. bScale 808 is constant for a given image and is used as a multiplying factor to normalize the tone mapping expressions which use bScale. b 809 is a product of bF actor and bScale. Ys bl norm 810 is a version of CF normalized to one for an input luminance which corresponds to Bmax. Ys bl mod norm 811 is tone mapping compression factor using bF actor in accordance with principles of this invention and normalized to one for an input luminance which corresponds to Bmax. Yns bl norm 812 and Yns bl mod norm 813 are variants of Bmax. Ys bl norm 810 and Ys bl mod norm 811, respectively, for which BASE is replaced by log(Y) to depict the global tone mapping factor or, alternately, the limiting case of the tone mapping operation for which local smoothing has been removed. These are the expressions used in plots depicted in Fig. 9. In the log plot 900 of Fig. 9, six characteristic tone mapping curves are depicted for various tone mapping equations. The plot 900 depicts normalized output luminance for each of the curves on the vertical axis as a function of input luminance Y on the horizontal axis. As explained above, for the tone mapping equations which include local operators, these plots indicate representative overall limiting characteristics with the local effects removed. Each of the six plots depicts the output of a normalized compression factor plotted against luminance which covers a range of approximately 5 million to one from 2.512 to 1.259 x 10⁷. Plot 901 is representative of the prior art bilateral filter, plots 902, 903, 904 and 905 are examples that include a modifying factor in accordance with this invention and plot 900 represents linear scaling. In their normalized form, each curve has an output value of 1 for the maximum luminance value. The line 907 depicts the minimum output value on the vertical axis visible with a display medium with a dynamic range of 256 to 1 that is configured to display tone mapped values of 1 as its brightest pixel value. Output value from portions of the curve above this line are visible and output values below this line are not visible, thus portion 908 of curve 902, portion 909 of curve 904 and portion 910 of curve 906 which fall below line 907 are not visible on such a display medium. For linear scaling, curve 910 is a straight line with unity slope that provides visibility for only a small portion of the image luminance range. On a linear scale, this is a tiny portion of the image luminance range. For the prior art tone mapping algorithm, curve 901 is also a straight line but tone mapping equation 901 provides flexibility to adjust the slope through adjustment of the compression ratio that is the second parameter assigned a value of 0.3 in the example. There is not flexibility in the tone mapping equation to further shape the curve. The 4 curves 902 through 905 are plotted using the equation 1013 of Fig. 8 that according to principles of this invention includes a term bFactor that provides needed flexibility to alter the shape of the curve by adjustment of the parameter ε that is the third parameter in the function Yns_bl_mod_norm(Y, c, ε) used for plots 902, 903, 904, and 905. The first parameter is luminance Y, and the second is the compression ratio. Curves 902 and 903 are both assigned a ε value of 2.0 that provides a modest curvature that is concave downward in the plots 902 and 903. Curves 904 and 905 are both assigned a ε value of 0.75 that provides a substantially more pronounced curvature that is concave downward in the plots 904 and 905. Curves 902 and 904 are compression ratios of 0.22 and 0.2, respectively, that give each curve a slope at Y = Bmax that approximately matches the slope of line 901. However, as noted, the curves have respective portions 908 and 909 that are not visible for a display with a dynamic range of 256 as described above. The compression ratio has been changed to 0.2 for curve 903 and to 0.1 for curve 905 to demonstrate the flexibility to adjust curves to make desired features visible. Adjustment of c in prior art tone mapping equation 901 also provides this flexibility but does not provide flexibility to adjust and thereby characterize the shape of the tone mapping curve. The adjustment of shape is preferably done as part of the tone mapping operation so that post processing steps are not needed and so that the values of BASE are readily available as the preferred variable on which to base the modification of the shape of the tone mapped curves.

[0080] Fig. 10 includes three rational expressions cf(x, a, b) 1001, cg(x, a, b) 1002, and ch(x, a) 1003 each of which is used as a factor in a modified tone mapping expression. The expressions are shown as functions of x; each when expanded has an x² term in the numerator resulting in a polynomial of degree 2, in the numerator and cf, eg, and ch have, respectively, an x², an x, and a 1 term in the denominator, resulting in a polynomial of degree 2 in the denominator of cf, a polynomial of degree 1 in the denominator of eg and a polynomial of degree zero in the denominator of ch. The expression Cg(BASE, ε, 2ε+Brange) is equal to the expression bFac- tor(BASE, ε) in Fig. 8. The expressions CF_f (BASE, c, a, b), CF₈(BASE, c, a, b), and CF_h(BASE, c, a), are modified compression factors formed using cf(BASE, a, b), Cg(BASE, a, b), and ch(BASE, a), respectively, as product terms times CF(BASE, c). CF_f, CF₈, and CFh each contain an additional factor that normalizes the respective pixel luminance values to 1 when BASE is equal to Bmax.

[0081 ] Fig. 11 includes a log plot 1100 of five tone mapping operators, applied without smoothing as explained in association with Figs. 8 and 9 on the vertical axis against luminance Y on the horizontal axis. The curve Yns_bl_norm(Y, 0.3) 1101 is the original tone mapping operator. It is used as a factor with different values for the compression ration c in each of the expressions 1102, 1103, 1104, and 1105 used for the remaining four plots. Expression Yns_bl_mod_norm(Y, 0.1, 0.75) 1102 which is defined in Fig. 8 and also plotted in Fig. 9 is included here for reference and, as explained previously, includes a modifying term bF actor which is a rational expression having a 2ⁿ order polynomial with the variable BASE in the numerator and a first order polynomial with the variable BASE in the d. As further explained above, this expression is equivalent to the expression CF_g(log(Y), 0.1, 0.75, 8.2) Y 1102 that is also plotted and also has the rational factor eg with a 2^nd order polynomial in its numerator and a first order polynomial in its denominator. Both 1102 and 1103 use a compression factor of 0.1 in the exponential factor. CFf(IOg(Y), 0.133, 0.7, 8) Y 1104 has the rational factor cf with a 2^nd order polynomial in its numerator and also a 2nd order polynomial in its denominator. CF_h(log(Y), 0.065, 0.75) Y 1105 has the rational factor cf with a 2^nd order polynomial in its numerator and a one (zero order polynomial) in its denominator. For the plots 1103 with the first order polynomial in the denominator, 1104 with the 2ⁿ order polynomial in the denominator, and 1105 with unity (zero order polynomial) in the denominator, and with adjustment of the parameters a and b and particularly with significant adjustment of the compression ratio c in the exponential term, the three expressions yield nearly identical results as indicated by the near coincidence ofthe overlaid plots of curves 1102, 1103, 1104 and 1105 shown as overlaid curve 1106 in Fig. 11. This result is preferably utilized to significantly simplify computation since the use ofthe new value of c has little or no effect on the computation ofthe exponential term and replacement ofthe denominator with unity in the rational expression considerably reduces both the complexity of the circuit and the time needed to compute the compression factor value CF₈. Since this computation is normally performed for each pixel in an image as part of the tone mapping operation, streamlining computational requirements can result in significant saving in the tone mapping operation. Fig. 12 depicts a system shown in block diagram form that includes one or more imaging devices which preferably have high dynamic range capabilities. Fig. 12 also includes an electronic circuit that performs a tone mapping operation in accordance with principles of this invention. In the device of Fig. 12, functionality of various blocks or portions thereof may be provided by general purpose computing elements that may also perform functions in other blocks. It is preferable to provide one or more specialized circuits to perform the computation intensive tone mapping operation in block 1212 of the diagram. Imaging device 1201 that is representative of the camera or cameras preferably includes a lens 1205, an imaging device 1206 that preferably captures high dynamic range images and an optional but preferable Floating Point Conversion unit 1207 to convert high dynamic range pixel data to floating point. The circuits to provide the floating point values in 1207 are preferably included as an integral portion of an integrated circuit which includes the imaging array of the camera 1201 as detailed in the disclosures incorporated by reference above. The pixel data is preferably serialized and transmitted to a unit 1209 that receives, buffers and edits image data preferably in floating point format. Additional second imaging device 1202, third imaging device 1203 and nth imaging device 1204 may optionally be included in the system and preferably have features similar to those provided for imaging device 1201. Image Selection and Editing unit 1209 preferably includes a digital signal processor or other processor unit and/or a graphics processing unit. The Selection and Editing unit 1209 is preferably capable of image selection, of adding text and op- tional graphics to image data, of optional image processing such as Bayer color interpolation, grouping of images, de- warping and resizing of images, image stitching, and optional feature recognition within images_. Pixels of an image selected and assembled for tone mapping and display are transmitted over path 1219 to Image pixel Luminance Extraction unit 1210 and to Tone Map Pixel Correction unit 1217 where pixel values received over path 1220 are multiplied by the tone mapping correction factor for the pixel received over path 1230. After pixel luminance extraction in unit 1210, pixel luminance values are transmitted over path 1221, preferably in floating point form to Logarithmic Conversion unit 1211 where the values are converted to logarithmic form and output on path 1222 preferably in fixed point, integer format but optionally in floating point format. The logarithmic and exponentiation conversion units preferably employ optimizations that are based on properties of the logarithmic and inverse exponential relationships between values in the log and linear domains. Many of the preferred features of the log and exponentiation conversion circuits described herein apply both to the logarithmic conversion from luminance space to log luminance space in 1211 and to the inverse exponential conversion from log luminance space back to linear space in 1215. Some of the specialized techniques for performing these specific conversions include use of lookup tables. (The use of lookup tables and various interpolation methods are used in prior art in other applications.) The property that a given increment in the logarithmic space or domain corresponds to a given ratio in the corresponding linear domain provides synergy with first converting the values to undergo logarithmic conversion to a normalized floating point form and partitioning logarithmic values to exponentiate into integral and fractional parts. The use of floating point values may be initiated at any point prior to the logarithmic conversion but the relative compactness of the floating point represen- tation along with the large numerical range of light levels captured by high dynamic range imaging devices such as in the disclosures incorporated by reference above make it preferable to convert to or preserve a floating point representation of pixel data early in the chain, even as part of the imaging device circuit. It is then preferable to utilize the floating point representation by provision of circuits in Image Selection & Edit unit 1209 and in Image Luminance Extraction circuit 1210 that operate using floating point arithmetic. For digital computation, binary format is a normal representation so the following will refer to binary representation with its natural relation to two to one ranges or octaves. For binary numbers two to one ranges or octaves are analogous to ten to one ranges or decades for a base ten number system. Various features of preferred circuits for the Logarithmic Conversion 1211 to convert linear to logarithmic values or for the Exponential Conversion 1215 to convert logarithmic values to linear form are described below. The description will focus on the binary system but may be extended to other bases such as natural log or base ten. Logarithmic representations in the various bases differ only by constant multiplying factors so one skilled in the art may readily convert between bases. Beginning with a binary representation or a non-normalized floating point representation, the binary exponent may be determined by determining the number of leading zeros in the binary representation of the number, subtracting this number from the starting numerical value for the exponent, and shifting the fractional or non-exponential part of the number left by this number of places. In standard floating point representations such as specified in the IEEE754 standard, an offset is added to the exponent to provide a range of negative exponent values and the leading one in the fractional non-exponential portion of the value is suppressed for fully normalized ranges. This leading one is the digit that, when no n- variable, approximately halves the size of a lookup table and/or decoding circuit needed for the linear to log. In an analogous way in scientific notation, it is customary to place exactly one nonzero digit before the decimal point of the non-exponential portion of the number which contains the fraction. From this it is seen that the fractional non-exponential part of the value referred to as the fractional part herein may optionally contain an integral portion whose value is preferably less than the radix of the number system. Other conventions may be adapted such as placement of the decimal just before the first nonzero digit. These options will not be covered in detail here and one skilled in the art may supply them. The logarithm of zero is not defined. In the wide dynamic range systems to which this system is particularly applicable, zero pixel or luminance values which do not convert to a finite logarithmic value are handled specially or, as an alternative, pixel values are adjusted to eliminate values of zero before performing the logarithmic conversion. For example, 0 values may be replaced by the smallest incremental nonzero pixel value or the smallest nonzero value may be added to every pixel value before conversion. With a normalized binary floating point representation of the luminance value, the integral portion of the logarithm to the base 2 of the number is equal to or directly related to the value of the binary exponent and the fractional or non-exponential portion is equal to or directly related to the logarithm of the fractional or non-exponential portion of the normalized binary floating point number. The range of this number in the normalized floating point representation spans only one octave so the linear to binary conversion needs also to span only one octave. Since 8 to 10 bits of resolution is typical for digital imaging pixel data and resolutions seldom exceed 14 bits, the normalized one octave representation of a pixel value or of its luminance value is not likely to have a useful accuracy which exceeds that provided by the analog to digital conversion of the pixel value to digital form. So, for example, with imagers that provide 10 bit resolution for readout of pixel values, logarithmic conversion may be performed by using a lookup table with 2¹⁰ or 1024 entries without substantial loss in the accuracy of the pixel data. Decoders or various interpolation techniques to further reduce lookup table size and or increase accuracy may also be provided. It is preferable but not required to provide values to be converted that are in fully normalized form. The benefit is that only one octave or more generally an interval of repetition equal to the base of the logarithm is covered by the data thereby limiting the number of lookup table entries or encoding combinations to approximately half of the number needed to handle values which may have leading zeros. Additionally this provision assures that significant digits in the fractional or non-exponential portions of the numbers are more fully utilized resulting in more consistent linear to logarithmic or logarithmic to linear conversion accuracy. For the inverse exponential conversion performed in block 1215, the integral portion of the logarithmic value may be mapped directly to the exponent of a binary representation of the exponentiated value and the fractional portion of the logarithm may be exponentiated using a lookup table or decoder similar to that provided for the linear to logarithmic conversion but mapping exponentially from logarithmic values to linear values instead of from linear values to logarithmic values as done for the logarithmic conversion. In a way that is analogous to the linear to logarithmic conversion, it is preferable to begin with a value for which the integral and fractional portions are separated. Then the integral part maps to an exponent of the base of the logarithmic value and the fractional portion may be converted using a lookup table. The resulting value may then be normalized in floating point form or retained in an integer format by shifting or optionally multiplying the converted fractional part by the value of the exponential part. Logarithmically encoded pixel luminance values are communicated from the

Logarithmic Conversion unit 1211 over path 1222 to the Tone Map Filter 1212. The filter 1212 is preferably similar to the one proposed by Durand and Dorsey that applies a bilateral filter to pixel data. This filter operates on the logarithmically encoded luminance values for pixels in the image and communicates a base layer value associated with each pixel over path 1224. Tone Map Filter 1212 operates on the logarithmically encoded pixel data and for each pixel site in the image performs a spacial blurring of the logarithmically encoded luminance for pixels by performing a weighted average of logarithmically encoded luminance values including luminance values for pixels at pixel sites in the image that surround the said pixel site. The spacial blurring operation for each said pixel site includes calculation of a weighted average of the logarithmically encoded luminance of the pixels in a spacial neighborhood of the said pixel site where the weighting factor decreases with increased spacial distance from the said pixel site and also with increased absolute difference in the logarithmically encoded luminance of the pixel value included in the average relative to the logarithmically encoded luminance of the pixel at the said site. The value computed as just indicated is referred to as the BASE value associated with the given pixel site. This BASE value is communicated to Compression Ratio Factor unit 1214 over path 1224, to Tone Map Compression Factor Modification unit 1216 over path 1225 and to Filter Parameter Adjustment unit 1213 over path 1226. The BASE value is preferably obtained using the bilateral filter on logarithmically encoded luminance values and a value of BASE is preferably supplied for each pixel location in the image. As just indicated, this filter provides a spacial blurring effect on the original image data in the log luminance domain and the blurring effect is weighted by inclusion of the distance in log luminance space to increasingly reduce the effect on the average of pixels whose luminance value in the logarith- mic domain is increasingly distant from that of the pixel at the site for which the value BASE is being computed. This is the feature that mitigates haloing effects. Other filters besides the bilateral filter used by Durand and Dorsey that include this feature may alternatively be used to practice this invention. In a preferred embodiment, the logarithmically encoded filtered luminance values, referred to as BASE values above, are communicated to three units. These include path 1226 to the Filter Parameter Adjustment unit 1213 that monitors the values of BASE, preferably over one or more images preceding the current one for repetitive frame rate imagers, and assembles data such as image histograms and averages of BASE and/or logarithmically encoded pixel luminance values on which to base selection of parameters which establish the compression ratio c communicated to the Compression Ratio Factor computation circuit in block 1214. Circuit 1214 provides a multiplying factor based on the compression ratio c that is applied to values of BASE and these scaled values are communicated over path 1228 to the Exponential Conversion circuit 1215 where the value is exponentiated to map it from the logarithmic to the linear domain. As an option, a constant value may also be communicated by the Filter parameter adjustment circuit over path 1227 for signed addition to the value calculated as a function of BASE and of c in the calculation performed prior to exponentiation. Addition of the logarithm of a factor in the logarithmic space prior to exponentiation is equivalent to multiplication following exponentiation so such a step may be used to perform an addition or subtraction of the logarithm of a constant factor to eliminate or simplify a multiplication step to scale the result after the exponential conversion in block 1215. This option is particularly useful for constants such as overall image scaling for normalization or other pixel scaling adjustment where the same value is applied to every pixel in the image. Then taking the logarithm of a constant mul- tiplying factor and using signed addition before exponentiation in place of multiplying by the value after exponentiation may result in significant reduction in the complexity of the computational circuit. The Tone Map Compression Factor Modification circuit 1216 receives values to establish filter parameter settings over path 1232 from the Filter Parameter Adjustment circuit 1213 and incorporates the parameter settings in a factor that is also a function of the value BASE received over path 1225 and/or the pixel log luminance value received over path 1223. The exponentially converted compression factor (CF) value that is a function of BASE and compression ratio c is multiplied by the factor calculated by the Tone Map Compression Factor Modification circuit 1216 and communicated from the Tone Map Compression Factor Modification circuit 1216 over path 1230 to the Tone Map Pixel Compression circuit 1217 as a modified pixel compression factor for a pixel. The Tone Map Compression Factor Modification circuit creates a mixed expression of logarithmically encoded luminance values that have been exponentiated (1229) and logarithmically encoded luminance values that have not been exponentiated (1225 and/or 1223). This use of a compression factor that includes both exponentiated and non-exponentiated logarithmically encoded values related to pixel luminance provides the flexibility to shape the tone mapping characteristic to achieve improvements in tonal balance and key of the scene as set forth in this invention. In the Tone Map Pixel Correction circuit, individual pixel values received on path 1220 are adjusted by the compression factor value, calculated by the circuit 1200 that corresponds to the pixel to create a tone mapped image that is preferably suitably encoded and scaled for communication to Image Display 1218 over path 1231. Circuits in Fig. 12 are depicted in simplified form with the intent of indicating preferred major communication paths between various components as one example of the application of the invention. Additional paths may be included and alternate embodiments of the invention may be structured quite differently. A device to apply bilateral filter calculations to an array of values is described herein. In applications, the device is often used to filter an array of logarithmically encoded luminance values that correspond to pixels in an image. A bilateral filtering operation may be applied to arrays of values that have a defined spatial relationship. This is a cumbersome definition and the term pixel implies the spatial relationship so the term pixel or pixel value will be used to describe a value from the spatially related array of values that are input to the bilateral filter with the understanding that the invention may also be used to filter spatially related arrays that may not be defined as pixels. One of a number of applications for the device of this invention is use of the bilateral filter to compress high dynamic range images for displaying them at video rate. For application to high dynamic range compression, pixel values are often encoded as the logarithm of the luminance of the scene at the pixel location. For various filtering operations, especially ones associated with image processing, the bilateral filtering operation is particularly useful since it performs spatial smoothing using averages that are weighted spatially according to the distance of a pixel from the reference pixel location and also according to the magnitude of the difference between the value of the pixel at the reference location and the value of the pixel being included in the average. In this specification, the term reference location or reference pixel is used to designate the pixel or array location p for which the bilateral filter value I (p) is being calculated. The weighting factors in the bilateral filter assign higher weight to pixels that are closer to the reference pixel and to pixels that have values that are close to the value of the reference pixel. The combined weighting factor is computed as a product of the spatial and the pixel weighting factors. The effect is to reduce or block the extension of smoothing to areas of high contrast including edges of higher contrast thereby limiting haloing and other artifacts that would otherwise result in unnatural image appearance and, depending on the use of the filter, in loss of image detail. Use of the filter may include but is not limited to use of Gaussian weighting factors. When the bilateral filter is used with Gaussian weighting factors, two sigma values are used to control the effective radii of the associated filtering effects, one for the spatial component and the other for the pixel value component. For image processing applications, the bilateral filter value is typically calculated for all or for a majority of the pixel sites in the viewable image and for each of these calculations, to minimize artifacts, it is preferable to include enough pixels in the weighted average so that pixels at sites that represent a relatively large percentage of the volume under the Gaussian surface are included in the calculation. For example, calculation over a 5 pixel by 5 pixel region in the image with the reference pixel at the center of the 5x5 pixel region has been shown to yield very good results in some applications. When too few values are included in the calculation, more artifacts will appear in filtered images. In general, there is no harm in extending the weighted average over larger arrays of pixels except for the time and computational resources that are needed and for possible extension of boundary effects at edges of the image. This invention may be practiced with nearly any array size. The hardware resources used for calculation of each of the individual bilateral filter values will increase a little more than in direct proportion to the number of pixels included in the calculation of each of the bilateral filter output values. The following equation is used in the preferred implementation of this invention:

J U^ - />j) ^• H_V (1/(?W(/O|) * /(9)

?εΩ(β)

Γ\P) ^<

]>_s(b-/ψ'w,(|/fø)-/(/o|)

<y<≡Ω(Q ) In the preceding equation, p and q are location coordinates, I(p) and I(q) are input values, preferably logarithmically encoded luminance values associated with pixels at locations p and q, respectively, and I^b(p) is the bilateral filter value associated with pixel at location p. |q - p| is spatial distance and |I(q) - I(p)| is the distance between I(p) and I(q). For high dynamic range image tone mapping, |I(q) - I(p)| is preferably in units of logarithmically encoded luminance. W_s(|q - p|) is the spatial weighting factor that is preferably a Gaussian expression having a sigma value σ_s and Wi(|I(q) - I(p)|) is the luminance weighting factor that is preferably a Gaussian expression having a sigma value O₁. For practical purposes, values included in the calculation for each point p are normally limited to ones that fall in a preferably square array with the point p preferably at the center of this array. The quality of results is normally satisfactory when the array used in the calculation is large enough to include pixels that have relatively large weighting factors that result from the product W_s(|q - p|)^'Wi(|I(q) - I(p)|) in the preceding equation. The numerator of I^b(p) is a summation of product terms each including a triple product of the spatial and the luminance weighting factors times I(q) and the denominator is a summation of the product of the same spatial and luminance weighting factors without the product with I(q). Division by the summation in the denominator serves to normalize the expression for the total value of the weighting factors. This normalizing effect helps to mitigate the effects of exclusion of terms with lower weight from the summation and also mitigates effects of using approximated values for the weighting factors. These approximations may, for example, result from use of lookup tables that have a limited number of entries with limited bit width to provide the value or partial value of W_s(|q - p|)^'Wi(|I(q) - I(p)|). To benefit from the compensating effect of the division by the summation of the weighting factors in calculating I^b(p), it is preferable to include the same set of values in the expressions for W_s(|q - p|)^'Wi(|I(q) - I(p)|) in products with pixel value included in the summation in the numerator as are included in the set of values that are directly summed in the denominator and to generally maintain a higher degree of precision in the sums, products and in the final division of the numerator by the denominator than may be provided for individual values for W_s(|q - Pl) W₁(II(Q) - I(p)|). Many calculations are needed. As an example, for calculation using 5x5, 7x7, or 9x9 array of pixels, each summation in the equation above has 25, 49, or 81 terms, respectively, and this evaluation is normally performed for each pixel in an image, perhaps with special treatment of pixels near the border of the image for which the full array of neighboring pixels is not available. A number of options are available for these points and include but are not limited to: not providing a bilateral filter value for these areas; using the original pixel value in place of a calculated bilateral since the bilateral data is a smoothed variant of the original data; or performing the bilateral calculation using available data values and bypassing or substituting a prearranged value for terms for which no data is available. A preferred option is to calculate bilateral filter values for terms that are on or near the image border and to suppress summation of or substitute zero for values of W_s(|q - p|) or Wi(|I(q) - I(p)|) when q is outside of the image. The normalizing value in the denominator then compensates for values that are missing from the summation that appears both in the numerator and the denominator. In a preferred embodiment of this invention, the circuit is constructed with the following attributes. The dimension of the array of pixel values to include in the calculation for each evaluation of I (p) is preselected and the circuit is preferably designed to include pixel values from the array in the calculation. The layout of the circuit provides temporary storage for the array of pixel values used to calculate an individual bilateral filter value and the values other than the reference value in the array are partitioned into groups, preferably with four pixel values in each group, so that pixels in each group are preferably approximately the same distance from the reference pixel. It is also preferable to configure the array for temporary storage so that stored values in a group are in close proximity one to another in order to reduce the length of data paths in the circuit. Pixels of each group are selected in sequence, preferably one at a time from each group but preferably all of the groups of pixels perform the selections simultaneously. Circuits are provided to calculate filter terms associated with each individual pixel selected from its associated group. The calculations are preferably performed in parallel for the individual pixels selected from each of the groups and the circuit preferably provides parallel addition of the terms computed in parallel to provide partial sums of the filter terms including a first partial sum for the summation in the numerator and a second partial sum for the summation in the denominator for the bilateral value being calculated. The second, the third, and the fourth pixels from each group are similarly selected in sequence and calculations performed and added to the previously accumulated partial sums. Terms for the reference pixel are preferably added to the sum of terms for the first selected pixel from each group as part of the parallel summing operation to initialize the accumulated partial sum and thereafter the partial sums for the second, third, and fourth pixels are added to the sum accumulated from the previous partial sums. Following addition of the terms from the fourth pixel of each group, the summations are complete and the numerator term is divided by the denominator term to provide the calculated bilateral value. Pipelining does occur at various stages in the embodiments provided to illustrate the invention and additional pipelining stages may optionally be added or some of the pipelining stages shown in the embodiments may be removed. In the exemplary design, a bilateral filter calculation may be completed every 4 clock cycles and, using this number of clock cycles per value calculated, most of the computational circuits that are provided for parallel operation perform an operation during substantially every clock cycle during the calculation of the bilateral filter pixel values. The full four clock cycle period to compute successive bilateral filter pixel values is available for the more computationally difficult divide operation used to divide the summation in the numerator by the summation in the denominator to provide the bilateral filter output value. In the design, circuits that are provided as approximate duplicates to provide parallel operation are each associated with a group of pixels that are all substantially the same distance from the reference pixel and the circuits are preferably specifically characterized to provide the spatial weighting factor based on the distance of pixels in associated group from the reference pixel. Each circuit associated with each group of pixels preferably utilizes a lookup table to provide the combined spatial and pixel value weighting factor as a function of the input address that is preferably generated as a function of the absolute value of the difference between the reference pixel value and the value of the pixel to which the weighting factor applies. The lookup table may optionally have predetermined values but is preferably configurable to permit adjustment in the sigma values or to even incorporate an alternate kernel function that may but does not need to be Gaussian. A detailed study has not been performed to verify this, but it is anticipated that 256 or even fewer lookup table entries having 8 bit word lengths will provide satisfactory resolution for the combined Gaussian weighting functions. Up to this point, most of the description has focused on calculation of a single value of

I (p). As indicated, such values are normally calculated for pixel locations over an entire image with omission of or special consideration for areas close to a border. It is not required but often preferable to calculate filter values in the same general order that image pixels are acquired that is pixel by pixel for each row and then row by row for the image frame. In examples herein, it is assumed that the sequence of calculation is pixel by pixel from left to right and row by row from top to bottom (This is an option that does not need to be followed to practice the invention.). To perform a calculation, pixel data is preferably available for the array of locations surrounding the reference pixel that is used in the calculation. Thus needed portions of a stripe of the image with a number of rows that equals or exceeds the number of rows used in the calculation is preferably provided to supply data for the calculation. The array of pixel data accessed for calculation of a I^b(p) value is preferably copied to a special buffer for fast access during the calculation. By performing the successive bilateral calculations using a neighboring pixel as the reference pixel for the immediately succeeding bilateral filter output pixel value calculation, the data needed for the successive calculations differs only by having one column (or row) dropped off and one new column (or row) introduced. This also greatly reduces the number of pixels that need to be copied from the image to the calculation circuits by the square root of the number of pixels in the kernel. For example this reduces the number of pixel values copied from the image buffer to the calculating circuit for each bilateral filter value calculated from 25 to 5 for a 5x5 array, from 49 to 7 for a 7x7 array, and from 81 to 9 for a 9x9 array. Additionally, in preferred designs, a shift register configuration is used for each row of values stored in the array accessed by the calculation circuits and a buffer is provided for the next column of pixel values to be introduced so that a switch from the pixel data for calculation of one bilateral value to the pixel data for calculation of its successor simply entails shifting each row of pixel data in the calculation buffer by one pixel location thereby picking up the column of pixels just introduced and discarding the oldest column of pixels. The entire interval between calculation of successive pixel values is available to fill the column buffer of the calculation circuit from the image buffer and the pixel transfer from the image buffer to the calculation circuit buffer pro- vides a convenient point to handle addressing logic to adjust for variation in the buffer location where image data may be stored in the input buffer.

[0093] In applications where the bilateral filter is provided as an inline component to process pixel data, data from the imaging device is normally presented pixel by pixel from a row and then row by row from an image frame. In the interest of reducing memory needed to buffer an image and to reduce delay in presentation of image data for viewing or further processing, a relatively narrow stripe consisting of successive rows of the image may suffice to provide data to perform the necessary operations. A number of rows that equals or exceeds the number of rows used for preprocessing steps such as Bayer interpolation where color filter arrays are used may be provided. Then additional buffer space may be provided to handle pixels acquired during the delay due to performance of successive calculations and buffer space may be provided for saving data in required format, for example, the Bayer interpolated pixel data, the logarithmically encoded luminance data, the bilateral filter output data. Then a number of rows of pixel data in the format to be filtered that equals or exceeds the number rows in the filter kernel minus one may be provided to be assembled to provide input to the bilateral pixel filter. For devices with this or similar organization of input data, it is preferable to compute data when it becomes available to reduce latency and buffer sizes. The use of memory above sounds like a lot but the total buffer memory size may still be a relatively small percentage of that needed to store an entire frame of the image and latency due to the processing steps may also be reduced to a relatively small percentage of the time between acquisition of successive image frames.

[0094] Fig. 13 indicates an array of pixel values that are used to calculate a bilateral filter value corresponding to the reference pixel 1319. The layout of the array in Fig. 13 preferably indicates the spatial relationship of pixels in the original array as used in calculation of the spatial weighting factors but does not represent the preferred physical layout of the data buffer array used for the calculation. A preferred physical layout will be indicted by the intermediate adjustment depicted in Fig. 14 and finally by the general layout after further adjustment shown in Fig. 15. The pixel data to be filtered may vary widely depending on the application. For logarithmically encoded luminance values from a high dynamic range image, 16 to 24 bit integer values may be typical but the invention is not limited to this range or to integer format. This just gives some perspective that with 18 bit integer values, for example, each of the 49 pixel values in the 7x7 array is a register that holds an 18 bit value and data paths like 1311 that link adjacent pixels in each row are preferably as wide as the registers. The pixel registers are organized in 7 rows 1301 through 1307 and each row is arranged as a shift register that is preferably configured to shift values from each pixel to its immediate neighbor away from the input side during a shift operation performed to present pixel values for calculation of a succeeding bilateral filter value. During a shift operation, data from the column of pixels on the left is lost and in the application new data is shifted from buffer registers, not shown in Fig. 13 but indicated in Figs. 16 and 21, into the pixel in column 1308 at the right hand input side of the shift registers. In more detail row 1301 is organized as a 7 stage shift register with first input register 1312, connecting bus 1311, second register 1313, etc. through seventh and final register stage 1318. Each of the 6 remaining rows 1302 through 1307 is configured as a seven stage shift register similar to the first. The array is organized to indicate the relative locations of pixels one to another from the image or other spatially arranged array that is being processed by the filtering operation. In Fig. 13 each pixel has a distance grouping designation on the top. The number, 9 in the first line at 1310 is the distance grouping designation for pixel 1312. A two digit number in the second line, 00 at 1309 has a first digit that represents a relative row number and a second digit that represents a relative column number to indicate the location of the pixel in the array. The numbering is non-negative and begins at 00 for pixel 1312 in the upper right corner of the array. The row and column numbering is only intended to keep track of pixels as the layout is altered in Fig. 14 and again in Fig. 15. Pixel 1319 at location 33 is the reference pixel. The distance grouping designation is of interest since, for a substantially uniform array, the location of a pixel relative to the reference pixel indicates its distance from the center pixel permitting pre-calculation of the value of W_s(|q - p|) for a pixel at a particular location in the array. As a further benefit that will be used in this invention, various groups of pixels in the array are substantially the same distance from the reference pixel so that the same value of W_s(|q - p|) may be used in the calculation for these pixels. Pixels with distance grouping designation 1 are each 1 pixel away(Here it is coincidental that grouping designation 1 is one pixel pitch unit from the reference pixel since the grouping designations are intended only to classify groups of pixels that are substantially the same distance from the reference pixel.) from the reference pixel 1319 and distance grouping designations for successively greater distances range to 9 for the four pixels at the corners of the array. Note that there are either 4 or 8 pixels in each of the grouping designations. For any pixel in the array other than the reference pixel, three other pixels at 90 degree rotational increments are substantially the same distance from the center reference pixel 1319. For pixels on the diagonals or on the horizontal or vertical center lines of the array, there are only 4 pixels with the same distance grouping designation that are the same distance from the center reference pixel. The remaining pixels that do not lie on a 45 degree diagonal or on a horizontal or vertical centerline of the array each have 8 pixels that are substantially the same distance from the center pixel. (Larger arrays may have equalities in distance groups in addition to ones described here due to geometric relationships such as the 3, 4, 5 right triangle. Such additional relationships do not limit the applicability of the groupings indicated herein.) Each such pixel has 3 others at 90 degree rotational increments and additionally there is a second set of 4 pixels having the same distance from the center that also has the 90 degree rotational symmetry from one pixel to the next but whose pixels also have mirror image symmetry relative to the first set. Letter a suffixes are used to designate one of the subsets having the 90 degree rotational symmetry and a letter b suffix is used to designate the other mirror image subset whose members also have the 90 degree rotational symmetry. All 8 of the members of one of these groups have the same value for the spatial weighting factor W_s(|q - p|) so computationally there is no distinction. In steps illustrated in Figs. 14 and 15, the layout of the array will be adjusted to provide spatial clustering of pixels other than the reference pixel into clustered groups of 4 pixels where pixels of each group are substantially the same distance from the reference pixel in the original array and thereby share the same spatial weighting factor W_s(|q - p|). The pixels on the 45 degree diagonals or the vertical and horizontal center lines also possess mirror image symmetry but the mirror image maps each of these particular sets onto itself so the additional set of equidistant pixels are not present. In Fig. 14, pixels on the side opposite the input side of the array of Fig. 13 are folded approximately about the centerline over the portion containing the shift register inputs. Then pixel spacing is adjusted so that the pixels nest together rather than overlying one another. Electrical shift register connections are preferably not altered in rearranging the layout in either of Figs. 14 or 15. The pixels 1312 through 1318 in row 1301 of Fig. 13 are mapped to pixels 1412 through 1418, respectively, in Fig. 14 and each row of pixels assumes a "hair pin" like configuration. The reference pixel 1419 is now on an outer boundary (left hand side) of the modified array. In Fig. 15 rows are spread apart and the half of the array that contains the last row is generally folded up over the other portion of the array with adjustments made so that the elements do not overly each other but nest together former last row next to first row, former second row next to next to last row etc. Another perspective is that alternate rows in the original layout now alternate one with the other with reversed row order for exactly one of the overlapped sets of rows. Row 1401 maps to row location 1501. Row 1407 is moved up to row location 1507 just below row location 1501. Row 1402 maps to row location 1502 just below row location 1507. Row 1406 maps to row location 1506 just below row location 1502. Row 1403 maps to row location 1503 just below row location 1506. Row 1405 maps to row location 1505 just below row location 1503. Row 1404 instead of mapping to the row shown in dashed outline at 333, is mapped to column location 1504. The grid 334 shown in dashed form has twelve cells in three rows of four cells each. Each of the cells contains a group of four pixel storage locations and pixels in each of the twelve dotted boxes have the same distance grouping designation. (Here a and b suffixes are disregarded. As indicated before distances are substantially equal for pixels having the same numerical distance grouping designation. The alternating presence of the mirror image set designations a and b verifies that the folding paradigm with its mirror imaging properties used to rearrange the cells does utilize the mirror image symmetry to cluster pixel value storage locations into groups each having four pixels that are substantially the same distance from the reference pixel in the original array. The techniques demonstrated to arrange the layout into groups of four pixels having substantially equal distance from the reference pixel extends to any square array of pixels with an odd number of rows and columns. In the circuits in Figs. 16 and 19, the layout is utilized to facilitate the addition of selection circuits to successively present pixel values for pixels that are substantially equidistant from the refer- ence pixel to a computation circuit that is characterized to compute values for pixels having the given distance from the reference pixel. The reorganization of the layout demonstrated in Figs. 14 and 15 is optional and many variants may be employed. The intent is to bring clusters of four pixel that are substantially equidistant from the reference pixel into closer proximity with each other to facilitative layout in selecting one of four of the pixel values in each of these clusters to compute the bilateral filter value as part of a multiple clock period operation that utilizes repetitious use of parallel circuits to compute a bilateral filter value. In Fig. 16 storage for pixel values used to compute a bilateral filter value with a seven by seven kernel is preferably arranged with clusters of four pixels where pixels in each cluster are approximately the same distance from the reference pixel. Pixel distance is indicated in Fig. 13 and a layout to cluster the pixels is indicated in Fig. 15. Only the distance grouping designation is indicated for each pixel storage site in Fig. 16, since this is the primary property used to distinguish handling of the pixels in Fig. 16. Pixel storage sites 1605 through 1611 correspond, respectively, to pixels 1512 through 1518 in Fig. 15. A pixel storage buffer labeled -3R at 1612 receives pixel data from bus 1604. The input select circuit 1602 reads pixel values preferably two at a time from the image input buffer 1601 and selects the appropriate bus 1603 or 1604 over which to communicate the pixel values to one or two of the column buffers in the set of seven buffers -3R through 3R. Buffers -3R through 3R are selectively enabled to receive a pixel value communicated over the input bus to which they are attached and select signals to each buffer are synchronized to register the desired new value in each of the buffer registers. The circuit is preferably configured to provide seven new pixel values for the seven column buffers -3R through 3R during a four clock cycle period so that the new column of pixel values is available to be shifted into the array to provide pixel data to calculate the next bilateral filter value. The reference pixel 1634 corresponds to pixel 1530 in Fig. 15. Its value is communicated to each of the 12 parallel calculation circuits on bus 1638. Twelve select circuits are added to the value storage shift register structure described in Fig. 15. Select circuit S6 1613 selects each one of the four pixels in the cluster of four pixels having a distance grouping designation of 6 in sequence, one at a time, and communicates the value on bus 1614 to a computation circuit having components 1615 through 1624 that are dedicated to computation of bilateral filter terms for the group (preferably of four pixels) that are substantially equal in distance from the reference pixel 1634. Reference to Fig. 13 indicates that pixels with a distance group designation of 6 are 3 pixels away from the reference pixel. The values written into the lookup table L6 1617 are set to include the spatial weighting factor for the 3 pixel distance just indicated. Values written into the lookup tables also include the effect of the sigma values used for the spatial and the pixel value filter terms and the weighting function used for the calculation. A product of spatial and value based Gaussian weighting functions is preferred. The effect of the spatial component is generally included by multiplying or scaling all of the table lookup values by the spatial weighting factor and the pixel value based weighting factor is included as a function of the lookup table address. A similar inspection of Fig. 13 for each of the 11 remaining lookup tables may be used to determine the distance to use to calculate the spatial weighting factor for the distance and the corresponding lookup table may be set to include the effect of the spatial weighting factor. Note here that there are three groups of eight pixels (groups with distance grouping designations 4, 7 and 8) that have the same distance grouping designation. This is the reason for duplicate S4, S7, and S8 selection circuits and duplicate L4, L7, and L8 lookup tables. This duplication permits uniform loading of all of the circuits in groups of four. If speed is not as much of an issue as circuit size, options such as shared use of a lookup table to replace the lookup tables that are duplicated is an option. Preferably values written into each lookup table are multiplied by the appropriate spatial weighting factor so that the product term is included in the final value. Provision of entries in each lookup table that include the effect of the spatial weighting factor appropriate for the distance of the pixels processed using the lookup table from the reference pixel is the preferred mechanism for applying the appropriate spatial weighting factors to each calculated term in the bilateral filter calculation. Provision of entries in each lookup table for which the pixel value based weighting factor is a function of the address of the entry in the lookup table is the preferred mechanism for applying the appropriate pixel value based weighting factors for each term in the bilateral filter calculation. The circuit 1615 preferably computes a lookup table address that is a valid address for the lookup table and for which the value of the address indicates the magnitude of the difference between the value of the reference pixel and the value of the pixel for which the weight sum is being calculated. As an example, the value may be limited in magnitude and low order bits discarded as needed to provide a range of lookup table address values matched to the address range provided for the lookup table entries. The lookup table memory may be initialized and used in the following way. The lookup table provides a value for the term: W_s(|q - p|)^'Wi(|I(q) - I(p)|). The lookup table address is generated in the circuit 1614 and is based on the magnitude of the difference between the value of the reference pixel and the value of the pixel being processed. It corresponds to the argument |I(q) - I(p)| in the expression for the weighting factor. The pixels processed using a given lookup table are chosen so |q - p| is substantially the same for all of them and it follows that the spatial Gaussian term W_s(|q - p|) is also the same so that the entry at each memory location in the given lookup table is scaled based on the value of W_s(|q - p|) corresponding to the pixels for which the table is used. Lookup tables used for pixels that have a different distance from the reference pixel will preferably be initialized with a different set of values that reflects the different value for W_s(|q - p|). When σ_s and or σi are changed or any other changes are made that alter the value of W_s(|q - p|)^'Wi(|I(q) - I(p)|), the lookup tables may be rewritten with values that reflect these changes. The register synchronized memory output value 1620 from lookup table L6 1617 represents the value of the product of the two weighting factors W_s(|q - p|)^'Wi(|I(q) - I(p)|) for the value of the selected pixel input on bus 1614. The registers 1616, 1618, 1622 and 1628 labeled with an R are preferably clocked D type flip-flop registers that provide a flip-flop for each bit in the respective bus into which they are inserted. For each line in the input bus, they serve to set their corresponding output value to the value of the corresponding bus input line. The new values are registered on the active edge of the clock transition and are held until the next active edge of the clock transition. The effect is to delay signals passing through them by one clock cycle and to assert changed values synchronously with the next clock. They may provide nearly a full clock cycle for the D input signal to settle so that each block of logic between a pair of these flip-fops has nearly a clock cycle of time to respond to inputs and provide an output. The circuits are arranged so that the effect of the delays are accounted for and the number of delay elements placed in separate data paths are adjusted to synchronize data flow in the paths as needed for proper operation. The effect in this circuit may be referred to as pipelining since elements in the chain such as address generator 1615, lookup table 1617, multiply circuit 1621 and combined adder stages 1625 and 1627 may still respond to a new input during each successive clock cycle but time available to perform the string of tasks is extended by 4 clock cycles (one clock cycle for each delaying register placed in the data path). Register 1616 in addition to providing most of a clock cycle to perform the magnitude of difference function 1615 also presents new address values to lookup table L6 1617 in a synchronized fashion. The two registers in the signal path between selected pixel input value 1614 and multiplier input 1619 serve to synchronize the pixel value input 1619 and the weighting factor input 1620. Multiply circuit 1621 provides the product of the combined bilateral filter weighting factor with the pixel value on bus 1624 after register synchronization. The weighting factor 1620 is input to adder 1625 that provides the first stage of the parallel addition circuit for the sum of the weighting factors used in the denominator of the bilateral filter value. The product of the pixel value and the weighting factor 1624 is input to adder 1626 that provides the first stage of the parallel addition circuit for the sum of the weighted pixel values used in the numerator of the bilateral filter value. Each of the 12 terms are handled preferably in parallel and in a nearly identical fashion to the one just described. There is a pipelining delay of four clock cycles but a new term is preferably introduced with each clock cycle and select circuit S6 1613 is preferably controlled so that another one of the four pixels with the distance grouping designation of 6 is selected on each clock cycle for input over bus 1614 to the circuit just described. Following this pattern using the combination of sequential and parallel processing and using limited pipelining, substantially every parallel circuit is used in substantially every clock cycle to complete summation of the terms for a bilateral filter value on every fourth clock cycle. In the diagram, the emphasis is on data flow showing registers, arithmetic components and data bus paths so most of the connecting lines in the diagram represent parallel data buses. This is the reason that an uncluttered physical layout is very beneficial for compact layout. Control paths such as data selector circuit select addresses are not shown and these functions are outlined in this description. For clarity in the block diagram in Fig. 16, select circuit input connections are shown as connections to associated shift register pixel value storage locations. For all of the shift register stage except for the last in each row, the same value as used by the shift register is normally also presented on the bus that links the value storage register to the next value storage register in the shift register chain. It is presumed that actual connections might be made anywhere along these buses where a particular signal value is available. Circuits (not shown) are also provided to initialize lookup table memory for implementation for which the lookup tables are programmable. Any of a number of arrangements may be used for this implementation. With CMOS imaging arrays, it is common to provide a serial interface over which imager register settings and instructions may be communicated. Provision of this type of interface with the capability to write values to the lookup tables is a desirable option. In applications where images are captured continually and where lookup table contents is changed during operation, duplicate copies of the tables may be implemented with provision to switch address and data paths of the tables between use as indicated in Fig. 16 and an interface to write new values into the table. With this provision, one set of tables may be used while the other is initialized and when both copies of the tables are initialized, operation may be switched quickly from one to the other to provide flexibility to switch back and forth between the two sets of programmed filter parameter settings very quickly. For some applications, the ability to make rapid transitions in the settings and even to alternate between settings is beneficial. Two partial sums are computed by the two nested parallel adder circuits that each perform a parallel sum of outputs from the 12 parallel computational circuits like the one just described. The circuits also include the input from reference pixel or accumulating register select circuits 1641 and 1642. The 12 parallel circuits handle the sum for all of the pixel values in the array except for the reference pixel 1634 that is included in the sum with a unity weighting factor. The unity weighting factor is selected by select register 1642 to be summed into the summation term for the denominator along with the first set of 12 values included in the summation for the denominator value and the value of the reference pixel, delayed enough by register 1639 to include the proper value, is selected by select register 1641 to be summed into the summation term for the numerator along with the first set of 12 values included in the summation for the numerator value. These partial sums that each include the reference pixel term are registered by the denominator accumulating register 1637 and the numerator accumulator register 1640, respectively, serving to initialize the registers and present the first of the four partial sums for addition to the next set of partial sums added in parallel for the next group of 12 values that are computed. For the three sets of values after the first, select register 1642 selects the value from the denominator accumulator 1637 for inclusion in each of the three partial sums after the first and select register 1641 selects the value from the numerator accumulator 1640 for inclusion in each of the three partial sums after the first so that at the conclusion of the forth partial sum, the denominator accumulator 1637 contains the sum for all 49 weighting factors for pixels in the 7x7 array and the numerator accumulated includes the sum of all 49 weighted pixel values for in the 7x7 array. Divider circuit 1636 inputs the numerator summation value from the numerator accumulator 1640 and the denominator summation value from the denominator accumulator register 1637 and performs the divide operation. Output block 1635 receives the bilateral filter output value from divide circuit 1636 and optionally saves the output bilateral filter value corresponding the reference pixel in a buffer memory or passes it directly to a circuit output or to another stage for inclusion in additional calculations. The divide circuit has four clock cycles to perform the division for each bilateral filter output value. Each of the two partial sums are preferably performed in parallel and are depicted as a binary tree with four successive adder stages forming a tree, the first stage summing values from six pairs of the twelve parallel computing circuits, to provide six output sums, the second stage summing three pairs of the six sums output from the previous stage to provide three output sums. These values are pipelined by registers in each output sum for each parallel adder tree as indicated by register 1628 in the denominator chain. The selected one of the reference pixel values and the accumulated partial sum for each adder chain is then added along with the three sums from the respective adder tree to provide four inputs that are reduced to two by the third adder stage and finally to one partial sum of 13 values for the numerator term and one partial sum of 13 values for the denominator term by the fourth and last stage of the adder chain. Dual input add circuits 1625, 1627, 1629 and 1632 provide one path through successive branches of the adder tree for the parallel adder for the denominator and dual input add circuits 1626, 1630, 1631 and 1633 provide one path through successive branches of the adder tree for the parallel adder for the numerator. The use of pipeline delay circuits has been intentionally avoided in the "feedback" paths from the accumulator register outputs back to the respective accumulator register inputs since such a delay would complicate the circuit needed to maintain desired operation. Thus, it is desirable when including summation of the accumulated partial sums from earlier stages of the accumulation sequence as inputs to the parallel add circuit, to introduce them at a stage that is free of pipelining delays from the point where they are introduced to the output of the parallel add circuit. Fig. 17 illustrates a 9x9 array 1700 arranged so that pixels are clustered in groups of 4 each with pixel values that are substantially the same distance from reference pixel 1702. Dashed line grid 1701 contains 4 rows of 5 cells each that each contains one of the clusters of four pixel storage sites that have the same distance from the reference pixel in the original array. [00103] Fig. 18 illustrates a 5x5 array 1800 arranged so that pixels are clustered in groups of 4 each with pixel values that are substantially the same distance from reference pixel 1802. Dashed line grid 1801 contains 2 rows of 3 cells each that each contains one of the clusters of four pixel storage sites that have the same distance from the reference pixel in the original array. Figs. 17 and 18 are included to illustrate that the layout to arrange the array of pixels in clusters of four pixel storage sites each that all have substantially the same distance from the center reference pixel does not just apply to the 7x7 array of Fig. 15 but may be extended to any square array with an odd number of 3 or more rows and columns.

[00104] Fig. 19 is a circuit very similar to Fig. 16 but it depicts a circuit arranged to compute bilateral filter values over a 5x5 array rather that over a 7x7 array so that 6 terms are computed in parallel so that every 4 clocks cycles another summation of 25 terms for expressions in the numerator and denominator of the expression for the bilateral filter output value may be computed. To illustrate that the layout arrangement is not rigidly defined, the array for storage of the pixel values is arranged as indicated in Fig. 18 so that it has a layout very similar to that for the 7x7 array in Fig. 16 but in Fig. 19, unlike Fig. 16, the array is rotated 90 degrees counterclockwise in the circuit. This is optional and general guidelines for arranging pixels in clusters of 4 pixels that are each substantially the same distance from the reference pixel is still followed. Three stages rather than 4 provide the parallel summation of the six terms computed in parallel with the reference pixel value or accumulated partial sum value as determined by selection circuits 1941 and 1942. For an analogously arranged circuit to handle summation over a 9x9 array, twenty terms would need to be computed in parallel and five levels would be needed for an analogous layout of the parallel adder circuit. The filter circuit that has been described may be implemented to filter images at video rate using a relatively small area on a CMOS integrated circuit silicon substrate and may even be included on the same substrate with an imaging array. Power dissipation may also be relatively small and price may be reasonable. The filter just described is used as the computation intensive portion of a high dynamic compression circuit that has been shown to retain and convey image detail in a pleasing way while providing a dramatic reduction in the dynamic range needed to present the image in comparison to the dynamic range recorded by a high dynamic range camera or other imaging device. Since the bilateral filtering operation is the computationally demanding step in one of the best ways to compress a high dynamic range image to a range that may be JPEG encoded, displayed, transmitted, and printed in a normal way; the computational circuit for the bilateral filter described herein to efficiently produce the filter values even at video rate is an enabling device to permit the high dynamic range compression to be packaged with a high dynamic range imaging device. This allows the high dynamic range image that is captured to be converted to a normal dynamic range at the camera or image capture source while retaining much of the high dynamic range information that is captured and to convey it to a viewer in a pleasing format using a combination of normal, relatively low dynamic range, devices for one or more of the steps of image data compression, image transmission including RF transmission, image storage, and image display including printing. These attributes make the device of this invention desirable for high dynamic range tone mapping applications to compress images captured by a high dynamic range imaging array to a normal displayable dynamic range that may be viewed using a conventional display or printed using normal printing techniques. Furthermore, after compression to a conventional dynamic range, using 8 bits or 256 values per color per pixel, for example, the data to render the image may be further compressed using conventional JPEG compression to further facilitate transmission or storage. The tone mapping may also be done using a minimal amount of image buffering storage space and with introduction of minimal added delay in the path between the image capture and image viewing.

[00106] Fig. 26 depicts an example of data storage for a system that receives pixel values 2602 from an imaging device and buffers them for color interpolation preferably using the color interpolation circuit presented as part of this invention. The results of the color interpolation are then buffered for tone mapping preferably using the tone mapping circuit presented as part of this invention. For a 752x480 wide VGA image, the memory may, for example, be included in the block ram provided in a Spartan-6 SC6SLX9 FPGA, a product announced by Xilinx.

[00107] The logic to perform the color interpolation and the tone mapping is preferably included in the same silicon device as the memory blocks described herein. Examples of preferred data formats are depicted for each of the memory blocks in Fig. 26. 2602 represents a memory location that is preferably configured with a FIFO (First in first out) storage register to provide a preferably small buffer for pixels received from an imager or other image pixel data source that is typically streamed from the imaging device at a relatively consistent rate as it is acquired and processing of the pixel data is preferably begun with relatively little delay. The pixel order is preferably in sequence pixel by pixel for successive pixels in a row and row by row for successive rows in an image. The color interpolation and the bilateral filter operation in the tone mapping each operate on their own individualized supporting array of pixel data. Pixel data from the camera or other image source is used to supply data for the color interpolation, and the logarithm of the pixel luminance value is calculated using the color interpolated output of the color interpolation circuit. For color images acquired using an imager having a color filter array, col- or pixel values are used along with interpolated RGB (Red, Green, Blue) color pixel values as the data input for the tone mapping. In the examples, a 5 row by 6 column array of imager pixel data is used for the color interpolation and a 5 row by five column array of the calculated, logarithmically encoded pixel luminance values is used for the bilateral filter calculation in the first stage of the tone mapping. The sizes of the supporting arrays are given as examples and the invention is not limited to supporting arrays of this size. Furthermore, the sizes of the supporting arrays for the color interpolation and for the tone mapping do not need to be the same. To acquire n rows by m columns of supporting data for the a calculation, approximately n minus one times the number of pixels per row in the image plus m pixels of image data need to be buffered to provide pixel data over the full supporting array to perform the calculations for a given pixel. As explained and provided for elsewhere, at pixel locations that are near to one of the image boarders, pixel data may not be available for the full supporting array. Examples are given of ways to perform the calculation using pixel data that is available and calculations may be performed after the image data available for the supporting array is acquired bypassing buffering operations for data that is not available. The portion of the tone mapping calculation that utilizes the supporting array preferably operates on values in the array that are based on the logarithm of the luminance calculated for each interpolated pixel value so the calculated log luminance values, or at least the interpolated pixel color values needed to support this calculation need to be buffered for the n minus one full rows plus the m pixels to acquire the n rows by m columns of supporting pixel data. After the supporting array based bilateral filter portion of the tone mapping operation, the result of the bilateral filter calculation is used in additional calculations and is combined with the original pixel color component values to obtain the tone mapped pixel output values so the pixel color component values need to be saved in buffer memory while log luminance data calculated from the color pixel values is acquired and used for the supporting array for the tone mapping operation. For n_c rows and m_c columns of data in the supporting array of pixel values for the color interpolation and n_t rows and m_t columns of data in the supporting array of pixel values for the tone mapping operation (n_c + n_t - 2) times the image row length in pixels plus (m_c + m_t) pixels need to be acquired, excepting abbreviated requirements for pixel locations that are close to a boarder of the image, to provide data to perform the combined color interpolation and tone mapping operations. A few additional pixel times may be needed to provide for pipelining delays in the calculations. For five rows of supporting data for the color interpolation and five rows of supporting data for the tone mapping operation, this requires only a little more than eight row times of delay and a little more than eight rows (four rows for each operation) of buffered data in comparison to 480 rows in the image used in the example. This represents only about 1.7 percent of the total image and minimizes the need for buffer memory and the added delay between acquisition and display or processing of an image for control applications. In Fig. 26, pixel values acquired from an imager are acquired and optionally temporarily buffered in input register or buffering array 2602. After optional conversion in pixel format, values from buffering register/s 2602 are stored in imager data row buffer array 2630. Buffer arrays 2630, 2631, and 2632 are preferably organized in similar arrangements, so the most detail will be provided for 2630. The buffer is preferably configured for cyclical access so the newest pixel is entered at the last pixel location at the end of buffer area 2604 that provides storage for the portion of the newest row of pixel data being entered overwriting the corresponding portion of the oldest pixel data stored in the pixel area 2605. For n rows of supporting data, n - 1 rows of storage are provided by partial rows 2604 and 2605, and full rows 2606, 2607, and 2608. Optionally, full rows of buffering space may be provided for each of the five rows of buffered data relaxing the need to carefully sequence access to data. A small number of temporarily storage locations for pixel data may be provided where needed to assure that pixel data needed for calculations may be acquired from the buffer 2630 before it is overwritten. Since the size of the memory blocks needed to provide row buffer space for imager pixel row buffer 2630, color vector row buffer 2631, and logarithmically encoded luminance value row buffer 2632 together consume a significant silicon area and the amount of memory needed to meet these storage requirements may be the limiting factor that determines the size and cost of an FPGA needed to implement the design for an FPGA based implementation, the preferred option to provide a shared space for the partial row storage needed for portions of the first and last rows of buffered image data is presented here. As indicated elsewhere, a column of pixel data is acquired simultaneously or in a preferably short time interval from buffer 2630 and after an optional format conversion is stored in the color interpolation register 2610 where it is used with adjacent columns of data previously saved in buffer area 2610 to provide ready access to the supporting kernel of pixel data for the color interpolation calculation. In a preferred sequence, to provide the new column of pixel values, one for each of the five rows of data in the kernel in the example, the pixel value about to be overwritten by the pixel from imager data from register 2602 is read from the beginning of pixel row buffer 0, and this value, the value about to be written to row buffer 4, and pixel values from corresponding pixel column locations in pixel row buffer 1 2606, pixel row buffer 2 2607, and pixel row buffer 3 2608, constitute the column of pixel values that are written to the working register array 2610 after optional format conversion. In a preferred implementation, the pixel value acquired from input register 2602 is then written to buffer register 2604 overwriting the value just read from pixel row buffer 0. As just indicated, buffer area with partial color row buffer 4 2612 and color row buffer

0 2613 in a shared area and color row buffer areas for rows 1, 2, and 3 at 2614, 2615, and 2616 are preferably handled in a similar way so one should refer to 2630 for the more detailed description. As noted earlier, the number of rows of storage provided for buffer 2630 is preferably equal to the n_c - 1 and the number of rows of storage provided for buffers 2631 and 2632 are preferably equal to n_t - 1. n_c and n_t are both five in the example but either or both may be other values and n_c does not need to equal n_t to practice the invention. Color vector values in buffers 2631 and logarithmically encoded luminance values in 2632 are preferably entered at nearly the same time and since the logarithmically encoded luminance values are calculated based on the corresponding color vector value, the two separate buffers may be administered as a combined, shared structure or as a further option, the logarithmically encoded luminance value may not be buffered but calculated as needed. The complicating factor for implementing this option is that when the logarithmically encoded luminance values are not buffered their values need to be calculated once for each row in which they are used in the kernel or supporting array (n_t or five times in the example) so the somewhat involved logarithmically encoded luminance computation may need to be repeated n_t -1 times after the first. Color vector values in 2631 generally need to be accessed for only one set of calculations to compute the final tone mapped pixel value and this may lead to some simplification in some applications so that buffer 2631 and color calculation delay buffer 2637 may optionally and even preferably for some applications be provided as a single first in first out or other block storage style of memory device. The only access needed in the preferred implementation is to read values from the first location of color row buffer 0 2613 before overwriting this location with the value input at the last location of color row buffer 4 2612. When the row correlated buffer as shown is used, color calculation de- lay buffer 2617 provides storage to cover the pixel processing time increments for the time that values are in the array 2627 during calculation and also additional pixel processing times to allow calculation pipeline delay times and scheduling times from the time that the value is read from color row buffer 2613 before it would otherwise be overwritten and the time that it is used in the calculation to provide the tone mapped pixel value.

[00110] The pixel acquisition information AA that is optionally included with the input pixel value is preferably buffered and kept correlated with the pixel for which it was generated and passed from the image pixel value input to the demosaiced, tone mapped pixel value output. The values AA are stored with the logarithmically encoded luminance value along with 16 bit logarithmically encoded luminance values to utilize the 18 bit storage locations provided in the Xilinx FPGA but may be buffered separately or may be grouped with the color vector values.

[00111] Examples of pixel data formats are given for an imager that provides high dynamic range pixel data encoded in a binary or other floating point data format. The data from the imager as indicated at 2601 may, as an example, be zero for zero values and may be fully normalized for nonzero values with the leading 1 in the binary value suppressed. The five bit binary exponent is EEEEE and the 9 bit binary value is A⁷YA⁷YA⁷YVA⁷Y. AA is optional data associated with the pixel value that may, for example, indicate if the pixel value is the result of a saturated reading or of an under-utilized A/D range. Such indications may indicate that the illumination of the pixel varied over the integration time, perhaps due to a varying light source or the presence of a high contrast edge in a part of the scene that is in motion during the exposure. Other reasons for anomalies may be due to the choice of imaging device settings for the image acquisition. In all of these cases, the information provided by AA may be helpful in responding appropriately to the acquired image data. The indication, if provided may optionally be fewer or more than two bits long. Pixel data in buffer 2631 may optionally be stored in the same format as 2601 or optionally in integer form or in a modified floating point form. Data is preferably converted to binary integer form (24 bits in the example) for the color interpolation calculation. In the preferred design, interpolated, high dynamic range, RGB color pixel values are provided by the color interpolation calculation and the luminance value is preferably calculated for each pixel value and preferably converted to a logarithm to the base 2 value having a binary encoding. This value may take the form of values 2618 of a five bit integral part IHII and an eleven bit fractional part FFFFFFFFFFF. The value AA is grouped and stored with the 16 bit logarithmically encoded luminance value primarily to utilize the 18 bit width provided for memory blocks in the Xilinx FPGA. The red, blue, and green components of the pixel color components may each need 24 bits or more to represent them in binary integer format without losing resolution. As a preferred option, to preserve needed resolution and represent the color values more compactly, each color component is converted to a floating point or preferably to a logarithmically encoded format, preferably like, or at least compatible with the format of the logarithmically encoded luminance value calculated for the pixel and the logarithmically encoded luminance valued is preferably subtracted from each of the red, green, and blue logarithmically encoded color component values for the pixel to create the color vector values to store in the buffer area. The subtraction in the logarithmic space corresponds to division to provide the ratio of each color component to the luminance value in linear space. This logarithmically encoded ratio typically covers a smaller range than the original pixel color component value enabling a more compact representation of the pixel data. The color components, when expressed as a ratio of color component value to luminance so that the resulting ratio is a di- mensionless value becomes transparent to tone mapping algorithms such as those provided herein so that the value is already in the same form that it assumes after tone mapping and its value is unchanged by the tone mapping, the entire content of each is incorporated herein by reference. In other words, the ratio becomes transparent to the tone mapping operation. Because the dimensionless ratio of the original color component to the luminance of the pixel is in a form that is not changed by the tone mapping operation, it is not subject to luminance compression factors that may deviate greatly from unity in the tone mapping operations. Thus, values representing the pixel color in dimensionless form may be encoded and stored in a resolution that supports its final use for rendering of the tone mapped image thereby reducing the buffer storage space and data link transmission bandwidth requirements. In many cases, the resolution needed for final rendering of the image may be supported by eight or fewer bits per color component. The preceding applies to RGB encoding but necessitates the redundant storage of three color components in addition to the logarithm of the luminance. It is preferable to use and convert to a color space that expresses luminance either directly or indirectly as one of its components. For example if the popular YUV pixel encoding is used where Y is luminance and U and V are color components, U/Y and V/Y are dimensionless as indicated and may be calculated before tone mapping and optionally expressed in logarithmic form. In calculation of the ratio, to avoid division by zero, a convention such as supplying a black equivalent for U/Y and V/Y (or R/Y, G/Y, and B/Y) may be used for this special case. The values just indicated may be used for the COLOR VECTOR values 2611. If the YUV or other color space having luminance as one of its components is used, since luminance Y is one of the three components, there are only two color dependent components rather than the three color dependent components present in the RGB color space. Then only the luminance term is affected by the tone mapping and only the U/Y and V/Y terms need to be stored in buffer 2631 during the tone mapping op- eration. If the RGB color space is used, only the separate luminance term is affected by the tone mapping operation and as with U/Y and V/Y, the R/Y, G/Y, and B/Y terms are transparent to tone mapping, but there are three terms instead of two. Since the logarithmically encoded luminance value is stored with the color vector value, the tone mapped pixel values in the form where they are not divided by the pixel luminance may be recovered by multiplying the color components expressed as dimensionless ratios by the tone mapped pixel luminance value to provide the tone mapped color pixel value. For logarithmically encoded values, addition of the logarithmically encoded pixel luminance to the logarithmically encoded color component in ratio form is the equivalent of taking the product of corresponding linearly encoded terms. If the pre tone mapped value is needed instead, then the color components that are in ratio form may be multiplied by the pixel luminance value that is not tone mapped. The advantage is that in the format just indicated, the pixel color information may be represented with reasonable resolution using fewer bits, (8 or 12 or fewer bits per color component in the examples as opposed to using as many as 24 bits or more in linearly encoded integer form) for each of the color components. The values generated as just described may, as an example, be encoded as a binary encoded logarithm to the base 2 with a four bit integral (signed or offset binary form) part IIII and an eight bit fractional part FFFFFFFF. Values that would otherwise be less than or greater than the range provided in the memory locations are preferably clamped to the corresponding minimum and maximum values for the range that is provided. In this way, values that might otherwise be badly in error if randomly clipped are set to their nearest equivalent value for the range provided. Values 2603 stored in row buffer 2630 may optionally be left in the same floating point format as indicated for values 2601 as received or optionally converted to an alternate format such as integer form at the input stage. Values 2611 are converted to 24 bit binary encoded integer format as indicated at 2609, preferably as part of the operation to read them from buffer 2630 for use as source data for the color interpolation calculation in register 2610. The color vector 2611 is preferably encoded compactly as a ratio using one of the options described above and may, for example be encoded as a pair of 8 bit values that need only 16 bits of storage space. Alternatively, the color information may be encoded as a 36 bit value made up of three 12 bit logarithmically encoded values generated as indicated above, with the three values for the respective red, green, and blue pixel color components as depicted in the alternate version for the first note of Fig. 26. The logarithmically encoded luminance values with the optionally included pixel acquisition information AA are preferably encoded as described previously and the five bit binary value IIIII and 11 bit fractional value FFFFFFFFFFF along with AA represent the data format 2618 preferably stored in log luminance row buffer 2632. The log luminance values 2626 read from buffer 2632 are preferably read without inclusion of the pixel acquisition information AA and used, preferably in the format in which they are stored, as the data base for the bilateral filter calculation that uses values from tone mapping register array 2627 as the source of pixel kernel values for the bilateral filter calculation. The buffer 2625 provides buffer storage for pixel acquisition information AA during the time starting when this data would be overwritten if left in buffer 2632 and ending when it is included with the output pixel value 2628. The output pixel value preferably includes values that are successively subjected to color interpolation and then to the tone mapping operations. The values are preferably output in a form that is ready for additional image processing such as stitching or de-warping and/or feature recognition or display. This form may, for example, be an eight or more bit integer representation for each color component as indicated in the second note in Fig. 26 and may include the pixel acquisition information AA. Other bit lengths may be provided for pixel data depending on the application. The features indicated in Fig. 26 may be applied for configurations of the device that may, for example, include tone mapping but not color interpolation or color interpolation but not tone mapping. In these applications, data items not needed for the configurations may be omitted. As pixel row buffer 4 expands to complete row 2605 and become a full row, pixel row buffer 0 shrinks to zero size. Calculations for pixels in the current row are completed for the border columns of pixels where pixels may be shifted to their appropriate positions in the array to perform calculations for pixels near the border prior to performing calculations for the next row of pixels. Options for finishing one row and beginning another include, shifting the pixels in the array 2610 to assume their correct positions for calculations for pixel locations near the right border of the array without introducing new columns of pixels that would be outside of the border, or entering new columns of pixels that are offset by one row and shifting them into the array as calculations are completed for pixels near the border of the previous row. In this case, columns of pixel values shifted in to initialize portions of the array 2610 for calculations for pixel locations in the next row are not accessed until calculations for pixel locations in the current row are complete and calculations for pixel locations in the next row for which they are properly aligned are begun. Then when calculations for pixel locations in the next row begin, pixels in columns at the start of the row will already be in the array 2610 and calculations for pixel locations in this new row may be initiated and pixels remaining in the array from calculations for pixel locations in the previous row should not be accessed for calculations for pixels near the border in the new row. When pixel row buffer 4 expands to fill all of row 2605 and pixel row buffer 0 shrinks to zero and ceases to exist, the row buffer numbering as depicted is all decremented by one at the start of the new row and pixel row buffer 4 in row 2605 becomes the new pixel row buffer 3 and pixel row buffer 1 in row 2606 now becomes the new pixel row buffer 0 and pixels are added to a newly formed pixel row buffer 4 at the start of row 2606. Thus, the row buffer locations associated with given rows in array 2610 advance cyclically by one row in row buffer array 2630 and this advance results from the incremental advance in rows in the image used for calculations related to pixels in successive rows of the image and data in row buffer 2630 is not moved but the row to which new pixel values are written overwriting the oldest pixel value advances cyclically through the array. For processing successive rows of image data, the row with the dual partial buffer interface progresses to the last row 2608 of the buffer array 2630 and then cycles back to row 2605 of the cyclic array.

[00115] The description here for buffer array 2630 and its associated calculation supporting array 2610 may be applied to row buffer array 2632 and the associated tone bilateral filter calculation supporting array 2627. In this case, the same kind of control to restrict access to values in the array 2627 that are outside of the image border or replace these values with zero or with another value appropriate to the calculation may be implemented to provide the same options in transitioning from one row to the next as are provided for the color interpolation calculations associated with buffer array 2630.

[00116] Each pixel, irrespective of any associated spectral characteristics, occupies a given spatial area within a two dimensional array of pixels. Often it is desirable to impart color information in addition to grayscale luminance for any given specially located pixel. Typically, when spectral filtering is incorporated, each pixel within an imaging device will have an associated spectral filter. Red, green and blue spectral filtering, more specifically a "Bayer" pattern represented by two green, one red and one blue spectral filtered pixel, has become prevalent.

[00117] In a typical application of the present invention, missing color values are determined for pixels in an image from an imager that provides one of three color values for each pixel location. Values for the missing pixel color components are determined using techniques that are suitable for but not limited to images having high dynamic range data. Examples are provided herein for a Bayer pattern with red, green, and blue filters. Many of the features of this invention extend naturally to arrays that employ filters of other colors including those with complementary cyan, magenta, and yellow filters, or to filter arrays including clear or substantially un- filtered pixels, and the invention is intend to extend to these applications.

[00118] Prior art includes techniques to improve the fidelity of missing color values that are supplied based on known patterns of spatial correlation between separate colors in the image. Examples are US Patent 7,502,505 B2, to Malvar et al, and US Patent 5,805,217Al, to Lu et al. Other prior art techniques provide further improvements based on detecting the presence and orientation of edges in the image. Many techniques to detect edges in the image are based on a determination of one or more first or second derivatives calculated using pixel samples, usually of the same color and from the same row or column for calculation of a given derivative value. An example is US2005/020733A1, to Malvar. Such techniques may employ one or more threshold values that are applied globally to determine when the value of a calculated derivative is large enough to be classified as an edge. Since most color filter arrays do not include adjacent pixels with the same color, adjacent rows or columns are not sampled in many of the derivative based calculations used in prior art thereby making them ineffective or inconsistent at best in detecting stripes that are one pixel wide. For high dynamic range data, pixel luminance values at edges may differ by thousands or even by a million to one in a scene making response of derivatives to an edge in a dimly lighted area much different than response to an edge in a brightly lighted area so comparison of the derivative values to preselected threshold values to determine the presence or absence of a significant edge does not work well with high dynamic range images. In one related embodiment, the present invention relies on a pattern based approach to detect both the presence and the orientation of edges in the image. US Patent 4,630,307, to Cok, classifies patterns of pixels as geometrical image features and selects from a plurality of image routines based on these features. In examples in the '307 specification, features are classified as edges, stripes, or corners without specifically classifying orientation. In a preferred configuration described in the specification, a set of 4 pixels neighboring the pixel site for which missing color values are being supplied is acquired and used to classify the image at the pixel site as an edge, stripe or corner and this classification is used to select from a plurality of interpolation routines to supply the missing pixel data. In the patent specification in '307 it is stated that the horizontal or vertical orientation of a one pixel wide stripe may not be determined by the four pixel sample and additional samples from an extended set of pixels are acquired in this case as part of the stripe based interpolation routine to interpolate pixel values for stripes and not as part of the pattern recognition routine used to select the interpolation routine for stripes. In the present invention, a sample of more than four, preferably 8 or more, pixels is used in an arrangement for which both the presence and direction of edges including those due to individual one pixel wide stripes may be detected based on the initial sample. Emphasis is on detecting directional orientation and presence or absence of edges based on the sample and making this determination both for discrete edges and for multiple edges that are generally parallel. This classification is preferably used to select an interpolation equation appropriate to the absence of an edge when none is detected and to select an algorithm appropriate to the direction of single or generally parallel multiple edges lying in selected ranges of directional orientation that are detected. A device configured in accordance with this invention performs interpolation using pixel data from pixels that are aligned in directions that are generally parallel to rather than perpendicular to edges in the image in the vicinity of the interpolation site. This results in smoother, sharper edges with greatly reduced zipper artifacts and fewer obviously miss-colored pixels. In a preferred implementation, a key is generated and modifications are made to circuits that perform the interpolation based on decoding of the key either via use of lookup tables and/or decoding circuit outputs. Use of a lookup table or decoder makes it relatively easy to implement a wide variety of options for adjustment to the interpolation circuit. These may optionally include in addition to the usual circuit configurations for nondirectional, and for horizontal and vertical edges, circuit configurations for edges with orientations that are diagonal upward to the right and for edges with orientations that are diagonal downward to the right. Specialized interpolations may also be provided for the border region of the image to use only values that are available and to further provide some degree of optimization in use of available data. As noted above, emphasis is on detection of edges and in their directional orientation without regard to the edge type as multiple (i.e. striped) or single. This does not exclude use of the flexibility of the pattern based image analysis to detect edge orientation and to further detect the type of edges, striped or single and optionally to further detect their specific orientation relative to the pixel for which interpolated values are being supplied (for example, if the pixel interpolation site is inside or outside of a stripe or which side of an edge it is on). Further, specialized interpolation may be provided for certain corner features that include an indication of the orientation of the corner. [00120] An embodiment of the present invention as described in examples herein is configured to be capable of, but not limited, to providing interpolated data at 30 or more frames per second and calculates all values based on the value of the key, the position of the pixel in the image, the color being interpolated, and optionally on data collected from prior processing of pixel data. The circuit that performs the interpolation is configured for a specific interpolation operation based on some or all of the inputs just enumerated and provides the interpolated value based on a sum of products of pixel values from the original image with signed, preferably integer, multiplying factors. The sum of products may be negative or exceed a nominal maximum pixel value. It is preferable to provide a clamping operation as part of the interpolation calculation that replaces any values that would otherwise be negative with zero and as a further option may also replace any values that would otherwise exceed a maximum positive limit with this maximum positive limiting value. The pixel values output are preferably scaled to an integral power of 2, 16 for example, times the input pixel values so that round off errors may be minimized in the calculation but, at or near the end of the calculation, pixel values may be easily rounded or truncated to provide properly scaled output values.

[00121] Fig. 22 depicts a simplified schematic of a preferred embodiment of an apparatus that may be implemented in a number of ways including: a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), the form of algorithm(s) executed by a corresponding processor, a combination thereof, or a sub-combination thereof configured to calculate and provide missing color values to an image that is typically acquired from an imager using a color filter array preferably a Bayer type filter pattern. Fig. 21 is a table of product term multipliers used by selectable interpolation equations to provide the missing color values. Fig. 23 is an extended table of product term multipliers that supplements the table in Fig. 21 with optional product term multipliers for use with pixels close to the border of the image. Figs. 21 and 23 also provide select register settings to read appropriate terms from the array of imager readings provided in the device in Fig 22. Figs. 2OA through 2OL represent various examples of pixel patterns and their associated keys generated and used by the apparatus of Fig. 22 in determining the interpolation equation to select for a pixel value that is computed and supplied by the apparatus. Figs. 24A through 24E depict a direction classifier for multiple fine line features of an image. Fig. 25 indicates classification of pixels near the border of the image used to provide interpolation calculations that are adapted to pixel sites that are near to one of the borders of the image so that the full array of supporting values to perform an interpolation is not available for these pixels. As a specific example of a preferred embodiment of the invention, an apparatus generates a key based on the values of five or more, preferably 8, like colored pixels selected from a neighborhood of one or more pixels for which missing color values are to be provided. The value of the key is used preferably as an index into a lookup table or as the input to a decoding apparatus to provide an indication or partial indication of which apparatus configuration to select from a multiplicity of selectable circuit configurations to provide the interpolated color value. In a preferred design given as an example, a sample of 8 green pixels having two pixels from each row and two pixels from each column including four consecutive rows and four consecutive columns are summed and a key is generated by individually comparing 8 times each of the pixel values used in the sum with the sum and assigning a value of "1" to the result of the comparison when 8 times the pixel value is greater than the sum of the eight pixel values and assigning a value of "0" otherwise. The eight binary digits, one for each pixel value compared, are assembled in a predetermined order to form an eight bit binary number that serves as a unique key or identifier of a two level image of the eight bit pixel array. The comparison of each of a multiplicity of pixel values to the sum is used to generate individual elements of a pattern and the entire pattern is then used in the determination of the apparatus configuration to select to provide interpolated color values for the pixel location. Basing the comparison on the average or sum of pixel values of the pixels used in the comparisons to generate the key has the effect of making the pattern generated strongly, and even primarily dependent on the relative value of pixels in the set used to generate the key and weakly dependent on the overall illumination of the pixels used to generate the key. This is in direct contrast to application of a predetermined or a globally established threshold value used in many gradient or derivative based edge detection arrangements and makes the invention applicable to images generated by high dynamic range imaging devices. In the example, each of the 256 patterns associated with the 256 possible values of the key may be viewed with 0 and 1 bit values coded as dark and light tiles, respectively, arranged geometrically as they appear in the pixel array from which the key is generated. Illustrations of this are provided in Figs. 2OD through 2OL. From these patterns, a choice, in configuration of the apparatus or in the interpolation equation to choose for each pattern may be made using any of a variety of techniques including but not limited to inspection of the patterns associated with the keys as indicated in the examples to determine the presence or absence of edges along with their directions. The choice of interpolation equations to associate with various values of the key may also be established through use of a metric such as a least square error comparison between actual and reconstructed images verses choice of the interpolation equation chosen for each value of the key. Once the choice of interpolation equation for each value of the key is established, these are the relations that are preferably encoded as a lookup table or as a decoding apparatus. In a preferred configuration, one eight bit sample and its associated key is used to select interpolation equations for each of two pixels. Preferably the key may be decoded differently in selecting the interpolation equation for each of the pixels for which it is used to provide flexibility to select the interpolation apparatus based on the specific position of the pixel site in the array of eight pixels that are sampled. The position of the pixel site at which the interpolation is performed relative to eight pixels used to generate the key is illustrated in Figs. 2OB and 2OC. As provided in the example, it is preferable that rows and columns containing pixels in the sample used to generate the key include those containing each pixel site where interpolation is performed and further include the row immediately above and the row immediately below each said pixel site where interpolation is performed and further include the column immediately to the left and the column immediately to the right of each said pixel site where interpolation is performed. The position of pixel 2011 illustrates the location of the first pixel for which the key is used in Fig. 2OB and the position of pixel 2013 illustrates the location of the second pixel for which the key is used in Fig. 2OC. Red and blue filtered pixels are not included in the group of 8 pixels used to generate the key, but two of the pixels used to generate the key lie in the same row as each pixel for which the key is used and two of the pixels used to generate the key lie in the same column as each pixel for which the key is used. Fig. 2OA depicts the eight green pixels 2001 through 2008 used to generate the key as indicated above. Note that the patterns of the array of 8 green pixels as selected to generate the key is depicted in consecutive locations in Figs. 2OA through 2OC. In most of the interpolation operations, the same equations are applied to supply interpolated red pixel values as to supply interpolated blue pixel values and the essential distinction is to keep track of whether a red or a blue value is being supplied and to output it to the storage location for the proper color. Also, values for green pixels are typically handled in the same way whether the pixel cite for which the green value is being supplied is a red or blue filtered value. Because of the checkerboard pattern of the green filtered pixels and the presence of blue filtered pixels in alternate rows with red filtered pixels in intervening rows, the position in the array and the color pattern of the five by five pixel array may be determined by an alternating odd/even row number for a given pixel in the Bayer pattern in combination with the accompanying, alternating odd/even column number for the pixel location. The combined odd/even classification for the row and the column provides four discrete combinations to identify the set of interpolation routines from which to select the "red or blue blind" interpolation equation for each pixel location and these selections will be offset by one column for odd and for even rows. Since the 8 pixel array used to generate the key is preferably correlated with this alternating pattern, the columns at which the key is acquired and used as indicated in Figs. 2OA through 2OC will also alternate by one column for interpolation operations provided for successive rows of pixels in the imaging array. As will be explained in the apparatus description associated with Fig. 22, pixels included in an interpolation operation are entered a column of 5 at a time into a six pixel wide by five pixel high shift register array containing a six stage shift register for each row. Each shift register cell is wide enough to contain the Bayer filtered color component read for the pixel, preferably in integer form. For example, for a high dynamic range sensor, this may require integer sizes and associated register widths of 24 bits or even more. Values are input on the right side and the six pixels in each of the five rows are shifted one pixel position to the left in preparation for supplying missing pixel color component values for the next pixel to the right. The oldest column of five pixels is lost from the array during the shift operation but supporting values are still present in the row buffer for image pixel values until row processing for a portion of the current row is complete and this portion of the oldest of the rows of buffered image data is no longer needed freeing this memory to be used in acquisition of the next row of image data. The dashed line square 2010 depicts the 25 pixel five by five array of pixel values used to calculate interpolated pixel values for the pixel I at the center pixel location 2009 of the five by five array. The previously generated key is used to select the apparatus arrangement to provide the interpolated values for pixel 2009 and the additional column that contains pixel values 2002 and 2006 one column to the right of the 25 pixel array containing support values for the interpolation is provided to permit generation of the key while the previously generated key is used for pixel 2009 so that the key generated for the pixels depicted in Fig. 2OA is ready to apply for the next two pixels 2011 in Fig. 2OB and 2013 in Fig. 2OC. The 25 pixel array providing the basis for the calculation is depicted as 2010, 2012, and 2014, respectively, in Figs. 2OA, 2OB, and 2OC that depict successive locations of pixels 2001 through 2008 used to generate the key as they are shifted left to perform interpolation operations for successive pixel locations in the row. The key generated from the 8 pixels 2001 through 2008 is normally used to select the apparatus configuration for pixel 2011 and is located as indicated by the 8 shaded pixels of Fig. 2OB during interpolation operations for the first of the two pixel locations 2011 to which it is applied and is located as indicated by the 8 shaded pixels of Fig. 2OC during interpolation operations for the second of the two pixel locations 2013 to which it is applied. During performance of the interpolation sequence in Fig. 2OC, the next key is preferably generated just as the current one was generated one pixel time early as depicted in Fig. 2OA while a previously generated key was used in selection of an apparatus configuration to perform the interpolation operations for pixel location 2009. As indicated above, interpolation locations 2011 and 2013 are each in rows and in columns containing pixels used to generate the key and the rows immediately above and immediately below and the columns immediately to either side of each of the interpolation locations for which the key is used also contain pixels used to generate the key. Figs. 2OD through 2OL illustrate 8 of the 256 or so possible patterns used in selection of particular interpolation equations or apparatus configurations to use for interpolation. Many variants of the steps to generate the key may be used to practice the invention. In the example used in a preferred embodiment, eight pixels are used because the sample is large enough to determine the orientation of individual one pixel wide stripes and also multiplication by 8 may be performed by providing an offset that is equivalent to shifting individual pixels three bit positions to the left relative to bit positions in the sum against which they are compared. The multiplication by 8 is performed to effectively compare each of the individual pixel values with the average of the 8 pixels used to generate the key. The sum of eight values is preferably performed using preferably parallel add operations preferably sharing adder and pixel value selection circuits used to calculate the sum of terms for the interpolated color values that are supplied. By sharing this circuitry, relatively modest increases in circuit complexity are sufficient to compute the key. In Fig. 2OD, the eight pixel values for green filtered pixels 2015 through 2022 are summed and the value of pixel 2015 shifted 3 bit positions to the left to multiply it by 8 is compared to the sum of the 8 pixels and 0 is placed in the most significant, left most bit position 7 of the key since 8 times the value of pixel 2015 is not greater than (is less than or equal to) the sum of the 8 pixel values. A circuit compares the value of pixel 2016 left shifted by 3 bit positions against the same sum and 1 is placed in bit position 6 of the key indicating that 8 times the value of pixel 2016 is greater than the sum of the 8 pixel values. This same operation is performed on the remaining 6 pixels, preferably in parallel for all of the 8 compare operations, and bits indicating the results of the compare operations are assembled in a prescribed or- der. The exact order or specific method of generating the key is not important if it is consistent and if lookup table entries and/or decoder circuits are correctly correlated with the relation of values of the key to the actual pattern of the two value image associated with the sampled pixels. Such modifications are considered to be within the scope of the invention. In the examples, the pixel compare results are assembled in order from the most significant to the least significant bit of the key going first from left to right and then from top to bottom in the array of associated pixels so that the results of the compare operations for pixels 2015 through 2022 are mapped in order to bits 7 through 0 of the key. As an option, it may be observed that in many applications it may make little difference whether the pattern is a bright feature in a darker field or a complementary dark feature in a bright field. In other words, if complementary patterns are to be treated in the same way, one of the 8 bits in the initial key value may be selected and the entire key may be conditionally complemented to create a resulting key for which one bit is always a one or always a zero. This halves the size of the lookup table or the decoding combinations needed to translate the key to select the appropriate circuit configurations to supply a particular interpolated pixel value. This is an option whose use is contingent on whether complementary patterns are to be treated in the same way and then on whether the saving in decoding resources outweighs the cost in time to perform the conditional complementing operation. The time to provide the conditional complement can be very small so use of the option is preferred but not required if the complementary patterns are deemed to be equivalent. Since the circuit has the information as to whether or not the key is complemented, this information may be used with the abbreviated result from the lookup table or decoding circuit used with the complementing option to still provide distinction in actions taken for complementary values of the initial key. For example, for the complementary patterns depicted in Figs. 2OK and 2OL and 24A through 24D, it is preferred to take distinctly different actions depending on the complementary state of the original key before conditional complementing. In this case, if the conditional complementing as just described is used, the distinction in actions needed may be effected by use of the signal that indicates whether the key was complemented in the conditional complementing operation along with the indication of the presence of one of the two patterns given by the key for to which the complementing option is applied. The ability to assign any interpretation to each of the patterns provides great flexibility in the assignment so examples given herein are only examples and the invention may be practiced assigning other interpretations for the patterns. There is not a discernible linear edge or stripe in pattern of Fig. 2OD so it's key is preferably decoded to select interpolation circuits configured for non-directional characteristics in the interpolation. The pattern in Fig. 2OE contains a horizontal stripe consisting of lighter pixels 2023 and 2024 so it's key is preferably decoded to select interpolation circuits configured for horizontal edge features in the interpolation process. Fig. 2OF and 2OG depict complementary vertical edges so their keys are preferably decoded to select interpolation circuits configured for vertical edge features in the interpolation. If for example, key values with a one in bit position 7 were complemented, the key for Fig. 2OF would be merged with the key for Fig. 2OG illustrating one instance of the option to halve the size of the lookup table or halve the number of decoding circuit combinations. The interpolation circuit options in the examples depicted in Figs. 21 and 22 include one to improve performance for edges that are directed diagonally up to the right and another one to improve performance for edges that are directed diagonally down to the right. The keys for patterns depicted in Figs. 2OH and 2OJ illustrate edge patterns that have edges that are directed diagonally up to the right and diagonally down to the right, respectively, so their keys are preferably decoded to select interpolation circuits configured for edge features that are direct diagonally up to the right and diagonally down to the right, respectively, in the interpolation. Fig. 2OK has an alternating pattern of darker pixels 2035, 2036, 2039, and 2040 and lighter pixels 2037, 2038, 2041, and 2042. This pattern indicates the presence of three edges but it is ambiguous whether they are three vertical edges at 2046, 2047 and 2048 or three horizontal edges at 2043, 2044 and 2045. The complementary pattern of Fig. 2OL has the same ambiguity. These are the only two of the 256 patterns that indicate this exact ambiguity and this will be useful since, hereinafter, a circuit that acts in response to each of these two patterns (or the key or keys associated with them) is provided to make a determination or partial determination of the orientation, vertical or horizontal, of the alternating darker and lighter stripes indicated by these patterns. As indicated above and applicable here, the pattern indicates the presence of two or more stripes that are next to each other, one lighter than the other as sensed by the green pixels used to generate the key. The stripe that is lighter than the other is bounded by a darker stripe that adjoins the lighter stripe on one side and a darker area that may but need not be a stripe on its other side and the darker stripe is bounded by the lighter stripe on its one side and by a lighter area that may but need not be a stripe on its other side. All of the indications of darker and lighter refer to levels measured by the pixels in the array used to generate the key. Such patterns may be present where there are two stripes that are each approximately one pixel wide that are adjacent with a dark stripe or area of undetermined width on one side and with a light stripe or area of undetermined width on other side. Images of picket fences or slatted shutters or blinds are likely sources of images that contain adjacent stripes that are approximately one pixel wide and these are often oriented vertically or horizontally. In addition to the ambiguity in direction, the other thing that makes such patterns especially difficult is that within an area of contiguous alternating dark and light stripes that are one pixel wide, all of the red filtered pixels will sense light from the dark stripes and all of the blue filtered pixels will sense the light from the light stripes or vice versa. Normally, the pixel width will not exactly match the width of alternating stripes in the image so there will be an interference pattern as the pixel alignment shifts incrementally a fraction of a pixel width with each successive stripe until alignment changes by one stripe. As the alignment shifts by one stripe the red filtered and blue filtered pixels will change roles from the one that was sampling the lighter stripes shifts to the one sensing the darker stripes and the alternate blue filtered or red filtered pixels changes in a complementary way from sensing the darker stripes to sensing the lighter stripes. This will be significant in the circuit provided to determine the vertical or horizontal orientation groups of contiguous stripes that are approximately one pixel wide in the image. Figs. 24A through 24D are similar to the patterns depicted in Figs. 2OK and 2OL each depict a cluster of pixels used to generate the key. Figs. 24A and 24C have the same key and have light pixels in their top rows alternating with darker pixels in the next, lighter pixels in the next and darker pixels in the bottom row. Figs. 24B and 24D have the complementary pattern and a top row of darker pixels, a next row of lighter pixels etc. The darker pixels assigned zero in the key are depicted with a heavier, darker, dot pattern than the lighter pixels. Figs. 24 A and 24B depict red filtered pixels at 2402 and 2404 in locations where they appear when interpolation is being performed for a row of pixels containing red filtered pixels and for this case blue filtered pixels appear in the row above including locations depicted at 2401 and 2403. Figs. 24C and 24D depict blue filtered pixels at 2406 and 2408 in locations where they appear when interpolation is being performed for a row of pixels containing blue filtered pixels and for this case red filtered pixels appear in the row above including locations depicted at 2405 and 2407. In Fig. 24A, if vertical stripes are present, blue filtered pixel 2401 will be on a lighter stripe aligning with the lighter pixels used to generate the key above and below it in a lighter column and red filtered pixel 2402 will be on a darker stripe aligning with the darker pixels used to generate the key above and below it in a darker column. Likewise in Fig. 24A, if horizontal stripes are present, blue filtered pixel 2401 will be on a darker stripe aligning with the darker pixels used to generate the key on either side of it in a darker row and red filtered pixel 2402 will be on a lighter stripe aligning with the lighter pixels used to generate the key on either side it in a lighter row. Note that darker and lighter have changed depending on whether the pattern is vertical or horizontal. A '+' suffix has been appended to the 'B' indicating the blue filtered pixel at 2401 to indicate that when stripes have a vertical orientation, pixel 2401 is in a lighter column and a '-' suffix has been appended to the 'R' indicating the red filtered pixel at 2402 to indicate that when stripes have a vertical orientation, pixel 2402 is in a darker column. From the description just given, roles will be reversed when the stripes are horizontal and 'B+' at 2401 will be in the darker row and 'R-' at 2402 will be in the lighter row. For Fig. 24B the complementary pattern as indicated by a different key or distinguished by use or non-use of complementing when the complementing option is used. For vertical stripes, the blue pixel at 2403 is in the darker column as indicated by the appended '-' and the pixel 2404 is in the lighter column as indicated by the appended '+'. For Figs. 24C and 24D that cover the same complementary patterns for interpolations in the row containing blue filtered pixels, the pattern of results are the same as for interpolations in the row containing the red pixels as just described except that red filtered pixels now occupy locations in the array occupied by blue filtered pixels in the arrays depicted in Figs. 24A and 24B and blue filtered pixels now occupy locations in the array occupied by red filtered pixels in the arrays depicted in Figs. 24A and 24B. Thus, the results follow the location in the array rather than the specific location of red and blue filtered pixels in the array and the reversed locations of the pixel in the lighter and darker column again follows the key (before possible conditional complementing) and the complementary or non-complementary pattern that it represents. Fig. 24E depicts a circuit used to perform a computation used to select the interpolation circuit or algorithm for vertical edges or horizontal edges when the key for the pixels exhibits one of the two patterns of rows that alternate between all 1 and all 0 as depicted and described in Figs. 2OK, 2OL, 24A, 24B, 24C, and 24D. In addition to using the accumulated result of the computation to select the vertical or horizontal interpolation routines, the computation is performed as will be described in response to the occurrence of a pattern of alternating all zero and all one rows as just described. The image is preferably partitioned into one or more preferably rectangular zones that are preferably established by using the row count value 2411 and column count value 2412 in circuit 2413 to partition the image into ranges of preferably contiguous columns preferably within contiguous rows that define rectangular regions in the image and providing preferably separate accumulating registers for each of these zones. Zone select circuit 2413 provides the accumulating register associated with the zone for which interpolated values are currently being provided to the register circuit 2422 in the computation circuit. The accumulating register values are preferably initialized to zero with each new image. Subtraction circuit 2416 inputs red or blue filtered pixel value S 13 2414 corresponding to pixel locations 2401 , 2403, 2405, and 2407 in Figs. 24A through 24D and alternate blue or red filtered pixel value S24 2415 corresponding to pixel locations 2402, 2404, 2406, and 2408 in Figs. 24A through 24D. Subtraction circuit 2416 provides the difference S 13 - S24 at 2417. This difference is added to the accumulating register for the zone 2422 when the pattern used to generate the key begins with a row of ones in the top row as in Figs. 24A and 24C and subtracted from the accumulating register 2422 when the pattern used to generate the key is the complementary one that begins with a row of zeros in the top row as in Figs. 24B and 24D. Inspection of the combinations in 24A through 24D will confirm that with this choice, for vertical stripes, the values sampled from the lighter stripes are added to the accumulating register value and the values sampled from the darker stripes are subtracted from the accumulating register value tending to make the resulting register value positive for the case that the stripes are vertical. Similarly, inspection of the combinations in 24A through 24D will confirm that with this choice, for horizontal stripes, the values sampled from the lighter stripes are subtracted from the accumulating register value and the values sampled from the darker stripes are added to the accumulating register value tending to make the resulting register value negative for the case that the stripes are horizontal. Then for pixels in the associated zone, when the key indicates one of the patterns of alternating rows of all zeros and all ones, the interpolation circuits for vertical edge features are selected when the accumulated value 2422 for the zone is positive and the interpolation circuits for horizontal edge features are selected when the accumulated value 2422 for the zone is negative. Block 2409 includes the circuit that responds to the key indicating the patterns of rows that alternate between all ones and all zeros and issues control signals 2410 to respond with the addition or subtraction of the difference in the two values as just described. As an option, the circuit may keep track of the first occurrence of the above mentioned keys for the image for a particular zone and respond by initializing the accumulated value to the initial value. As another option, the register values may be set, preferably to zero, when interpolation for a new image begins. As a further option for successive video frames, since images tend to be repetitive, initialization may not be performed between successive frames. When the option to bypass initialization between successive frames is selected and also as an option when initialization is performed, it is preferable to limit the extent of the positive or negative excursion of the accumulating register. One way to implement this is to clamp the value to a desired range and another way is to inhibit addition of positive values to the accumulated value when register 2422 already exceeds a specified positive threshold value and to inhibit addition of negative values to the accumulated value when register 2422 already falls below a specified negative threshold value.

[00129] The algorithm just described does not always give the desired sign since difference in pixel values due to color may exceed the difference between luminance of the lighter and darker stripes. The preferred configuration that accumulates the difference in pixel values helps somewhat. For zones that include areas where blue/red pixels are aligned with lighter/darker stripes and also includes areas where the alignment has shifted so red/blue pixels are aligned with lighter/darker stripe, the shift in dark and light stripe alignment tends to reverse the bias created by color differences and move toward an average for which the sign of the accumulated value properly indicates the direction of the stripes. These factors make it preferable to establish a balance where the magnitude of the accumulated value, if limited, is permitted to be large enough to permit averaging over areas where the red and blue pixels transition several times between sampling lighter and darker stripes. This consideration also makes it prudent to make zones wide enough to sample along an appreciable expanse of an area such as a picket fence. For example, a trial with zones 32 pixels high by 256 pixels wide gave good results for an image size approximately equivalent to wide VGA.

[00130] In summary, an indicator is associated with a portion of an image. This indicator is modified in response to specific patterns of alternating ones and zeros in the pattern image that may result from either close spaced vertical or close spaced horizontal edges in the associated images. The indicator provides an indication of whether horizontal or vertical edges are represented by these specific patterns and their indication is used at least in part to determine selection of interpolation equations for vertical or horizontal edge feture in response to detection of the specific patterns. In the example, the circuit responds to the same patterns to initiate modification of the value of the indicator and to initiate use of the value of the indicator to at least in part establish the choice of the demosaicing circuit. Since, for images that are processed from top to bottom, once a horizontal zone boundary is crossed, a new set of zones is entered and the set of zones just left will not be revisited. This crossing of the horizontal zone boundary may be used as a trigger to initialize the accumulating register associated with each zone in the row of zones being entered and only enough accumulating registers need to be provided to provide one for each of the zones in the row of horizontally aligned zones. The initialization does not need to be complete but may be a set to reduce the magnitude of the indicator value, for example by a set ratio, to retain carry over from zone to zone while reducing the indicator value to prevent results from one zone from dominating and thereby masking weaker features of another zone. For the wide VGA image in the example above, there are approximately 15 vertically aligned zones and only three horizontally aligned zones so three accumulating registers may provide enough storage for the circuit to provide an accumulating register to associate with each of the active zones. Fig. 22 depicts a simplified schematic of an apparatus configured to provide interpolated values to supply missing color components for an image acquired using a color filter array such as a Bayer pattern to acquire the image. To provide interpolated values, the interpolation circuit sums product terms based on pixel values selected from a 5 by 5 supporting array of pixels with the pixel location for which interpolated values are supplied centered in the 5 by 5 array. Input buffer 2213 provides storage for portions of five consecutive rows of image data need to provide image data to supply interpolated values for a row of pixels. For the calculation stage, 5 seven stage shift registers 2208 through 2212 provide convenient access to pixel values needed to supply interpolated values for individual pixel locations including generation of a key on which detection of edges along with their directional orientation are based. Each of the shift register stages provides storage for a pixel value, preferably in integer form. For conventional image data, this typically requires integer widths of 8 to 14 bits, but for example, for a particular high dynamic range application, 24 bits are needed for each pixel location. With each new pixel site for which interpolation is performed, 5 pixel values are read from the input buffer 2213 by selection circuit 2214 and if not already provided in the desired form, they are preferably converted to the desired form. For example, to conserve space, pixel data from a high dynamic range imager may be communicated in a more compact floating point format (This may be a specialized floating point format preferably related to selectable integration periods of certain high dynamic range image acquisition devices.) and it may be preferable to leave the data in this format to conserve row buffer memory space, converting it to integer form in block 2435 just before placing each of the pixel values from the row buffers forming the column of five pixel values in one of the five input buffer registers in column 2207 that forms the input buffer stage for the shift register based array of storage locations for data accessed to provide the interpolated values. In typical operation, pixel values are presented in buffering column 2207 and each of the five rows 2208 through 2212 are shifted left by one pixel location as interpolated values are supplied for each successive pixel location. Pixel row 2210 corresponds to a row of pixels for which interpolated values are supplied with pixel location S22 corresponding to the pixel location for which interpolated values are being supplied. [00132] The pixel values from the array of locations SOO through S45 are accessed by eight selection circuits of which SA 2224 is one and by an additional eight dedicated connections of which the connection to S33 2240 is one. The eight selection circuit outputs and the eight dedicated connections are each routed to a selectable shift position circuit to provide multiplier selections that represent multiplying factors that are integral powers of 2 (optionally including 2 ). Shift selection block SSA 2226 is one such circuit that provides a selection of multiplying factors of 1, 2, 4, or 8 at 2225. Other inputs provide selectable multiplying factors of 2, 4, 8, or 16 or of 1, 4, 8, or 16. The output of each of the 16 selectable multiplication circuits is routed to the input of a 16 input parallel adder circuit one of which is one of the two inputs of adder ADO 2228. Each add input is provided with the option to effectively turn off the input by providing 0 or to add or subtract the input. Subtraction is preferably implemented by complementing individual bits and also providing a carry in signal to effectively provide a two's complement when the subtract 'M' option is selected. Four two input add circuits AD8 through ADB accept the outputs from the eight adders ADO through AD7. The outputs of these four circuits are buffered by pipeline delay registers R 2230 and input to two adders ADC 2233 and ADD and their outputs are input to add circuit ADE 2234 that provides the sum of up to 16 input terms. The parallel add circuit is used both to provide the sum of preferably 8 selected green pixel values that is temporarily registered in REF 2231 and to provide the sum of selected terms for the interpolated color values that are temporarily registered in PIXOl 2235. If the high dynamic range pixel values are 24 bit integers and these may be shifted up to 4 bit positions to provide a multiply by 16 and a sign bit is provided, 30 or more bits may be needed for the adders and registers REF 2231 and PIXOl 2235. IfPIXOl is negative, it is preferably replaced by 0 by the clamp pixel value circuit 2236 as part of the calculation for the interpolation and optionally 2236 may also replace pixel values that exceed a specified value by a specified maximum value. A luminance value is calculated at 2237, for example by providing a weighted sum of green, red, and blue values that may, for example, be in a ratio of 60/40/2 for green/red/blue. The calculated luminance and the original green, red, and blue values are optionally scaled and converted in pixel convert block 2238 and stored for output or for further processing such as tone mapping at 2239. For tone mapping, the logarithm of the luminance is preferably calculated, preferably using conversion to fully normalized binary floating point followed by use of a lookup table or other conversion circuit to convert to a logarithmic value over a one octave range. It is preferable to convert the color components to a logarithmic form also. Then multiplying factors to adjust color balance may be applied as additive constants in the logarithmic domain and the log of the luminance may be subtracted from each of the logarithmically encoded color component values for the corresponding pixel to provide the logarithm of the ratio of the color component to the luminance. This value has a smaller range of values than the original high dynamic range color value and may, for example be reasonably encoded as a 12 bit value so that the three color components may be stored in 36 memory words provided in FPGAs such as those available from Xilinx. Since the logarithm of the luminance of each pixel is used in the tone mapping calculation, it is available to be added back to the scaled color components as one of the final steps in an optional tone mapping operation that preferably follows the demosaicing for applications that handle high dynamic range input data. Most cameras of reasonable quality, even ones not classified as wide dynamic range, provide image data with more than 8 bits of resolution making them useful candidates for the combined demosaicing and tone mapping circuits of this invention. Additionally, the tone mapping, with appropriate choice of compression ratio, may be applied to expand rather than compress the dynamic range making it useful in fog or in viewing X-ray images and in certain images of limited dynamic range that may be present under conditions of limited illumination, so these also are desirable candidates for application of these circuits. As an example, to generate the key, green pixel values at S03, S05, S 12, S 14, S23, S25,

S32, and S34 are selected by asserting the proper select settings 2223 for select circuits SA through SH 2224, selecting unity gain for each at 2221 and selecting P for the addition for the eight inputs listed above and 0 for the remaining eight unused inputs at 2222 and registering the sum in REF at 2231. Compare circuits CBO through CB7 2216 compare eight times S34, S32, S25, S23, S14, S12, S05, and S03, respectively with the sum in REF. Each of CBO through CB7 outputs a 1 if eight times its respective pixel input value is greater than the sum of the eight from REF. These eight one bit values are assembled as bits 0 through 7, respectively, of an eight bit key used to identify the pattern of individual bit values relative to the effective average. (Here eight times each value is compared against the sum to avoid a division step. The multiplication by 8 is performed by displacing specified bit connections by three bit positions relative to the sum. This is the technique used to effectively compare each of the eight bit values against the average of the eight bit values to generate the key that is indicative of the pattern.) The value of the key 2217 is routed to the key decode circuit 2229 where the value may optionally be compressed, as for example with the complementing circuit described earlier, and then a lookup table or other decoding circuit may be used to classify the image represented by the key preferably providing information on existence and direction of edges as well as on specialized multiple edge patterns such as indicated in Figs. 2OK, 2OL, and 24A to 24E. Block 2218 provides information on the color of the filter and position in the color filter array for the pixel for which interpolated results are being supplied. Block 2218 optionally provides additional information about position in the array relative to the border as indicated in Fig. 25 to provide information to choose specialized interpolation routines for pixel locations next to or close to the image border where the full 5 by 5 array of supporting pixel data is not available. Color interpolation control circuit 2219 takes inputs decoded from the key in decoder circuit 2229 and of the position in the pixel array from position indicating circuit 2218 and generates outputs to provide the input sum for the key and interpolated filter outputs as indicated by the signal selection indications and the signed multiplying coefficients in Figs. 21 and 23. The color interpolation control circuit responds to the inputs and generates selection control signals at 2220 to select the proper input pixel value for each of the select circuits SA through SH that have an active input. Circuit 2219 generates shift selection signals 2221 to provide the proper multiplier for each of the 16 inputs that are active. Circuit 2219 also generates gating and sign selection signals for each of the 16 inputs. '0' is selected for inputs that are unused for a particular sum, 'P', plus, is selected for terms that are added and 'M', minus, is selected for terms that are negative (or to be subtracted). As indicated earlier, the summed terms are registered in REF 2231 for the sum used to generate the key and in PIXOl 2235 for the sum used as the first stage in providing the interpolated color value. Fig. 21 is a table indicating preferred interpolation term selection and multiplying coefficients used to generate the key and also to generate various interpolated color components as a function of the location in the color array and the existence and orientation of an edge as indicated by decoding of the key with optional inclusion of augmented edge direction indications such as provided by the circuit of Fig. 24E. The various selections of terms, and of multip- lying coefficients indicated in Fig. 21 are preferably implemented as part of the color interpolation control circuit of block 2219 in Fig. 22. In Fig. 21, column 2101 indicates the interpolation pattern as indicated by the pixel position and color indicating circuit 2218 of Fig. 22 and the interpolated color value or key being calculated. 'D' indicates a diagonal interpolation pattern used to supply a red or blue interpolated value at a blue or red filtered pixel location, respectively. 'C indicates a crossed interpolation pattern used to supply a green interpolated value at a blue or red filtered pixel location. 'H' indicates a horizontal interpolation pattern used to supply a red interpolated value at a green filtered pixel location in a row containing red and green filtered pixels or to supply a blue interpolated value at a green filtered pixel location in a row containing blue and green filtered pixels. 'V indicates a vertical interpolation pattern used to supply a red interpolated value at a green filtered pixel location in a column containing red and green filtered pixels or to supply a blue interpolated value at a green filtered pixel location in a column containing blue and green filtered pixels. 'K' is for calculation of the sum for the KEY. Column 2102 indicates the existence and/or orientation of an edge in the pattern. 'N' is for nondirectional, no edge. 'V is for a vertical edge or edges. 'H' is for a horizontal edge or edges. 'U' is for an edge or edges that are diagonal upward to the right. 'D' is for an edge or edges that are diagonal downward to the right. Columns 2103 are for pixel locations 0 through 4 of row 0. Columns 2104 are for pixel locations 0 through 4 of row 1. Columns 2105 are for pixel locations 0 through 4 of row 2 and pixel 22 of this row is the site for which interpolated values are supplied. Columns 2106 are for pixel locations 0 through 4 of row 3. Columns 2107 are for pixel locations 0 through 4 of row 4. Columns 2108 are for pixel 05 from row 0 and pixel 25 from row 2 used to calculate the sum of green pixels during the interpolation operation for the pixel preceding the ones for which the sum will be used. Together the 25 elements in the 5 by 5 pixel portions of the five rows and the two additional pixel locations indicate the 27 pixel values accessible at any one time for calculation of the key and of interpolated values. The column headings for columns associated with individual pixels contain two digit numbers the first indicating the row number and the second indicating the column number of each pixel value in the shift register array of Fig. 22. In Fig. 22, the same numbering is used but an 'S' is used as a prefix for the pixel locations. Summed values for pixel 22 and pairs of values for the first row of values for pixels 02, 20, 24, and 42 indicate provision to access these five pixel locations simultaneously for two sum terms. The dual sums may be used to provide multiplying factors that are not integral powers of 2. Minus signs indicate that terms are subtracted and blank entries indicate that no sums or zero terms are present for these entries. The first row gives the interpolation circuit settings for a pixel value to be supplied using interpolation pattern 'D' and edge classification 'N' that are used in combination for diagonal pattern and a non-directional interpolation, the next row 'D' 'V, Vl ' for diagonal pattern and a vertical interpolation, etc. and the last row 'K' 'K' is used to provide the sum of eight green values for calculation of the key. The next to the last row labeled SEL indicates select circuit SA, SB, SC, SD, SE, SF, SG, or SH or the direct input 11, 12, 13, 22, 22, 31, 32, or 33 used to access pixel values from the shift register array for summations in Fig. 22. Dual entries indicate dual access to these pixel values and the capability to provide two sum terms using the values. The select circuits SA through SH can each provide only one input at a time and are arranged so that all of the nonzero terms may be summed staying within this restriction. The select inputs provide capability to access the 27 pixel values and provide dual access for five of these using the sixteen summing inputs. The bottom row labeled INPT indicates the select setting asserted on control lines 2220 by control circuit 2219 of Fig. 22 to access the specified element. Dual entries refer to the separate set- tings for the dual select elements indicated in the preceding row. Columns 2109 indicate the select settings just noted for each configuration of the circuit as indicated in the associated row of the table. For interpolation sites that are zero or one row or column away from a nearest border of the image, not all of the 25 pixel values are available from the supporting matrix. There are many options that may be used to practice this invention and handle the border conditions. A preferred one is to add capability to the logic circuit to detect the border conditions and to provide interpolation routines that operate using available pixel values. With these provisions alternative options such as, special initialization steps or reduction in the size of the interpolated image may be avoided. With display size often matched to imager size, the option to maintain the original image size is a desirable one. Fig. 25 depicts an array having seven rows and eight columns that provide an example of a classification that may be assigned to pixels that are zero or one pixel locations away from a nearest border. TL, TR, BL, and BR refer respectively to pixels that are in the top left, top right, bottom left, or bottom right portions of the image as indicated in Fig. 25. TO, LO, RO, and BO indicate pixels that are not in one of the corner zones and are, respectively, next to (zero pixels away from) the top, left, right, or bottom border of the image. Hl and Vl refer, respectively, to horizontal and vertical edge classifications for pixels that are not in one of the corner zones and are one pixel away from a nearest border as indicated by an 'Hl ' or 'Vl ' in column 2102 of Fig. 21. Any of the border classifications preferably takes preference over use of the key, but the interpolation pattern as indicated in column 2101 of Fig. 21 and column 2301 of Fig. 23 are still used. In the example, interpolation at border pixel locations has been simplified since relatively few of the pixels in the image fall within this classification. As an option, additional better optimized interpolation circuits may be provided and some of these may use values from the key. Fig. 23 is structured in a way similar to Fig. 21 and includes an indication of pixel value selections and multiplying factors that may be used to provide interpolated values for pixels with the TL, TR, BL, BR, TO, LO, RO, or BO border classifications as indicated in column 2302.

[00136] To implement provision of interpolation routines for pixel locations that are near to a border, logic block 2218 of Fig. 22 may be expanded to provide border location classifications as indicated in Fig. 25 and color interpolation control 2219 may be expanded to recognize and respond to these indications along with the others and to respond issuing appropriate control signals for pixel selection at 2220, multiplying factor selection at 2221, and 0, add, or subtract selection at 2222 to implement the set of interpolation equations from Fig. 23 and for Vl, Hl, TO, BO, LO and RO from Fig. 21 in addition to the ones already implemented from Fig. 21 as described above.

[00137] Figs. 21 A, 22A, and 23A are similar to Figs. 21 , 22, and 23, respectively, but implement two options one to replace the 16 term parallel adding circuit with an 8 term parallel add circuit that may be used to add separately chosen terms on each of two add cycles and these terms may be added to yield a result that is similar to if not identical to that achieved with the 16 term serial adder circuit. Optionally, when terms fit into a single set of 8, the second add does not need to be provided and when two adds are provided, a term from the array may be included in each sum with signs and multiplying coefficients that are not necessarily the same for each of the two additions. The other option is based on the generation of multiple pattern images using features that are presented along with the terminology used to describe it as part of Fig. 28 and the related description. The generation of the pattern image based on use of the average of the values of pixels in the pattern (or other threshold value) as a reference is replaced with genera- tion of a set preferably of more than one pattern image where each of the pattern images is preferably based on the use of one of the pixel values in the pattern array as a reference. Additionally, for n pixels in the pattern array, it is preferable to generate n pattern images using the value of each of the n pixel values in the pattern array as a reference pixel value. Then, preferably, each of the n pattern images is analyzed to detect a pattern and the results are combined and prioritized to generate an indication of the presence or absence of a pattern detected in the values of the pixels in the pattern array and to further indicate characteristics such the existence of edges along with an indication of their orientation. The existence of specialized patterns such as the multiple edge patterns for which vertical or horizontal orientation of the edges is ambiguous based on the pattern image alone are also preferably detected and their presence and distinguishing characteristics are preferably indicated. The circuit implementations share many similar, if not identical, features and the description will center on these differences. In Fig. 22, eight of the 16 terms that are selectively added with selectable signs and multiplying coefficients are provided by select registers SA 2224 through SH and eight additional terms SI l through S33 2240 are routed directly to the remaining eight adder inputs. Color interpolation control circuit 2219 responds to inputs from 2218 that indicates the pixel position relative to the border, the color of the color filter for the pixel and the color of the interpolated color component that is being provided. It also responds to information about the presence of patterns such as edges along with their orientation that are detected in the pattern image. These inputs are used to classify the interpolation equation to be applied according to the type of interpolation as indicated in columns 2101 and 2301 in the tables of Figs. 21 and 23 and according to the position relative to the image border or the presence of patterns including edge orientation as indicated in columns 2102 and 2302. Remaining entries in a row indicate pixels and coefficients used to provide the interpolated value. The next to the last rows of tables in Figs. 21 and 23 each having 'SEL' as a row heading indicates the select register or directly connected input or inputs that may be used to select pixel values for pixels indicated by the pixel designation indicated in the column headings in the first row of the tables. The last rows of the tables each having 'INPT' as a row heading indicates the number of the select register input used to select the pixel designated in the associated column heading. Aside from rows at the top and bottom of the tables, as just described, other rows indicate signed multiplying coefficients for terms to include in the sum to generate a particular interpolated value or to generate the average of the values of pixels in the reference image array. Columns grouped under 2209 and 2309 indicate selection setting for the eight select registers SA through SH used in Fig. 22 to select values from specified from the pixel that are specified in the row in the table for the interpolation equation. The color interpolation control circuit is configured, based on data from the tables in Figs. 21 and 23, to respond to inputs from blocks 2218 and 2229 to select the applicable row from either the table in Fig. 21 or in Fig. 23 and to generate signals on control signal paths 2220, 2221, and 2222 that result in selection in the correct terms and coefficients to generate the appropriate sum of terms as indicated by the entries in row selected from one of the tables to provide the interpolated color value for the interpolation equation. For the circuit of Fig. 22A, are all similar in function to counterparts in Fig. 22 but are typically used to perform two add operations for interpolated color values that are generated and are configured to select different input pixels. Pixel value holding register PIXOl 2235 of Fig. 22 is modified to PIXOl ACCUM 2235A of Fig. 22A and provided with the capability to add the first sum to the second and also to holding the resulting value. The differences in the circuit configurations are intended primarily to repartition the work using fewer resources repe- titively with the eight parallel add circuits to accomplish substantially similar overall results. The average based and multi pattern image based pattern recognition may be used somewhat interchangeably, but additional clock cycles naturally utilized by repetitive use of the eight inputs add circuit does fit well with added compare cycles used to assemble the compare result matrix for the multi pattern based pattern recognition. Tables in Figs. 21 A and 23A are similar to Figs. 21 and 23, respectively, but the next to the last rows each have the 'SELA' heading and the row replaces the row with the corresponding row with the 'SEL' heading and the last rows each have an 'INPTA' heading and the row replaces the corresponding row with the 'INPT' heading. Entries in the 'SELS' rows indicate the one of the select registers SA 2223A through SH of Fig. 22A connected to the pixel indicated in the column heading and the entry just below it in the 'INPTA' row indicates the select register input to which the pixel is attached. Several of the pixels have double entries indicating that the pixel may be accessed by more than one select register.

[00139] The multi pattern image construction preferably providing pattern detection for each of the pattern images is implemented in circuits depicted in dashed line box 224 IA and described in more detail in connection with Fig. 28.

[00140] Fig. 26 depicts an example of data storage for a system that receives pixel values 2602 from an imaging device and buffers them for color interpolation preferably using the color interpolation circuit presented as part of this invention. The results of the color interpolation are then buffered for tone mapping preferably using the tone mapping circuit presented as part of this invention. For a 752x480 wide VGA image, the memory may, for example, be included in the block ram provided in a Spartan-6 SC6SLX9 FPGA, a product announced by Xilinx. The logic to perform the color interpolation and the tone mapping is preferably included in the same silicon device as the memory blocks described herein. Examples of preferred data formats are depicted for each of the memory blocks in Fig. 26. 2602 represents a memory location that is preferably configured with a FIFO (First in first out) storage register to provide a preferably small buffer for pixels received from an imager or other image pixel data source that is typically streamed from the imaging device at a relatively consistent rate as it is acquired and processing of the pixel data is preferably begun with relatively little delay. The pixel order is preferably in sequence pixel by pixel for successive pixels in a row and row by row for successive rows in an image. The color interpolation and the bilateral filter operation in the tone mapping each operate on their own individualized supporting array of pixel data. Pixel data from the camera or other image source is used to supply data for the color interpolation, and the logarithm of the pixel luminance value is calculated using the color interpolated output of the color interpolation circuit. For color images acquired using an imager having a color filter array, color pixel values are used along with interpolated RGB (Red, Green, Blue) color pixel values as the data input for the tone mapping. In the examples, a 5 row by 6 column array of imager pixel data is used for the color interpolation and a 5 row by five column array of the calculated, logarithmically encoded pixel luminance values is used for the bilateral filter calculation in the first stage of the tone mapping. The sizes of the supporting arrays are given as examples and the invention is not limited to supporting arrays of this size. Furthermore, the sizes of the supporting arrays for the color interpolation and for the tone mapping do not need to be the same. To acquire n rows by m columns of supporting data for the a calculation, approximately n minus one times the number of pixels per row in the image plus m pixels of image data need to be buffered to provide pixel data over the full supporting array to perform the calculations for a given pixel. As explained and provided for elsewhere, at pixel locations that are near to one of the image boarders, pixel data may not be available for the full supporting array. Examples are given of ways to perform the calculation using pixel data that is available and calculations may be performed after the image data available for the supporting array is acquired bypassing buffering operations for data that is not available. The portion of the tone mapping calculation that utilizes the supporting array preferably operates on values in the array that are based on the logarithm of the luminance calculated for each interpolated pixel value so the calculated log luminance values, or at least the interpolated pixel color values needed to support this calculation need to be buffered for the n minus one full rows plus the m pixels to acquire the n rows by m columns of supporting pixel data. After the supporting array based bilateral filter portion of the tone mapping operation, the result of the bilateral filter calculation is used in additional calculations and is combined with the original pixel color component values to obtain the tone mapped pixel output values so the pixel color component values need to be saved in buffer memory while log luminance data calculated from the color pixel values is acquired and used for the supporting array for the tone mapping operation. For n_c rows and m_c columns of data in the supporting array of pixel values for the color interpolation and n_t rows and m_t columns of data in the supporting array of pixel values for the tone mapping operation (n_c + n_t - 2) times the image row length in pixels plus (m_c + m_t) pixels need to be acquired, excepting abbreviated requirements for pixel locations that are close to a boarder of the image, to provide data to perform the combined color interpolation and tone mapping operations. A few additional pixel times may be needed to provide for pipelining delays in the calculations. For five rows of supporting data for the color interpolation and five rows of supporting data for the tone mapping operation, this requires only a little more than eight row times of delay and a little more than eight rows (four rows for each operation) of buffered data in comparison to 480 rows in the image used in the example. This represents only about 1.7 percent of the total image and minimizes the need for buffer memory and the added delay between acquisition and display or processing of an image for control applications. In Fig. 26, pixel values acquired from an imager are acquired and optionally temporarily buffered in input register or buffering array 2602. After optional conversion in pixel format, values from buffering register/s 2602 are stored in imager data row buffer array 2630. Buffer arrays 2630, 2631, and 2632 are preferably organized in similar arrangements, so the most detail will be provided for 2630. The buffer is preferably configured for cyclical access so the newest pixel is entered at the last pixel location at the end of buffer area 2604 that provides storage for the portion of the newest row of pixel data being entered overwriting the corresponding portion of the oldest pixel data stored in the pixel area 2605. For n rows of supporting data, n - 1 rows of storage are provided by partial rows 2604 and 2605, and full rows 2606, 2607, and 2608. Optionally, full rows of buffering space may be provided for each of the five rows of buffered data relaxing the need to carefully sequence access to data. A small number of temporarily storage locations for pixel data may be provided where needed to assure that pixel data needed for calculations may be acquired from the buffer 2630 before it is overwritten. Since the size of the memory blocks needed to provide row buffer space for imager pixel row buffer 2630, color vector row buffer 2631, and logarithmically encoded luminance value row buffer 2632 together consume a significant silicon area and the amount of memory needed to meet these storage requirements may be the limiting factor that determines the size and cost of an FPGA needed to implement the design for an FPGA based implementation, the preferred option to provide a shared space for the partial row storage needed for portions of the first and last rows of buffered image data is presented here. As indicated elsewhere, a column of pixel data is acquired simultaneously or in a preferably short time interval from buffer 2630 and after an optional format conversion is stored in the color interpolation register 2610 where it is used with adjacent columns of data previously saved in buffer area 2610 to provide ready access to the supporting kernel of pixel data for the color interpolation calculation. In a preferred sequence, to provide the new column of pixel values, one for each of the five rows of data in the kernel in the example, the pixel value about to be overwritten by the pixel from imager data from register 2602 is read from the beginning of pixel row buffer 0, and this value, the value about to be written to row buffer 4, and pixel values from corresponding pixel column locations in pixel row buffer 1 2606, pixel row buffer 2 2607, and pixel row buffer 3 2608, constitute the column of pixel values that are written to the working register array 2610 after optional format conversion. In a preferred implementation, the pixel value acquired from input register 2602 is then written to buffer register 2604 overwriting the value just read from pixel row buffer 0. As just indicated, buffer area with partial color row buffer 4 2612 and color row buffer

0 2613 in a shared area and color row buffer areas for rows 1, 2, and 3 at 2614, 2615, and 2616 are preferably handled in a similar way so one should refer to 2630 for the more detailed description. As noted earlier, the number of rows of storage provided for buffer 2630 is preferably equal to the n_c - 1 and the number of rows of storage provided for buffers 2631 and 2632 are preferably equal to n_t - 1. n_c and n_t are both five in the example but either or both may be other values and n_c does not need to equal n_t to practice the invention. Color vector values in buffers 2631 and logarithmically encoded luminance values in 2632 are preferably entered at nearly the same time and since the logarithmically encoded luminance values are calculated based on the corresponding color vector value, the two separate buffers may be administered as a combined, shared structure or as a further option, the logarithmically encoded luminance value may not be buffered but calculated as needed. The complicating factor for implementing this option is that when the logarithmically encoded luminance values are not buffered their values need to be calculated once for each row in which they are used in the kernel or supporting array (n_t or five times in the example) so the somewhat involved logarithmically encoded luminance computation may need to be repeated n_t -1 times after the first. Color vector values in 2631 generally need to be accessed for only one set of calculations to compute the final tone mapped pixel value and this may lead to some simplification in some applications so that buffer 2631 and color calculation delay buffer 2637 may optionally and even preferably for some applications be provided as a single first in first out or other block storage style of memory device. The only access needed in the preferred implementation is to read values from the first location of color row buffer 0 2613 before overwriting this location with the value input at the last location of color row buffer 4 2612. When the row correlated buffer as shown is used, color calculation delay buffer 2617 provides storage to cover the pixel processing time increments for the time that values are in the array 2627 during calculation and also additional pixel processing times to allow calculation pipeline delay times and scheduling times from the time that the value is read from color row buffer 2613 before it would otherwise be overwritten and the time that it is used in the calculation to provide the tone mapped pixel value. The pixel acquisition information AA that is optionally included with the input pixel value is preferably buffered and kept correlated with the pixel for which it was generated and passed from the image pixel value input to the demosaiced, tone mapped pixel value output. The values AA are stored with the logarithmically encoded luminance value along with 16 bit logarithmically encoded luminance values to utilize the 18 bit storage locations provided in the Xilinx FPGA but may be buffered separately or may be grouped with the color vector values.

[00145] Examples of pixel data formats are given for an imager that provides high dynamic range pixel data encoded in a binary or other floating point data format. The data from the imager as indicated at 2601 may, as an example, be zero for zero values and may be fully normalized for nonzero values with the leading 1 in the binary value suppressed. The five bit binary exponent is EEEEE and the 9 bit binary value is WWWVW. AA is optional data associated with the pixel value that may, for example, indicate if the pixel value is the result of a saturated reading or of an under-utilized A/D range. Such indications may indicate that the illumination of the pixel varied over the integration time, perhaps due to a varying light source or the presence of a high contrast edge in a part of the scene that is in motion during the exposure. Other reasons for anomalies may be due to the choice of imaging device settings for the image acquisition. In all of these cases, the information provided by AA may be helpful in responding appropriately to the acquired image data. The indication, if provided may optionally be fewer or more than two bits long. Pixel data in buffer 2631 may optionally be stored in the same format as 2601 or optionally in integer form or in a modified floating point form. Data is preferably converted to binary integer form (24 bits in the example) for the color interpolation calculation.

[00146] In the preferred design, interpolated, high dynamic range, RGB color pixel values are provided by the color interpolation calculation and the luminance value is preferably calculated for each pixel value and preferably converted to a logarithm to the base 2 value having a binary encoding. This value may take the form of values 2618 of a five bit integral part IHII and an eleven bit fractional part FFFFFFFFFFF. The value AA is grouped and stored with the 16 bit logarithmically encoded luminance value primarily to utilize the 18 bit width provided for memory blocks in the Xilinx FPGA. The red, blue, and green components of the pixel color components may each need 24 bits or more to represent them in binary integer format without losing resolution. As a preferred option, to preserve needed resolution and represent the color values more compactly, each color component is converted to a floating point or preferably to a logarithmically encoded format, preferably like, or at least compatible with the format of the logarithmically encoded luminance value calculated for the pixel and the logarithmically encoded luminance valued is preferably subtracted from each of the red, green, and blue logarithmically encoded color component values for the pixel to create the color vector values to store in the buffer area. The subtraction in the logarithmic space corresponds to division to provide the ratio of each color component to the luminance value in linear space. This logarithmically encoded ratio typically covers a smaller range than the original pixel color component value enabling a more compact representation of the pixel data. The color components, when expressed as a ratio of color component value to luminance so that the resulting ratio is a di- mensionless value becomes transparent to tone mapping algorithms, such as those provided herein, so that the value is already in the same form that it assumes after tone mapping and its value is unchanged by the tone mapping. In other words, the ratio becomes transparent to the tone mapping operation. Because the dimensionless ratio of the original color component to the luminance of the pixel is in a form that is not changed by the tone mapping operation, it is not subject to luminance compression factors that may deviate greatly from unity in the tone mapping operations. Thus, values representing the pixel color in dimensionless form may be encoded and stored in a resolution that supports its final use for rendering of the tone mapped image thereby reducing the buffer storage space and data link transmission bandwidth requirements. In many cases, the resolution needed for final rendering of the image may be supported by eight or fewer bits per color component. The preceding applies to RGB encoding but necessitates the redundant storage of three color components in addition to the logarithm of the luminance. It is preferable to use and convert to a color space that expresses luminance either directly or indirectly as one of its components. For example if the popular YUV pixel encoding is used where Y is luminance and U and V are color components, U/Y and V/Y are dimension- less as indicated and may be calculated before tone mapping and optionally expressed in logarithmic form. In calculation of the ratio, to avoid division by zero, a convention such as supplying a black equivalent for U/Y and V/Y (or R/Y, G/Y, and B/Y) may be used for this special case. The values just indicated may be used for the COLOR VECTOR values 2611. If the YUV or other color space having luminance as one of its components is used, since luminance Y is one of the three components, there are only two color dependent components rather than the three color dependent components present in the RGB color space. Then only the luminance term is affected by the tone mapping and only the U/Y and V/Y terms need to be stored in buffer 2631 during the tone mapping operation. If the RGB color space is used, only the separate luminance term is affected by the tone mapping operation and as with U/Y and V/Y, the R/Y, G/Y, and B/Y terms are transparent to tone mapping, but there are three terms instead of two. Since the logarithmically encoded luminance value is stored with the color vector value, the tone mapped pixel values in the form where they are not divided by the pixel luminance may be recovered by multiplying the color components expressed as dimensionless ratios by the tone mapped pixel luminance value to provide the tone mapped color pixel value. For logarithmically encoded values, addition of the logarithmically encoded pixel luminance to the logarithmically encoded color component in ratio form is the equivalent of taking the product of corresponding linearly encoded terms. If the pre tone mapped value is needed instead, then the color components that are in ratio form may be multiplied by the pixel luminance value that is not tone mapped. The advantage is that in the format just indicated, the pixel color information may be represented with reasonable resolution using fewer bits, (8 or 12 or fewer bits per color component in the examples as opposed to using as many as 24 bits or more in linearly encoded integer form) for each of the color components. The values generated as just described may, as an example, be encoded as a binary encoded logarithm to the base 2 with a four bit integral (signed or offset binary form) part IHI and an eight bit fractional part FFFFFFFF. Values that would otherwise be less than or greater than the range provided in the memory locations are preferably clamped to the corresponding minimum and maximum values for the range that is provided. In this way, values that might otherwise be badly in error if randomly clipped are set to their nearest equivalent value for the range provided. Values 2603 stored in row buffer 2630 may optionally be left in the same floating point format as indicated for values 2601 as received or optionally converted to an alternate format such as integer form at the input stage. Values 2611 are converted to 24 bit binary encoded integer format as indicated at 2609, preferably as part of the operation to read them from buffer 2630 for use as source data for the color interpolation calculation in register 2610. The color vector 2611 is preferably encoded compactly as a ratio using one of the options described above and may, for example be encoded as a pair of 8 bit values that need only 16 bits of storage space. Alternatively, the color information may be encoded as a 36 bit value made up of three 12 bit logarithmically encoded values generated as indicated above, with the three values for the respective red, green, and blue pixel color components as depicted in the alternate version for the first note of Fig. 26. The logarithmically encoded luminance values with the optionally included pixel acquisition information AA are preferably encoded as described pre- viously and the five bit binary value IIIII and 11 bit fractional value FFFFFFFFFFF along with AA represent the data format 2618 preferably stored in log luminance row buffer 2632. The log luminance values 2626 read from buffer 2632 are preferably read without inclusion of the pixel acquisition information AA and used, preferably in the format in which they are stored, as the data base for the bilateral filter calculation that uses values from tone mapping register array 2627 as the source of pixel kernel values for the bilateral filter calculation. The buffer 2625 provides buffer storage for pixel acquisition information AA during the time starting when this data would be overwritten if left in buffer 2632 and ending when it is included with the output pixel value 2628. The output pixel value preferably includes values that are successively subjected to color interpolation and then to the tone mapping operations. The values are preferably output in a form that is ready for additional image processing such as stitching or de-warping and/or feature recognition or display. This form may, for example, be an eight or more bit integer representation for each color component as indicated in the second note in Fig. 26 and may include the pixel acquisition information AA. Other bit lengths may be provided for pixel data depending on the application. The features indicated in Fig. 26 may be applied for configurations of the device that may, for example, include tone mapping but not color interpolation or color interpolation but not tone mapping. In these applications, data items not needed for the configurations may be omitted. As pixel row buffer 4 expands to complete row 2605 and become a full row, pixel row buffer 0 shrinks to zero size. Calculations for pixels in the current row are completed for the border columns of pixels where pixels may be shifted to their appropriate positions in the array to perform calculations for pixels near the border prior to performing calculations for the next row of pixels. Options for finishing one row and beginning another include, shifting the pixels in the array 2610 to assume their correct positions for calculations for pixel locations near the right border of the array without introducing new columns of pixels that would be outside of the border, or entering new columns of pixels that are offset by one row and shifting them into the array as calculations are completed for pixels near the border of the previous row. In this case, columns of pixel values shifted in to initialize portions of the array 2610 for calculations for pixel locations in the next row are not accessed until calculations for pixel locations in the current row are complete and calculations for pixel locations in the next row for which they are properly aligned are begun. Then when calculations for pixel locations in the next row begin, pixels in columns at the start of the row will already be in the array 2610 and calculations for pixel locations in this new row may be initiated and pixels remaining in the array from calculations for pixel locations in the previous row should not be accessed for calculations for pixels near the border in the new row. When pixel row buffer 4 expands to fill all of row 2605 and pixel row buffer 0 shrinks to zero and ceases to exist, the row buffer numbering as depicted is all decremented by one at the start of the new row and pixel row buffer 4 in row 2605 becomes the new pixel row buffer 3 and pixel row buffer 1 in row 2606 now becomes the new pixel row buffer 0 and pixels are added to a newly formed pixel row buffer 4 at the start of row 2606. Thus, the row buffer locations associated with given rows in array 2610 advance cyclically by one row in row buffer array 2630 and this advance results from the incremental advance in rows in the image used for calculations related to pixels in successive rows of the image and data in row buffer 2630 is not moved but the row to which new pixel values are written overwriting the oldest pixel value advances cyclically through the array. For processing successive rows of image data, the row with the dual partial buffer interface progresses to the last row 2608 of the buffer array 2630 and then cycles back to row 2605 of the cyclic array. [00149] The description here for buffer array 2630 and its associated calculation supporting array 2610 may be applied to row buffer array 2632 and the associated tone bilateral filter calculation supporting array 2627. In this case, the same kind of control to restrict access to values in the array 2627 that are outside of the image border or replace these values with zero or with another value appropriate to the calculation may be implemented to provide the same options in transitioning from one row to the next as are provided for the color interpolation calculations associated with buffer array 2630.

[00150] Fig. 27 is a simplified flow diagram of the operation of a device configured to accept an image with missing color components and provide the missing color components. For example, when Bayer filter patterns are used, only one of the three color components is normally supplied at each pixel location and the device preferably supplies pixel values for each of the two missing components for each pixel in the image. Pixels are input at 2701 from an image source such as an imager having a Bayer filter array to provide one color component for each pixel location. In a preferred embodiment, missing pixel values are provided for each of the two missing color components based on calculations that use pixel data from a five row by five column supporting array of input pixel values with calculations made for the pixel that is centered in this supporting array. Pixel data is stored in a buffer at 2702 after optional format conversion and conditioning that may include but is not limited to color correction. The decision circuit 2703 and delay circuit 2704 operate together to delay transfer of data to the calculation buffer

2705 until it is available in the row buffer 2702. When the data is available, it is copied, preferably a column of values at a time, to the calculation buffer at 2705 and when data is available in buffer 2705 to support the calculation for another pixel, control is passed to decision block

2706 where a check is made to see if a new key should be calculated. If a new key is needed, it is calculated and otherwise its calculation is bypassed. As indicated in the more detailed description of a preferred circuit, a value for the key is calculated based on pixels in a neighborhood of the pixel or pixels for which missing color components are being supplied. The calculation circuit is configured to calculate the key at 2707 and the key is decoded at 2708 to provide an indication of the presence of edges along with their orientation and this information is used in selecting an appropriate conversion algorithm or conversion circuit configuration to provide missing color components for each of the pixels for which a particular key is used. Optionally, the pattern indicated by the key may be interpreted differently for the individual pixel locations for which it is applied and/or may be used to detect the presence and orientation of features other than or in addition to edges. The calculation circuit is configured to calculate the value of a missing color component for the pixel for the pixel location currently centered in the supporting array of pixel values at 2709. The calculation algorithm chosen and executed in a dedicated circuit as indicated here or optionally as a routine in a software program is based on a number of factors that may include but are not limited to, the color of the missing color component being calculated, the color of the Bayer filter for the current pixel for which the calculation is being performed, the location of the filter color for the current pixel relative to other filter colors in the color filter pattern, the proximity of the current pixel to a boundary of the image, the decoded value of the key for the current pixel. After configuring the calculation circuit or optionally selecting an appropriate calculation routine based at least in part on factors indicated above, a calculation is performed to provide an intermediate value for the missing color component. The intermediate value may be negative or may exceed a range provided for the pixel value. In block 2711 , the intermediate value is clamped to the accepted pixel output range to provide the value for the missing color component that is stored in a buffer for output or for fur- ther processing that may include color correction at 2712. There are normally two color components to provide for each pixel and in decision block 2703 a determination is made as to whether there is another color component to provide for the pixel in which case control is passed to block 2709 and if all of the color components have been provided for the current pixel, control is passed to 2703 to service the next pixel. In the circuit depicted in Figs. 22 and 22A, selection of the circuit configuration to calculate one or more missing color components for a given pixel or pixels is based in substantial part on pattern detection performed for a preselected array of pixels that preferably have green filters in the color filter array. The preselected array of pixels is used as the base for a pattern image and is referred to as the pattern array. Values that are preferably binary (either one or zero) are calculated for individual pixels in the pattern array preferably based on comparisons of values of the individual pixels in the pattern array to a threshold value. The single bit binary values of the compare outputs are referred to as pattern values and the image formed by pixels that are given the pattern values and arranged to generally match the geometric layout of the pattern array will be referred to as the pattern image. Pattern values in the pattern image are sampled and analyzed to detect patterns in the pattern image that correspond to patterns such as edges and edge orientations in the original pixel values recorded in the image. In the circuit of Fig. 22, the circuit that is selectively configured to calculate the various interpolated values is shared to calculate the average of the values of the pixels in the preselected pattern array. Then a pattern image is formed by, for example, assigning a pattern value of one to pixels in the pattern image that correspond to pixels in the array whose values are approximately greater than the average and assigning a pattern value of zero to pixels in the pattern image that correspond to pixels in the array whose values are approximately less than the average. In the circuit of Fig. 22, a key is generated from the binary pattern values and used as an index into a table or as an input to a logic circuit to select or to generate a value that is indicative of the circuit configuration that is appropriate for the interpolation operation. In the circuit of Fig. 22, register 2231 holds the average value that is compared in compare circuits 2216 against pixel values from pixels in the preselected pattern array and the binary outputs of the compare circuits provide the binary values for the pattern image that is generated. In block 2217, these binary compare values are arranged in a predetermined sequence to provide a key that is indicative of the pattern image pixel values and in block 2229 the key is decoded to provide an indication of the circuit configuration appropriate for the pattern image. In preferred configurations, the patterns that are detected in the pattern image include those that indicate the presence and the orientation of approximately horizontal and approximately vertical edges in the pattern image. Optionally, diagonal edge features or other features the pattern image may also be detected. As an example, these other features may include detection both of edges that span greater distances and ones that span shorter distances and the shorter and longer edges may be treated either as a common or as discrete patterns. The circuit of Fig. 22 that uses the average as the compare threshold for the pattern performs well and the threshold provided by the average adapts well to both very brightly and very dimly lighted areas in an image as well as to midrange lighting conditions so that use of the average is one of the preferred ways to provide the threshold level used to generate the pattern image. One limitation of the average as the base for the one/zero classification of pixels in the pattern image is that when the pixels in the pattern array includes both very dim and very bright pixels, the average may be skewed in a way that provides too few or too many ones or zeros in the pattern image to make it as useful as it might otherwise be to provide an indication of patterns that are present. More generally, compare threshold levels that provide other balances in the relative number of ones and zeros in the pattern image than that provided by using the average may reveal patterns in the image that are missed in the single pattern image provided by the circuit using the average value of the pixels in the pattern array as just described. Carrying this one step further, it is preferable to select compare thresholds to generate a set of different pattern images that include ones with differing numbers of ones or of zeroes, for pixels in the pattern image (at least for those not containing pixels of equal value). In an alternate embodiment depicted in Figs. 21 A, 22A, 23 A and 28 and preferred for color interpolation for very high dynamic range images, most of the circuit of Fig. 22 is retained but instead of providing the average 2231, compare circuits 2216 are reconfigured and preferably used multiple times to provide a structured indication of results of compares of brightness of pixels in the pattern array relative to one another. The compare circuits shown as CBl 2810 through CB9 2805 in Fig. 28 are depicted as 2242A in Fig. 22A. Blocks 2242A, 2243A, 2244A, 2245 A, and 2246A denoted in dashed line box 224 IA in Fig. 22A correspond generally to the more detailed representation in Fig. 28. Compare result storage elements BOl 2815 through B89 2828 provide the comparison result matrix 2243 A. Pixel array 2831 in combination with values stored in 2800 and pattern detection logic provided by logic expressions in block 2840 provide the base for the multiple patterns detected on the multiple pattern images in block 2244A of Fig. 22A. Logic equations for ME, CME, H, V, DD and the prioritizing indication 2858 provide the detail for combining and prioritizing the pattern results to provide information to make a pattern selection in blocks 2245 A and 2246A. The compare indications from CBl through CB9 that indicate the results of comparisons, one to another, of pixel values in the pattern array are used directly, preferably without additional compares, to generate multiple pattern images for the pattern array and these pattern images or their associated key values are preferably used to at least in part select or configure the calculation circuit to provide the interpolated color values. In a preferred embodiment, the pixel value selected as a reference pixel in the pattern array is used in a manner similar to put in place of the average used in Fig. 22 and compared against other pixel values in the pattern array to generate a set of binary values that indicate how the brightness of the selected pixel compares with the brightnesses of other pixels in the pattern array. For comparison of pixel 'a' against pixel 'b', the compare value for comparison of pixel 'b' against pixel 'a' may be inferred as the logical complement of the result of a comparison made when the comparison order is reversed. In paragraphs that follow, the term reference pixel will be used to convey meaning of the pixel in the pattern array whose value is used as the reference value for comparison for a particular subset of results preferably obtained as a direct or as an inferred comparison. The results of the compares are preferably encoded so that a pixel in the pattern image is assigned a pattern value of one if its intensity is approximately greater than the selected reference pixel and a pattern value of zero otherwise. Similar compares are preferably performed using other (preferably all other) pixels in the pattern array as the reference pixel and these other pixels are preferably selected one by one in sequence as the reference pixel so that a set of results for comparisons of pairs of pixel values for pixels in the pattern array is generated. The array of comparison values constructed as just indicated is preferably arranged to provide data that corresponds to separate pattern images with each pattern image associated with the pixel in the pattern array that was used as the reference pixel to generate the pattern image. It is preferable to limit the number of comparisons that are made by assuming that the result of comparing pixel "a" against pixel "b" is the logical complement of comparing pixel "b" against pixel "a" as indicated above. When all of the pixels in the pattern array are included as reference pixels either through direct or implicit comparisons so that compare results for all pairs of pixels in the pattern array are included, these results provide information needed to generate a pattern image and its key for each pixel in the pattern array as it is used as the reference pixel with ones assigned to pixels that are approximately greater in brightness than the associated reference pixel and zeros assigned to pixels whose brightness is approximately less than that of the associated reference pixel. The reference pattern image value associated with the reference pixel may be assigned a pattern value of either a zero or one, but it is preferable to establish a uniform convention and to use one or the other assignment consistently. If the reference pixel is assigned an associated pattern value of zero there will be no pattern images that are all ones and if the reference pixel is assigned an associated pattern value of one there will be no pattern images that are all zeros. But, in either case, for n pixels in the reference array there will a pattern image that contains exactly one one, another that contains exactly two ones, etc. through a pattern image that contains exactly n-1 ones. Another way of stating this is that the set of reference images generated will be constructed so that for a reference image having n pixels, each of the n pixels is used as a reference pixel to generate an associated pattern image. Then in this set of n pattern images, when none of the pixel values in the pattern array are equal, there is one that has exactly r pixels that have a pattern value of one for every integral value of r between and including 1 and n-1. Thus, all of the pattern images generated by segregating the reference image into non-empty groups of larger and smaller pixel values and assigning a pattern image value of one to the pixels with the larger values and a pattern image value of zero to the pixels with the smaller values are provided. In the circuit description, some of the statements are logically correct only when all pixels in the pattern array have discrete values that are when none of the pixels in the pattern array have equal values. In the circuit implementation, the circuit would be considerably complicated if the cases of equal pixel values were detected and treated as special cases. Furthermore, when pixel values are equal or nearly equal, the choice of the circuit used for the interpolation does not normally change results that much. Additionally, slight noise would easily alter the equality status anyhow making it prudent to sidestep the complicating issues presented when equal values are treated as special cases. The circuit is preferably configured so that approximations introduced to avoid handling equal pixel values as special cases do not lead to circuit malfunction or to highly objectionable results. Provision of a consistent bias in treatment of comparison results for equal pixel values is one way to reduce the number of logical flaws that might otherwise propagate into objectionable circuit behavior. In the example, a compare value of one is assigned when the value of the pixel compared against a selected reference pixel is greater than the selected reference pixel and a compare value of zero is assigned otherwise. This is consistent with presuming a bias that when a pixel of equal value is compared against the selected reference pixel, it will be assigned a value of zero. In the pattern images that are generated, there is an implied self comparison of the selected pixel against itself and this is preferably also assigned a value of zero when the compare criterion just indicated is used. If the compare criterion to which a one is assigned is changed from greater than to greater than or equal to (i.e. not less than); then, the implied self comparison values are preferably assigned a value of one to be self consistent. In certain alternate designs, the assigned compare values of one and zero may be reversed since the configuration of the interpolation circuit may in most cases be the same for a pattern images and its negative or complementary pattern image. When such a reversal is used, care should be taken to properly handle special cases that do depend on high or low intensity or that for various other reasons might not be transparent to the one/zero inversion. One such ex- ample, as explained elsewhere, is that of patterns from portions of an image with multiple edges spaced approximately one pixel width apart. In the description of the circuit in Fig. 28, it is presumed that pixels in the pattern array have discrete values and that features such as those just described are provided to prevent or at least limit undesirable performance when equal pixel values are encountered. The statements above are not intended to limit the scope of the invention but to provide a preferred option to simplify the circuit by structuring it to operate satisfactorily without treating all cases when pixel values are equal as special ones.

[00154] In Fig. 28, GO through G9 are used to indicate pixel locations or associated pattern values of pixels that preferably have green filters in the color filter array and which are preferably positioned as indicated by the array 2830. The actual respective values of these pixels are indicated by PO through P9, respectively. 2831 indicates the key constructed according to equation 2843 associated with the pattern image 2830. The data paths for these values and for the selected pixel value of one of the pixels PO through P4 2804 at 2802 are preferably wide enough to provide full width data paths for transmission of the pixel values.

[00155] The tags S12, S32, S03, S23, S43, S14, S34, S05, S25 and S45 indicate storage registers in Fig. 22A that are preferably connected to the respective inputs P9, P8, P7, P6, P5, P4, P3, P2, Pl, and PO when the circuit 2800 of Fig. 28 is included in the circuit of Fig. 22A. Pixel array 2830 indicates the location of pattern array pixels GO through G9 in the imaging array. These pixels are preferably ones with green filters in the color filter array and the imaging array is preferably used when interpolated pixel values are calculated for the pixel location at G6 and for the neighboring non-green pixel location between Gl and G6. Select circuit 2801 responds to a select control signal, not shown in the simplified logic diagram, to place the selected one of pixel values PO, Pl, P2, P3, or P4 on bus 2802 thereby routing the selected pixel value to the inputs of compare circuits CBl (2810) through CB9 (2805) where the pixel values of Pl through P9, respectively, are compared against the selected value that is used as the reference pixel value. Each compare circuit preferably outputs a one bit compare value. The output of CB9 2805 is asserted on column line 2811 and may be stored in the storage flip-flop: B09 2812 by asserting storage enable line 2806, B 19 by asserting storage enable line 2814, B29 by asserting storage enable line 2819, B39 by asserting storage enable line 2820 or B49 2822 by asserting storage enable line 2821. Values from compare circuits CB8 through CBl that have storage flip-flops in the same row are saved along with the output from CB9 when a storage enable signal is asserted. Output 2813 is the non-complemented output and 2818 is the complemented output of storage flip-flop (or memory cell) B09. Complemented output 2813 is included because it represents the value of the transpose term B90 that is not provided as a separate storage register because it would be a duplication of the information provided by B09. Particularly for the copy used to obtain the ten compare results beginning with B59 2826 in row 5 and including locations in this row and in succeeding rows through B89 2828 in row 8, these values would need extra logic to acquire the extra transpose terms at the time that the copied over values were acquired. For each of the ten diagonal terms BOO through B99, the first and second numerical digits in the name are equal and these terms each imply a self comparison of the reference pixel against itself and are preferably either all zero or all one as explained above. The complement outputs and the constant diagonal terms are included for completeness in the description and it is presumed that they may be optimized out in an actual logic implementation. Storage of compare results in rows 4 through 0 (terms B4j through BOj for terms in column j of each row 4 through 0) is synchronized with selection of P4 through PO so that the Bij term represents the result of comparing pattern array pixel value Pj against pattern array reference pixel value Pi for i and j taking on values 0 through 9. The outputs of the complement (Bji) of Bij provide values for term Bji that serve to fill in the missing terms in the triangular matrix to provide values for a full 10 by 10 matrix. The 10 values of BOO through B09 then provide the pattern image pixel values when PO is the reference pixel and in general for completed 10 element row i BiO through Bi9 provide the pattern image pixel values when Pi is the reference pixel. In the example in Fig. 28, columns of pixel values in the array used as the base for calculation of the interpolated values are shifted to the left as interpolated values are provided for each pixel location and the operations indicated in association with Fig. 28 are performed with the pixels in a single location. This is explained in more detail in the description of Fig. 22A. Additionally, it is presumed that the calculation to be described in association with Fig. 28 was previously performed two pixel location increments earlier when the pixel value that is now in G5 was in GO, the pixel value that is now in G6 was in Gl, the pixel value that is now in G7 was in G2, the pixel value that is now in G8 was in G3, and the pixel value that is now in G9 was in G4. Because of the serial sequence corresponding values calculated for interpolation at the proceeding pixel or pixels for BOl, B02, B03, B04, B12, B13, B14, B23, B24, and B34 are still valid but now apply to corresponding pixels as indicated above so they are copied to B56, B57, B58, B59, B67, B68, B69, B78, B79, and B89, respectively, by asserting a store enable signal at 2725. Following this, while pixel values at PO through P9 are stable, select circuit 2701 is configured by signals not shown in the simplified circuit to select signals P4, P3, P2, Pl, and PO in sequence and gate the selected pixel value to bus 2702 where it is input to compare circuits CB9 2805 through CBl 2810 and compare values are saved in appropriate rows of the triangular matrix as described above. Logic expressions 2840 are preferably implemented in logic circuits to provide pattern recognition that is based on patterns detected in one or more of the pattern images constructed from the comparison results saved in memory cells Bij in circuit 2800. Equation 2841 is a statement of the fact that self compare values are 0 (or optionally 1 depending on the compare criteria). Equation 2842 indicates that the comparison of "b" to "a" is the logical complement of the comparison of "a" to "b" and is used to fill out the rows to 10 elements each for the triangular array in circuit 2800. The expression 2843 provides ten sets of values for KEYi for values of i ranging from 0 to 9. KEYi is an ordered list of the values in the i^l row of the array of values provided by circuit 2800 and completed using equation 2842. Ten pattern images are provided by setting the ten pattern array values G9 through GO 2830 equal to corresponding values in KEYi as indicated at 2844. NBi 2845 is zero or false when Bi2, Bi4, Bi6, Bi8 and Bi5 are all zero or all one and is used to screen out blank full zero or full one patterns for Vi and Hi. A vertical pattern Vi 2846 for the pattern image associated with the i^th row is asserted when the five pairs of values (B i2, BiI), (Bi4, Bi3), (Bi6, Bi7), (Bi8, Bi9), and (Bi5, Bi6), each pair having elements from the same column, are all matching pairs as indicated by exclusive or values of zero and the matching pairs are not all zero (or all one) as indicated by a nonzero, true, value of NBi. For the vertical patterns, there are two columns in the pattern array that contain 3 elements. To demonstrate that there are options in defining the patterns, the pairs (Bi6, Bi7) and (Bi5, Bi6) are both matched against each other so that all three elements G5, G6, and G7 must match for the vertical pattern detection Vi to be asserted while GO is not included at all in the vertical pattern criterion. Many other options for pattern recognition may be used to practice the invention. A horizontal pattern Hi 2847 for the pattern image associated with the i^th row is asserted when the five pairs of values (Bi2, Bi7), (Bi4, Bi9), (Bi6, BiI), (Bi8, Bi3), and (Bi5, BiO), each pair having elements from the same row, are all matching pairs as indicated by exclusive or values of zero and the matching pairs are not all zero (or all one) as indicated by a nonzero, true, value of NBi. In the example, the elements Bi2, Bi4, Bi6, Bi8 and Bi5 are each elements of different pairs both for the expression Vi used to indicate the vertical pattern match and for the expression Hi used to indicate the horizontal pattern match. Additionally, because the match indicates equality of members of each of the individual pairs, the values of all 10 of the elements may be inferred from the five values Bi2, Bi4, Bi6, Bi8 and Bi5 when a horizontal match Hi is asserted and the values of the nine elements Gl through G9 may be inferred by the five values Bi2, Bi4, Bi6, Bi8 and Bi5 when a vertical match Vi is asserted. Use of the smaller subset of elements Bi2, Bi4, Bi6, Bi8 and Bi5 to detect the full one pattern, the full zero pattern and the multiple edge patterns MEi and complementary multiple edge pattern CMEi using this subset of pixels results in a substantial saving in the logic circuits needed to detect and distinguish patterns of interest. Another way of stating this is that a pattern detection circuit is simplified by preferably choosing single representatives from each subset of elements where the elements in each of the subsets must match to fulfill a primary pattern matching condition. Then, for a pattern matching condition, the values of the representatives provide an indication of the values of the elements in the larger group of combined subsets. Matches of patterns in the group of representatives may then be used to categorize patterns that fulfill the primary pattern matching condition. The technique is preferably extended to more than one primary matching condition by arranging distinct subsets for each primary matching condition so that they share the same representatives for each of the primary matching conditions. Then tests for patterns within the set of representatives may apply to either or both of the primary patterns. This may be further extended to more than two primary patterns and/or may be applied only to portions of primary patterns.

[00157] The equations for MEi 2848 and CMEi 2849 employ the technique indicated above to provide simplified logic circuits to detect multiple edge patterns along with classification of these patterns into each of the two complementary forms as explained in association with Figs. 2OK, 2OL, 24A, 24B, 24C, and 24D. The technique is also used to provide NBi 2845 that is used to provide simplified logic circuits for both the vertical pattern Vi matching and the horizontal pattern Hi matching to screen out all zero and/or all one pattern.

[00158] As a preferred option, logic circuits DUi 2854 and DDi 2855 are provided to detect edges that are oriented diagonally up or down, respectively, in going from left to right.

[00159] In a preferred embodiment, logic circuits are provided to determine NBi 2845, Vi 2846,

Hi 2847, MEi 2848, CMEi 2849, DUi, and DDi for each value of i (0 through 9 in the example). The MEi terms are "or"ed together to provide an overall multiple edge pattern indication ME 2850. Similarly, CMEi terms are "or"ed together, Hi terms are "or"ed together, Vi terms are "or"ed together, DUi terms are "or"ed together, and DDi terms are "or"ed together, to provide CME 2851, H 2852, V 2853, DU 2856, and DD 2857, respectively. More than one pattern may be detected and it is preferable to assign a priority as indicated in the listing 2858 or optionally some other screening criteria to choose a result when multiple patterns are detected. In a preferred embodiment, ME (1st), CME, H, V, DD, and DU are given priority in that order so that a match occurring for the pattern with the highest priority is asserted and overrides any lower priority matches that may be asserted. The pattern array 2830 of this example includes pixels from five rows and four columns in the imaging array and there is advantage in including pattern features that extend over the entire or at least a larger part of the pattern array. Vertical- Iy oriented features are the most neglected in this respect. Because of the sequential processing of pixels in a row, it is possible to include results of previous, preferably the immediately previous set of pattern images as part of the pattern determination for the current pixel set. If no pattern features are detected in the current pattern set and if a vertical edge pattern was detected in the immediately previous pattern set, then a vertical edge pattern is used for this interpolation set also, but the vertical edge detection is preferably not propagated farther than from the immediately preceding edge detection to the next. Finally, if no edges are detected the nondirec- tional pattern N is preferably the default indiction when no other pattern features are detected. In a preferred embodiment, the logic just indicated is implemented in a Xilinx Spartan 6 series FPGA. With the six inputs, 64 bit lookup table devices used to implement logic functions, the logic just described may be implemented with a reasonable number of programmable logic elements. The pattern matching circuit just described performs a complex function that is similar to looking at the pixel values in the pattern array and beginning with a very high threshold as a reference value, lowering the threshold until one pixel is assigned a one in the pattern image and looking for a pattern in this pattern image and continuing this sequence, further lowering the threshold until two pixels are assigned a one in the pattern image and looking for a pattern in this pattern image and continuing this sequence until all but one pixels are assigned a one in the pattern image and looking for a pattern in this pattern image. In the preferred embodiment, by using values of pixels in the pattern array as references, calculations to find averages or medians, or use of multiple unnecessary repeated trials are avoided. Additionally, by using all of the pixels in the pattern array as reference pixels, all of the patterns, i.e. those with one one, two ones etc. through n-1 ones are provided. Since the pattern detection circuits effectively detect patterns in pattern images with any number of ones, it is not necessary to classify the patterns as to the number of ones in the pattern but only to look for patterns in all of the pattern images knowing that, for a pattern image with n pixels that have distinct values, patterns with one one through patterns with n- 1 ones are all included. The surprising result has been that in implementations tried, it may require less hardware to implement pattern detection than to count ones in an image and to port pattern images with predetermined numbers of ones to an appropriate pattern recognition circuit.

[00161 ] Logic may be provided to detect additional patterns such as diagonal edges. The description has focused on provision of edge and feature detection used to select interpolation equations or calculation circuits or routines to supply missing color values for images acquired using a color filter array. The circuit is not limited to this function and may be adapted to other tasks such as image based feature extraction that might, for example, be used to detect horizontally separated pairs of lights such as distant taillamps or headlamps for a headlamp dimmer control application. One application of such feature extraction beyond simple location of the features in the image would be to respond to probable headlamps and taillamps (detected as close spaced but horizontally separated light sources) to select specialized color interpolation routines to improve the color interpolation, since, particularly for taillamps, color is an important distinguishing feature. One way that this could be used is to cross sample or average color components detected at the pair of lamps and because of their separation improve the accuracy of the interpolated color values that are provided. Locations in the image might also be tabulated to facilitate further image processing.

[00162] Patterns that are of interest each have a certain number or numbers of ones and zeros and the patterns will show up only in pattern images with the corresponding number or one of the corresponding numbers of ones and zeros. Pixel values need to be ordered to know how many ones and zeros each will yield when used as a reference pixel to generate a pattern image with a known number of ones and zeros. Several patterns with different numbers of ones and zeros are needed to detect all of the patterns of interest. For a pattern image with n pixels it is preferable to generate patterns with every possible number of ones between 1 and n-1 and analyze each for possible patterns. By including and searching all of the pattern images of interest, on may be assumed that all appropriate patterns will be included in the composite results. This assurance may be given without knowing the number of ones and zeros in specific patterns only when all pattern images of interest are included. It should be understood that the above detail description is provided for enabling one of ordinary skill in the art to make and use the invention as recited in the appending claims. In no way should this description be interpreted as limiting the scope of the invention to any given embodiment, therefore, the appending claims are intended to include all equivalent structure and equivalent function within the respective scope.

Claims

CLAIMSWhat is claimed is:

1. An apparatus, comprising: an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm generates a plurality of patterns with all possible ones between one(l) and (n-1) for a pattern image comprising n pixels to detect features of said spectrally mosaiced, high dynamic range, digital image.

2. An apparatus as in claim 1 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

3. An apparatus as in claim 1 wherein said algorithm is further configured to generate a set of binary values indicative of the relative brightness of a reference pixel compared to the brightnesses of other pixels in said pattern array.

4. An apparatus as in claim 3 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

5. An apparatus as in claim 4 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

6. An apparatus as in claim 3 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

7. An apparatus as in claim 1 , wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

8. An apparatus as in claim 7 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

9. An apparatus as in claim 7 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

10. An apparatus as in claim 7 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

11. An apparatus as in claim 10 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

12. An apparatus as in claim 11 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

13. An apparatus as in claim 12 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

14. An apparatus, comprising: electronic circuitry for performing at least a portion of the calculations associated with an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm implements a pattern based logic comparison wherein a pixel value selected as a reference pixel is compared against other pixel values in a pattern array to generate a set of binary values that indicate how the brightness of said reference pixel compares with the brightnesses of other pixels in the pattern array.

15. An apparatus as in claim 14 wherein said detected features are at least in part used to determine selection of an equation to interpolation calculate missing color data for one or more pixels within said pattern image.

16. An apparatus as in claim 14 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

17. An apparatus as in claim 16 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

18. An apparatus as in claim 14 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

19. An apparatus as in claim 14, wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

20. An apparatus as in claim 19 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

21. An apparatus as in claim 19 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

22. An apparatus as in claim 19 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

23. An apparatus as in claim 22 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

24. An apparatus as in claim 23 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

25. An apparatus as in claim 24 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

26. An apparatus, comprising: an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm generates a pattern of results based on comparisons of pixels in a pattern array with a given pixel selected as a reference pixel in the pattern array, said pattern of results is analyzed to detect features of said spectrally mosaiced, high dynamic range, digital image.

27. An apparatus as in claim 26 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

28. An apparatus as in claim 26 wherein said algorithm is further configured to generate a set of binary values indicative of the relative brightness of a reference pixel compared to the brightnesses of other pixels in said pattern array.

29. An apparatus as in claim 28 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

30. An apparatus as in claim 29 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

31. An apparatus as in claim 28 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

32. An apparatus as in claim 26, wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

33. An apparatus as in claim 32 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

34. An apparatus as in claim 32 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

35. An apparatus as in claim 32 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

36. An apparatus as in claim 35 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

37. An apparatus as in claim 36 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

38. An apparatus as in claim 37 wherein data associated with a second series of spectrally demo- saiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

39. An apparatus, comprising: an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm generates two or more patterns of re- suits based on comparisons of pixels in a pattern array with different pixels selected as a reference pixel in the pattern array, said patterns of results are analyzed to detect features of said spectrally mosaiced, high dynamic range, digital image.

40. An apparatus as in claim 39 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

41. An apparatus as in claim 39 wherein said algorithm is further configured to generate a set of binary values indicative of the relative brightness of a reference pixel compared to the brightnesses of other pixels in said pattern array.

42. An apparatus as in claim 41 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

43. An apparatus as in claim 42 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

44. An apparatus as in claim 41 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

45. An apparatus as in claim 39, wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

46. An apparatus as in claim 45 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

47. An apparatus as in claim 45 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

48. An apparatus as in claim 45 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

49. An apparatus as in claim 48 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

50. An apparatus as in claim 49 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

51. An apparatus as in claim 50 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

52. An apparatus, comprising: an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm generates patterns of results based on comparisons of pixels in a pattern array with a different pixel from the pattern array selected as a reference pixel in the pattern array so that every pixel in the array is used as a reference pixel, said patterns of results are analyzed to detect features of said spectrally mosaiced, high dynamic range, digital image.

53. An apparatus as in claim 52 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

54. An apparatus as in claim 52 wherein said algorithm is further configured to generate a set of binary values indicative of the relative brightness of a reference pixel compared to the brightnesses of other pixels in said pattern array.

55. An apparatus as in claim 54 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

56. An apparatus as in claim 55 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

57. An apparatus as in claim 54 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

58. An apparatus as in claim 52, wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

59. An apparatus as in claim 58 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

60. An apparatus as in claim 58 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

61. An apparatus as in claim 58 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

62. An apparatus as in claim 61 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

63. An apparatus as in claim 62 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

64. An apparatus as in claim 63 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

65. An apparatus, comprising: an algorithm for calculating missing color data, said algorithm is configured to receive a spectrally mosaiced, high dynamic range, digital image and to calculate missing color data, said algorithm implements a pattern based logic comparison wherein a pixel value selected as a reference pixel is compared against other pixel values in a pattern array to indicate how the brightness of said reference pixel compares with the brightnesses of other pixels in the pattern array.

66. An apparatus as in claim 65 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

67. An apparatus as in claim 65 wherein said algorithm is further configured to analyze said set of binary data to detect patterns in said data.

68. An apparatus as in claim 67 wherein said algorithm is further configured to select an interpolation equation based at least in part on detected patterns in said data.

69. An apparatus as in claim 65 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel to generate more than one set of binary data.

70. An apparatus as in claim 65, wherein said spectrally mosaiced high dynamic range digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

71. An apparatus as in claim 70 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

72. An apparatus as in claim 70 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

73. An apparatus as in claim 70 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

74. An apparatus as in claim 73 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

75. An apparatus as in claim 74 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

76. An apparatus as in claim 75 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

77. An apparatus, comprising: electronic circuitry for performing at least a portion of the calculations associated with an algorithm for calculating missing color data, said algorithm is configured to receive data associated with a spectrally mosaiced digital image and to calculate missing color data, said algorithm implements an average based comparison wherein a pixel value selected as a reference pixel is compared against the average of pixel values in a pattern array to detect features.

78. An apparatus as in claim 77 wherein said detected features are at least in part used to determine selection of an interpolation equation to calculate missing color data for one or more pixels within said pattern image.

79. An apparatus as in claim 77 wherein said algorithm is further configured such that more than one pixel is used as a reference pixel.

80. An apparatus as in claim 77, wherein said spectrally mosaiced digital image comprises a plurality of red spectrally filtered pixels, a plurality of green spectrally filtered pixels and a plurality of blue spectrally filtered pixels.

81. An apparatus as in claim 80 wherein said missing color data is associated with a red spectrally filtered pixel, green and blue color data are calculated.

82. An apparatus as in claim 80 wherein said missing color data is associated with a green spectrally filtered pixel, red and blue color data are calculated.

83. An apparatus as in claim 80 wherein said missing color data is associated with a blue spectrally filtered pixel, red and green color data are calculated.

84. An apparatus as in claim 83 configured to receive data associated with a first series of spectrally mosaiced, high dynamic range, digital images from an imaging device and output a second series of digital images having missing color data imputed.

85. An apparatus as in claim 84 wherein data associated with said first series of spectrally mosaiced, high dynamic range, digital images is received at a rate greater than, or equal to, twenty-five images per second.

86. An apparatus as in claim 85 wherein data associated with a second series of spectrally demosaiced, high dynamic range, digital images is output at a rate greater than, or equal to, twenty-five frames per second.

87. An apparatus, comprising: circuitry for performing at least a portion of the calculations associated with an algorithm for mapping a high dynamic range digital image onto a display medium having a dynamic range lower than said high dynamic range digital image, said algorithm is configured to receive a high dynamic range digital image and decompose said high dynamic range digital image into an intensity layer and a color layer, said algorithm is further configured to bilateral tone map said intensity layer to obtain a first contrast reduction factor, said algorithm is further configured to modulate said first contrast reduction factor with a rational expression to obtain a second contrast reduction factor and recombine said color layer and said intensity layer using said second contrast reduction factor to obtain a second digital image having a dynamic range lower than said high dynamic range digital image.

88. An apparatus as in claim 87 configured to receive a series of high dynamic range digital images from a high dynamic range source and output a second series of digital images having a dynamic range lower than said series of high dynamic range digital images.

89. An apparatus as in claim 88 wherein said series of high dynamic range digital images is received at a rate greater than, or equal to, thirty images per second.

90. An apparatus as in claim 89 wherein said second series of digital images is output at a rate greater than, or equal to, thirty frames per second.

91. An apparatus, comprising: circuitry for performing at least a portion of the calculations associated with an algorithm for mapping a high dynamic range digital image onto a display medium having a dynamic range lower than said high dynamic range digital image, said algorithm is configured to receive a high dynamic range digital image and decompose said high dynamic range digital image into an intensity layer and a color layer, said algorithm is further configured to bilateral tone map said intensity layer to obtain a first contrast reduction factor, said algorithm is further configured to modulate said first contrast reduction factor with a rational expression to obtain a second contrast reduction factor and recombine said color layer and said intensity layer using said second contrast reduction factor to obtain a second digital image having a dynamic range lower than said high dynamic range digital image, said apparatus further comprising circuitry for performing at least a portion of the calculations associated with an algorithm for calculating and supplying missing color data, said algorithm is configured to receive a spectrally mo- saiced digital image and to calculate and supply missing color data, said algorithm implements a patterned based look-up table.

92. An apparatus as in claim 91 configured to receive a series of high dynamic range digital images from a high dynamic range source and output a second series of digital images having a dynamic range lower than said series of high dynamic range digital images.

93. An apparatus as in claim 92 wherein said series of high dynamic range digital images is received at a rate greater than, or equal to, thirty images per second.

94. An apparatus as in claim 93 wherein said second series of digital images is output at a rate greater than, or equal to, thirty frames per second.

95. An apparatus as in claim 91 configured to receive a series of mosaiced digital images from an imaging device and output a second series of digital images having missing color data added.

96. An apparatus as in claim 95 wherein said series of high dynamic range digital images is received at a rate greater than, or equal to, thirty images per second.

97. An apparatus as in claim 96 wherein said second series of digital images is output at a rate greater than, or equal to, thirty frames per second.

98. An apparatus, comprising: an algorithm for performing at least a portion of the calculations associated with mapping a high dynamic range digital image onto a display medium having a dynamic range lower than said high dynamic range digital image, said algorithm is configured to receive data associated with a high dynamic range digital image and to calculate histogram statistics to characterize a digital key value of an image.

99. An apparatus as in claim 98 wherein the algorithm is further configured to analyze the shape of said histogram to calculate said digital key value.

100. An apparatus as in claim 98 wherein said image histogram is calculated on an output of a bilateral filter.

101. An apparatus as in claim 100 wherein bilateral filter output values are in log space and are quantized into a finite number of bins in order to make a histogram calculation tractable.

102. An apparatus as in claim 101 wherein a histogram minimum bin, H_mm, is calculated by locating a first histogram bin whose count is above a given count threshold, Ht_hres_h, and a neighboring bin counts also exceed Hthresh-

103. An apparatus as in claim 101 wherein a histogram maximum bin, H_max, is calculated by locating the last bin whose count is greater than Ht_hres_h, and whose neighboring bin counts also exceed Hthresh-

104. An apparatus as in claim 101 wherein a rolling window of size N_wm is passed over bins between H_mm and H_max and an arbitrary bin of a window with a largest total bin count is labeled as the histogram peak bin, H_peak-

105. An apparatus as in claim 104 wherein histogram bins H_mιn, H_max, and H_peak are then referred back to corresponding image referred values to generate B \_mm, B \_max and B_hpeak and these values are used to compute said digital key value in a manner substantially similar to the following: r_j £5h%>eak ^hrntn

■LJhmai ■'-'hmin where

B_frey ^~ Digital key value

B_hmtn ^~ Hist ogi am minimum value

B_hmao ^~ Histogram maximum value

B_hprak — Histogram peak value between D}_ιmιn and B_f,_nιox

106. An apparatus as in claim 98 wherein said digital key value rejects outlier pixels and outlier image content.

107. An apparatus as in claim 98 wherein a digital key value is used to automatically adjust a compression ratio, c, in a manner substantially similar to the following:

C-min T ( J- £*key) ' [fmax Crtnn )

C brightness where c — calculated compression ratio C_rri_ax ^~ The maximum desired compression ratio (■'_mm = The minimum desired compression ratio brightness = parameter to control output bright ;ness

108. An apparatus as in claim 107 wherein a compression ratio calculated for image scenes with a low-key value will approach a maximum compression ratio, c_max, which will result in a compression factor, CF, calculation which maximizes a (c-1) term and thus compresses the image less.

109. An apparatus as in claim 107 wherein a compression ratio calculated for image scenes with a high-key value will approach a minimum compression ratio, c_mm, which will result in a compression factor, CF, calculation which minimizes a (c-1) term and thus compresses the image more.

110. An apparatus as in claim 107 wherein a digital key value is obtained which smoothly transitions between extremes in subsequent frames of a high dynamic range image stream.

111. An apparatus as in claim 110 wherein the smooth transition of the digital key between extremes in subsequent frames of a high dynamic range image stream is accomplished using time averaging.