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Publication numberWO2010079448 A3
Publication typeApplication
Application numberPCT/IB2010/050045
Publication date2 Sep 2010
Filing date7 Jan 2010
Priority date8 Jan 2009
Also published asUS8332580, US20090303767, WO2010079448A2, WO2010079449A1, WO2010079450A2, WO2010079450A3, WO2010079451A1
Publication numberPCT/2010/50045, PCT/IB/10/050045, PCT/IB/10/50045, PCT/IB/2010/050045, PCT/IB/2010/50045, PCT/IB10/050045, PCT/IB10/50045, PCT/IB10050045, PCT/IB1050045, PCT/IB2010/050045, PCT/IB2010/50045, PCT/IB2010050045, PCT/IB201050045, WO 2010/079448 A3, WO 2010079448 A3, WO 2010079448A3, WO-A3-2010079448, WO2010/079448A3, WO2010079448 A3, WO2010079448A3
InventorsAvidan Akerib, Eli Ehrman, Josh Meir, Moshe Meyassed, Yair Alpern, Oren Agam
ApplicantZikbit Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
System, method and apparatus for memory with control logic to control associative computations
WO 2010079448 A3
Abstract
An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and control logic to control the associative computation.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3868642 *21 Aug 197225 Feb 1975Siemens AgHierrarchial associative memory system
US4491932 *1 Oct 19811 Jan 1985Yeda Research & Development Co. Ltd.Associative processor particularly useful for tomographic image reconstruction
US5604742 *31 May 199518 Feb 1997International Business Machines CorporationCommunications system and method for efficient management of bandwidth in a FDDI station
US5751987 *4 May 199512 May 1998Texas Instruments IncorporatedDistributed processing memory chip with embedded logic having both data memory and broadcast memory
US20050165995 *17 Mar 200528 Jul 2005Italtel S.P.A.System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative COMMON BUS protocol
Classifications
International ClassificationG06F12/00
Cooperative ClassificationG11C11/005, G06F15/7821, G11C15/00, G06F9/3879, G11C7/1006
European ClassificationG06F9/38S1, G11C15/00, G11C7/10L, G06F15/78P1D, G11C11/00C
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