WO2010036575A3 - Methods and systems for preventing feature collapse during microelectronic topography fabrication - Google Patents

Methods and systems for preventing feature collapse during microelectronic topography fabrication Download PDF

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Publication number
WO2010036575A3
WO2010036575A3 PCT/US2009/057490 US2009057490W WO2010036575A3 WO 2010036575 A3 WO2010036575 A3 WO 2010036575A3 US 2009057490 W US2009057490 W US 2009057490W WO 2010036575 A3 WO2010036575 A3 WO 2010036575A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
systems
fabrication
topography
collapse during
Prior art date
Application number
PCT/US2009/057490
Other languages
French (fr)
Other versions
WO2010036575A2 (en
Inventor
Mark I. Wagner
James P. Deyoung
Tony R. Kroeker
Original Assignee
Lam Research Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corporation filed Critical Lam Research Corporation
Priority to JP2011529128A priority Critical patent/JP5680539B2/en
Priority to KR1020117006728A priority patent/KR101663843B1/en
Priority to CN200980136973.5A priority patent/CN102160149B/en
Priority to TW098131869A priority patent/TWI496209B/en
Publication of WO2010036575A2 publication Critical patent/WO2010036575A2/en
Publication of WO2010036575A3 publication Critical patent/WO2010036575A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02101—Cleaning only involving supercritical fluids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

Methods and systems for preventing feature collapse subsequent to etching include adding a rinse liquid to a microelectronic topography having remnants of another rinse liquid arranged upon its surface and subsequently exposing the topography to a pressurized chamber including a fluid at or greater than critical pressure. The methods include flushing from the pressurized chamber liquid arranged upon the topography and, thereafter, venting the chamber in a manner sufficient to prevent liquid formation therein.
PCT/US2009/057490 2008-09-24 2009-09-18 Methods and systems for preventing feature collapse during microelectronic topography fabrication WO2010036575A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2011529128A JP5680539B2 (en) 2008-09-24 2009-09-18 Method and system for preventing feature collapse during microelectronic topography manufacturing
KR1020117006728A KR101663843B1 (en) 2008-09-24 2009-09-18 Methods and systems for preventing feature collapse during microelectronic topography fabrication
CN200980136973.5A CN102160149B (en) 2008-09-24 2009-09-18 Methods and systems for preventing feature collapse during microelectronic topography fabrication
TW098131869A TWI496209B (en) 2008-09-24 2009-09-22 Methods and systems for preventing feature collapse during microelectronic topography fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/237,070 US8153533B2 (en) 2008-09-24 2008-09-24 Methods and systems for preventing feature collapse during microelectronic topography fabrication
US12/237,070 2008-09-24

Publications (2)

Publication Number Publication Date
WO2010036575A2 WO2010036575A2 (en) 2010-04-01
WO2010036575A3 true WO2010036575A3 (en) 2010-06-03

Family

ID=42036562

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/057490 WO2010036575A2 (en) 2008-09-24 2009-09-18 Methods and systems for preventing feature collapse during microelectronic topography fabrication

Country Status (6)

Country Link
US (1) US8153533B2 (en)
JP (1) JP5680539B2 (en)
KR (1) KR101663843B1 (en)
CN (1) CN102160149B (en)
TW (1) TWI496209B (en)
WO (1) WO2010036575A2 (en)

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Also Published As

Publication number Publication date
CN102160149A (en) 2011-08-17
US20100072169A1 (en) 2010-03-25
US8153533B2 (en) 2012-04-10
KR20110063774A (en) 2011-06-14
CN102160149B (en) 2014-09-17
WO2010036575A2 (en) 2010-04-01
KR101663843B1 (en) 2016-10-07
TWI496209B (en) 2015-08-11
JP2012503883A (en) 2012-02-09
JP5680539B2 (en) 2015-03-04
TW201021115A (en) 2010-06-01

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