WO2009114796A1

WO2009114796A1 - Correlated electron material with morphological formations

Info

Publication number: WO2009114796A1
Application number: PCT/US2009/037140
Authority: WO
Inventors: Carlos A Paz De Araujo; Matthew D. Brubaker; Jolanta Celinska
Original assignee: Symetrix Corporation
Priority date: 2008-03-13
Filing date: 2009-03-13
Publication date: 2009-09-17

Abstract

A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming. The material exhibits at least one morphological formation.

Description

CORRELATED ELECTRON MATERIAL WITH MORPHOLOGICAL FORMATIONS

FIELD OF THE INVENTION

The invention in general relates to integrated circuit memories, and in particular, to the formation of non-volatile integrated circuit memories containing materials which exhibit a change in resistance.

BACKGROUND OF THE INVENTION

Non-volatile memories are a class of integrated circuits in which the memory cell or element does not lose its state after the power supplied to the device is turned off. The earliest computer memories, made with rings of ferrite that could be magnetized in two directions were non-volatile. As semiconductor technology evolved into higher levels of miniaturization, the ferrite devices were abandoned for the more commonly known volatile memories such as DRAMs (Dynamic Random Access memories) and SRAMs (Static-RAMs).

The need for non-volatile memories never went away. Thus, in the last forty years, many devices were created to fulfill this need. In the late 70's, devices were made with a metallization layer which either connected or disconnected a cell. Thus, at the factory one could set values in a non-volatile way. Once these devices left the factory, they could not be re-written. They were called ROMs (Read Only Memories), in 1967, Khang and SZE at Bell Laboratories proposed devices which were made using field effect transistors (FETs) which had within layers of materials in the gate, the ability to trap charge. In the late 70's and early 80's devices which could be written by the user and erased by de-trapping the electrons via ultra-violet light (UV) were very successful. The UV both required the device to be removed from the circuit board and placed under a UV lamp for over 15 minutes. These non-volatile memories were called PROMs or programmable - ROMs. The writing process involved forcing current from the substrate below to these trap sites. This process of making the electrons pass through layers of materials which have an opposing potential energy barrier is known as quantum tunneling, a phenomenon that only occurs because of the wave-particle duality of the electron. Many types of sandwiches of materials for the gate stack of these FETs were tried and the technology received many names such as MNOS (Metal-Nitride-Oxide- Semiconductor), SNOS ([PoIy] Silicon-Gate Plus MNOS), SONOS (Silicon-Oxide Plus MNOS) and PS/O/PS/S (Polysilicon Control Gate-Silicon Dioxide - Polysilicon Floating Gate — and a thin tunneling oxide on top of the silicon substrate). This kind of erasable and thus read/write non-volatile device was known as EEPROMs for electrically- erasable-PROMs, an unfortunate misnomer since they are not just read only. Typically EEPROMS have large cell areas and require a large voltage (from 12-21 volt) on the gate in order to write/erase. Also, the erase or write time is of the order of tens of microseconds. However, the worse limiting factor is the limited number of erase/write cycles to no more than slightly over 600,000 - or of the order of 105 - 106. The semiconductor industry eliminated the need of a pass-gate switch transistor between EEPROMs non-volatile transistors by sectorizing the memory array in such a way that "pages" (sub-arrays) could be erased at a time in memories called Flash memories. In Flash memories, the ability to keep random access (erase/write single bits) was sacrificed for speed and higher bit density.

The desire to have low power, high speed, high density and indestructibility has kept researchers working in non-volatile memory for the last forty years. FeRAMs (Ferroelectric RAMs) provide low power, high write/read speed and endurance for read/write cycles exceeding 10 billion times. Magnetic memories (MRAMs) provide high write/read speed and endurance, but with a high cost premium and higher power consumption. Neither of these technologies reaches the density of Flash, and thus Flash remains the non-volatile memory of choice. However, it is generally recognized that Flash will not scale easily below 65 nanometers; thus, new non-volatile memories that will scale to smaller sizes are actively being sought.

To this end, there has been much research over the last ten to twenty years on memories based on certain materials that exhibit a resistance change associated with a change of phase of the material. In one type of variable resistance memory called a PCM (phase change memory), a change in resistance occurs when the memory element is briefly melted and then cooled to either a conductive crystalline state or a nonconductive amorphous state. Typical materials vary and include GeSbTe, where Sb and Te can be exchanged with other elements of same properties on the Periodic Table. These materials are often referred to as chalcogenides. See, for example, Stephan Lai, "Current Status of the Phase Change Memory and Its Future", Intel Corporation, Research note RN2-05 (2005); United States Patent No. 7,038,935 issued to Darrell Rinerson et al., May 2, 2006; United States Patent No. 6,903,361 issued to Terry L. Gilton on June 7, 2005; and United States Patent No. 6,841 ,833 issued to Sheng Teng Hsu et al., January 1 1 , 2005. However, these resistance-based memories have not proved to be commercially useful because their transition from the conductive to the insulating state depends on a physical structure phenomenon, i.e., melting (at up to 600⁰C) and returning to a solid state that cannot be sufficiently controlled for a useful memory. Recently, a resistance switching field effect transistor has been disclosed using a

Mott-Brinkman-Rice insulator, such as LaTiO3. In this material, according to the theory proposed, the addition of holes via an interface with a Ba(1-X)SrXTiO3 layer changes the material from an insulator to a conductor. See United States Patent No. 6,624,463 issued to Hyun-Tak Kim et al. on September 23, 2003. This FET uses the Mott- Brinkman-Rice insulator as the channel in the FET. However, no example of fabrication of actual devices is given.

Another variable resistance memory category includes materials that require an initial high "forming" voltage and current to activate the variable resistance function. These materials include PrxCayMnzOe, with x, y, z and e of varying stoichiometry, transition metal oxides, such as CuO, CoO, VOx, NiO, TiO2, Ta2O5, and some perovskites such as Cr; SrTiO3. See, for example, "Resistive Switching Mechanisms of TiO2 Thin Films Grown By Atomic-Layer Deposition", B. J. Choi et al., Journal of Applied Physics 98, 033715(2005), "Reproducible Resistive Switching In Nonstoichiometric Nickel Oxide Films Grown By RF Reactive Sputtering For Resistive Random Access Memory Applications", Jae-Wan Park, et al., J. Vac. Sci. Technol. A 23(5), Sept/Oct 2005, "Influence Of Oxygen Content On Electrical Properties Of NiO films grown By RF Reactive Sputtering", Jae-Wan Park, et al., J. Vac. Sci. Technol. B 24(5), Sept/Oct 2006, "Nonpolar Resistance Switching Of Metal/Binary-Transition-Metal Oxides/Metal Sandwiches: Homogeneous/inhomogeneous Transition of Current Distribution", I. H. lnone et al., arXiv:Cond-mat/0702564 v.1 26Feb2007, and United States Patent Application Publication No. 2007/0114509 A1 , Memory Cell Comprising Nickel-Cobalt Oxide Switching Element, on an application of S. Brad Herner. These memories are referred to as ReRAMs, to distinguish them from the chalcogenide type memories. These papers postulate that the resistance switching is due to the formation of narrow conducting paths or filaments connecting the top and bottom electrodes by the electroforming process, though the presence of such conducting filaments are still a matter of controversy with respect to the actual physical mechanism. It is believed by Applicants that when electroforming is used the bulk of the non-filament region does not provide true memory switching but a metastable electron storage which is due to charge trapping and detrapping in oxygen vacancies. This is further evidenced by the fact that none of these papers demonstrate conductive and insulative states that are stable over the necessary temperature range for a commercial memory. Further, the resistance switching tends to fatigue over many memory cycles. Moreover, based on the ReRAM art to date, the use of such materials must be said to be speculative, since the high voltage-high current electroforming step simply is not compatible with dense chip architecture. In fact, the Herner patent application reference merely speculates that a combination of nickel and cobalt oxides will eliminate the required high amplitude pulses, without providing an actual example to demonstrate it.

In summary, there have been literally hundreds if not thousands of papers and patent applications written on resistive memories in the last ten years, most of which have been speculative. However, a workable resistance switching memory has never been made, because no one knows how to make a thin film resistance switching material that is stable over time and temperature. Further, all resistance switching mechanisms developed up to now have been inherently unsuitable for memories, due to high currents, electroforming, no measurable memory windows over a reasonable range of temperatures and voltages, and many other problems. Thus, there remains a need in the art for a non-volatile memory that has low power, high speed, high density and stability, and in particular, such a memory that is scalable to feature sizes well below 65 nanometers.

SUMMARY OF THE INVENTION The invention solves the above and other problems by incorporating a Correlated

Electron Material (CEM) in a memory, preferably a non-volatile memory. CEMs are materials that exhibit an abrupt conductor/insulator transition due to electron correlations rather than solid state structural phase changes, i.e., crystalline/amorphous, or filamentary phase changes. Because these materials have never before been used in a memory, those skilled in the memory art are generally unfamiliar with them. Therefore, a more complete description of these materials will be given in the Detailed Description of the Invention below.

A feature of the invention is that the CEM materials are formed in the conductive state, and no forming voltage or current is necessary to change them into a variable resistance material.

Another feature of one embodiment of the invention is that the correlated electron materials of the invention, which are essentially crystalline in structure, exhibit detectable morphological features or irregularities in their structure. Although these morphological features have not been conclusively identified, it is theorized that they are carbon nano tubes or simply irregularities in the structure of the correlated electron material. Regardless of their exact composition, it is clear that the morphological features or irregularities in the crystal formation are both vital to the memory function and capable of being reliably reproduced by the methods described herein.

It is theorized that the morphological features, especially in the case of carbon nano tubes, may serve to emit electrons into the bulk of the CEM substrate. This emission lowers the potential barrier for electrons entering the bulk of the CEM substrate, thus allowing the Mott transition state (discussed in more detail below) to be achieved at lower bias levels. Carbon nano tubes are well known to be ideal electron emitters since they are long, thin, and good conductors. Nano tubes take advantage of field amplification effect; electric field lines are concentrated around a very sharp object. Another feature is that the memory cell or resistive switching cell formed with the

CEM exhibits one morphological feature per cell. The occurrence of a single morphological feature per cell may be achieved according to a number of alternative methodologies. By testing CEMs of various materials at various sizes the percentage of initially off CEM resistive switching cells may be determined. A Poisson Yield Analysis may be conducted to determine the surface concentration of the features. The resistive switching cell may be sized accordingly, such that if one feature occurs per area A, then the resistive switching cell may have a size of area A.

Another feature of this invention is that depending on the deposition technique used, if the surface concentration is variable over the deposited wafer, then variable sized resistive switching cells are formed in order to maintain a single morphological feature per cell.

Another feature of this invention is the formation technique for the CEM. The thickness of the CEM deposited may have an important impact on the existence of the morphological features. Only a deposited CEM of a certain thickness will exhibit morphological features. Therefore, deposited layers of CEM without morphological features may be used as capping layers. Deposited CEM exhibiting a high concentration of morphological features may be capped in order to reduce the concentration of morphological features.

Another feature of the invention is that the conductor/insulator transition may be induced simply by the application of a small voltage or current to the material, i.e., a voltage of the order of the voltage applied to a DRAM, that is, no more than five volts and, more preferably, no more than a few volts.

In one embodiment an integrated circuit resistive switching component includes a resistive switching cell, including a correlated electron material (CEM). The CEM material exhibits at least one morphological formation. The integrated circuit resistive switching component further includes a switching circuit for placing the resistive switching cell in a first resistive state and a second resistive state. The resistance of the second resistive state is higher than the first resistive state.

A feature of the integrated circuit resistive switching component is that the CEM in the first resistive state changes to the second resistive state by increasing the voltage applied to the CEM to a set voltage. A feature of the integrated circuit resistive switching component the CEM in the second resistive state changes to the first resistive state by increasing the voltage applied to the CEM to a reset voltage. Another feature is that the reset voltage is higher than the set voltage. Another feature is that the CEM in the first resistive state, remains in the first resistive state if no voltage is applied to the CEM. Another feature is that the CEM in the second resistive state remains in the second resistive state if no voltage is applied to the CEM.

Another feature is that the integrated circuit resistive switching component also includes a sensing circuit for determining whether the resistive switching cell is in the first resistive state or the second resistive state and providing an electrical signal corresponding to the first resistive state or the second resistive state. Another feature is that the sensing circuit determines whether the resistive switching cell is in the first resistive state or the second resistive state by applying a current to the CEM. Another feature is that CEM material has exactly one morphological formation. The morphological feature may be a nano carbon tube. The nano carbon tube acts as a field emitter, lowering the potential barrier for electrons to enter the CEM material.

A feature of the composition of the CEM material is that it is formed by depositing at least one bulk layer and at least one capping layer. Another feature is that the at least one bulk layer exhibits morphological formations. Another feature is that the morphological formations are in a vein in trench like pattern. Another feature is that the trench width is 0.2 to 0.3 micrometers.

Yet another feature is that the vein to vein spacing is 0.5 to 1.5 micrometers. An additional feature is that the veins have a hexagonal-like packing. Another feature is that the veins propagate into the interior of the hexagonal-like packing. Furthermore, the veins may be approximately 50 nanometers wide. Additionally, the veins may resemble filamentatious carbon. Another feature includes that the at least one capping layer has a smooth appearance. Additionally, the at least one capping layer may not exhibit morphological formations. Furthermore, the at least one bulk layer may exhibit surface morphological formations.

In one embodiment the CEM deposition material may be NiO. The NiO may be deposited using a spin on deposition method. A 0.2M solution may be used for the bulk layer. A 0.1 M solution may be used for the capping layer. A feature may include depositing three bulk layers. Another feature may include that six capping layers are deposited. The CEM may have a defined area. The CEM may include at least one bulk layer having numerous morphological formations over the area of the CEM, at least one capping layer, deposited over the bulk layer. The at least one capping layer may have no morphological formations over the area of the CEM and the at least one bulk layer may be capped with sufficient layers of the at least one capping layer to result in a substrate having one morphological formation, detectable on the surface, over the area of the CEM.

A feature of the resistive switching cell may include that its state is capable of being determined 108 times with less than 50% fatigue. An additional feature may include that the CEM switches resistive states due to a Mott-transition in the majority of the volume of the CEM. The CEM may be a material selected aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium, zinc and combinations thereof. A feature includes that the resistive switching cell, switching circuit, and sensing circuit may function as a memory device.

One embodiment of a method of writing to a resistive switching thin film memory element, includes applying an electric field or voltage to the thin film to cause the concentration of electrons, nc, in an energy band in the majority of the volume of the material to increase to or greater than a value given by (nC)1/3a = 0.26 where "a" is the Bohr radius.

Another embodiment of a method of making a non-volatile integrated circuit memory includes depositing a correlated electron material (CEM) and completing the memory to include the CEM in an active element in the memory. Another embodiment of a method of making a non-volatile integrated circuit resistive switching component includes calculating an area of the resistive switching memory cell to be formed and depositing a correlated electron material (CEM), such there is a probability that a single morphological formation is formed in the area of the resistive switching memory cell. A feature of this method may include that the depositing is accomplished using spin on techniques. A feature of this method may include using a solution having a molarity of CEM calculated to yield a single morphological formation for the area of the resistive switching memory. Another feature of this method may include that the depositing at least one bulk layer and at least one capping layer on top of the at least one bulk layer and the feature that the at least one bulk layer exhibits a plurality of morphological formations and the at least one capping layer exhibits no morphological formations.

Another feature of this method may include that the at least one bulk layer is capped with the at least one capping layer such that the deposition yields a single morphological formation for the area of the resistive switching memory. Another feature may include that the depositing is accomplished by liquid source misted chemical deposition. Yet another feature of this method may include three bulk layers, each having a thickness of approximately 100 angstrom, and six capping layers, each having a thickness of approximately 50 angstroms, are deposited.

Another embodiment of a method of writing to a non-volatile, resistive switching thin film memory element includes providing a memory cell including a thin film of correlated electron material (CEM), wherein the CEM has at least one morphological formation and applying an electric field or voltage to the thin film to cause the concentration of electrons, nC, in an energy band in the majority of the volume of the material to increase to or greater than a value given by (nC)1/3a = 0.26 where "a" is the Bohr radius. An embodiment of an integrated circuit memory having a memory cell includes a semiconductor having a first active area, a second active area, and a channel between the active areas and a layer of a variable resistance material (VRM) directly above the channel. A feature of this embodiment includes that the variable resistance material comprises a correlated electron material (CEM) and the CEM has at least one morphological formation. Another feature of this embodiment includes that the memory cell further includes a first conductive layer between the VRM and the channel. Another feature includes that the first conductive layer comprises a plurality of conductive layers.

Yet another feature includes that the memory cell further includes a layer of an insulating material between the VRM and the channel. Another feature includes that the memory cell includes a field effect transistor (FET). Another feature may include the memory cell comprises a JFET structure. Another feature may include that the memory cell includes a MESFET structure. Another feature may include that the memory cell includes a MOSFET structure.

An embodiment of a resistive switching memory includes memory cells arranged in rows and columns, each the memory cell being a resistive switching memory cell including a resistive switching material and each of the memory cells comprising a conductor/variable resistance material/conductor (M/VRM/M) stack formed on a channel in a semiconductor, the variable resistance material includes a correlated electron material (CEM) and the CEM has at least one morphological formation. The embodiment may also include a write circuit for placing selected ones of the resistive switching memory cells in a first memory cell resistive state or a second memory cell resistive state depending on information input into the memory, the resistance of the material is higher in the second resistance state than in the first resistance state. The embodiment may further include a read circuit for sensing the state of the memory cell and providing and electrical signal corresponding to the sensed state of the memory cell. A feature of the embodiment may include that each of the cells comprises a field effect transistor (FET). Another feature may include each of the cells comprises a JFET.

An embodiment of a method of operating an integrated circuit memory includes providing a memory cell including a semiconductor having a first active area, a second active area, and a channel between the active areas; and controlling the conductance of the channel using a variable resistance material, wherein the variable resistance material comprises a correlated electron material (CEM) and wherein the CEM has at least one morphological formation. A feature of the method may include that the controlling includes controlling a voltage across the channel or a current in the channel using the variable resistance material. Another feature of the method may include that reading a voltage across the channel, a current in the channel, or a resistance in the channel.

An embodiment of a method of reading a non-volatile, variable resistance memory cell, the variable resistance memory cell including a correlated electron material (CEM) and the CEM having at least one morphological formation may include measuring the capacitance of the memory cell; and using the measured capacitance, determining the logic state of the memory cell. A feature of the method may include that the memory cell includes a diode in series with the VRM and the measuring comprises measuring the capacitance of the diode in series with the VRM. An embodiment of a method of making a non-volatile integrated circuit memory may include depositing a variable resistance material (VRM) on a semiconductor directly above a channel in the semiconductor, the variable resistance material comprises a correlated electron material (CEM) and the CEM has at least one morphological formation; and completing the memory to include the VRM in an active element in the memory. A feature of the method may include that the depositing comprises forming a conductor/VRM/conductor stack. Another feature of the method may include that the forming comprises forming the stack over a JFET channel.

An embodiment of a resistive switching cell may include a top electrode; a bottom electrode; a variable resistance material (VRM), wherein the variable resistance material comprises a correlated electron material (CEM). A feature of the method may include that a VRM falls between the top and bottom electrode. Another feature may include that the CEM has at least one morphological formation. Yet another feature may include that the CEM has exactly one morphological formation.

Another feature may include that the bottom electrode composed of tungsten and titanium nitride. Anther feature may include that the bottom electrode is composed of a first layer of titanium nitride, a layer of tungsten, and a second layer of titanium nitride. Another feature may include that the first layer of titanium nitride is 200 angstroms thick, the layer of tungsten is 200 angstroms thick, and the second layer of titanium nitride is 200 angstroms thick. Another feature may include that the top electrode is composed of titanium nitride and aluminum. Another feature may include that the top electrode is composed of a first layer of titanium nitride, a layer of aluminum, and a second layer of titanium nitride. Another feature may include that the first layer of titanium nitride is 200 angstroms thick, the layer of aluminum is 500 angstroms thick, and the second layer of titanium nitride is 200 angstroms thick. Another feature may include that an interfacial dielectric is formed in between the bottom electrode and the VRM during annealing. Another feature may include that the interfacial dielectric limits the active contact area between the bottom electrode and the VRM.

An embodiment of a method for forming an integrated circuit resistive switching component may include oxidizing a silicon wafer; depositing an adhesion layer; depositing a bottom electrode; depositing a transition metal oxide (TMO); annealing the TMO; depositing a top electrode; applying a photoresist to the top electrode and TMO; and etching the top electrode and TMO. A feature may further include depositing an inter-layer dielectric. Another feature may include that the TMO is NiO. Another feature may include that the TMO is formed by depositing three bulk layers of NiO using a 0.2M solution and depositing six capping layers of NiO using a 0.1 M solution. Another feature may include that the bulk layers exhibit at least one morphological formation. Yet another feature may include that the bottom electrode composed of tungsten and titanium nitride. Another feature may include the top electrode is composed of titanium nitride and aluminum. The method may further include annealing the TMO.

The conductor/insulator transition in the memory according to the invention is theorized to be a purely quantum mechanical phenomenon, in contrast to melting/solidification or filament formation, which are classical physics phenomena. The quantum mechanical transition can be understood in several ways. One way is in terms of band structure. When the materials are formed, the relevant electron orbitals, i.e., the bands that are being filled by the increasing electrons in each succeeding element in the period table, overlap. In the transition metal oxides, these are d-orbitals. This creates a partially-filled double band that is conductive in the same way that a metal is conductive. When a small voltage or current is applied mobile electrons are added to the bands. When the bands become full enough that the coulomb repulsion becomes great enough, the partially filled bands split, with the filled p-orbital between them. This creates a filled band and an empty band separated by a significant energy, which is the band structure for a Mott-charge transfer insulator (See FIG. 14). When the electric field applied to the material becomes large enough to cause a transition between the split orbitals, electrons begin to jump from the lower band to the upper band, which reduces the coulomb repulsion, causing the correlated electron system to collapse back into the original state in which the orbitals overlap. The quantum mechanical transition can also be understood in terms of a Mott transition. In a Mott transition, a material switches from a paramagnetic conductive state to an anti-ferromagnetic insulative state when the Mott transition condition (nC)1/3a = 0.26 is reached, where nC is the concentration of electrons and "a" is the Bohr radius. This is sometimes explained as a "crowded elevator" phenomenon: when an elevator has only a few people in it, the people can move around easily, which is analogous to the conducting state, but when the elevator reaches a certain concentration of people, the people can no longer move, which is analogous to the insulative state. However, it should be understood that this classical explanation, like all classical explanations of quantum phenomenon, is only an incomplete analogy. In the Mott transition the spins of the electrons also play a significant role. In the paramagnetic state the spins disordered, while in the anti- ferromagnetic state the spins are anti-aligned; that is, the spins of electrons align in a regular pattern with neighboring spins pointing in opposite directions. The preferred CEM materials according to the invention feature vacancy coordination passivation, and oxygen vacancy coordination passivation in particular. As known in the art, oxides, and transition metal oxides in particular, are densely populated with vacancies. The vacancy coordination sphere is the region about an ion or electron in which vacancies can affect the ion or electron. Vacancies within this vacancy coordination sphere can thermally detrap, and the electron can move to the vacancy site. This destabilizes the high resistance state. This is the principle reason for the instability of prior art variable resistance materials. In the materials according to the invention, the effect of the oxygen vacancies is cancelled, preferably by novel ligand structure of the CeRAM materials according to the invention. As mentioned above, a feature of the preferred embodiment of the invention is the presence of extrinsic ligands that stabilize the CeRAM material. As known in the art, transition metal oxides include an intrinsic ligand, namely oxygen. An extrinsic ligand is an element or compound other than oxygen that participates in the coordination sphere of the transition metal ion. Preferably, the stabilization is via a direct metal-extrinsic ligand bond, though the bond of the extrinsic ligand may also be with an intrinsic ligand. Carbon is an example of an extrinsic ligand element, and ammonia is an example of an extrinsic ligand compound. Carbon is the preferred extrinsic ligand. All the best memory switching films made by the inventors, including all that crystallized in the ON state included an extrinsic ligand.

There are disclosed preferred methods for making CEMs and integrated circuits utilizing CEMs. In particular, chemical solution deposition (CSD) methods, preferably utilizing a metallorganic precursor, and most preferably, octane, are disclosed. Preferably, the chemical solution provides the element carbon. These methods preferably include a reaction in a gas containing the extrinsic ligand elements that stabilize the CEM or a gas containing the anion to which the ligand bonds, or both. The reaction may take place in an anneal process in a gas containing the ligand, the anion, or both. Or the reaction may take place in a reactive sputtering in a gas containing the ligand, the anion, or both.

The disclosure also includes novel preferred architectures for CEM memories, which architectures can also be applied to other variable resistance materials (VRMs), which include chalcogenides, RRAM materials, and other materials. There is also disclosed preferred memory architectures and methods. These memory architectures and methods include a memory in which the memory element comprises a variable resistance material and a diode in series, which, in one embodiment, the memory element is read by measuring its capacitance. The memory architectures also include a variable resistance JFET in which a variable resistance material controls the current flow in and/or the voltage across the JFET channel.

The invention provides a resistive switching integrated circuit memory comprising: a resistive switching memory cell including an correlated electron material (CEM); a write circuit for placing the resistive switching memory cell in a first resistive state or a second resistive state depending on information input into the memory, wherein the resistance of the CEM is higher in the second resistance state than in the first resistance state; and a read circuit for sensing the state of the memory cell and providing an electrical signal corresponding to the sensed state of the memory cell. Preferably, the CEM is essentially homogenous. Preferably, the memory is capable of being read 108 times with less than 50% fatigue. Preferably, the memory has a memory window that changes less than 50% over a temperature range of from minus 50⁰C to 75°C. Preferably, the resistance of the CEM in the second memory cell state is more than 200 times the resistance in the second memory cell state. Preferably, the CEM switches resistive states due to a Mott-transition in the majority of the volume of the CEM. Preferably, the CEM comprises a material selected from the group consisting of aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium and zinc, which preferably is linked to a cation such as oxygen or other types of ligands. Preferably, the memory is a non-volatile memory. Preferably, the memory is a random access memory. Preferably, the memory is a cross-tie memory. Preferably, the memory comprises a plurality of the memory cells arranged in rows and columns. Preferably, the memory cells comprise a metal/CEM/metal (M/CEM/M) stack formed on a semiconductor. Preferably the M/CEM/M stack is formed on a diode. Preferably, the diode is selected from the group consisting of a junction diode and a Schottky diode.

The invention also provides a method of forming a resistive switching memory, the method comprising: providing a substrate; forming a transition metal oxide on the substrate by crystallizing it directly into a conducting state without an electroforming process; and completing the resistive switching memory to include the transition metal oxide in an active element in the memory. Preferably, the forming comprises a liquid deposition process. Preferably, the forming comprises an anneal. In a further aspect, the invention provides a method of writing to a resistive switching thin film memory element, the method comprising applying an electric field or voltage to the thin film to cause the concentration of electrons, nc, in an energy band in the majority of the volume of the material to increase to or greater than a value given by (nC)1/3a = 0.26, where "a" is the Bohr radius. In yet another aspect, the invention provides a method of making a non-volatile integrated circuit memory, the method comprising: depositing a correlated electron material (CEM); and completing the memory to include the CEM in an active element in the memory. Preferably, the CEM is essentially homogeneous. Preferably, the depositing comprises a process selected from the group consisting of: a chemical solution deposition (CSD) process; depositing a metal and oxidizing it; and sputtering.

In addition, the invention provides a method of writing to a non-volatile, resistive switching thin film memory element, the method comprising: providing a memory cell including a thin film of correlated electron material (CEM); and applying an electric field or voltage to the thin film to cause the concentration of electrons, nC, in an energy band in the majority of the volume of the material to increase to or greater than a value given by (nC)1/3a = 0.26, where "a" is the Bohr radius.

The invention also provides a resistive switching integrated circuit memory comprising: a resistive switching memory cell including a resistive switching material comprising a transition metal compound containing an extrinsic ligand; a write circuit for placing the resistive switching memory cell in a first resistive state or a second resistive state depending on information input into the memory, wherein the resistance of the resistance switching material is higher in the second resistance state than in the first resistance state; and a read circuit for sensing the state of the memory cell and providing and electrical signal corresponding to the sensed state of the memory cell. Preferably, the transition metal compound is a transition metal oxide. Preferably, the extrinsic ligand comprises carbon or ammonia.

In yet another aspect, the invention provides a method of making a non-volatile resistive switching integrated circuit memory, the method comprising: providing an integrated circuit substrate; forming a resistive switching material on the substrate, the resistive switching material comprising a transition metal oxide and an extrinsic ligand capable of passivating oxygen vacancies in the transition metal oxide in at least a coordination region about each atom of the transition metal; and completing the integrated circuit to include the resistive switching material in an active element in the integrated circuit. Preferably, the extrinsic ligand is selected from the group consisting of carbon and ammonia. In still another aspect, the invention provides a method of making a non-volatile resistive switching integrated circuit memory, the method comprising: providing an integrated circuit substrate; forming a resistive switching material on the substrate, the resistive switching material comprising a transition metal compound capable of switching between a conducting state and an insulating state; stabilizing the vacancies in the transition metal compound; and completing the integrated circuit to include the resistive switching material in an active element in the integrated circuit. Preferably, stabilizing comprises utilizing an extrinsic ligand is selected from the group consisting of carbon and ammonia.

In a further aspect, the invention provides a precursor for making a resistive switching material capable of switching between a conducting state and an insulating state, the precursor comprising a transition metal and a ligand capable of stabilizing the insulating state so that the material has a memory window that changes less than 50% over a temperature range of from minus 50⁰C to 75°C. Preferably, the transition metal is selected from the group consisting of aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium, zinc and combinations thereof. Preferably, the ligand is selected from the group consisting of carbon, carbon compounds and ammonia. Preferably, the ligand comprises one or more elements selected from the group consisting of oxygen, hydrogen, fluorine, carbon, nitrogen, chlorine, bromine, sulfur, and iodine. In another aspect, the invention provides a resistive switching integrated circuit memory comprising: a resistive switching memory cell including a resistive switching material comprising a transition metal and carbon; a write circuit for placing the resistive switching memory cell in a first resistive state or a second resistive state depending on information input into the memory, wherein the resistance of the resistance switching material is higher in the second resistance state than in the first resistance state; and a read circuit for sensing the state of the memory cell and providing and electrical signal corresponding to the sensed state of the memory cell. Preferably, the resistive switching material comprises a transition metal compound containing carbon. In still another aspect, the invention provides a method of making a resistive switching integrated circuit memory, the method comprising: providing a substrate and a metallorganic precursor including a metal moiety suitable for forming a desired variable resistance material (VRM); applying the precursor to the substrate to form a thin film of the precursor; heating the precursor on the substrate to form the VRM; and completing the integrated circuit to include the VRM as an active element in the integrated circuit. Preferably, the precursor comprises octane. Preferably, the applying comprises a process selected from the group consisting of: spin-coating, dipping, liquid source misted deposition, chemical vapor deposition and atomic layer deposition. Preferably, the heating comprises annealing in oxygen. Preferably, the metal moiety comprises nickel. Preferably, the method further patterning the resistance switching material using an etch. Preferably, the etch comprises ion milling.

The invention also provides a method of making a variable resistance material, the method comprising: providing a metallorganic precursor including a metal moiety suitable for forming a desired variable resistance material (VRM); applying the precursor to a substrate to form a thin film of the precursor; and heating the precursor on the substrate to form the VRM.

The invention also provides a precursor for making a variable resistance material (VRM), the precursor comprising a metallorganic solvent and one or more metals. Preferably, the metallorganic solvent comprises octane. Preferably, the metal comprises a transition metal. Preferably, the transition metal comprises nickel.

In a further aspect, the invention provides an integrated circuit memory having a memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. Preferably, the variable resistance material comprises a correlated electron material (CEM). Preferably, the memory cell further includes a first conductive layer between the VRM and the channel. Preferably, the first conductive layer comprises a plurality of conductive layers. Preferably, the memory cell further includes a layer of an insulating material between the VRM and the channel. Preferably, the memory cell comprises a field effect transistor (FET), such as JFET structure, a MESFET structure, or a MOSFET structure. In still another aspect, the invention provides resistive switching memory comprising: a plurality of memory cells arranged in rows and columns, each the memory cell being a resistive switching memory cell including a resistive switching material and each of the memory cells comprising a conductor/variable resistance material/conductor (M/VRM/M) stack formed on a channel in a semiconductor; a write circuit for placing selected ones of the resistive switching memory cells in a first memory cell resistive state or a second memory cell resistive state depending on information input into the memory, wherein the resistance of the material is higher in the second resistance state than in the first resistance state; and a read circuit for sensing the state of the memory cell and providing and electrical signal corresponding to the sensed state of the memory cell. Preferably, each of the cells comprises a field effect transistor (FET). Preferably, each of the cells comprises a JFET.

The invention also provides a method of operating an integrated circuit memory, the method comprising: providing a memory cell including a semiconductor having a first active area, a second active area, and a channel between the active areas; and controlling the conductance of the channel using a variable resistance material. Preferably, the controlling comprises controlling a voltage across the channel or a current in the channel using the variable resistance material. Preferably, the method further comprises reading a voltage across the channel, a current in the channel, or a resistance in the channel. The invention also provides a method of reading a non-volatile, variable resistance memory cell, the method comprising: measuring the capacitance of the memory cell; and using the measured capacitance, determining the logic state of the memory cell.

The invention also provides a method of making a non-volatile integrated circuit memory, the method comprising: depositing a variable resistance material (VRM) on a semiconductor directly above a channel in the semiconductor; and completing the memory to include the VRM in an active element in the memory. Preferably, the depositing comprises forming a conductor/VRM/conductor stack. Preferably, the forming comprises forming the stack over a JFET channel. Preferably, the depositing comprises depositing a correlated electron material (CEM). The invention provides denser memory arrays and faster program and erase cycles, such as by eliminating reliance upon hot carrier injection and Fowler-Nordheim tunneling from the silicon substrate as in the conventional Flash memory. Further, the invention provides a non-volatile memory with lower voltage program and erase cycles than prior art memories such as Flash, thereby enabling lower power operation. The invention also provides higher endurance of program and erase cycles, for example, by eliminating breakdown of gate oxide used as a tunneling oxide in Flash memory. The invention also provides continued scaling of the memory element, such as by eliminating programming via tunneling from the substrate and being affected by the deleterious aspects of shrinking channel length. Numerous other features, objects, and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the current in amperes versus bias voltage in volts curves for an

NiO resistor according to the invention;

FIG. 2 is the same curves as shown in FIG. 1 except on a logarithmic scale which shows higher resolution at the smaller values of current;

FIG. 3 illustrates a silicon wafer with CEM "elements" comprising a CEM material according to the invention sandwiched between two electrodes;

FIG. 4 shows a cross-sectional view of one of the "elements" of FIG. 3 taken through the line 4-4 of FIG. 3;

FIG. 5 is a graph of voltage versus current illustrating the SET and RESET functions for an NiO element having a diameter of 50 microns; FIG. 6 is a graph of voltage versus current illustrating the SET and RESET functions for an NiO element with the CEM material doped with 5% cobalt and having a diameter of 50 microns;

FIG. 7 show graphs of voltage versus current illustrating the SET and RESET functions for three NiO elements having different diameters illustrating how the memory window changes with element diameter;

FIG. 8 show graphs of voltage versus current in the high resistance state for four NiO sandwiches having different diameters;

FIG. 9 show graphs of voltage versus current density in the high resistance state for the four elements of FIG. 8; FIG. 10 shows a graph of current in amps versus bias voltage in volts for the ON and OFF states after the NiO CEM was held at 150⁰C for five minutes; FIG. 1 1 shows a graph of resistance in ohms versus temperature in degrees centigrade for the ON and OFF states illustrating the stability of these states at higher temperatures;

FIG. 12 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, illustrating the ON, OFF, RESET, and SET modes;

FIG. 13 is an illustration of the energy bands of a Mott-Hubbard insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani;

FIG. 14 is an illustration of the energy bands of a charge transfer type insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani; FIG. 15 is a cross-sectional view of a M/CEM/M n-p diode switching cell;

FIG. 16 is an equivalent circuit diagram for the M/CEM/M p-n diode switching cell of FIG. 15;

FIG. 17 is cross-sectional view of a M/CEM/M-metal/semiconductor or Schottky diode switching cell according to the invention; FIG. 18 is a cross-sectional view of a M/CEM/M-MESFET switching cell according to the invention;

FIG. 19 is a cross-sectional view of a M/CEM/M-JFET switching cell according to the invention;

FIG. 20 is an equivalent circuit diagram of the a M/CEM/M-JFET of FIG. 19; FIG. 21 is a cross-sectional view of a M/VRM/M-MOSFET switching cell according to the invention;

FIG. 22 is a cross-sectional view of a 1 transistor/1 resistor CEM switching cell according to the invention;

FIG. 23 is an equivalent circuit diagram of the 1 transistor/1 resistor CEM switching cell of FIG. 22;

FIG. 24 is a cross-sectional view of a M/VRM-MESFET switching transistor according to the invention in which the VRM forms a Schottky barrier with the semiconductor channel;

FIG. 25 illustrates the cross-sectional equivalent circuit diagram for a CEM memory in a cross-tie architecture;

FIG.26 illustrates the cross-sectional equivalent circuit diagram for an alternative CEM memory in a cross-tie architecture;

FIG. 27 illustrates a chain cell architecture for a CEM memory according to the invention; FIG. 28 illustrates a cross-sectional view showing the structure of one embodiment of a memory cell of the memory of FIG. 27; FIG. 29 illustrates an exemplary memory utilizing any of the memory cells disclosed herein;

FIG. 30 is a graph comparing the voltage versus current curves for the diode portion of FIG. 15 and the SET and RESET functions of the switching cell of FIG. 15 with nickel oxide as the CEM;

FIG. 31 is a graph comparing the voltage versus current in the OFF and ON states for the switching cell of FIG. 30;

FIG. 32 is a graph comparing the capacitance versus voltage for the diode only portion of the structure of FIG. 15 and the M/CEM/M-diode switching cell of FIG. 15 with a nickel oxide CEM;

FIG. 33 is a graph comparing the dissipation versus voltage curves for the ON and OFF states of the switching cell of FIG. 15 and the diode only structure;

FIG. 34 is a graph comparing the voltage versus current curves for the JFET only portion of the structure of FIG. 19 with the and the SET and RESET functions of the switching cell of FIG. 19 with nickel oxide as the CEM;

FIG. 35 is a graph showing time versus voltage for voltage pulses applied to the gate and source of the switching cell of FIG. 19 with nickel oxide as the CEM;

FIG. 36 is a graph showing the measured voltage on the drain of the switching cell of FIG. 19 in response to the voltage pulses applied as show in FIG. 35; FIG. 37 is a graph of the resistance of the CEM and parasitic resistance of the interconnects in series versus bias voltage for the SET and RESET states showing that high parasitic resistance will create an unstable condition;

FIG. 38 is a flow chart showing the process of fabricating the CEM "capacitors" of FIGS. 3 and 4; FIG. 39 is an Arrhenius curve of the log of 1/Tau versus 1/T(1/K) for prior art sputtered NiO (without carbon) illustrating that the transition from the high resistance state to the low resistance state is caused by detrapping of electrons from oxygen vacancies in the sputtered NiO;

FIG. 40 shows a graph of Kelvin temperature versus resistance in Ohms for the ON and OFF states for a CEM thin film according to the invention and for a prior art thin film that crystallizes in the OFF state and requires forming before exhibiting variable resistance;

FIG. 41 is a graph of number of reading cycles versus resistance in Ohms for the ON and OFF states for a CEM thin film according to the invention, demonstrating that there is little of no fatigue; FIG. 42 is a graph of current versus voltage on a linear scale of a CEM film formed according to an embodiment of a method for forming CEM films;

FIG. 43 is a graph of current versus voltage on a logarithmic scale of a CEM film of FIG. 42; FIG. 44 is a graph of the thickness of dielectric layers formed versus the anneal temperature for a bottom electrode;

FIG. 45 is a graph of current versus voltage for an initial trace of a wafer of W/TiN/NiO/Pt;

FIG. 46 is a graph of current versus voltage for a wafer of W/TiN/NiO/Pt after hysteresis;

FIG. 47 is another graph of current versus voltage for a wafer of W/TiN/NiO/Pt showing the reverse polarity;

FIG. 48 is a graphical depiction of the yield of devices formed according to one embodiment of a method of forming CEM devices; FIG. 49 is a graph of current versus voltage for a wafer of W/TiN/NiO/TiN/AI;

FIG. 50 is an image of a smooth film of 0.1 M solution of NiO and a graph of voltage versus current for the film;

FIG. 51 is a graph of voltage versus current for the film of FIG. 50;

FIGS. 52-54 show images of a film of a 0.15M solution of NiO; FIG. 55 is a graph of current versus voltage for the film of FIGS. 52-54 after one day of recovery and four days of recovery;

FIG. 56 is a graph of current versus voltage after hysteresis for the film of FIGS. 52-54;

FIG. 57 is an image of a smooth film of 0.2M solution of NiO; FIG. 58 is a graph of voltage versus current for the film of FIG. 57;

FIG. 59 is a graph of current versus voltage for the deposition of three bulk layers of NiO 0.2M solution followed by various numbers of capping layers of NiO 0.1 M solution;

FIG. 60 is a graph of current versus voltage after full hysteresis for the deposition of three bulk layers of NiO 0.2M solution followed by various numbers of capping layers of NiO 0.1 M solution;

FIG. 61 is a graph of set and reset voltages versus cycle number for uncapped NiO layers;

FIG. 62 is a graph of set and reset voltages versus cycle number for capped NiO layers; FIGS. 63-65 are graphs of current versus voltage for various sizes of CEM resistors;

FIG. 66 is a graph of Poisson yield analysis for various sized resistors;

FIG. 67 is a graph of the number of devices off versus the device area; FIG. 68 is a graph of surface feature density versus radius;

FIG. 69 is a graph of feature density versus radius;

FIG. 70 is a graph of current versus voltage showing the reset for various locations on a wafer;

FIG. 71 is a graph of the fatigue for reading cycles; FIG. 72 is a graph of the degradation of the off state resistance versus temperature; and

FIG. 73 is a diagram of a liquid source misted chemical deposition system.

DETAILED DESCRIPTION OF THE INVENTION The present disclosure provides transition metal oxides as exemplary correlated electron materials (CEM), though the invention is applicable to other CEM materials as well. Nickel oxide, NiO, is disclosed as the exemplary transition metal oxide. The exemplary NiO materials discussed herein are doped with extrinsic ligands which stabilize the variable resistance properties. In general, this may be written as NiO(Lx), where Lx is a ligand element or compound and x indicates the number of units of the ligand for one unit of NiO. One skilled in the art can determine the value of x for any specific ligand and any specific combination of ligand with NiO or any other transition metal, simply by balancing valences. The preferred NiO variable resistance materials disclosed herein include at least a ligand containing carbon, which may indicated by NiO(Cx).

The preferred variable resistance materials discussed herein are Correlated Electron Materials. A Correlated Electron Material (CEM) is a material that switches from a first resistive state to a second resistive state, with the second resistive state having a resistance at least one hundred times higher than the first resistance state, and the change in resistance is primarily due to correlations between the electrons. Preferably, the CEM material changes from a paramagnetic conductive state to an anti- ferromagnetic insulative state when the Mott transition condition (nC)1/3a = 0.26 is reached, where nC is the concentration of electrons and "a" is the Bohr radius. More preferably, the resistance of the second state is at least two hundred times the resistance of the first state, and most preferably, five hundred times. Generally, these materials include any transition metal oxide, such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators. Several embodiments representing switching materials are nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr doped strontium titanate, lanthanum titanate, and the manganate family including praesydium calcium manganate and praesydium lanthanum manganate. In general, oxides incorporating elements with incomplete d and f orbital shells exhibit CEM resistive switching properties. Preferably, resistance can be changed by setting at one voltage and resetting at a second voltage. Preferably, no electroforming is required to prepare a CEM. The invention contemplates that many other transition metal compounds can be used in the invention. For example, {M(chxn)2Br}Br2 where M can be Pt, Pd, or Ni, and chxn is 1 R,2R-cyclohexanediamine, and other such metal complexes may be used.

It is a feature of the invention that the conduction of the CEM materials is area independent. That is because the conduction is a quantum mechanical phenomenon and is related to the transition probability through the film. This conduction, G, is given by:

G = (q2pmpNiG7hm)T, where q is the electron charge, pm, is the density of states in the electrode, pNiO is the density of states in the nickel oxide, m is the mass of the charge carrier, and T is the transmission probability through the film. FIG. 1 shows the current in amperes (amps) versus bias voltage in volts curves for an NiO(Cx) CEM according to the invention. FIG. 2 shows the same curves except the absolute value of the current is plotted logarithmically to show more detail in the low current values. As has become the nomenclature in the art, the point at which the CEM changes in resistance from a conductor to an insulator is called the RESET point, while the point at which the resistance changes from an insulator to a conductor is called the SET point. Unlike other variable resistance materials, the CEMs are crystallized in the conducting state. We shall refer to this as the ON state and the insulative state will be called the OFF state. The solid line 40 is the ON state curve for positive voltages and the solid line 60 is the ON curve for negative voltages. The dotted line 54 is the OFF curve for positive voltages, while the dotted line 62 is the OFF curve for negative voltages. As the voltage is increased, the current rises at 47, until the RESET voltage is reached, which is about 0.65 volts, which is also the point at which critical electron density is reached, then, at point 48 the material suddenly becomes insulative and the current drops sharply along curve 49. The current stays low along the line 52 as the voltage rises until the SET voltage is reached at about 1.65 volts, which corresponds to the Neel temperature for these materials, at which point the material again becomes conductive and the current rises along line 54. If the voltage is returned to zero and then raised again when the CEM is in the insulative state, the current follows the line 44, while if the voltage is returned to zero after the material becomes conducting, that is after the VSET point, the current follows the line 47. It is evident from FIGS. 1 and 2 that the write memory window exists between VRESET and VSET, while the read memory window exists between the ON and OFF state current level. It is also evident from FIGS. 1 and 2 that these memory windows are easily large enough for a viable commercial memory. Thus, it can be seen that a CEM is a preferable VRM, though the architectures disclosed herein can be used with any variable resistance switching material. Turning now to FIGS. 3 and 4, a silicon wafer 1 having CEM integrated circuit elements, such as 77 and 80 formed on it is shown. FIG. 4 shows a cross-section through element 80 taken through line 4-4 of FIG. 3. Element 80 is formed on a silicon substrate 82 having a silicon dioxide coating 84. Optionally, a thin layer 86 of titanium or titanium oxide may be formed on oxide layer 84, though the elements reported on herein did not have such a layer. A bottom electrode layer 88 is formed on either layer 86 or directly on oxide layer 84. Layer 86 is an adhesion layer to assist the bottom electrode layer 88 in adhering to silicon dioxide layer 84. CEM material 90 (composed of a transition metal oxide is formed on bottom electrode 88, preferably by a liquid deposition process, such as spin coating, misted deposition, CVD or atomic layer deposition. The deposition of the CEM material will be described in greater detail below. Then top electrode 92 is formed on CEM layer 90. The elements 77, 80, etc. are then patterned by etching down to bottom electrode 88. The CEM material is subjected to a recovery annealing. Then an inter-layer dielectric 94 is deposited. At this point a contact vias 96 is added. Typically integrated circuit formation techniques, known to those skilled in the art, may then be applied to the CEM Integrated circuit elements, such as interconnect metallization, further interconnection etching, passivation, etc. The CEM integrated circuit element appears to have no fundamental issues with mainstream metallization processes and materials that are know to those skilled in the art. In one embodiment, the bottom electrode layer 88 may be formed of Titanium

Nitride (TiN) and Tungsten (W). Alternatively, the electrode is formed with a layer of TiN, followed by a layer of W, followed by a layer of TiN. Alternatively, the bottom electrode layer 88 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of W, and a 200 angstrom layer of TiN. After the CEM is deposited, it must be annealed. During the annealing process, due to oxidation, an interfacial dielectric layer may form over the bottom electrode. A purely tungsten electrode is oxidized by the annealing yielding an interfacial dielectric of over 1000 angstroms. A protective layer of titanium nitride provides some protection against oxidation and yields only a 100-200 angstrom thick interfacial dielectric as a result of annealing. The top electrode layer 92 may be formed of Titanium Nitride (TiN) and Tungsten

Aluminum (Al). In one alternative embodiment, the electrode is formed with a layer of TiN, followed by a layer of Al, followed by a layer of TiN. In one alternative embodiment, the top electrode layer 92 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of Al, and a 200 angstrom layer of TiN. The bottom electrode layer 88 and the top electrode layer 92 may be formed of platinum. Electrodes of such a composition may be useful in testing scenarios.

FIGS. 42-46 show the "memory" switching behavior of a number of embodiments of a NiO CEM. The NiO CEM in these embodiments is comprised three bulk layers and six capping layers. The bulk layers are deposited via spin on deposition with a 0.2M NiO solution and the capping layers are deposited via spin on deposition using a 0.1 M solution. Further details of the CEM deposition are discussed below.

As can be seen in FIG. 42, the results of testing on a wafer formed CEM having a platinum top electrode and a platinum bottom electrode. The resistor or CEM cell dimensions for the formed memory switching device is approximately 10 by 20 micrometers. As can be seen from FIG. 43, after full hysteresis is achieved, the Pt/NiO/Pt CEM cell exhibits memory switching behavior, similar to that described in reference to FIG. 1. The two dotted lines with smaller dots depict the On-state for the CEM cell. The solid lines depict the Off-state.

Various electrodes may be used in the formation of the memory cell, although since the CEM material must be annealed at 450 degrees Celsius (as discussed below), certain types of electrodes may not be appropriate. FIG. 44 shows the results of testing 2 types of electrodes a tungsten electrode and a tungsten titanium nitride. As shown, as the temperature rises a thicker layer of interfacial dielectric forms. The tungsten titanium nitride electrode appears to yield thinner interfacial dielectric layers and therefore was used in further testing.

FIG. 45 shows test results for a CEM memory switching cell having a tungsten and titanium nitride bottom electrode, a NiO CEM portion, and a platinum top electrode. As shown, the CEM cell is initially in the off-state. After hysteresis (FIG. 46), the CEM cell exhibits memory switching. Graph of the switching profile for a CEM cell prepared with a tungsten and titanium nitride bottom electrode is substantially similar to the current versus voltage graph of FIG. 1. The resistor composed of CEM material for this embodiment has dimensions of approximately 20 X 20 micrometers. Since the CEM material for this resistor is estimated to have a feature density of approximately 1 feature for 100 square micrometers, the expected dimensions of the resistor are 10 X 10 micrometers. One reason that a resistor of 20 X 20 micrometers exhibits memory switching is due to the interfacial dielectric material that forms over the bottom electrode due to the 450 degree anneal. This may limit the contact area of the bottom electrode with the CEM resistor.

One technique that may be employed in the construction of CEM resistors is intentionally limiting the contact area by forming an interfacial dielectric so that the CEM resistor exhibits memory switching due to the limited contact area. Through this procedure, CEM resistors with a greater estimated feature density may be utilized.

FIG. 47 shows more test results for a CEM memory switching cell having a tungsten and titanium nitride bottom electrode, a NiO CEM portion, and a platinum top electrode. As can be seen, the forward polarity is well behaved. The reverse polarity, however, shows poor reset characteristics. This is thought to be primarily due to surface roughness at the NiO and top electrode interface.

FIG. 48 shows the results of the formation of a wafer having CEM memory switching cells formed with a tungsten and titanium nitride bottom electrode, a NiO CEM portion, and a platinum top electrode. In this figure, round dots represent devices exhibiting proper memory switching and square dots represent those that do not exhibit proper switching. As can be seen, the yield for CEM memory switching cells exhibiting memory switching is good: 78% of the devices exhibit memory switching.

FIG. 49 shows the results of the formation of a wafer having CEM memory switching cells formed with a tungsten and titanium nitride bottom electrode, a NiO CEM portion, and a titanium nitride and aluminum top electrode. As is clear for the current versus voltage graph, this embodiment exhibits good memory switching characteristics.

The deposition of the CEM material is one aspect of the invention which may be accomplished via multiple techniques. One such deposition technique is referred to as spin-on deposition. In spin on deposition a liquid is dispensed onto a wafer surface while the wafer is rapidly rotated in order to uniformly distribute the liquid. The material is solidified using a low temperature bake. Other techniques for deposition may include liquid source chemical deposition and those deposition techniques known to those skilled in the art.

In one embodiment metalorganic deposited NiO is used in as the CEM. A bottom electrode is deposited. In one alternative the bottom electrode may be a platinum electrode with a silicon base. Spin-on deposition is used for the deposition of NiO. After deposition, the CEM is annealed at a temperature of 450 degrees Celsius in a diffusion furnace. A top electrode is deposited and photoresist is applied. Then the stack is etched to achieve the desired size components.

In one example of the formation of CEM material, the molarity of the solution used has an effect on whether the CEM material has memory switching function. FIG.

50 shows the results of a deposition of a NiO deposition with a 450 degree anneal. A

0.10M solution yields a smooth film with no discernable features or irregularities. The detection of features may be accomplished by way of a scanning electron microscope.

As shown in FIG. 51 , this smooth film exhibits threshold switching characteristics, causing it less likely to be suitable for memory applications.

FIGS. 52-54 show the result of a 0.15M deposition and a 450 degree anneal. A

0.15M solution yields a film with a spotty appearance, suggesting the existence of irregularities or morphological features in the deposited CEM material. As can be seen in FIG. 55, initially, the result of this deposition yields threshold switching characteristics. After aging (FIG. 56), this film takes on the characteristics of memory switching.

FIG. 57 shows the result of a 0.20M deposition and a 450 degree anneal. The use of a 0.20M solution yields a high density of irregularities or morphological features.

The morphological features appear to be in a vein in trench like pattern. The film resulting from this deposition initially is in the "on" state (FIG. 58). However, despite voltage increases, the resistance of the material is very low and no "reset" is possible.

Multiple layers of CEM may also be deposited in order to form the CEM. Table I shows the results of such depositions. The detection of features was accomplished by way of a scanning electron microscope. As can be seen, addition layers tend to add to the features or irregularities of the CEM. The deposition of one and two layers of 0.1 M solution results in a smooth film. At three and four layers, the film takes on a uniform splotchiness.

Table I

For deposition using a 0.2M solution as the number of layers deposited increase the veins take on the appearance of filamentatious carbon. After one layer is deposited, vein like patterns can be detected. At two layers of deposited NiO, the veins take on a hexagonal packing and the spacing of the veins decreases. At three and four layers the veins appear to be filamentatious carbon and the veins propagate into the hexagonal packing. For one layer of deposition the vein in trench pattern has a trench width of 0.2 to 0.3 micrometers. The vein spacing appears to be approximately 1 micrometer. With two layers of deposition, the vein to vein spacing shrinks to approximately 0.75 micrometers. At 3 layers of deposition and above the veins appear to be 50 nanometer filamentatious carbon in 0.2 micrometer trenches. Furthermore, the veins propagate into the hexagonal patterns.

In addition to depositing multiple layers of a single concentration, capping may be used to change the function of the CEM. For example, Table Il shows the results of capping 0.2M layers. Three uncapped layers of NiO deposited by 0.2M solution does not result in memory switching characteristics, nor does three layers capped by 2 layers of 0.1 M NiO solution. Depositing four capping layers, yields a CEM that is initially in the "on" state, however the resistance of the CEM is still too low for reset to occur. It is of note that this structure (3 layers of 0.2 M (bulk) capped with 4 layers of 0.1 M) functions similarly to a single layer resulting from the deposition of a 0.2M solution. Table Il

The deposition of 3 layers of 0.2M solution capped by 6 layers of 0.1 M solution yields a CEM that has memory switching properties. The resulting CEM is Born-On, MS bipolar, and may be reset. The capping layers reduce the initial on state reset current and at the same time preserve the born-on behavior.

As can be seen in FIGS. 59-62, the use of capping layers reduces the set voltage of the CEM and cause the set voltage to be more precise. Furthermore, the precision in the reset value is improved by the addition of the capping layers. As smooth capping layers are added the prevalence of the vein patterns (features or irregularities) is reduced, resulting in a smoother fagade. The proper density of features appears to be important to the function of the CEM as a memory switch.

FIG. 59 depicts the initial trace for a the deposition of 3 layers of 0.2M solution capped by various numbers of layers of 0.1 M solution capping layers. As is shown in the graph, 0-4 capping layers yields a CEM film that does not exhibit memory switching. When six capping layers are used the CEM exhibits memory switching on its initial trace. FIG. 60 shows a graph of the deposition of 3 layers of 0.2M solution capped by 6 layers of 0.1 M solution, exhibiting the memory switching of the CEM. The dotted line depicts the on-state and the solid line depicts the off-state. The addition of capping layers may be used to reduce the initial On-state reset current and preserve born-on behavior for a CEM device. Therefore, a technique that may be utilized in forming CEM devices that exhibit memory switch may begin with the utilization of two types of CEM deposited materials: initially on CEM material with resistance so low that no reset is possible and CEM material that exhibits threshold switching (no matter what voltage is applied, the material only allows for so much current, i.e. as voltage increases, resistance increases). Layers of threshold switching material may be added to an initially on CEM with no reset voltage. By the addition of layers of threshold switching CEM material, the initially on characteristic may be retained, however reset of the CEM device may become possible. FIG. 61 shows set (solid circles) and reset voltages (empty circles) for a CEM device deposited according to a uniform deposition process where each layer of deposited CEM material is a result of the same deposition solution concentration. FIG. 62 shows set and reset voltages for a bulk layer and capping layer process. As is clear, not only does the bulk layer and capping layer process yield memory switching, but the precision of the set and reset voltages is greater.

FIGS. 63-65 depicts the results of current versus voltages traces on varying size resistors formed by depositing three bulk layers using a 0.2M concentration of NiO that is capped by six smooth layers of 0.1 M NiO. It appears to be the case that in order for the resistors (or CEM memory cells) to register an initially on state, there must be at least one morphological feature or irregularity on the resistor. As can be seen from FIG. 54, 70% of the 7.5 urn square resistors were initially in the off state, suggesting that only 30% of the resistors had at least one feature or irregularity. For the 10 urn square 70% of the resistors were initially on (and therefore had at least one surface feature). For the 15 urn square, 87.5% of resistors exhibited the on state.

Since the morphological features cannot be easily detected, conclusions have been drawn based on the results shown in FIG. 63-65. From these results the expected yield of features or irregularities was determined according to Poisson Yield Analysis techniques as shown in FIG. 66. For a CEM created by depositing three bulk layers using a 0.2M concentration of NiO capped by six smooth layers of 0.1 M NiO, the concentration of features is approximately 1 feature per 100 um2. The yield analysis rests on the assumption that CEM resistors exhibiting memory switching and initially in the on state are those that exhibit approximately one surface feature.

Poisson Yield analysis is based on the Poisson distribution: J(k, λ) = (λ^ke^"k)/k!. This basic equation may be converted to the equation Y=e^"DA where Y is the percentage of devices with no surface features, A is the device area, and D is the surface density of a feature. If the natural logarithm of Y is plotted vs. the area, a line fitted to the plotted points can approximate the expected surface features for a certain area. As shown in FIG. 66, this is approximately 1 surface feature for every 100 urn² for a CEM composed of 3 bulk layers formed from 0.2M solution and 6 capping layers formed from 0.1 M solution of NiO.

The feature density may not be uniform across a deposited wafer. As can be seen in FIG. 67-68, the feature density is relatively constant in the center of the wafer (1 per 100 um2), however, beyond 20 mm from the center of the wafer, the feature density diverges. The density of surface features may lead the function of the CEM as a memory device, so the uniformity of feature density may have a bearing on where CEMs are formed and the size of the CEM formed. In one embodiment, CEMs are formed in respect to the expected density of the wafer, such that each CEM has a high probability of having a single feature. In one embodiment, CEMs are formed by depositing three bulk layers using a 0.2M concentration of NiO capped by six smooth layers of 0.1 M NiO. The area of the CEMs are etched such that their area is 100 um2. In one alternative, the CEMs are only formed in the area of the wafer exhibiting relatively constant feature density (less than 20 mm from the center of the wafer). FIG. 69-70 shows the correlation of feature density to initial reset current. The dotted line in Fig. 70 is from the upper left portion of the wafer. The dashed line is from the lower right potion of the wafer. The dotted and dashed line is from the middle of the wafer. As is clear in Fig. 69 the feature density varies with the radial position measured on the wafer.

The fatigue of a CEM device formed with 3 bulk layers of NiO 0.2M and 6 capping layers of NiO 0.1 M is low as shown by FIG. 71. In Fig. 71 the triangular points are representative of tests at 85 degrees Celsius and the circular points are representative of tests at 25 degrees Celsius. The reset and set voltage for the CEM device is very steady even after 107 cycles. Furthermore, as shown in FIG. 72, the resistance of the off state does not degrade up to temperatures of 150 degrees Celsius. The Off is depicted by the dotted line and hollow points and the on is depicted by the solid line and points. Alternatively, different depositions are used yielding different feature densities.

The areas of the CEMs are determined in relation to the feature density, such that each CEM is likely to have one and only one feature. In one embodiment the area of the CEM is adjusted as the radius from the center of the wafer departs from the area of the wafer having a uniform density. Therefore, in one embodiment a CEM is used to achieve a distribution of vein patterns (features or irregularities) in order to achieve memory switching characteristics as described in reference to FIGS. 1 and 2. This is achieved as described above, by the proper distribution of vein patterns. This yields a CEM with on and off states where the off state has a resistance of at least 100 times that of the on state. FIG. 73 depicts an example of a conceptual layout for a liquid source misted chemical deposition (LSMCD) apparatus, which is an alternative deposition technique for the CEM. LSMCD may be an effective technique for the deposition of CEM, since LSMCD typically yield an even deposition of substrate. Therefore, if LSMCD is used to deposit CEM, then variations in the morphological feature density may be reduced or eliminated. This would allow for a large percentage of the deposition area to be utilized without compensating for variations in feature density by modifying the area of the memory cell. LSMCD allows for controlled depositions of 4 - 100 nanometers. The layers of CEM deposited are generally in this range. The LSMCD uses same precursors as spin-on to preserve carbon chemistry. The LSMCD 7610 is integrated with Wafer Handler 7620, Rapid Thermal Processing (RTP) or Laser Thermal Processing (LTP) module 7630, and Wafer Loadlock 7640. The process of LSMCD involves the flow of a liquid 7675 to be deposited from reservoir 7680 flowing to the atomizer 7670. The atomized mist 7660 flows to showerhead 7650 and through field screen 7655. It is deposited on wafer 7665 which is in rotation provided by rotator 7690 powered by high voltage connection 7685. As shown in FIG. 51 , each bulk layer deposited is typically on the order of 100 angstroms or 10 nanometers. Each capping layer is typically on the order of 50 angstroms of 5 nanometers. Since the CEM film deposited is very thin, LSMCD may be better suited for the deposition of CEM material.

The various elements 77, 88 can then be tested by attaching one probe to platinum surface 88 and touching a fine probe to the top electrode, such as 92, of the element to be tested, such as 80. The various curves discussed below were generated in this manner.

It should be understood that figures such as FIGS. 3, 4, 15, 17 - 19, 22 and 24 depicting integrated circuit devices are not meant to be actual plan or cross-sectional views of any particular portion of actual integrated circuit devices. In actual devices, the layers will not be as regular and the thicknesses may have different proportions. The various layers in actual devices often are curved and possess overlapping edges. The figures instead show idealized representations which are employed to explain more clearly and fully the method of the invention than would otherwise be possible. Also, the figures represent only one of innumerable variations of devices that could be fabricated using the designs and methods of the invention. As conventional in the art, the term "metal" when referring to an electrode or other wiring layer generally means a conductor. As known in the art, such "metal" electrodes and/or wiring layers can be made of polysilicon or other conductive material and are not necessarily made of metal.

FIG. 12 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, to better illustrate the ON, OFF, RESET, and SET modes. The material is crystallized in the ON state and the current rises along the ON curve as voltage is increased up VRESET. The current then drops to the OFF curve and increases gradually along the OFF curve until VSET is reached, at which point it increases toward the ON curve. However, in devices, the current is limited the dotted line, lset to prevent overcurrent. The read and write margins are shown in the figure. As shown by FIGS. 6 and 7, the NiO(Cx) films according to the invention follow these idealized curves better than any prior art material.

The CEMs are typically oxides formed from elements that have a partially filled 3d band and materials with partially filled 3f bands in the Periodic Table. The most well known of these oxides are vanadium oxide and nickel oxide. The materials with partially filled 3d bands or partially filled 3f bands are sometimes described also as Metal/Insulator phase transition materials. However, such metallic to insulator transition can also occur in combining transition metals with other materials of systems such as sulfides, iodines, tellurides, and others that do not involve oxygen. In all such materials, which includes groups IMB up to and including group MB (from column three to twelve across the Periodic Table - for half filled 3d materials) and the elements 57 to 71 and 89 to 103 for the half filled 3f band, clear description of the electronic bands is still lacking due to the strong coulombic correlation between electrons. However, the narrow 3d and narrow 3f orbitals cause strong electron correlations, and such correlations are responsible for a switching mechanism that can be voltage activated. For understanding the invention, it is important to separate this switching process which is triggered by a critical electron population from other switching processes, such as solid state phase changes. Herein, we shall refer to materials which employ the above-described switching process as "Correlated Electron Materials" (CEMs) and the basic unit of electrode/CEM/electrode as a "Mott-Bardeen Switch" (MBS). The easiest conceptual description of such materials is that in the insulating state the interaction energy between electrons is so strong that the effective mass (m*) is much heavier than the electron mass in the electron gas phase, which is known as the Rice-Brickman description. Thus, a switch between masses (caused by the overlap of the electron wave functions in 3d-subands (or 3f-subbands) at a certain operational voltage sets the state of the material from insulator to metal (and vice-versa) by increasing or decreasing the interaction energy relative to the energy gap. In the past, such change in the electron mass was attained mainly by a change in temperature, and these materials were studied for their thermodynamic properties, implying a change in physical structure. However, as explained herein, the electronic transitions due to correlated electrons occur at room temperature or over a useful temperature region for device operation, and in both polarities of the applied voltage. Thus, when the term "phase change" is used herein with respect to a CEM, it relates to the change of an electronic phase. Also, the transition causes a hysteresis of the current versus voltage characteristic yielding two resistive states which are stable for an undetermined period of time producing a nonvolatile memory behavior. Such memories are quite promising because they are not only non-volatile, but the electronic phase change is resistant to radiation damage and the memories can be made very dense.

A CEM with a single conducting electrode and the other surface contacted to an insulator or another CEM will be called "Metal/CEM Bardeen Barrier" or an "MCB barrier", better described by what is known in the literature as a "Bardeen Transfer Hamiltonian" which, when used with different effective mass tensors across the metal to CEM barrier, with or without the aid of vacancies, describes well the metal to CEM tunneling with an effective mass switch occurring as the electron enters the CEM from the common metal electrode, and an electronic phase transition is caused which produces the switching action; and when such an MCB barrier is in contact to a semiconducting material such as polysilicon which is a common floating gate material, this shall be called an "MCB to floating gate switch". These definitions will become useful as the complexities of the many embodiments of this invention are described below. Whether the theoretical descriptions are referring to a switch in effective mass or opening and closing of sub-bands in the density of states of the CEM, or the reaching of a critical electron density, the utility of the switching action and the stability of the final state (metal or insulating) and the control of such action is a central point of the invention for non-volatile memories applications.

In the preferred CEM described herein, extrinsic ligand-forming dopants are added to the transition metal compounds. However, it should be understood that correlated electron switching can occur in materials other than materials including ligands. The extrinsic ligands stabilize the metals in the compounds to a stable valence state. With such stabilization, electroforming is no longer necessary. Herein, stabilized means with respect to both time and temperature. In particular, it means that the electrical properties critical to reliable memory operation, including the RESET voltage, the SET voltage, and the memory window, i.e., the voltage or capacitance difference between the non-conducting and conducting states, does not change more than thirty percent over operational time period and temperature range, i.e., over a time period of three years, and more preferably, five years, and most preferably, ten years, and a temperature range from 0 ⁰C to 60 ⁰C, more preferably from -20 ⁰C to 80 ⁰C, and most preferably from -50 ⁰C to 100 ⁰C. More preferably, these electronic parameters do not change more then twenty-five percent, and most preferably, they do not change more than twenty percent.

Some ligands may be less useful than others because they are not stabilizing under all circumstances. Preferably, the invention utilizes ligands that stabilize the orbital valence states, and particularly the 3d orbital states. For example, the complex [Ti(H2O)6]3+ is not stabilizing for conventional CMOS processing because when it is annealed the water evaporates leaving uncompensated titanium, which can take many different valence states. Such a material will require electroforming. However, it can be stabilizing in other processes. The preferred ligands comprise one or more elements selected from the group consisting of oxygen, hydrogen, fluorine, carbon, nitrogen, chlorine, bromine, sulphur, and iodine. Some useful ligands for various metals are shown in Table III. In this table, the metal of interest is given in bold, followed by the formula for the complex the metal forms with the ligand of interest. Table III

Aluminum

[AI(OH)4]-

[AIF6]3-

Cadmium [Cd(CN)4]2- cis-Cd(NH3)4CI2 trans-Cd(NH3)4CI2

Chromium

Cr(acac)3 [Cr(CN )6]4-

[Cr(en)3]3+

[CrF6]4-

[Cr(NH3)6]3+

[Cr(OH2)6]3+ [CrO4]2- cis-Cr(acac)2(OH2)2 trans-Cr(acac)2(OH2)2 cis-[Cr(NH3)4CI2]+ trans-[Cr(NH3)4CI2]+ [Cr(NH3)5Br]2+

[Cr(NH3)5CI]2+

[Cr(NH3)5(0S03)]+ cis-[Cr(OH2)4C12]+ trans-[Cr(OH2)4C12]+ [Cr(OH2)5Br]2+

[Cr(OH2)5CI]2+ [Cr2O7]2- Cobalt [CoBr4]2- [CoBr6]4- [CoCI4]2-

[Co(CN)6]3- [Co(en)3]3+ [CoF6]3- [Co(NH3)6]2+ [Co(NH3)6]3+

[Co(OH2)6]2+ [Co(03C)3]3- Cis[Co(en)2CI2]+ trans-[Co(en)2CI2]+ cis-[Co(OH2)4(SCN)2]+ trans-[Co(OH2)4(SCN)2]+ cis-[Co(NH3)4CI2]+ trans-[Co(NH3)4CI2]+ cis-Co(NH3)4(NO2)2 trans-Co(NH3)4(NO2)2 cis-Co(NH3)4(ONO)2 trans-Co(NH3)4(ONO)2 cis-[Co(ox)2(OH2)2]- trans-[Co(ox)2(OH2)2]- cis-[Co(en)2(NO2)CI]+ trans-[Co(en)2(NO2)CI]+ [Co(NH3)5CI]2+ [Co(NH3)5(NO2)]2+ cis-[Co(NH3)Br(en)2]2+ trans-[Co(NH3)Br(en)2]2+

Copper [Cu(CN)2]- [Cu(NH3)4]2+ [Cu(OH2)6]2+ cis-[Cu(en)2(0H2)2]2+ trans-[Cu(en)2(OH2)2]2+ Gold

[Au(CN)2]- lron

[Fe(CW)- [Fe(CN)6]3-

[Fe(CN)6]4-

Fe(CO)5

[Fe(EDTA]2-

[Fe(en)3]3+ [Fe(OH2)6]2+

[Fe(OH2)6]3+

[fe(ox)3]3-

[Fe(SCN)6]3- cis-[Fe(en)2(NO2)2]+ trans-[Fe(en)2(NO2)2]+

[Fe(OH)(OH2)5]2+

Manganese

[MnCI6]4-

[Mn(CN)6]3- [MN(CN)6]4-

[Mn(en)3]2+

[Mn(OH2)6]2+

[MnO4]-

Mercury [HgS2]2-

[HgCI3]-

[Hgl4]2-

Molybdenum

[MoO4]2- Nickel

[NiBr4]2-

[Ni(CN)4]2-

Ni(CO)4

[Ni(en)3]2+ [Ni(NH3)4]2+

[Ni(NH3)6]2+ [Ni(OH2)6]2+ [Ni(ox)2]2- [Ni(penten)]2+ cis-Ni(en)2CI2 trans-Ni(en)2CI2

Palladium [PdCI4]2- Platinum [PtCI4]2- [PtCI6]2-

[PtCI6]4- [Ptl4]2- [Ptl6]2- [Pt(NH3)4]2+ Pt(en)CI2 cis-Pt(NH3)2CI2 trans-Pt(NH3)2CI2 cis-Pt(NH3)2CI4 trans-Pt(NH3)2CI4 Pt(NH3)2(ox)

[Pt(NH3)3Br]+ trans-[Pt(NH3)4CI2]2+ cis-[Pt(NH3)4CI2]2+ cis-[Pt(NH3)4l2]2+ trans-[Pt(NH3)4l2]2+

Rhenium [ReO4]- Rhodium [RhCI6]3- [Rhl2(CO)2]- cis[Rh(phen)2CI2]+ Ruthenium [Ru(NH3)6]2+ [Ru(phen)3]2+ [Ru(NH3)5CI]2+

Silver [Ag(S2O3)2]3-

[Ag(N H3)2]+

Tin

[SnCI6]2- [Sn(OH)6]2-

[Sn(OH)3]-

Titanium

[TiO]2+

Vanadium [V(en)3]3+

[VO]2+

[VO2]+

[VOCI4]2-

Zinc [Zn(CN)4]2-

[Zn(NH3)4]2+

Based on the above discoveries, Applicants have for the first time applied ligand field theory to the understanding of a resistance switching mechanism in transition metal compounds. Ligand field theory was developed in the 1930's and 1940's as an extension of crystal field theory. See for example, "Ligand Field Theory" in Wikepedia, the free encyclopedia at http://en.wikipedia.org/wik/Ligand _field theory, which is incorporated by reference herein to the same extent as though fully disclosed herein. As explained therein, the energy difference between certain molecular orbitals (MO's) is called ΔO, where the "O" stands of octahedral. This size of this energy difference, ΔO, determines the electronic structure of d orbitals. We have found that, in the thin-film regime used in the fabrication of the devices according to the invention, the stability of the memory window between the OFF state and the on state is substantially proportional to the stability of ΔO. Thus, the preferred dopant ligands are those which result in a large and stable ΔO. Some useful dopant ligands in descending order of the size of the ΔO they create are: CO, CN-, PPh3, NO2-, phen (1 ,10-phenanthroline, biby (2,2'-bipyridine), en (enthylenediamine), NH3, py (pyridine), CH3CN, NCS-, H2O, C2O42-, OH-, F-, N3-, N03-, Cl-, SCN-, S2-, Br-, and I-. Theoretically, the crystal field splitting energy (ΔO) is not directly related to the Mott-charge transfer barrier or the Rice-Brickman mass. But, the stability of the metal-native ligand coordination sphere allows the electron-electron correlations inductive of these transitions to occur in a particular material as the nuances of the bonding and crystal structures are set in place. In any case, the technical relevant effect is to control or stabilize the oxidation number (or coordination sphere) in such a way the local stoichiometry is "nominal" or otherwise suitable to induce the necessary electron correlation conditions. "Extrinsic ligand" or "dopant ligand" is defined herein to be the ligand material added to transition metal complexes to stabilize the multiple valence states of the transition metals. The ligand splits the d-orbitals. We use the term "extrinsic" or "dopant" because the ligand complex is an extrinsic material added to the lattice that is not intrinsic to the lattice structure of the transition metal compound. For example, in NiO, the oxygen is an intrinsic ligand, and (CO)4, in forming Ni(CO)4, is the extrinsic ligand. Similarly, other variants such Ni5(CO)12 (nickel carbonate) include a form of CO as extrinsic ligands to the basic NiO lattice. This is analogous to the use of the term dopant in semiconductor technology. That is, in semiconductor technology adding a dopant to silicon, for example, does not change the silicon so much that we refer to it as another compound. Likewise, the dopant ligand added to say, nickel oxide, does not change the fact that the material is nickel oxide. But, local correction of the many possible oxidation numbers (valences) of Ni, such as Ni vacancies, interstitials and oxygen vacancies that modify the nominal "+2" valence value, is achieved with ligands that mediate with the intrinsic ligand yielding a stable net oxidation number and eliminate the defect induced change in charge state.

The band structure of correlated electron materials according to the invention is complex and depends not only on the d-orbitals of the transition metals but also on the p-orbitals of the neighboring oxygen atoms. This is explained in detail in Introduction to the Electron Theory of Metals, Uichiro Mizutani, Cambridge University Press, Cambridge, UK, 2001 , particularly pages 444 - 447. Figures 14.9(a) and 14.9(b) from page 446 of this book are reproduced herein at FIGS. 13 and 14. The Δ used in this section is different than the discussed above, so we shall refer to it as Δt, since it is the charge transfer energy, i.e., the energy to transfer of 3d electrons to the oxygen atom. In these figures U is the d-orbital coulomb energy, sometimes referred to as the correlation energy, and EF is the Fermi level of the transition metal.

In both the Mott-Hubbard insulator of FIG. 13 and the charge transfer-type insulator of FIG. 14, when the density of electrons is small, U is small, and the d-orbitals 183, 192 and 184, 193 overlap forming a wide d band with few electrons, while the filled p-orbital 182, 191 is split from and below the d-band. The d-orbital thus behaves much like a metal, and the material is conducting. As the density of electrons becomes large, differences occur. When Δt is larger then U, as in FIG, 13, the d-orbitals split into a pair of separated bands 189 and 190, and the p-orbital 188 remains below the d-orbital bands.

When Δt is smaller than U, the p-orbital of the intrinsic ligand splits the d-orbital which tends to stabilize the d-orbital valence, yielding a net oxidation state of zero, for example, Ni+20-2. In such conditions, the insulator is a charge-transfer insulator, which leads to lower operating voltages. Thus, correlated electron systems in which Δt < U are preferred systems. One way of understanding the resistive change of the CEM materials can be seen most easily using FIG. 14. As indicated above, when the density of electrons is small, the two d-orbital bands 192 and 193 overlap and a conductor results. As the density of electrons increases, it will reach a point where the coulomb repulsion is so high that the d-orbitals 194 and 195 split with the filled p-orbital valence band between them. One d-orbital 194 is essentially filled, while the other 196 is empty. It requires a large amount of energy for electrons to jump from the lower band 194 into the upper band 196. And, even if a d-d transition could occur with the aid of a hole in the p-orbital band, this requires a higher voltage, which is useful in the insulator to metal transition but not in the metal to insulator transition. Thus, this material will be an insulator with high resistance when the lower voltage induces a metal to insulator transition purely caused by increasing the local density of electrons. However, when the electric field created by the applied voltage becomes large enough, some electrons will begin to jump to the upper band 196. This creates an overlap of the upper empty band and lower filled d-bands, the condition of a highly conductive state with small coulomb repulsion, and the system collapses back to the state shown at the left in FIG. 14. From FIG. 14, it is also clear that transitions can be made from the p-orbital to the d-orbital which create "holes", which can be filled by electrons from filled d-bands. The interaction of d-d orbital transitions is highly dependent on the existence of p-orbitals in these CEM compounds. The absence of an oxygen atom in the lattice induces a +2 charge, i.e., a doubly charged vacancy, which would be neutralized if the oxygen would return with its -2 valence. Since this does not happen once the defect is in place, the Ni or other transition metal no longer coordinates or bonds normally with the oxygen, Thus, the emission of up to two electrons into this positive potential, makes the Ni become +4, with the result that it is no longer useful for a Mott or charge transfer condition. It is at this point that mediation between the defect and an extrinsic ligand, re-establishes the oxidation state of the nickel. Without the ligand, the unbalanced, unstable insulative state is either heavily saturated with coordination destroying oxygen vacancies or equally detrimental and related excess nickel anions in interstitial sites in the lattice. The metal-ligand-anion (MLA) bond which stabilizes the correlated electron material in some embodiments can be formed in many ways. For example, it may be formed in an anneal or other reaction process. For example, the CEMs may be annealed in a gas that contains the ligand chemical element, the anion element, and preferably also includes both the ligand element and the anion. Any gas incorporating any of the ligands above may be used. The gas may be formed through conventional precursor vaporization processes, such as heating and bubbling. As another example, the CEM may be reactive sputtered in a gas containing the ligand chemical element, the anion or both. Again, any of the ligands above may be used. As an example, for NiO, with a carbon ligand and an oxygen anion, CO and CO2 are possible annealing gases. The anneal may be performed with one or more of these gases, or may be performed in a mixture of an inert gas, such as argon or nitrogen, with the gas containing either the ligand element, the anion element, or both.

For additional understanding of ligand field theory and the related ligand chemistry, see An Introduction to Transition-Metal Chemistry: Ligand-Field Theory, Leslie E. Orgal, Methuen & Co. Ltd., London, 1960.

An alternative understanding of the resistive switching phenomenon can be obtained from Mott Insulator theory, as explained, for example, in Metal-Insulator Transitions, Sir Nevill Mott, Second Edition, Taylor & Francis, London, 1990, and the Hubbard Model, as explained, for example, in The Hubbard Model, Arianna Montorsi Ed., World Scientific, Singapore, 1992. This understanding can be briefly summarized by considering the basic voltage versus current curve showing the effect of the resistance switching on the current as the voltage is increased, as, for example, that shown in FIG. 5. At zero voltage, the NiO is in a paramagnetic phase, and has zero current. As the voltage is increased, the current rises in the region 110, due to the fact that the electric field is giving electrons enough energy to jump up into the conduction band. The number of electrons continue to increase until the Mott transition condition (nC)1/3a = 0.26, where nC is the concentration of electrons and a is the Bohr radius, is reached at point 115. As described by Mott, at this point the electron gas condenses and the material becomes an anti-ferromagnetic insulator. This is the RESET state. As the voltage continues to increase along line 112, there is a minor increase in current until the point 116 where the electric field energy becomes equal to what the thermal energy would be if the material was at the Neel temperature, which is about 550K for NiO. At this point, there is an electronic phase change of the material back to the paramagnetic state, which state remains even if the voltage is reduced back to the lower voltage range of portion of the curve. This is the SET state. In some modern theoretical approaches to this phase transition, the term "electron liquid" refers to the state of heavy mass and this "electron condensation" phenomenon, and, electron gas refers to the uncorrelated electron. Electron liquids, such as in the Landau theory of "Fermi-liquids" are still a very immature area of condensed matter physics and the term is used here only to describe highly correlated electrons, as in the liquid state, versus non interacting electrons as in the electron gas.

FIGS. 15 - 28 illustrate some of the non-volatile memories according to the invention. In this context, the word "substrate" can mean the underlying semiconductor material 82 (FIG. 4), 331 , 351 , etc. on which the integrated circuit is formed, as well as any object, such as layer 88 in FIG. 4 or layer 342 in FIG. 15, on which a thin film layer, such as 90 or 344, respectively, is deposited. In this disclosure, "substrate" shall generally mean the object to which the layer of interest is applied. For example, when we are talking about a thin film 90 of FIG. 4, the substrate on which it is initially deposited may include various elements, in particular, bottom electrode 88. The long horizontal dimensions of substrates 82, 331 , 351 , etc. define planes that are considered to be a "horizontal" plane herein, and directions perpendicular to this plane are considered to be "vertical". The terms "lateral" or "laterally" refer to the direction of the flat plane of the semiconductor substrate, that is, parallel to the horizontal direction. Terms of orientation herein, such as "above", "top", "upper", "below", "bottom" and "lower", mean relative to substrate 82, 331 , 351 , etc. That is, if a second element is "above" a first element, it means it is farther from semiconductor substrate 82, 331 , 351 etc.; and if it is "below" another element, then it is closer to semiconductor substrate 82, 331 , 351 , etc. than the other element. Terms such as "above", "below" or "on" do not, by themselves, signify direct contact. However, terms such as "directly on" or "onto" do signify direct contact of one layer with an underlying layer. However, "directly above" does not require direct contact, but rather means that if a line is drawn perpendicular to the underlying substrate and the line passes through the first element, it also will pass through the second element. It is understood that thin films of CEM fabricated in accordance with the invention have various shapes and conform to various topographies and features of an integrated circuit substrate. Accordingly, thin films of CEM in accordance with the invention are formed on planar substrates, in trenches and vias, on vertical sidewalls, and in other various non-horizontal and three-dimensional shapes.

The term "thin film" is used herein as it is used in the integrated circuit art. Generally, it means a film of less than a micron in thickness. The thin films disclosed herein are typically less than 500 nanometers (nm) in thickness. A thin film of correlated electron material fabricated by a method in accordance with the invention typically has a final thickness in a range of about from 20 nm to 300 nm, preferably in a range of about from 25 nm to 150 nm. The thin films having a thickness of about 60 nm or less are specifically designated "ultra-thin films" in this specification.

FIG. 15 is a cross-sectional view of a M/CEM/M n-p diode switching cell 330. FIG. 16 is an equivalent circuit diagram for the M/CEM/M p-n diode switching cell of FIG. 15. Cell 330 is formed on a semiconductor wafer, which is preferably silicon, but also may be gallium arsenide, germanium, silicon-on-insulator (SOI), or any other suitable semiconducting substrate, Wafer 331 preferably includes an isolation layer 332, an n- type region 334, a p+ active area 336, and a metal/CEM/Metal electronic phase change device 340 formed on active area 336. N-type region 334 and p+ active area 336 form a n-p junction diode 335. Device 340 includes a bottom electrode 342, a CEM layer 344, and a top electrode 348. Electronic phase change device 340 is preferably part of a cross-tie structure.

FIG. 17 is cross-sectional view of an M/CEM/M-metal/semiconductor or Schottky diode switching cell 350 according to the invention. Cell 350 comprises a Metal/CEM/Metal switching element 352 fabricated on a semiconductor wafer 351. Wafer 351 includes isolation layer 354 and n-type doped area 355. Variable resistance element 352 comprises a lower electrode 357, a CEM layer 355, and a top electrode 359. The Schottky diode is formed at the interface of the n-type area 355 and electrode 357. Variable resistance device 352 is preferably part of a cross-tie structure.

FIG. 18 is a cross-sectional view of an M/CEM/M-MESFET 370 according to the invention. Cell 370 is essentially an MESFET in which a CEM variable resistance element 380 is the gate of the MESFET 370. Cell 370 comprises a Metal /CEM/Metal switching element 380 fabricated on a semiconductor wafer 371 , which is preferably gallium arsenide, but may also be germanium, silicon, or any other suitable semiconductor. Wafer 371 includes isolation layer 374, n-type doped area 375 including channel 378, and p+ type active areas 376 and 377. Variable resistance switching element 380 comprises a lower electrode 381 , a CEM layer 382, and a top electrode 383. Variable resistance device 380 is preferably part of a cross-tie structure. FIG. 19 is a cross-sectional view of a M/CEM/M-JFET memory switching cell 400 according to the invention, and FIG. 20 is an equivalent circuit diagram of the a M/CEM/M-JFET 400 of FIG. 19. This structure is essentially a JEFET in which a variable resistance switching element 404 forms one side of the JFET gate. M/CEM/M- JFET 400 is formed on semiconductor wafer 401 comprising a backside gate contact layer 410, a p+ substrate, and n-type region 414, which is preferably an epitaxial layer. N+ active areas 417 and 418 and p+ region 419 are formed in n-type region 414. Metallization contacts 422 and 422 are formed on active regions 417 and 518, respectively. Metal layer 426, CEM 427, and metal layer 425 are formed over p+ region 419.

FIG. 21 is a cross-sectional view of a M/VRM/M-MNOSFET memory switching cell 430 according to the invention. Device 430 comprises a p-type semiconductor 433 on an isolation layer 432, n+ active areas 439, and gate stack 434. Gate stack 434 includes insulator 435, which is preferably silicon dioxide, conductive gate 436, VRM layer 437, and top electrode 438.

FIG. 22 is a cross-sectional view of a 1 transistor/1 resistor CEM switching cell 440 according to the invention, and FIG. 23 is an equivalent circuit diagram of the 1 transistor/1 resistor CEM switching cell of FIG. 22. Cell 440 is formed on semiconductor wafer 444, which is preferably p-type silicon, but may be any other semiconductor. N- type active areas 452 and 453 are formed in wafer 444 and gate insulator 456 and gate 458 are formed over channel region 455 between the active areas as in conventional CMOS structures. A CEM device 446 is formed on one active area 453 and a metallization contact layer 466 is formed on the other active area. CEM device comprises bottom electrode 460, CEM layer 462, and top electrode 464. While this structure is similar to 1T/1C DRAM and ferroelectric memory structures, CEM layer 462 does not store charge but rather switches resistance states. The resistance state can be identified by the voltage drop across the CEM device 446.

FIG. 24 is a cross-sectional view of a M/l/S switching transistor 530 according to the invention in which the insulator is a CEM, that is, a metal/VRM/Semiconductor switch. M/CEM/S switch 530 is formed on a semiconductor wafer 532, which is preferably silicon but may be any other suitable semiconductor. An isolation layer 540 is formed at the bottom of the wafer, and either a p-type or n-type region 534 forms the channel region 555, on either side of which are implants 542 and 544 which form active regions. A CEM layer 552 is formed on channel 555 and a metal layer 560 is then formed on CEM layer 552.

A basic CEM cross-tie array is shown in FIG. 25. FIG. 25 illustrates the cross- sectional equivalent circuit diagram for a CEM memory in a cross-tie architecture. In the cross-tie architecture, first conducting lines 616 running in a first direction form a cross- tie with second conducting lines 615 running in second direction, which second direction is preferably perpendicular to the first direction. At each point where the lines cross, a memory cell, is formed. In the simplest cross tie memory shown in FIGS. 25 and 25, a CEM layer, such as 617, is sandwiched between the conductors615 and 616. This memory is preferably operated by setting all cells to the conducting state, they writing selected cells to the insulating state. For example, if the reset voltage is 1 volt, CEM element 617 may be reset to an insulating state by placing Vi volt on line 616 and Vi volt on line 615. The other lines are held at zero volts. The non-selected CEM elements, such as 617, will not be reset because the voltage placed on them will always be less than the reset voltage. Individual cells may be read by placing a small read voltage across the lines corresponding to that cell and holding all other lines in the open state. If the selected cell is conducting, there will be much less of a voltage drop across it than if it is insulating. The state of the cell can thus be read by sense amplifiers know in the art. While this simple cell structure preferably is operated using a block erase, other cross tie cell architectures using a CEM that are true random access memories for both write and read, will be discussed below.

FIG. 26 illustrates another cross-tie memory 100 according to the invention having a CEM layer 105 between cross-tie electrodes 102 and 107. This is the same as the memory 600 of FIG. 25 except that a Schottky diode 109 is formed at the intersection of CEM layer 105 and top electrode 102.

FIG. 27 illustrates a chain cell CEM memory array 650 according to the principles of the present invention. The memory array 650 is composed of memory cells, such as 120, that include a CEM memory element 629 connected in parallel with a switch 621. In one embodiment, the switch 621 may be a MOS transistor. Alternatively, other types of transistors may be utilized. The memory array 650 may be configured by forming series or chains 638 of memory cells 620. As shown, the chains of memory cells 620 may be connected along bit lines BL1-BL4. Word lines WL1-WL4, such as 630, may be connected to memory cells via gate terminals, such as 626, of the switches along a row 636 of memory cells 620. Each bit line may have a select switch, such as 640, and sense switch, such as 644, connected thereto used to control access to memory cells 620 along the corresponding bit lines BL1-BL4. For example, to access a memory cell 620 having switch 621 , select switch 640 and control switch 644 are selectably turned on. Below each control switch, such as 644, may be a sense amplifier SL1-SL4 that is used for reading data stored in the memory cells along the corresponding bit line as understood in the art.

FIG. 28 is a cross-sectional view showing the preferred physical structure of a memory cell 620 in the chain cell memory array 650 of FIG. 27. This physical structure may also be used for other memories having memory cell including a transistor and a resistor. Memory cell 620 includes transistor 621 and phase change resistor 629. Transistor 629 comprises semiconductor 770, preferably silicon, having doped source active region 624 and doped drain active region 622, silicon oxide layer 772 and gate 626, preferably, polysilicon. An interlayer dielectric 776 covers transistor 621. Vias 778 and 779 are formed in interlayer oxide 776 and filled with metallization to form posts 782 and 786, which serve as electrodes. A thin CEM layer 629 is deposited to connect posts 782 and 786. As known in the art, the resistance R of element 629 is R= pl/A, where p is the resistivity, I is the length of the CEM element as shown in FIG. 28, and A is the area of the CEM element perpendicular to the current flow. As shown in FIG. 28, A is very small, equal the thickness of layer 629 times its width into the paper. Since the thickness can be extremely small and controlled quite precisely, the resistance in this structure easily can be made large and controlled. The structure of FIG. 28 also makes it easy to link together the chain cells of FIG. 27, with the drain of one transistor 621 sharing the same doped region as the source of the next transistor 639, and the posts 782 and 786 serving double duty as the posts for the neighboring cells as well. Preferably, element 629 is a CEM, but may be any material with a variable resistance.

As previously described, the switches, such as 640 and 644 at the top and bottom, respectively, of the bit lines BL1-BL4 are row/column select switches and sense switches, respectively. The select switches 640 and sense switches 644 are used to select a certain bit and to separate the memory array 650 from extrinsic circuitry. For example, if memory cell 620 is to be selected, select switch 640 and sense switch 644 are turned on and the other select and sense switches are turned off. In addition, word line 630 is grounded, i.e., signal WL1 is made zero, and each of the other word line signals WL2, WL3, and WL4 are turned high. By applying a low voltage onto word line WL1 , switch 621 remains or is turned off so that current is forced through element 629 connected in parallel to switch 621. Because word lines signals WL2, WL3, and WL4 are high, each of the corresponding switches 639, 640, and 641 , are turned on such that current flows through the switches and bypasses each of the other resistive elements, respectively, connected in parallel. The process of being able to select one memory cell along a bit line enables random access writing and reading. While not writing to or reading from the memory array 650, select switches, such as 640, and sense switches, such as 644, may be turned off so that memory array 650 is isolated from the extrinsic circuitry, thereby keeping electrical noise from memory array 650. It should be understood that memory array 650 is shown as a 4x4 chain array, and may be sized and dimensioned as desired, such as 128x128 or much larger.

FIG. 29 is a block diagram of a memory circuit 900 including an exemplary electronic phase change memory array 902 according to the principles of the present invention connected to write and read circuitry. The memory cells in phase change memory array 902 may be any of the memory cells described above. In one embodiment, phase change memory array 902 is formed of 128x128 memory cells. However, variable resistance memory array 902, preferably an electronic phase change memory array, may have virtually any size as understood in the art. Variable resistance memory array 902 may be connected to a 7-bit decoder word line drive circuit 904 via word lines 906. Memory array 902 may be further coupled to a 3-to-1 bit multiplexer 908 and sense amplifiers/input-output transistors 910 via bit lines 912. Control logic circuitry 914 may be in communication with (i) the decoder 904 via control lines 916, (ii) multiplexer 908 via control lines 918, and (iii) sense amplifier 910 via control lines 920. Extrinsic input lines may include an address input line 922 and control lines 924. A data output line 926 may be used to output data from memory circuit 900 via sense amplifiers/transceivers 910.

In operation, an extrinsic processor may be used to drive the control logic 914. Control logic circuitry 914 communicates with decoder 904, multiplexer 908, and sense amplifiers 910, which, in combination, are used to write data into phase change memory array 902 and read data stored in phase change memory array 902. Control logic 914 and decoder 904 comprise a write circuit 928 for placing the resistive switching memory cell in a first resistive state or a second resistive state depending on information input into the memory, and control logic 914, multiplexer 908, and sense amps 910 comprise a read circuit 929 for sensing the state of the memory cell and providing and electrical signal corresponding to the sensed state of the memory cell. As known in the art, the first resistance state may correspond to a logic "0" state and the second resistance state may correspond to a logic "1" state, or vice versa. Herein, for convenience, we have referred to the first resistance state as the ON or low resistance state and the second resistance state as the OFF or high resistance state. The CEM may be implemented in Field Programmable Gate Arrays (FPGAs).

FPGAs typically consist of an array of configurable logic blocks (CLBs) and routing channels. An FPGA CLB may consist of a lookup table and a flip-flop. The lookup table typically is a four input lookup table, however, fewer or greater inputs may be used (including six inputs). The CEM material may be used in constructing the flip-flop of the FPGA, due to its distinct high resistance and low resistance states. Furthermore, the CEM can be integrated into offset, gain, and tuning adjustment apparatuses and electrostatic discharge devices, as will be clear to those skilled in the art in light of this disclosure.

CEM technology may also be implemented in conjunction with Analog Arrays and Field Programmable Analog Arrays. The CEM may be implemented as switches between Configurable Analog Blocks, allowing them to be electrically coupled and decoupled from each other. Furthermore, since CEMs may be used as "capacitors", they may be integrated into the design of the Configurable Analog Blocks as will be apparent to those skilled in the art in light of this disclosure.

CEM technology may also be implemented in display technology. For instance, LCD displays utilizing thin film transistor technology (TFT-LCD) could implement CEM material in their design. As previously described, CEM cells can be readily switched from an on state to an off state and visa versa. In a TFT-LCD, each pixel of the display has a transistor associated with it, allowing each pixel to be individually controlled. The associated transistor must be small so that it does not block light transferred though each pixel. The CEM cells described herein are sufficiently small for this purpose. Typically, transistors in a TFT LCD are composed of silicon. A CEM cell may be substituted for the silicon transistor in a TFT LCD. This usage offers numerous advantages. One advantage is potential power saving, since a low voltage is required to switch the CEM cell. Furthermore, advantageous display management techniques may be utilized, since the CEM cell, once switched, remains switched until the proper voltage is applied. Therefore, an electric field need not be maintained in order to keep a particular pixel active.

The correlated electron resistance switching material is particularly suited for memories, preferably non-volatile memories. A wide variety of such memories are possible, some of which have been discussed above.

Since a CEM retains the resistance state it is place in indefinitely with no voltage or electric field applied to it, all of the CEM devices described herein are inherently nonvolatile switching devices. As known in the art, non-volatile switching devices can be used as or in non-volatile memories. Thus, all of the devices described above also comprise a non-volatile memory cell, or cells in the case of the structures which show multiple CEM elements. Thus, it should be understood that whether the device has been referred to as a CEM layer, a switch, a switching cell, a memory cell or a memory in the above discussion, has been determined by the context, and in all cases the other terms apply also. All of the above cells are written to by applying either a SET or RESET voltage between the bottom and top electrodes, or in the case of the device of FIG. 16, across the electrodes 682 and 686, or in the case of the device 530 of FIG. 12, or between the upper electrode 560 and one or more of the source 542, the drain, 544, and the semiconductor 534. The devices having a VRM stack located over a channel are read by controlling the conductivity of the channel with the state of the VRM material. For example, in the 370 of FIG. 6, if a read voltage is applied to the upper electrode 383, the voltage on the lower electrode 381 will be higher if VRM 382 is conducting, and lower if VRM 382 is high resistive. This difference in voltage on bottom electrode 381 will result in a different conductivity of channel 378, which can be read by applying a voltage across source 377 and drain 376 and reading the resistance, a voltage, or a current. The CEM switching cell 440 of FIG. 10 can be read similarly to a ferroelectric or DRAM memory, using the select transistor 454 to select the cell to be read or written. A voltage or current is placed across the cells, and the resistance state of the CEM determines the voltage or charge developed across the cell, and by sense amplifiers 910. It is evident that if the CEM is conductive, the voltage drop across the CEM will be much smaller than the voltage drop when the CEM is insulating. It is evident that this read can be described in terms of reading a resistance, a voltage, or a current. That is, referring to FIG. 1 , if a read voltage of, say about 0.3 volts, is place across the cell, there will be a large resistance, voltage, or current difference between a cell that is in the state represented by curve 47 and a cell that is in the state represented by the curve 44. In any description, it is evident that the read is inherently non-destructive because the read voltage is well below VRESET and VSET.

The variable resistance - diode configuration, such as shown in FIG. 15, and the variable resistance — JFET configuration, such as shown in FIG. 19, provide important advantages for memory operation. In the variable resistor-diode architecture, the one- way current flow action of the diode introduces an asymmetry in the I-V hysteresis. Under reverse bias, the diode only allows a small reverse saturation current, in approximately the uAmp range, to flow. The current flow is small and almost all voltage potential drops across the diode, which is a further feature that prevents switching of the variable resistance. Hence, the reverse bias hysteresis traces are flat. Under forward bias conditions, the diode starts to flow current at the diode turn on voltage. Above the turn on voltage, the diode is behaving more or less as a short, thus switching of the variable resistance takes place normally. The main result in the hysteresis curves under forward bias is that they are offset by the built-in potential of the diode. The importance of this configuration is that we can now switch the variable resistance element normally under forward bias for writing the memory state. We can also apply reverse bias and not worry about disturbing the memory state. This reverse bias condition is useful to perform a non-destructive read out (NDRO). This may be done by measuring the depletion capacitance of the reverse-biased diode. Before getting to the NDRO of the variable resistance-diode architecture, it is helpful to review the capacitance-voltage characteristics of a stand alone diode first. Under reverse bias conditions, there is a layer at the interface of the pn junction that is depleted of free carriers. This is the called the depletion layer. The depletion layer gets wider under larger biasing, while it gets thinner under smaller biasing. The depletion layer can be considered as a parallel plate capacitor with the width of the depletion layer being the spacing between the plates. Hence, the capacitance of the diode will be smaller at large reverse bias and larger at small reverse bias. This capacitance can be measured by superimposing a high frequency AC signal on top of the static reverse bias voltage. Now consider the variable resistor in series with the diode. When the variable resistor is in the ON (low resistance) state, there is not much effect to the C-V curves as the variable resistance only introduces a small series resistance. However, when the variable resistance is in the OFF (high resistance) state, there is a significant series resistance and capacitance. These series components reduce the overall measured depletion layer capacitance. In this way, the resistance state of the variable resistance element can be determined from the measured capacitance. The read process is very different from the usual read process for memories because a capacitance is measured rather than a voltage or current. However, it should be understood that read processes as discussed above, that include a measurement of resistance, voltage or current, are a preferred method of reading.

Write operation of the CeRAM-JFET, such as shown in FIG. 19, is similar to the write operation of the CeRAM-diode. The gate is forward biased with respect to the drain (or source) line. The gate stack of the CeRAM-JFET has the same architecture and equivalent circuit as the CeRAM-diode configuration. Unlike a MOSFET, where the gate oxide prevents any current flow, the gate of the JFET can be forward biased to flow current for writing the resistive state.

For the read operation, the depletion region created by the JFET gate stack is directly responsible for modulating the conductivity between the source and drain. As gate reverse bias is increased, the depletion region extends into the channel region and reduces the source-drain conductivity. In the limiting case, the channel becomes completely "pinched off' and the JFET is OFF. In a sense, the CeRAM-JFET is similar to a FLASH structure. FLASH is a single transistor that uses a gate stack that is able to store a static charge which thereby modifies the channel conductance. The CeRAM- JFET is also a single transistor that uses a variable resistor in the gate stack as a programmable voltage divider. By turning the variable resistor off, part of the gate bias is dropped on the variable resistor, which reduces the bias level applied to the JFET gate. This in turn increases the source-drain conductivity. The major difference between the FLASH and CeRAM-JFET devices is that the control charge on the FLASH gate is static, while the voltage dividing behavior of the CeRAM-JFET is dynamic and determined by the RC constant of the gate stack. Read operation of the CeRAM-JFET is thereby accomplished through the transient response of voltage pulses. A pulse is applied simultaneously to the gate and the source. These pulses need to be in opposite polarities to keep the gate reverse biased. The measured voltage on the drain line yields the memory state of the variable resistor. For the variable resistor ON state, the entire gate pulse is dropped on the JFET gate and the JFET channel is pinched off. This results in a lower channel conductivity and a lower voltage on the drain line. For the variable resistance OFF state, only part of the gate bias pulse is dropped on the JFET gate. The resulting source-drain conductance is higher, and a larger drain voltage is measured.

With proper design, the MOSFET with a VRM on the gate device 430 shown in FIG. 9 may be used in place of the JFET-VRM scheme described above. While, as mentioned above, the MOSFET gate oxide 435 prevents DC current flow through the VRM 437, the RC characteristic of the VRM/MOS gate stack 434 allow for a transient current/voltage response that is sufficient to switch the VRM during pulsing. By proper scaling of the VRM and gate oxide thickness and area, the MOS capacitance and the VRM resistance can be engineered to permit a write function that switches the VRM material 437. Writing to the VRM is thus accomplished even though no direct current can flow through the gate stack. Readout of the MOSFET-VRM circuit is performed by the same method as the JFET-VRM read function described above.

Those skilled in the art will recognize that in the memory structures above which utilize n and/or p doping, the n and p dopings can be interchanged.

FIG. 30 is a graph comparing the voltage versus current curves for the diode portion of FIG. 15 and the SET and RESET functions of the M/CEM/M-diode switching cell 330 of FIG. 15 with nickel oxide as the CEM. The diode curve is at 210, the ON curve which leads into the RESET function is at 212, and the OFF curve that leads into the SET function is at 214. As known in the art, when the diode is forward biased, the device does not conduct until a threshold is reached and then the current rises exponentially. With the CEM device formed over the diode, the current is essentially zero up to the threshold voltage, due to the action of the diode, then rises, but not quite so quickly, due to the resistance of the CEM layer. The threshold voltage is about 1.7 for this diode. At about 2.3 volts, the current begins to drop and becomes essentially zero at about 2.6 volts, as the resistance has greatly increased. Then, at about 3.1 volts, the current again increases, indicating the CEM material has switched back to a low resistance state. If the voltage is lowered, the current will follow the ON curve. A feature of M/CEM/M-diode device 330 is that resistive switching occurs only when the diode is forward biased. Reverse bias prohibits switching. This is a significant improvement over the prior art as this feature prevents disturb in a cross-tie memory.

FIG. 31 is a graph comparing the voltage versus current in the OFF and ON states for the M/CEM/M-diode switching cell of FIG. 15 with a nickel oxide - carbon CEM. FIG. 32 compares the capacitance versus voltage curves for the ON and OFF states and for the diode only, and FIG. 33 compares the dissipation versus voltage for the ON and OFF states. As can be seen from FIG. 31 , the resistivity in the OFF state is 11 kOhms, while it is only 58 ohms in the ON state. As a result, the current in the ON state can easily be differentiated from that in the OFF state, with just a small applied voltage, such as 0.5 volts. Thus, the memory window is very large. From FIG. 32, the read margin is over 300 picofarads. In the ON or low resistance state, the voltage is primarily dropped across the reverse bias diode. This is a depletion capacitance state. The capacitance as shown in FIG. 32 and the dissipation as shown in FIG. 33 are similar to the same quantities in the diode only. In the OFF or high resistance state, the voltage is partially dropped across the CEM resistor, and the dissipation increases according to tan(d) = ωRC. Because the state of the switch or memory can be read with a voltage much lower than the RESET or SET voltage, and unless the RESET of SET voltage is reached, the system always remains in the same state, the M/CEM/M-diode switching cell permits the fabrication of a no-disturb, non-destructive readout memory. FIG. 34 is a graph comparing the voltage versus current curves for the JFET SET and RESET functions of the M/CEM/M-JFET switching cell 400 of FIG. 19 with nickel oxide as the CEM with nickel oxide as the CEM, and also comparing these curves for the voltage versus current curve of the JEFET. The well-known JFET curve is at 250, the ON curve leading to the RESET function is at 254, and the OFF curve leading to the SET function is at 256. As can be seen from the figure, no switching is possible when the JFET gate/drain junction is reverse biased. With forward bias, the device does not conduct until a threshold is reached and then the current rises exponentially. With the CEM device formed over the diode, the current is essentially zero up to the threshold voltage, due to the action of the diode, then rises, but not quite so quickly, due to the resistance of the CEM layer. The threshold voltage is about 0.8 volts for this diode. At about 1.4 volts, the current begins to drop and becomes essentially zero at about 1.6 volts, as the resistance has greatly increased. Then, at about 3.1 volts, the current again increases, indicating the CEM material has switched back to a low resistance state. If the voltage is lowered, the current will follow the ON curve. A feature of M/CEM/M-JFET device 400 is that resistive switching occurs only when the JFET is forward biased. Reverse bias prohibits switching. This is a significant improvement over prior art memories as this feature prevents disturb in a cross-tie memory.

FIG. 35 is a graph showing time versus voltage for voltage pulses applied to the gate and source of the switching cell 400 of FIG. 19 with nickel oxide as the CEM, and FIG. 36 is a graph showing the measured voltage on the drain of the switching cell 400 of FIG. 19 in response to the voltage pulses applied as show in FIG. 34. In FIG. 34, the gate voltage is the approximately negative one volt curve 274 and the source voltage is the approximately six volt curve 272. Since the gate voltage puts a reverse bias on the M/CEM/M stack 404, no switching occurs. When the CEM layer is ON, essentially no gate voltage is dropped on the CEM resistor, thus the gate bias is the applied bias of about -1 volt. When the CEM resist is OFF, significant gate voltage drops across the CEM layer, thus the gate sees less bias voltage. Thus, the gate voltage when the CEM switch is ON is larger than the gate voltage when the CEM switch is OFF, and in the ON state the JFET channel will be small, i.e., closer to pinch-off, and thus the measured drain voltage is lower at 288 for the ON state than at 280 for the ON state. Thus, the state of the switching CEM element 404 effectively controls drain voltage by modulation the JFET transconductance. The difference between the drain voltage more than half a volt, and thus is easily measured. Thus, the M/CEM/M-JFET 19 provides added insurance that memory readout will be a no-disturb non-destructive memory readout when the source and gate of the device is pulsed.

FIG. 37 is a graph of the resistance of the CEM and parasitic resistance of the interconnects in series versus the SET bias voltage and versus the RESET voltage, showing that high parasitic resistance will create an unstable condition. The parasitic resistance and the CEM resistance act as a voltage divider, with the voltage drop over each being roughly proportional to the resistance. The SET voltage curve 290 is flat, because the parasitic resistance is negligible as compared to the resistance of the OFF state. The voltage required to RESET the CEM rises as the series resistance rises. At the point 294, the RESET voltage becomes larger than the SET voltage. In this condition, when the RESET voltage is reached, the CEM will suddenly become insulative, and the system will fall down to the line 290, and the system will then want to SET, or change to the conductive state. Thus, the material will oscillate between the conductive and insulative states. To avoid this, the parasitic resistance should be kept below about 50 Ohms. For this reason, raw array type memories, as suggested by some prior art papers, will not work unless they are subdivided into smaller arrays. According to one aspect of the invention, thin films of resistive correlated electron material, such as nickel oxide, are deposited via a liquid deposition process, preferably a process in which carbon is introduced into the material. These processes include MOCVD, spin on, dipping, liquid source misted deposition, atomic layer deposition (ALD), other CSD (chemical solution deposition) methods, or by depositing a metal and then oxidizing it with a carbon donor compound present in the atmosphere. In the preferred CSD methods, metallorganic precursors are deposited and reacted to form the desired material. Octane is the preferred solvent for the transition oxide precursors. Single layer films showed cracking, but multilayer films were of electronic device quality. These represent "first try" results, and the experience of the Applicants indicates that good extremely thin films are possible with any liquid source deposition process, including MOCVD and with the process of depositing a metal and then oxidizing it. Results with a furnace anneal of 450⁰C show that on Pt, the films are smooth and are fine-grained. We have shown that the results remain good with anneals in the range of 550⁰C to 650°C. Also, as discussed more fully elsewhere, it is found to be advantageous to include carbon ligand doping in the material. Further, it has been found that annealing in a gas containing the ligand materials is advantageous. Further, the gas preferably also includes the anion to which the ligand bonds the metal. For example, annealing of nickel oxide in carbon monoxide (CO) or carbon dioxide (C02) provides the carbon ligand and the oxygen anion in the metal-ligand-anion bonds that stabilize the nickel oxide. Alternatively, the CEM materials may be sputtered and then annealed in the ligand-containing gas, or may be reactive sputtered in the ligand- containing gas. For example, nickel may be reactive sputtered in CO or CO2.

FIG. 38 is a flow chart showing the preferred process 930 of fabricating the CEM sandwich elements of FIGS. 3 and 4. In process 932 a substrate is prepared. The substrate is preferably a silicon wafer with a silicon oxide coating. The substrate may be baked to remove any contaminants. Simultaneously, at 931 , a CEM precursor is prepared. The precursor contains metal moieties suitable for forming the desired CEM or other variable resistance material upon deposition and heating. For example, if nickel oxide is the desired variable resistance material, then the precursor will contain nickel. The precursor is preferably a liquid containing carbon, preferably a metallorganic precursor. This may be an off-the-shelf precursor purchased from a chemical company, such as Kojundo Chemical Co. of Tokyo Japan. Or the precursor may be prepared just prior to deposition.

At 934 a bottom electrode is deposited. This electrode may include an adhesion layer and/or a barrier layer as known in the art. Preferably, the electrode is platinum. Then, the precursor is deposited in process 936. The may be any of the processes mentioned above. After depositing the precursor is heated to form a crystallized CEM or other variable resistance material. In the preferred embodiment, the heating process comprises a bake process 938 and an anneal process 942. However, a wide variety of heating processes may be used, including baking on a hot plate, furnace anneal, rapid thermal processing (RTP), sometimes called rapid thermal annealing (RTA), or any other process that will crystallize the film. In process 938, the deposited precursor on the wafer is baked, such as on a hot plate, and preferably at a temperature between 100⁰C and 300 ⁰C for a time of between 1 minute and ten minutes. Preferably, two bakes are used at different temperatures, more preferably with the second bake at the higher temperature. The deposition and bake steps are repeated at 940 for as many times as required to obtain the desired thickness of films. After the desired thickness is reached, the dried layers are annealed to form a crystallized film at 942. Preferably, the annealing is at a temperature of from 450 ⁰C to 650 ⁰C, with the lower temperature most preferred, and is for a time from 20 minutes to 1 hour. The anneal may be performed in oxygen or in a gas containing a desired ligand. At 944 the top electrode is deposited. This is preferably platinum.

The top electrode and CEM material is then patterned, preferably by a dry etch, and most preferably by ion milling with argon. The etch has been found to be helpful in obtaining stable materials. Then follows a recovery anneal, preferably at a temperature of from 450 ⁰C to 650 ⁰C and preferably for from 30 minutes to 1.5 hours, and preferably, in oxygen. The integrated circuit is then completed at 954 to include the CEM material, or other variable resistance material, as an active element in an integrated circuit. Here, "active element" means an element that changes in response to the application of current or voltage, in contrast to, say, a passivation insulator. Example I A 2000 A (Angstrom) layer of platinum was deposited on a wafer with a silicon dioxide coating. Then a 0.2 molar nickel oxide precursor in an octane solution was deposited by spin coating the platinum layer at 3000 rpm (rounds per minute). The nickel oxide precursor is available from Kojundo Chemical Company, Tokyo, Japan. The precursor was baked at 150 ⁰C for 1 minute, and then at 260 ⁰C for four minutes to produce an approximately 100 A dry layer. The spin-on deposition and baking processes were repeated six times for a total thickness of 600 A. Then, a crystallization anneal was performed in a furnace at 450 ⁰C in an oxygen atmosphere for 40 minutes to produce a 600 A layer of the CEM nickel oxide according to the invention. Electron microscopy revealed that a significant amount of carbon was present in the material, with the carbon coming from the octane precursor. A top electrode of 2000 A of platinum was deposited. Then, the top electrode and CEM layer were patterned by dry etching, preferably ion milling, down to the bottom electrode platinum layer. Finally, a recovery anneal was performed in a furnace at 450 ⁰C in an oxygen atmosphere for approximately one hour to produce the films discussed with respect to FIGS. 9-12 above. Example Il

This example was made in the same way as Example I above except that 5% ammonia was added to the precursor. The films produced yielded similar results.

The invention includes an annealing process for CEMs. The CEM may be annealed in a gas containing at least one chemical element for forming a ligand which stabilizes the electronic properties of the CEM. Preferably, the CEM is a transition metal and the chemical element comprises carbon. Preferably, the gas comprises a gas selected from CO and CO2. Preferably, the CEM is nickel.

The invention also provides a sputtering method of making a CEM. The material may be sputtered, and then annealed as described above. Or reactive sputtering of the CEM in a gas containing at least one chemical element for forming a ligand which stabilizes the electronic properties of the CEM may be employed. Preferably, the CEM is a transition metal and the chemical element comprises carbon. Preferably, the gas comprises a gas selected from CO and CO2. Preferably, the CEM is nickel oxide.

FIG. 39 is an Arrhenius curve of the log of 1/Tau versus MJ(MK) for prior art sputtered NiO (without carbon) illustrating that the transition from the high resistance state to the low resistance state is caused by detrapping of electrons from oxygen vacancies in the sputtered NiO. To generate this Arrhenius curve the relaxation time for the material to return to the insulative state after SET, Tau, was measured for a number of temperatures in the working range of a proposed variable resistance memory (below 70 ⁰C) for NiO films made by sputtering and without including any carbon ligand. As known in the art, the slope of the Arrhenius curve 960 is proportional to the activation energy for the mechanism that is causing the relaxation. The slope found from curve 960 yields an activation energy of approximately o.47 eV. This is essentially the activation energy for detrapping of electrons from oxygen vacancies in NiO. See, "Surface Metallic Nature Caused By An In-Gap State Of Reduced NiO: A Photoemission Study", N. Nakajima et al., Journal of Electron Spectroscopy and Related Phenomena, 144 147 (2005) pp. 873-875. Thus, the variable resistance phenomenon of the prior art NiO devices is dominated by the trapping and detrapping of electrons in oxygen vacancies. FIG. 40 shows a graph of Kelvin temperature versus resistance in Ohms for the

ON and OFF states for a CEM thin film according to the invention and for a prior art thin film that crystallizes in the OFF state and requires forming before exhibiting variable resistance. As shown in the graph, for the CEM material, NiO(Cx) in this case, the ON and OFF states vary only a little with temperature over the entire 400 ⁰K temperature range. Both curves rise a little at the higher temperatures. The rise is essentially uniform for both the ON and OFF state, so the resistance window remains essentially the same. Clearly, a memory made with the CEM material will be stable over any temperature range that memories should be stable over. However, for the prior art NiO film, without carbon, the OFF state changes linearly with temperature, while the conducting state is essentially flat. The resistance window changes by more than 500%. Just over the reasonable range that a memory must work, from about 250 ⁰K to about 350 ⁰K, the memory window changes by about over 100%. This prior art material clearly could not be used in a memory.

FIG. 41 is a graph of number of reading cycles versus resistance in Ohms for the ON and OFF states for a CEM thin film according to the invention. Measurements were made at both 25 ⁰C and 85 ⁰C. Reading fatigue measures the resistance in Ohms versus number of read cycles, where a read cycle comprises the application of a read voltage of one volt across the resistance element for a sufficient time to come to equilibrium with a reference voltage, followed by the removal of the voltage for a sufficient time to come to equilibrium at zero voltage. The measurements of reading fatigue were made for both the ON state and the OFF state at 85 ⁰C and 25°C. The ON state was measured out to 1010 cycles and the OFF state was measured only to 108 cycles because of time constraints. Both curves were flat, i.e., showing essentially no change in the measured resistance values, for the 25°C measurement, and showing a minor variation of about two percent for the 85°C measurement. This graph demonstrates there is little or no fatigue for the CEM material. Thus, a memory made of CEM material will be stable over any conceivable number of read cycles. Write fatigue has not yet been measured due to time constraints, though every indication is that it also will be essentially nil.

It is a feature of the invention that the effect of oxygen vacancies is canceled in the CEMs according to the invention. The fact that the CEM materials are in the low resistance state, or ON state, as-deposited demonstrates this vacancy coordination passivation effect. The vacancy coordination sphere is the region about an ion or electron in which vacancies can effect the ion or electron. As shown by FIG, 39, vacancies within this vacancy coordination sphere trap electrons which are subsequently thermally detrapped. This destabilizes the high resistance state. This is the principle reason for the instability of prior art variable resistance materials. In the materials according to the invention, the effect of the oxygen vacancies is cancelled, by the ligand structure of the CeRAM materials according to the invention. As shown by FIGS. 10, 11 and 40, the resistance states of the CEMs according to the invention are thermally stable. This further demonstrates vacancy coordination passivation. The particular systems, memory designs, and methods described herein are intended to illustrate the functionality and versatility of the invention, but the invention should not be construed to be limited to those particular embodiments. It is evident that those skilled in the art may make numerous uses and modifications of the specific embodiments described, or equivalent structures and processes may be substituted for the structures and processed described. For example, the memory is shown with the electronic phase change elements and their associated transistors arranged in columns. The phase change elements may just as well have been arranged in rows. Thus, herein, the arrangement is referred to as a row/column arrangement. Further, while in some instances the preferred type of semiconductor wafer has been specified, it should be understood that in any of the devices described, any semiconductor can be used. Further, in many instances the specific type of semiconductor has been specified, e.g., n-type, p-type, n+, p+, etc., those skilled in the art will recognize that other types may be used. For example, most devices work essentially the same if n-type is replaced with p- type and p-type replaced with n-type. As another example, though platinum electrodes have been given as examples, those skilled in the art will recognize that such electrodes are preferably formed with a thin adhesive layer of titanium, and that the entire literature of oxide structures on platinum/titanium electrodes and the top electrode literature involving platinum, titanium, tungsten, and other materials can be applied. Any place a semiconductor is mentioned, those skilled in the art will recognize that gallium arsenide, germanium, germanium/silicon and other semiconductor technologies can be substituted. As mentioned above, the term "metal" or "M" is used herein to indicate any suitable conductor, including metals such as platinum and tungsten, or polysilicon or other conventional conductors known in the art.

Since certain changes may be made in the above systems and methods without departing from the scope of the invention, it is intended that all subject matter contained in the above description or shown in the accompanying drawings may be interpreted as illustrative and not in a limiting sense.

Claims

CLAIMS WE CLAIM:

1. An integrated circuit resistive switching component comprising:

(a) a resistive switching cell, including a correlated electron material (CEM), wherein the CEM material exhibits at least one morphological formation;

(b) a switching circuit for placing the resistive switching cell in a first resistive state and a second resistive state, wherein the resistance of the second resistive state is higher than the first resistive state.

2. The integrated circuit resistive switching component of claim 1 , wherein the CEM in the first resistive state changes to the second resistive state by increasing the voltage applied to the CEM to a set voltage.

3. The integrated circuit resistive switching component of claim 2, wherein the CEM in the second resistive state changes to the first resistive state by increasing the voltage applied to the CEM to a reset voltage.

4. The integrated circuit resistive switching component of claim 3, wherein the reset voltage is higher than the set voltage.

5. The integrated circuit resistive switching component of claim 2, wherein the CEM in the first resistive state, remains in the first resistive state if no voltage is applied to the CEM.

6. The integrated circuit resistive switching component of claim 3, wherein the CEM in the second resistive state remains in the second resistive state if no voltage is applied to the CEM.

7. The integrated circuit resistive switching component of claim 1 , further comprising:

(c) a sensing circuit for determining whether the resistive switching cell is in the first resistive state or the second resistive state and providing an electrical signal corresponding to the first resistive state or the second resistive state.

8. The integrated circuit resistive switching component of claim 7, wherein the sensing circuit determines whether the resistive switching cell is in the first resistive state or the second resistive state by applying a current to the CEM.

9. The integrated circuit resistive switching component of claim 1 , wherein the CEM material has exactly one morphological formation.

10. The integrated circuit resistive switching component of claim 1 , wherein the CEM material is formed by depositing at least one bulk layer and at least one capping layer.

11. The integrated circuit resistive switching component of claim 10, wherein the at least one bulk layer exhibits morphological formations.

12. The integrated circuit resistive switching component of claim 1 1 , wherein the morphological formations are in a vein in trench like pattern.

13. The integrated circuit resistive switching component of claim 12, wherein the trench width is 0.2 to 0.3 micrometers.

14. The integrated circuit resistive switching component of claim 12, wherein the vein to vein spacing is 0.5 to 1.5 micrometers.

15. The integrated circuit resistive switching component of claim 12, wherein the veins have a hexagonal-like packing.

16. The integrated circuit resistive switching component of claim 15, wherein the veins propagate into the interior of the hexagonal-like packing.

17. The integrated circuit resistive switching component of claim 12, wherein the veins are approximately 50 nanometers wide.

18. The integrated circuit resistive switching component of claim 12, wherein the veins resemble filamentatious carbon.

19. The integrated circuit resistive switching component of claim 10, wherein the at least one capping layer has a smooth appearance.

20. The integrated circuit resistive switching component of claim 10, wherein the at least one capping layer does not exhibit morphological formations.

21. The integrated circuit resistive switching component of claim 10, wherein the at least one bulk layer exhibits surface morphological formations.

22. The integrated circuit resistive switching component of claim 10, wherein the CEM deposition material is NiO.

23. The integrated circuit resistive switching component of claim 22, wherein at least one bulk layer and the at least one capping layer are deposited using a spin on deposition method.

24. The integrated circuit resistive switching component of claim 23, wherein a 0.2M solution is used for the bulk layer.

25. The integrated circuit resistive switching component of claim 23, wherein a 0.1 M solution is used for the capping layer.

26. The integrated circuit resistive switching component of claim 23, wherein three bulk layers are deposited.

27. The integrated circuit resistive switching component of claim 26, wherein six capping layers are deposited.

28. The integrated circuit resistive switching component of claim 1 , wherein the CEM has an area.

29. The integrated circuit resistive switching component of claim 28, wherein the CEM comprises:

(i) at least one bulk layer having numerous morphological formations over the area of the CEM;

(ii) at least one capping layer, deposited over the bulk layer, wherein the at least one capping layer has no morphological formations over the area of the CEM and wherein the at least one bulk layer is capped with sufficient layers of the at least one capping layer to result in a substrate having one morphological formation, detectable on the surface, over the area of the CEM.

30. The integrated circuit resistive switching component of claim 7, wherein the state of the resistive switching cell is capable of being determined 10⁸ times with less than 50% fatigue.

31. The integrated circuit resistive switching component of claim 1 , wherein said CEM switches resistive states due to a Mott-transition in the majority of the volume of said CEM.

32. The integrated circuit resistive switching component of claim 7, wherein said CEM comprises a material selected from the group consisting of aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium, zinc and combinations thereof.

33. The integrated circuit resistive switching component of claim 7, wherein the resistive switching cell, switching circuit, and sensing circuit function as a memory device.

34. A method of writing to a resistive switching thin film memory element, said method comprising applying an electric field or voltage to said thin film to cause the concentration of electrons, nc, in an energy band in the majority of the volume of said material to increase to or greater than a value given by (nC)1/3a = 0.26 where "a" is the Bohr radius.

35. A method of making a non-volatile integrated circuit memory, said method comprising:

(a) depositing a correlated electron material (CEM); and

(b) completing said memory to include said CEM in an active element in said memory.

36. A method of making a non-volatile integrated circuit resistive switching component, comprising:

(a) calculating an area of the resistive switching memory cell to be formed;

(b) depositing a correlated electron material (CEM), such there is a probability that a single morphological formation is formed in the area of the resistive switching memory cell.

37. The method of claim 36, wherein the depositing is accomplished using spin on techniques.

38. The method of claim 37, wherein a solution having a molarity of CEM calculated to yield a single morphological formation for the area of the resistive switching memory.

39. The method of claim 36, wherein the depositing includes depositing at least one bulk layer and at least one capping layer on top of the at least one bulk layer, wherein, the at least one bulk layer exhibits a plurality of morphological formations and the at least one capping layer exhibits no morphological formations.

40. The method of claim 39, wherein the at least one bulk layer is capped with the at least one capping layer such that the deposition yields a single morphological formation for the area of the resistive switching memory.

41. The method of claim 36, wherein the depositing is accomplished by liquid source misted chemical deposition.

42. The method of claim 36, wherein three bulk layers, each having a thickness of approximately 100 angstrom, and six capping layers, each having a thickness of approximately 50 angstroms, are deposited.

43. A method of writing to a non-volatile, resistive switching thin film memory element, said method comprising:

(a) providing a memory cell including a thin film of correlated electron material (CEM), wherein the CEM has at least one morphological formation; and

(b) applying an electric field or voltage to said thin film to cause the concentration of electrons, nC, in an energy band in the majority of the volume of said material to increase to or greater than a value given by (nC)1/3a = 0.26 where "a" is the Bohr radius.

44. An integrated circuit memory having a memory cell including:

(a) a semiconductor having a first active area, a second active area, and a channel between said active areas; and

(b) a layer of a variable resistance material (VRM) directly above said channel.

45. The integrated circuit memory of claim 44, wherein said variable resistance material comprises a correlated electron material (CEM) and wherein the CEM has at least one morphological formation.

46. An integrated circuit memory as in claim 45, wherein said memory cell further includes a first conductive layer between said VRM and said channel.

47. An integrated circuit as in claim 46 wherein said first conductive layer comprises a plurality of conductive layers.

48. An integrated circuit as in claim 45, wherein said memory cell further includes a layer of an insulating material between said VRM and said channel.

49. An integrated circuit as in claim 45, wherein said memory cell comprises a field effect transistor (FET).

50. An integrated circuit as in claim 49, wherein said memory cell comprises a JFET structure.

51. An integrated circuit as in claim 49, wherein said memory cell comprises a MESFET structure.

52. An integrated circuit as in claim 49, wherein said memory cell comprises a MOSFET structure.

53. A resistive switching memory comprising:

(a) a plurality of memory cells arranged in rows and columns, each said memory cell being a resistive switching memory cell including a resistive switching material and each of said memory cells comprising a conductor/variable resistance material/conductor (M/VRM/M) stack formed on a channel in a semiconductor, wherein said variable resistance material comprises a correlated electron material (CEM) and wherein the CEM has at least one morphological formation;

(b) a write circuit for placing selected ones of said resistive switching memory cells in a first memory cell resistive state or a second memory cell resistive state depending on information input into said memory, wherein the resistance of said material is higher in said second resistance state than in said first resistance state; and

(c) a read circuit for sensing the state of said memory cell and providing and electrical signal corresponding to the sensed state of said memory cell.

54. A memory as in claim 53 wherein each of said cells comprises a field effect transistor (FET).

55. A memory as in claim 53 wherein each of said cells comprises a JFET.

56. A method of operating an integrated circuit memory, said method comprising:

(a) providing a memory cell including a semiconductor having a first active area, a second active area, and a channel between said active areas; and

(b) controlling the conductance of said channel using a variable resistance material, wherein said variable resistance material comprises a correlated electron material (CEM) and wherein the CEM has at least one morphological formation.

57. A method as in claim 56 wherein said controlling comprises controlling a voltage across said channel or a current in said channel using said variable resistance material.

58. A method as in claim 56 and further comprising reading a voltage across said channel, a current in said channel, or a resistance in said channel.

59. A method of reading a non-volatile, variable resistance memory cell, wherein said variable resistance memory cell includes a correlated electron material (CEM) and wherein the CEM has at least one morphological formation, said method comprising:

(a) measuring the capacitance of said memory cell; and

(b) using said measured capacitance, determining the logic state of said memory cell.

60. A method as in claim 59 wherein said memory cell comprises a diode in series with said VRM and said measuring comprises measuring the capacitance of said diode in series with said VRM.

61. A method of making a non-volatile integrated circuit memory, said method comprising:

(a) depositing a variable resistance material (VRM) on a semiconductor directly above a channel in said semiconductor, wherein said variable resistance material comprises a correlated electron material (CEM) and wherein the CEM has at least one morphological formation; and

(b) completing said memory to include said VRM in an active element in said memory.

62. A method as in claim 61 wherein said depositing comprises forming a conductor/VRM/conductor stack.

63. A method as in claim 61 wherein said forming comprises forming said stack over a JFET channel.

64. A resistive switching cell, comprising:

(a) a top electrode;

(b) a bottom electrode;

(c) a variable resistance material (VRM), wherein said variable resistance material comprises a correlated electron material (CEM).

65. The resistive switching cell of claim 64, wherein the VRM falls between the top and bottom electrode.

66. The resistive switching cell of claim 64, wherein the CEM has at least one morphological formation.

67. The resistive switch cell of claim 64, wherein the CEM has exactly one morphological formation.

68. The resistive switching cell of claim 64, wherein the bottom electrode composed of tungsten and titanium nitride.

69. The resistive switching cell of claim 64, wherein the bottom electrode is composed of a first layer of titanium nitride, a layer of tungsten, and a second layer of titanium nitride.

70. The resistive switching cell of claim 69, wherein the first layer of titanium nitride is 200 angstroms thick, the layer of tungsten is 200 angstroms thick, and the second layer of titanium nitride is 200 angstroms thick.

71. The resistive switching cell of claim 64, wherein the top electrode is composed of titanium nitride and aluminum.

72. The resistive switching cell of claim 64, wherein the top electrode is composed of a first layer of titanium nitride, a layer of aluminum, and a second layer of titanium nitride.

73. The resistive switching cell of claim 72, wherein the first layer of titanium nitride is 200 angstroms thick, the layer of aluminum is 500 angstroms thick, and the second layer of titanium nitride is 200 angstroms thick.

74. The resistive switching cell of claim 70, wherein an interfacial dielectric is formed in between the bottom electrode and the VRM during annealing.

75. The resistive switching cell of claim 74, wherein the interfacial dielectric limits the active contact area between the bottom electrode and the VRM.

76. A method for forming an integrated circuit resistive switching component, the method comprising:

(a) oxidizing a silicon wafer;

(b) depositing an adhesion layer;

(c) depositing a bottom electrode;

(d) depositing a transition metal oxide (TMO);

(e) annealing the TMO;

(f) depositing a top electrode;

(g) applying a photoresist to the top electrode and TMO; and (h) etching the top electrode and TMO.

77. The method of claim 76, further comprising:

(i) depositing an inter-layer dielectric.

78. The method of claim 76, wherein the TMO is NiO.

79. The method of claim 78, wherein the TMO is formed by depositing three bulk layers of NiO using a 0.2M solution and depositing six capping layers of NiO using a 0.1 M solution.

80. The method of claim 79, wherein the bulk layers exhibit at least one morphological formation.

81. The method of claim 76, wherein the bottom electrode composed of tungsten and titanium nitride.

82. The method of claim 76, wherein the top electrode is composed of titanium nitride and aluminum.

83. The method of claim 76, further comprising:

(i) annealing the TMO.

84. The method of claim 83, wherein the annealing of (i) is at a temperature of 450 Celsius.

85. The method of claim 76, wherein the TMO is etched to an area such that there is one surface feature for said area.

86. A variable resistance material (VRM), comprising correlated electron material (CEM).

87. The VRM of claim 85, wherein the CEM has at least one morphological formation.

88. The VRM of claim 85, wherein the CEM is formed from NiO,

89. The VRM of claim 85, wherein the CEM is a transition metal oxide.

90. The VRM of claim 85, wherein the CEM is formed of three bulk layers of NiO deposited from a 0.2M solution and six capping layers of NiO deposited from a 0.1 M solution.

91. The VRM of claim 89, wherein the CEM exhibits at least one surface feature.

92. The VRM of claim 85, wherein the CEM has one surface feature per area of a device.

93. The VRM of claim 92, wherein said area is 100 square micrometers.

94. The VRM of claim 92, wherein said area is 200 square micrometers.

95. The VRM of claim 92, wherein said area is 400 square micrometers.