WO2009105095A1 - Redriver with two reference clocks and method of operation thereof - Google Patents
Redriver with two reference clocks and method of operation thereof Download PDFInfo
- Publication number
- WO2009105095A1 WO2009105095A1 PCT/US2008/054399 US2008054399W WO2009105095A1 WO 2009105095 A1 WO2009105095 A1 WO 2009105095A1 US 2008054399 W US2008054399 W US 2008054399W WO 2009105095 A1 WO2009105095 A1 WO 2009105095A1
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- WIPO (PCT)
- Prior art keywords
- redriver
- inbound
- outbound
- clock
- elastic buffer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Definitions
- One architecture that can be used to increase the storage capacity of a system with such server blades involves installation of a storage blade in proximity to the server blade.
- the server blade and the storage blade communicate through an x4 PCl-Express (PCIe) link.
- PCIe PCl-Express
- the backplane used with the blades does not support a common reference clock.
- the current x86 clock architecture implements a low cost crystal plus clock generator with multiple output frequencies, the clock source on servers as well as on server blade systems tends to have a large phase jitter.
- most chip vendors implement low cost digital CDR (clock-data-recovery) circuitry, which may not work properly in a high phase jitter environment.
- the redriver further includes an outbound elastic buffer that has the separate reference clock for an outbound elastic buffer interface between the redriver and the external component, the common reference clock for an outbound elastic buffer interface between the North-Bridge and the redriver, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound linear shift registers.
- the redriver includes dock recovery logic coupled an external component side of the redriver and to a North-Bridge side of the redriver.
- the redriver has an inbound data portion and an outbound data portion
- the redriver includes an inbound elastic buffer comprising means for adjusting inbound data to compensate for a non-common reference clock, and an outbound elastic buffer comprising means for adjusting outbound data to compensate for a non-common reference clock.
- the redriver further includes a common reference clock coupled to a first side of the redriverr, a low jitter reference clock coupled to a second side of the redriver, and clock recovery logic coupled to the first and the second sides of the redriver.
- Figures I A and IB illustrate embodiments of multiple blade architectures;
- Figure 2 illustrates frequency variations allowed with spread spectrum clocking;
- Figure 3 illustrates an embodiment of a multiple blade architecture using two reference clocks
- Figure 4 illustrates an embodiment of a two reference clock redriver architecture.
- Figure 5 illustrates an embodiment of an elastic buffer operation used with the two reference clock redriver architecture for a fast recovered clock
- Figure 6 illustrates an embodiment of an operation of the elastic buffer for a slow recovered clock
- Figures 7 - 9 illustrate alternate applications of two reference clock architectures
- Figure 10 is a flowchart illustrating an embodiment of a method for operating a computer system component having two reference clocks.
- a computer system encompasses any number of architectures including, for example, blade server systems, blade storage systems, a notebook computer and its docking station, a PCl-Express expansion system, and any other computing system that may use devices that do not have a common reference clock. Examples of such architectures are provided in Figures 4 and 7 - 9.
- a computer also encompasses a portion, or subset, of components comprising the computer system.
- reference clocks include low-grade system clocks, low jitter clocks, and clocks embedded in data streams.
- signal conditioners include signal amplifiers, redrivers, and similar devices.
- Signal conditioners may be used to adjust and correct for signal level attenuation and noise (jitter) by using equalization and pre- emphasis/de-emphasis techniques, for example, so that the receiving end has die margins needed to deliver low bit error rates with high-speed signal protocols, such as PCI- Express.
- signal conditioner On such signal conditioner is a redriver.
- Spread-spectrum clocking is used in the design of synchronous digital systems, especially those containing microprocessors, to reduce the spectral density of the electromagnetic interference (EMI) that these systems generate.
- a synchronous digital system is one that is driven by a clock signal that, because of its periodic nature, has an unavoidably narrow frequency spectrum. In fact, a perfect clock signal would have all its energy concentrated at a single frequency and its harmonics, and would therefore radiate energy with an infinite spectral density.
- Practical synchronous digital systems radiate electromagnetic energy on a number of narrow bands spread over the clock frequency and ils harmonics, resulting in a frequency spectrum thai, at cettain frequencies, can exceed the regulatory limits for electromagnetic interference.
- spread spectrum clocking is used to reshape the system ' s electromagnetic emissions to comply with the electromagnetic compatibility
- EMC Electrometic Control
- Spread-spectrum clocking distributes the energy so that it falls into a large number of the receiver's frequency bands, without putting enough energy into any one band to exceed the statutory limits.
- spread-spectrum clocking can create challenges for designers because modifying the system clock runs the risk of the clock/data misalignment.
- Spread spectrum clocking is accomplished by slowly modulating the frequency of the system clock back and forth a small amount.
- the PCI-Express Specification allows down spread spectrum clocking; that is, data rate may be modulated +0% to -0.5% from nominal data rate frequency, at a modulation rate in the range of 30Khz to 33Khz. See Figure 2.
- the PCl-Express Specification still requires the transmitter and receiver clocks to be within +/-300 ⁇ pm of each other even when spread spectrum clocking is enabled. This requirement can not be guaranteed in systems with a non- common reference clock.
- PCI-Express uses a source synchronous riming architecture.
- a source synchronous liming architecture both data and a clock are transmitted from the originating device's driver. The receiving device recovers the clock to allow synchronization of the data.
- PCl-Express uses a scheme where the forwarded clock is embedded into the data stream using [BM's 8B/10B encoding tables. This encoding mechanism ensures that the data stream will have a sufficient number of 0-to-l and 1-to-0 transitions to allow the clock to be recovered. This mechanism obviates the need to minimize skew, but creates, instead, a two-clock domain. That is, due to the allowed 600 ppm tolerance band, two devices connected to each other by a PCl-Express connection can, and most likely will, be operating at slightly different frequencies.
- a storage blade product is provided for installation next to any C-class server blade. Communication between the server blade and storage blade is through a x4 PCl-Express link.
- PCl-Express link configurations Two possible PCl- Express link configurations, direct and indirect, are shown in Figures IA and IB, respectively.
- Figure IA a half height C-class server blade IO is coupled to a storage blade 20.
- a direct link is established when PCI-Express bus 18 is connected directly from North-Bridge (NB) 14 on the server blade 10 to SAS control card 24 on the storage blade 20 by way of connections 16 and 26.
- Also shown on the cards 10 and 20 are clocks 12 and 22, respectively. Note that the clocks 12 and 22 are non-common reference clocks, a fact that can lead to system failures when spread spectrum clocking is enabled,
- a full height C-class server blade 30 is installed next to storage blade 20.
- PCl-Express bus 38 on the C-class server blade 30 is connected from the North- Bridge 14 to a redriver chip 32, and then from the redriver chip 32 to the SAS control card 24 on the storage blade 20.
- the use of the redriver chip 32 accounts for additional signal loss due to a longer trace length of the PCl-Express bus 38.
- the redriver chip 32 is mounted on a mezzanine card 34.
- the two blades 20 and 30 employ non-common reference clocks 22 and 12, respectively. To resolve the problems posed by spread spectrum clocking in server/storage blade applications, the architectures disclosed herein provide two reference clocks.
- FIG. 3 An example of such an architecture is shown in Figure 3 in which a storage blade 100 is mated to a server blade 120.
- the server blade 120 may be any type of server blade including, for example, a C-class server blade.
- the storage blade includes a PC .-Express card 24, connectors 26 and a low jitter clock 1 10.
- a low jitter clock typically has less than 100 ppm (parts per million) of phase jitter.
- low cost clocks have more than 300 ppm of phase jitter.
- With a low jitter clock not only is the phase jitter low, but also the low jitter clock is resistant to power noise modulation, and the clock frequency is very stable. Note that any blade that does not use a common reference clock cannot accommodate spread spectrum clocking.
- the server blade 120 includes North-Bridge 14, PCI-Express link 130, connectors
- the elastic buffer can experience an overflow or an underflow error condition, To eliminate these errors, the elastic buffer fill and drain rates may be adjusted,
- One means for adjusting these rates involves addition or removal of special symbols that are used in PCI- Express architectures. These symbols are known as SKP symbols, and are found in SKP ordered sets. SKP ordered sets are used to maintain synchronization between a transmitter and a receiver and to prevent overflow or underflow error conditions. The receiver can discard the SKP characters. An SKP ordered set consists of a single COM symbol followed by three SKP symbols. Other means for adjusting the fill and drain rates will be discussed later.
- the rate at which SKP ordered sets are transmitted is derived from the maximum frequency tolerance allowed between two devices, namely 600 ppm. At this level, the local clocks of the two devices shift one clock cycle every 1 ,666 cycles Therefore, the transmitter must schedule a SKP ordered set to be sent more frequently than every 1,666 clock cycles.
- the PO-Express Specification defines the period between SKP ordered set transmissions as between 1,180 and 1,538 symbol times.
- the storage blade side of the redriver 200 uses a separate low jitter clock 210.
- the low jitter reference clock 210 does not use spread spectrum clocking.
- the storage blade 100 also uses a separate low jitter reference clock 1 10. which also does not allow for spread spectrum clocking
- the reference clocks 1 10, 140, and 210 have standard 100 MHz clock sources, which are used as inputs to phase locked loops (PLLs) to generate higher frequency clocks for internal logics and COR (Clock Data Recovery)
- PLLs phase locked loops
- COR Lock Data Recovery
- PLl., 145 may convert the 100 MHz clock to 2.5 GHz.
- Data 160 from the storage blade 100 enters the inbound elastic buffer 220 at a nominal 2.5 GHz and data 165 exiting the inbound elastic butter 220 exits at a nominal
- Local clock A signal 145 which is derived from the output of PLL 142 based on the common reference clock. Local clock A signal 145 also is used to clock data out of inbound elastic buffer 220
- FIG 5 illustrates an embodiment of an elastic buffer operation used with the redriver 200 of Figure 4 for a fast recovered clock.
- Elastic buffer 220 receives an inbound data stream and provides a modified inbound data stream.
- the elastic buffer 220 may be operated such that it is normally half full, or just below trip point A.
- buffer logic within the elastic buffer 220 first removes idle data from the inbound data stream if the PCI-Express link is in the active state (i.e., if the link has been powered up and passed the link training states).
- PCl Express is designed such that the information contained in each DLLP is also contained in subsequent DLLPs of the .same type, so that a DLLP that is corrupted or lost in transit has a minimal effect on link performance. If multiple successive DlJ.. Ps of the same type are lost, however, performance degradation will occur (it can cause transaction replay and/or inhibit the issuance of new transactions).
- DLLPs begin with an unscrambled 11 SDP" framing symbol followed by a DLLP Type byte.
- the buffer logic within the elastic buffer 220 may be designed to remove four DLLP types in particular: Acknowledges. Posted Credit Updates, Non-posted Credit Updates, and Completion Credit Updates.
- the herein described flexible buffers use semaphores to prevent deletion of multiple DLLPs of the same type. For example, a fast recovered clock may cause the buffer logic to discard a Posted Credit Update DLLP. When this occurs, an internal Posted Credit Update semaphore is set to prevent the logic from discarding another Posted Credit Update until another Posted Credit Update (of the same virtual channel) passes through. The second Update contains the same number of credits as the previous packet plus it may contain additional credits. Passing the second packet through removes a potential bottleneck in outbound, posted cycles. Finally, should the contents of elastic buffer 220 reach trip point C, the buffer logic discards a Transaction Layer Packet (TLP) from the inbound data stream.
- TLP Transaction Layer Packet
- the buffer logic accomplishes this by looking for the TLP start framing symbol (STP), and discarding every symbol until it detects the HND symbol. This will cause the transmitter to replay the TLP. either due to a Negative Acknowledge (Nak) of a subsequent TLP or due to an Acknowledge (Ack) timeout.
- the sequence number for the removed TLP is stored in local register for comparison to future outbound Ack packets.
- TLP disposal logic resets itself for the next time the elastic buffer fills beyond trip point C. This prevents excessive TLP replays, which can seriously hamper link performance.
- the buffer logic associated with a typical elastic buffer such as the elastic buffer associated with components upstream and downstream of the elastic buffer 220, adds SKP symbols to the buffer contents.
- the buffer logic associated with the elastic buffer 220 adds a SKP ordered set to the data stream. Note that since the redriver 200 is an intermediate buffer and not the final receiver on the link, the redriver 200 must not alter the size of the SKP ordered set. However, in some cases, even the addition of SKP symbols is not enough to prevent emptying the elastic buffer
- the redriver 200 includes typical PCI Express components such as a 10/8b decoder 221, descrambler 222, linear feedback shift register (LSFR.) 223, SKP/idle insertion module 225, scrambler 226, 8b/10b encoder 227, and outbound linear feedback shift register (LSFR) 229 as shown in Figure 6.
- the decoder 221 converts the 10-bit inbound symbols to 8-bit bytes
- the descrambler 222 uses the LSFR 223 to convert the bytes to unscrambled bytes. At this point the data stream can be analyzed for the aforementioned framing symbols.
- FIG. 5 and 6 illustrate operation of (he inbound elastic buffer 220.
- the inbound elastic buffer 220 is a two reference clock elastic buffer architecture.
- the outbound elastic buffer 240 also is a two reference clock architected butter, and the architecture and method for preventing overflow and underflow of the outbound elastic buffer 240 is similar in all pertinent respects to the architecture and method applicable to the inbound elastic buffer 220.
- Figures 7 - 9 illustrate embodiments of computer systems employing redrivers to ensure signal continuity and fidelity across multiple connections and vary ing-length trace lengths.
- Figure 10 is a flowchart illustrating an embodiment of a method 500 for operating a computer system, such as the computer system of Figure 3, having a two reference clock architecture.
- the redriver 200 receives an inbound data stream (inbound in the sense that the data stream emanates from storage blade 100), the inbound data stream having a recovered clock.
- buffer logic associated with inbound elastic buffer 220 notes the recovered clock
- the inbound elastic buffer 220 determines if the recovered clock is fast relative to the system clock 140. If the recovered clock is fast, the method 500 moves to block 515 and the link is checked to see if the link is active. If the link is active, the method 500 moves to block
- the method 500 moves to block 516 to determine if the link is in the "Configuration. Idle" training sub-state. If the link is not in "Configuration. Idle”, then in block 518, the buffer logic associated with the buffer 220 removes a training ordered set. [f the link is in the "Configuration.Idle” sub-state, the method 500 moves to block 517 and the buffer logic associated with the inbound buffer 220 removes idle data from the inbound data stream. At this point the logic forwards inbound data to NB (block 560), Following blocks 517 or 518 the method 500 moves to block 560. In block 520, the buffer logic associated with the inbound buffer 220 determines if the recovered clock still is too fast.
- the method 500 moves to block 525 and the buffer logic removes a DLLP symbol and sets a corresponding semaphore The method 500 then moves to block 530 3n block 530. the buffer logic again determines if the recovered clock is too fast. If the recovered clock still is too fast, then in block 535, the butter logic removes a TLP packet from the data stream and sets a TLP semaphore The method then moves to block 560.
- the method 500 moves to block 560 Returning to block 520. if the recovered clock is not too fast, the method 500 moves to block 560.
- the method 500 moves to block 540 and the buffer logic associated with the inbound flexible buffer 220 determines if the recovered clock is too slow. If the recovered clock is not too slow, the method 500 moves to block 560. If the recovered clock is too slow, the method 500 moves to block 545 and the link is checked to see if the link is active. If the link is active, the method 500 moves to block 546 and idle data are added to the inbound data stream If the link is not active, then in block 547 the buffer logic adds SKP symbols to the inbound data stream.
- the method then moves to block 550 and the buffer logic again checks to see if the recovered clock is too slow If the recovered clock still is too slow, the method 500 moves to block 555 and the buffer logic adds idle data to the inbound data stream The method then moves to block 560 and the inbound data stream is passed to the North- Bridge 14.
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2008/054399 WO2009105095A1 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
CN200880127260.8A CN101946219B (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
KR1020107018505A KR101419292B1 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
US12/918,050 US8166334B2 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
EP08730240.2A EP2255263B1 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
JP2010547602A JP5138050B2 (en) | 2008-02-20 | 2008-02-20 | Redriver having two reference clocks and operation method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/US2008/054399 WO2009105095A1 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
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WO2009105095A1 true WO2009105095A1 (en) | 2009-08-27 |
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PCT/US2008/054399 WO2009105095A1 (en) | 2008-02-20 | 2008-02-20 | Redriver with two reference clocks and method of operation thereof |
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US (1) | US8166334B2 (en) |
EP (1) | EP2255263B1 (en) |
JP (1) | JP5138050B2 (en) |
KR (1) | KR101419292B1 (en) |
CN (1) | CN101946219B (en) |
WO (1) | WO2009105095A1 (en) |
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- 2008-02-20 US US12/918,050 patent/US8166334B2/en active Active
- 2008-02-20 WO PCT/US2008/054399 patent/WO2009105095A1/en active Application Filing
- 2008-02-20 JP JP2010547602A patent/JP5138050B2/en not_active Expired - Fee Related
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JP2011138472A (en) * | 2009-12-31 | 2011-07-14 | Via Technologies Inc | Serial bus device and clock difference compensation method |
JP2011186968A (en) * | 2010-03-11 | 2011-09-22 | Ricoh Co Ltd | Adaptor, information device, information system and communication method |
US8938567B2 (en) | 2010-03-11 | 2015-01-20 | Ricoh Company, Limited | Communication apparatus, communication system and adapter |
US9361249B2 (en) | 2010-03-11 | 2016-06-07 | Ricoh Company, Ltd. | Communication apparatus, communication system and adapter |
JP2012128717A (en) * | 2010-12-16 | 2012-07-05 | Ricoh Co Ltd | Communication apparatus and communication system |
Also Published As
Publication number | Publication date |
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EP2255263A4 (en) | 2011-08-31 |
JP5138050B2 (en) | 2013-02-06 |
KR101419292B1 (en) | 2014-07-14 |
KR20100123836A (en) | 2010-11-25 |
EP2255263A1 (en) | 2010-12-01 |
EP2255263B1 (en) | 2013-07-31 |
US20100315135A1 (en) | 2010-12-16 |
US8166334B2 (en) | 2012-04-24 |
CN101946219B (en) | 2013-03-20 |
CN101946219A (en) | 2011-01-12 |
JP2011519077A (en) | 2011-06-30 |
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