WO2009103723A1 - Method for channel encoding, method and apparatus for channel decoding - Google Patents

Abstract

A channel encoding method is disclosed, which comprises dk-encoding and NRZI precoding, the output of which obeys a repeated minimum transition runlength constraint and is FSM decodable with a given lookahead depth. Occurrences of RMTR violating critical bit sequences are replaced by same length replacement sequences containing extended zero runs; and the FSM decodability with a given lookahead depth is achieved by using only those replacement sequences that are decodable with the given lookahead depth. A pertaining FSM channel decoding method and channel decoding apparatus, as well as using the FSM in trellis decoding, are disclosed.

Description

Method for channel encoding, method and apparatus for channel decoding

FIELD OF THE INVENTION

The present invention relates to data detection and channel encoding and decoding for partial response channels, for example to channel encoding and decoding digital data under a run- length-limited code with a Repeated Minimum Transition Runlength constraint .

BACKGROUND OF THE INVENTION

For high density optical storage, a so-called (1,7) RLL code having parity preservation and prohibiting certain RMTRs, also known as "17PP" code, is known and is being used. In this, "RLL" stands for "runlength limited", and the nomenclature " (1,7)" is a specific instance of a general, widely used nomenclature, according to which a code is termed to be " (d, k) runlength limited". The notation " (1,7) RLL" then denotes, that the code obeys a lower runlength limit of d=l and an upper runlength limit of k=7. This means that in a sequence of code bits generated according to such a code, consecutive bits having a first binary value are separated by at least 1 and at most 7 consecutive bits having the other binary value. After a widely used NRZI modulation step, denoting a Non-Return-to-Zero- Inverted modulation, this amounts to an output bit sequence which changes its polarity after between 2 and 8 basic time intervals T. "RMTR" stands for "Repeated Minimum Transition

Run", and "pp" stands for "Parity preserve / Prohibit repeated minimum-transition run". The code is of code rate 2/3, signifying that for every 2 bits of payload, 3 code bits are generated.

For the 17PP code, a decoder structured as a Finite State Machine or FSM, and having 21 states and 79 state transitions also called "branches" has been described in: MIYAUCHI et al Soft-Output Decoding of 17 Parity Preserve/Prohibit Repeated Minimum Transition Runlength (PP) Code. Japanese Journal of Applied Physics. 2004, VoI 43 No 7B, pages 4882-4883. Finite state machine decoders for binary data receive code bits in groups or tuples of a first length, and produce therefrom data bits in groups or tuples of a second length smaller than the first length. In an example FSM decoder, according to the above mentioned code rate, code tuples have a length of 3, and data tuples have a length of 2. The Miyauchi decoder can be seen to have the disadvantage of having a large number of states and state transitions corresponding to a complicated structure and a big implementation effort.

US 4337458 A describes a (1,7) RLL channel code and a pertaining FSM decoder having a markedly smaller number of 6 states and 24 state transitions. However, this code does not obey any RMTR- limitation. Depending on the data being coded, it may produce minimum transition runs of arbitrary, unlimited length. With d=l, the minimum transition run is "10", so that the repeated minimum transition run becomes (..,1,0,1,0, ...) . Also, the decoder of US 4337458 A is not usable on RMTR-limitation obeying codes .

European Patent Application EP 1 988 636 Al, which was unpublished at the priority date of this application, describes a channel encoding method and apparatus, where a known (d, kl) RLL encoding is combined with a separate postprocessing which achieves compliance with a RMTR constraint. The postprocessing does so by substituting instances of a predefined forbidden sequence, which would violate the RMTR constraint, by individual replacement sequences containing a runlength outside the internal upper runlength limit kl but within an upper runlength limit k>kl . The individual replacement sequences are selected from a set of two predefined replacement sequences.

The encoding method of EP 1 988 636 Al can be seen to have the drawback, that the bitstreams generated from that method are such, that for decoding any code tuple therefrom, the next two code tuples have also to be known. With other words, decoding the code bit sequences produced by the method of EP 1 988 636 Al has a delay of two code tuples, because some code bit sequences are not decodable with a lookahead of only one code tuple. With other words, the maximum lookahead depth needed for decoding data that have been coded according to EP 1 988 636 Al is two code tuples . This can be seen as a drawback of a more complicated decoder structure and implementation effort.

In a typical known read channel of storage systems, first a so- called PR or partial response equalizer is employed which shapes the inter-symbol-interference in such a way that the physical channel in series with the equalizer together behave like the so-called PR target. The PR target is an FIR filter that models the storage channel. Using the PR equalizer output, data detection is then carried out e.g. by means of a Viterbi detector which has a trellis structure matched to the PR target. In the Viterbi trellis, the minimum run-length constraint of an assumedly underlying RLL code is taken into account. After Viterbi data detection, RLL decoding is performed. Another known read channel structure interprets the effects of the processing steps RLL encoding, non-return-to-zero precoding, and PR channel as one single finite state machine (FSM) , and uses this state machine in a trellis decoder. This amounts to jointly performing data detection and RLL decoding. Obviously, the latter approach is the optimal solution, but it typically is of a higher complexity than the former approach.

An example for joint data detection and RLL decoding has been investigated for the 17PP modulation code employed in Blu-ray disc standards, see "Application of turbo codes to high-density optical disc storage using 17PP codes", JJAP, vol. 44, pp. 3471- 3473. However, the Finite State Machine derived there has 32 states and 118 branches for PR channels with channel order 3, which is of quite high computational complexity.

INVENTION

It is an aspect of this invention to provide a channel encoding method the output of which is runlength limited, RMTR- limitation-obeying and low complexity FSM decodable with a lookahead of one code tuple.

It is an aspect of this invention to provide a low complexity FSM-based decoding method and decoding apparatus for the runlength limited and RMTR-limitation-obeying channel code.

It is an aspect of this invention to provide a channel code which allows for DC control. Aspects of the invention are achieved by the features in the independent claims, further developments and variants are achieved by the features in the dependent claims.

It is one embodiment of encoding according to the invention to perform a conventional (d,k) runlength encoding step and to followit by a separate replacement step as described above. Equivalently it is another embodiment of encoding according to the invention to directly provide the bitstream that results from the then merely conceptual steps of (d,k) runlength encoding and subsequent replacement .

It is an aspect of the invention, that digital data are channel decoded by steps of, when a current state and a received code triplet are as listed in one of the lines of the Decoding Table (code according to this invention) , outputting a data duplet and transiting to a next state as listed in that line of the Decoding Table.

It is an aspect of the invention, that an apparatus for channel decoding digital data has 9 states and 30 state transitions and is equipped and configured to perform a decoding method according to the invention. The apparatus allows to decode data that have been coded using an RMTR-limitation-obeying code.

It is an aspect of the invention to have recognized that among the two predefined replacement sequences generically proposed by EP 1 988 636 Al, one replacement sequence, when used, causes the resulting output bitstream to need a decoding lookahead of more than one code triplet. This effect occurs in two of the three cases that must be distinguished according to where in the grid of code triplets the replacement takes place. Not using those replacement sequences that would need a two code triplet lookahead, achieves that the coded bitstream is decodable witha one code triplet lookahead. This directly leads to a small and compact decoder structure. Another advantageous and astonishing fact is, that for one of the above mentioned three cases, both replacement sequences are decodable with a lookahead of one code triplet, so that for this case, a degree of freedom remains: suitably choosing one or the other of the two predefined replacement sequences enables that the DC content or low frequency content of the resulting bitstream is influenced into a desired direction.

In an advantageous extension, this invention also provides a Finite State Machine which enables that, on data encoded with the code of this invention, simultaneous data detection and RLL decoding is performed. For this, the RLL encoder, the NRZI- mapper, and the PR channel of a storage channel are all together regarded as a single equivalent RLL-NRZI-PR Finite State Machine, which may be obtained by extending an encoder/decoder FSM of the RLL code. A low-complexity RLL-NRZI-PR FSM is disclosed for the (1,9) -RLL code of the invention. In this, low complexity refers to the number of states and branches in the corresponding trellis representation. The disclosed combined FSM makes it possible that detectors based on Viterbi, Max-Log-MAP, or SOVA algorithms are used.

DRAWINGS

Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description .

In the Figures : Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention;

Fig. 2 shows the state diagram of a Finite State Machine decoder for a known channel code. Fig. 3 shows the system model in the presence of an RLL encoder .

EXEMPLARY EMBODIMENTS

Data storage, as a transformation of signals in time, is modelled as a bandlimited channel, and for digital signal readout in particular, the bit clock is commonly regenerated from the read out signal. Both facts are reasons that Run-Length Limited channel codes also known as RLL codes are widely used on digital storage media. All through the following, we assume binary data consisting of bits having values selected from the two binary values "0" and "1". In a first conversion step, RLL channel codes convert any sequence of arbitrary payload words into a sequence of channel words that has at least a minimum number d and at most a maximum number k of "0" valued bits between consecutive "1" valued bits; in a shorthand notation, such codes are also known as " (d,k) codes", accordingly. After the conversion step, a transcoding or precoding step takes place, where the sequence of channel words from the first step is converted to an output signal or output sequence where each of the "l"s in the sequence of channel words causes a change in the output signal. With other words, whenever the sequence of channel words contains a "1", the output sequence, depending on which binary value it currently has, will change either from "0" to "1", or from "1" to "0". Where the sequence of channel words contains a "0", the output sequence maintains and repeats its current value unchanged. In optical storage, changes of the output sequence correspond to transitions between "pit" and "space". In magnetical recording, changes are for instance between a "plus" and a "minus" magnetical orientation. The transcoding step is also known as NRZI coding. For reasons of mathematical tractability, the output values of the NRZI decoding are typically considered to be xe{-l,+l}.

Regardless of the recording technology, the limitations on the distance of the "l"s in the sequence of channel words before NRZI coding translate into the physically homogeneous regions between consecutive state changes on a storage track being of a length that is upper and lower limited to the (d÷l)-fold and the (k÷l)-fold, respectively, of a basic length unit often called

In recent high density storage, it has been found as vital that codes additionally obey another constraint: It is forbidden, with other words it must not occur in the channel coded bitstream, that too many runs of the minimum allowed length (d+1) are immediately consecutive. This is known as a Repeated Minimum Transition Runlength or RMTR constraint, and if demanded for a storage channel, must be obeyed by any channel encoding method or apparatus to be used thereon. RMTR constrained RLL channel codes are used in recent high-density optical storage media, like blue laser optical discs. Same as the lower runlength limitation itself, the RMTR constraint aims at reducing the high frequency portions of the channel signal.

For various reasons connected to signal regeneration on the storage readout side, it is important that the output signal being written onto the medium is "DC free", with other words, that, at least on average, this signal contains as much of "pit" as of "space", or as much of "plus" as of "minus" in the magnetic case. As a criterion to measure this desirable property, the Running Digital Sum or RDS is used. In the domain of the symmetrically valued output values e{-l,+l} given after NRZI coding, the RDS corresponds to the time integral or sum taken from some start time tO up to a current time t. Alternatively, the RDS is derived before the NRZI precoder, i.e. in the domain of the dk-encoded data. This amounts to sequentially using the runs of "0"s between the isolated "l"s to alternatively count up and down in an up-down-counter. In addition to the RDS itself, its variation is also used as a criterion whether a code is DC-free. This variation is often designated as Digital Sum Variation or DSV and defined as DSV=max (RDS) -min (RDS) +1.

In a digital data storage system, Error Correcting Coding also denoted as ECC is typically used: Incoming data to be stored are being ECC encoded prior to being channel encoded; and correspondingly, the read back signal from the storage medium is channel decoded and then ECC decoded, in sequence . Among the many ECC decoding approaches, so-called "soft input" algorithms like those known in the art as "BCJR", "Max-Log-MAP" or "SOVA" are known to be particularly powerful, but they require a reliability or confidence information about the channel decoded symbols entering them. An important property of channel codes is whether or not they are decodable with a Finite State Machine FSM; also termed the code's "FSM decodability" . Having an FSM decodable channel code is a prerequisite for using soft output channel decoding methods, which in turn provide the sought reliability information for subsequent soft decision ECC decoding, or for a soft decision joint channel and ECC decoding. In these decoding methods, which are trellis based, the state transition structure of the decoding FSM is used as a trellis.

In Finite State Machine decoding, an internal state of the decoder takes into account a current tuple of code bits, also termed a current code symbol, together with some more, subsequent code bits. In this, the number of code bits that are needed in addition to the code bits of the current code symbol, is also termed the lookahead depth of the FSM decoder. As an example, a channel code that is FSM decodable with a lookahead depth of 3 code bits means that, for determining the current state of the decoder, the code bits of the current code symbol together with 3 more, subsequent code bits from the code bit sequence are needed.

Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention. It can best be understood by comparing it with a counterpart of a known code.

Fig. 2 shows the state diagram of a Finite State Machine decoder for the known (1,7) RLL channel code of US 4337458 A. The code is described by its encoding rule, namely by a basic coding table and a substitution coding table. Both tables describe the transformation of certain data words - in this case data duplets comprising two bits - into code words - in this case code triplets comprising three bits. In the basic coding table, code triplets starting with a "1", as well as code triplets ending with a "1" both exist. Therefore, if just the basic coding table were applied straightforwardly, some pairs of consecutive data duplets would be transformed into consecutive code triplets where a triplet ending in a "1" is followed by a triplet starting with a "1", which would be in violation of the minimum runlength limitation d=l of the code. In order to avoid this violation, the substitution coding table is used for those cases where the next two data duplets have one of the values listed therein. The basic coding table together with the substitution coding table completely describe the code of US 4337458 A, the code is encodable with a lookahead of two data bits. The code is also decodable with a lookahead of one code triplet comprising three code bits.

Basic coding table Substitution coding table Data Code Data Code

00 101 00.00 101.000

01 100 00.01 100.000 10 001 10.00 001.000 11 010 10.01 010.000

With respect to the basic coding table and the substitution coding table, a widely followed notational convention is used here, in that a dot "." is written in the middle of data duplet pairs and code triplet pairs to denote those cases where a substitution according to the substitution coding table has occurred. This eases reading longer strings of data bits or code bits, because it intuitively illustrates the positions where substitutions apply or have been applied. As an example, the encoding of a data bit string of "00 00 00" when written as

"00.00 00" -> "101.000 101" indicates that it was the first pair of "00" duplets, and not the second one, where substitution has been applied.

The state diagram of Fig. 2 is presented in a modified Mealy automaton style. Six balloons Sl, S2, S3, S4, S5, S6 symbolise the states of the decoder, and the arrows joining them correspond to the state transitions that can regularly occur in (1,7) RLL coded sequences. A decoder output, i.e. a recognised data duplet, is associated to every state transition and is accordingly written at or near each arrow. In normal Mealy style, a decoder input, i.e. a code triplet, would also be associated to every state transition and ascribed to the arrows. But the FSM decoder of Fig. 2 has the special property that, for each specific state, all state transitions ending in that state relate to the same decoder input. This enables, that a simplified notion is used in Fig. 2, where the decoder input is ascribed to the states instead of to the state transitions. With this understanding, the diagram of Fig. 2 illustrates the decoding of any regular sequence of code triplets: A path as dictated by the code triplets in received order is being traversed in the diagram, and the output duplets of the branches thus traversed are being output sequentially.

The decoding as represented by the state diagram of Fig. 2 is equivalently described by the following decoding table, which lists, in its 24 table line entries, 24 combinations of a current state, the received code triplet, the next state, and the decoded data duplet. Each of these combinations represents one branch in the state diagram. In the decoding table the combinations are grouped and ordered by their current state and ordered by their code triplet.

Table 1: Decoding Table (prior art code)

Current code next data state triplet state duplet

Sl 001 S4 00

Sl 010 S6 00

Sl 100 S5 00

Sl 101 S3 00

S2 001 S4 01

S2 010 S6 01

S2 100 S5 01

S2 101 S3 01

S3 000 Sl 00

S3 001 S4 00

S3 010 S6 00

S4 000 Sl 10

S4 001 S4 10

S4 010 S6 10

S5 000 S2 00

S5 001 S4 01

S5 010 S6 01

S5 100 S5 01

S5 101 S3 01

S6 000 S2 10

S6 001 S4 11

S6 010 S6 11

S6 100 S5 11

S6 101 S3 11

Application of the coding tables above shows that, with the

(1,7) RLL channel code of US 4337458 A, a data sequence "11 00 11 00 11 00 11 ..." is coded into a repeated minimum transition run or RMTR of "010 101 010 101 010 ..." of potentially unlimited length. This illustrates that the code of US 4337458 A does not obey any RMTR limitation, the data sequence in question will be termed "critical bit sequence" in the following.

It is an aspect of the present invention, that channel encoding comprises runlength encoding user data into an interim bitstream, and subsequently searching and replacing RMTR patterns in the interim bitstream. The overall result of runlength encoding and replacing amounts to a modified channel code which does obey an RMTR limitation. Specifically, the interim bitstream is sequentially scanned for occurrences of a code bit sequence "101010101010" or its inverse, which constitutes a sixfold RMTR, and all found occurrences are replaced by a replacement sequence that has the same length as the RMTR pattern being replaced. The replacement sequence contains a zero run of a length larger than the maximum runlength of the runlength encoding step, which will translate into a corresponding run after NRZI modulation. For the case of RMTR=5, depending on the position of the sixfold RMTR sequence within the grid of code triplets, three cases with some replacement options have to be distinguished.

The first case is given when a data duplet of "10", translating to a code triplet of "001", precedes the sixfold RMTR sequence:

10 11 00 11 00 IX ... data

001 010 101 010 101 0?? ... (1,7) RLL code bit sequence

In this, "X" stands for a data bit having any value, i.e. "0" or "1". According to the basic coding table and the substitution coding table, a data duplet "IX" translates into code triplets "001" or "010", together symbolised here by "0??". The resulting sequence of 18 code bits exhibits a forbidden RMTR: Starting at the 3rd bit of the 1st code triplet, it contains at least 6 consecutive instances of a single "0" surrounded on both sides by "1", which is the characteristic of a short homogenious region after NRZI. For eliminating the RMTR from the code bit sequence, a first replacement sequence of

"001 000 000 000 101 OXX" is used. In this, the range of changed triplets is highlighted by underlining. The replacement introduces a run of 9 consecutive "0"s. The bit sequence resulting from the replacement is decodable with a lookahead of 3 code bits.

The second case is given when a code triplet of "XXO", i.e. a code triplet that ends in a "0", precedes the sixfold RMTR sequence that results from the data duplets "11 00 ...". Such a code triplet results when the basic coding table is being applied to data duplets "01" or "11"; it also results as the second code triplet when the substitution code table is being applied to any of the data duplet pairs contained therein. The notion of the data duplet being indicated as "??", together with the code triplet being indicated as "XXO" shall symbolise these cases .

?? 11 00 11 00 11 ... data

XXO 010 101 010 101 010 ... (1,7) RLL code bit sequence

Here, a fourth replacement sequence "XXO 010 100 000 000 010" is used. As above, underlining highlights the exchanged parts. The bit sequence resulting from the replacement is decodable with a lookahead of 3 code bits.

The third case is given when a code triplet of "X00", i.e. a code triplet ending in "00", precedes the sixfold RMTR sequence that results from the data duplets "00 11 ...": 0? 00 11 00 11 0? ... data

XOO 101 010 101 010 1OX ... (1,7) RLL code bit sequence

Here, two replacement sequences eliminating the forbidden RMTR exist, namely a fifth replacement sequence

"XOO 100 000 000 010 10X" and a sixth replacement sequence "XOO 101 000 000 000 10X". It is important to note, that in this third case, both replacement sequences can be decoded with a lookahead of 3 code bits, so that selectively using either the fifth or the sixth replacement sequence allows to control the DC content of the code bit sequence. That the fifth and sixth replacement sequence have a different influence on the DC content can most easily be illustrated if one keeps in mind the NRZI precoding which is the next processing step performed on these bit sequences. Specifically, every "1" in the replacement output causes the polarity of the NRZI output to toggle. Noting, that the long run of zeroes in the fifth replacement sequence appears after a single preceding "1", whereas in the sixth replacement seqeuence it appears after two preceding "l"s, it is easy to see that, after an arbitrarily selected initial polarity of the NRZI output signal, the output of NRZI precoding the fifth replacement sequence and the output of NRZI precoding the sixth replacement sequence will have the particularly long run at opposing polarities. Hence, by chosing the fifth/sixth replacement sequence, the DC content can be either increased or decreased at will.

An important finding of the invention is, that even though only such replacement sequences are used, which are FSM decodable with a lookahead of three code bits, in the third case two alternatively usable replacement sequences exist. Selecting from these two possible replacement sequences constitutes a degree of freedom of the encoding process, which allows to perform a DC control of the resulting coded bitstream. With other words, by suitably selecting, whenever the third case is given, either the fifth or the sixth replacement sequence, the long term average of the outputted coded bit sequence can be influenced into a desired direction. This average corresponds to the low frequency content of the stored data signal. Having a small low frequency content is important for avoiding difficulties for any control loops of the storage system or transmission channel. These control loops may encompass focus or tracking or clock regeneration .

Other configurations of data preceding the sixfold RMTR sequence either can not occur as a regular output of the encoding as defined by the two coding tables, or are equivalent to one of the three cases considered above.

Fig. 1 shows the state diagram of a Finite State Machine decoder according to the invention, shown in the same style as used in Fig. 2. Compared to the state diagram of Fig. 2, three additional states S7, S8, S9 exist, along with a total of 30 branches. Decoding the above mentioned first replacement sequence amounts to transiting the state sequence S4, Sl, S7, S9, S3, S6 in that order. Decoding the above mentioned fourth replacement sequence amounts to transiting the state sequence S6, S6, S5, S2, S8, S6 in that order. For the above mentioned fifth replacement sequence, in case the leading X is "0", the decoding amounts to transiting the state sequence S2, S5, S2, S8, S6, S3 in that order. In case the leading X is "1", the decoding amounts to transiting the state sequence S5, S5, S2, S8, S6, S3 in that order. For the above mentioned sixth replacement sequence, in case the leading X is "0", the decoding amounts to transiting the state sequence S2, S3, Sl, S7, S9, S3 in that order. In case the leading X is "1", the decoding amounts to transiting the state sequence S5, S3, Sl, S7, S9, S3 in that order.

The state diagram of the code according to the invention, shown in Fig. 1, corresponds to the following decoding table:

Decoding Table (code according to this invention)

Current code next data state triplet state duplet

Sl 000 S7 11

Sl 001 S4 00

Sl 010 S6 00

Sl 100 S5 00

Sl 101 S3 00

S2 000 sδ 11

S2 001 S4 01

S2 010 S6 01

S2 100 S5 01

S2 101 S3 01

S3 000 Sl 00

S3 001 S4 00

S3 010 S6 00

S4 000 Sl 10

S4 001 S4 10

S4 010 S6 10

S5 000 S2 00

S5 001 S4 01

S5 010 S6 01

S5 100 S5 01

S5 101 S3 01

S6 000 S2 10

S6 001 S4 11

S6 010 S6 11

S6 100 S5 11

S6 101 S3 11 Decoding Table (code according to this invention, continued)

Current code next data state triplet state duplet

S7 000 S9 00 sδ 010 S6 00

S9 100 S5 11 S9 101 S3 11

In the decoding table above, the modifications and extensions due to the 3 new states S7, S8, S9 are emphasized in bold typeface .

With other words, a channel encoding method is disclosed, which comprises dk-encoding and NRZI precoding, the output of which obeys a repeated minimum transition runlength constraint and is FSM decodable with a given lookahead depth. Occurrences of RMTR violating critical bit sequences are replaced by same length replacement sequences containing extended zero runs; and the FSM decodability with the given lookahead depth is achieved by using only those replacement sequences that are decodable with the given lookahead depth. A pertaining FSM channel decoding method and channel decoding apparatus are disclosed.

In the following, it is described how, for the code of this invention, a combined FSM can be derived, which then enables trellis decoding.

With the (1,9) -RLL code of rate 2/3 of this invention, the maximum number of repeated minimum transition runlengths (RMTRs) in the coded data sequence is limited to 5. This RLL code is FSM-decodable, i.e., the decoding can be accomplished by means of a finite-state machine. In the following, s [n] denotes states of the FSM, u[n] denotes infowords, and c[n] denotes codewords. The following Table 2 illustrates state transitions in the decoder FSM. Except for using the new notation and employing an encoding point of view, it corresponds to the "Decoding Table (code according to this invention) " given above.

Table 2: State transition table for the (1,9) -RLL decoder of this invention An important feature of this (1,9) -RLL decoder FSM is that for each of the states designated as "previous state", the RLL codebits are identical for all upcoming state transitions. This fact can be exploited for the construction of an RLL-NRZI-PR FSM. It means with other words, that the "current RLL codebits" to be output can be decided as soon as a state is being entered as the "previous state", whereas for determining the "current state" to be transitioned to, not only the "previous state", but also the "current infobits" must be taken into account.

To facilitate the discussion, Fig. 1 shows the system model for a typical storage system in the presence of an RLL encoder. The RLL encoder of rate 2/3 has u[n] = [ul[n], u2 [n] ] as infoword and a[n] = [al[n], a2 [n] , a3[n] ] as codeword, as used in Table 2. Corresponding to u[n] or a[n], data symbols after NRZI are x[n]=[xl[n] , x2[n], x3[n] ] .

If k and x[k] denote a bit time index and the output symbol from the NRZI mapper at the time index k, respectively, then xl[n]=x[3n], x2 [n] =x [3n+l ] , x3 [n] =x [3n+2] . Note that, given x3 [n-1] =x [3n-l] serving as phase reference, and given the current codeword a[n] = [al[n], a2[n], a3 [n] ] , three data symbols after NRZI can be obtained as xl [n] =x3 [n-1] al [n] , x2[n]=x3[n- 1] al [n] a2 [n] , x3 [n] =x3 [n-1] al [n] a2[n]a3[n] . In this, data symbols x[k], a[k] are assumed to take values +1 or -1. In the following, the mapping 0 -> +1, 1 -> -1 is assumed, and {0, 1} and {+1, -1} are used interchangeably, which should be clear from the context .

According to Fig. 1, each infoword u[n] will generate three channel output bits, namely, z[n]=[z[3n], z[3n+l], z[3n+2] ] . Referring the output of the PR channel at time index k as z [k] , and denoting as hθ, hi, ..., hL the coefficients of the PR channel of memory length L, the channel output bits z [k] result as z [k] =hθx [k] +hlx [k-1] +...+hLx [k-L] . An important aspect of this is, that each channel output depends on L+l data symbols after NRZI. Therefore, three channel outputs z[3n], z[3n+l], z[3n+2] depend on data symbols x[3n-L], x[3n-L+l], ..., x[3n+2], i.e. a total of L+3 data symbols after NRZI are necessary. Putting RLL encoder, NRZI-mapper, and PR channel together, an equivalent RLL-NRZI-PR channel is obtained. This RLL-NRZI-PR channel can be represented by an FSM with u[n] as inputs and z[n]=[z[3n], z[3n+l], z[3n+2]] as outputs, see Fig. 3.

The derivation of the FSM for the RLL-NRZI-PR channel is accomplished by extending the RLL decoder FSM in Table 2. Because Table 2 only provides data symbols a[n] before NRZI, a single extra data symbol after NRZI is necessary as a phase reference. Therefore, states in the RLL-NRZI-PR FSM are defined as

s' [n] = [s[n], x[3(n+l)-l]],

where s [n] denotes a state in RLL decoder FSM as in Table 2, and x[3(n+l)-l] serves as the phase reference. This effectively constitutes a doubling of the number of states.

Data symbols x[3n], x[3n+l], and x[3n+2] can be determined from the state transitions s[n-l]-> s[n] of Table 2, if the phase reference x[3n-l] is available. For a specific state s [n] in Table 2, the upcoming RLL codebits are the same, which can be exploited to obtain data symbols x[3(n+l)], x[3(n+l)+l], and x[3(n+l)+2] . That is, given the phase reference x[3n-l] and a state transition s[n-l]-> s [n] in Table 2, data symbols x[3n-l], x[3n], ..., x[3n+5] will be available. Consequently, the state transition table for the RLL-NRZI-PR FSM can be obtained as given in the following Table 3, which is suitable for PR channels with 1<=L<=4. Note that in order to obtain three PR channel outputs, a total of L+3 data symbols after NRZI are necessary. From Table 3, seven data symbols after NRZI are available, so that the Table covers all PR channel memory lengths L<=4. )

Table 3: State transition table for the (1, 9) -RLL-NRZI-PR FSM

For the case of a PR channel having coefficients h0, hi, h2, i.e. L=2, the following Table 4 shows the complete state transition table for the RLL-NRZI-PR FSM, including the PR channel outputs. In the 4th column of Table 4, those symbols are emphasized by underlining, which are involved in evaluating the PR channel outputs. The RLL-NRZI-PR FSM takes as inputs the u[n] and outputs the z[n+l] .

Table 4: State transition table for a (1, 9) -RLL-NRZI-PR channel with L=2

It must be noted, that at the PR channel output of this example, even for arbitrary PR channel coefficients, only 6 different values can appear at all. These result from combinations of positive or negative PR channel coefficients, and are abbreviated in Table 4 as follows :

Hl = +h2+hl+hθ

H2 = +h2+hl-hθ

H3 = +h2-hl-hθ

H4 = -h2-hl-hθ

H5 = -h2-hl+hθ

H6 = -h2+hl+hθ

Depending on the specific values of the PR channel coefficients, some of these 6 values may actually be identical. This is most easily illustrated by assuming h2=hl=hθ=l.

For all PR channels with L<=4, the number of states and the number of branches are the same for the RLL-NRZI-PR FSM, namely, 18 states and 60 branches, respectively. Compared to the RLL- NRZI-PR FSM derived for the 17PP code, the number of branches is reduced by approximately one half for L=3. For L=4, an even larger reduction of complexity can be expected. In the 4th column of Table 3, those data symbols x[3(n+l)-l] are emphasized by underlining, which serve as phase reference in states s' [n] . Because Table 2 only provides data symbols before NRZI, a single extra data symbol after NRZI is necessary to provide a phase reference anyway. Therefore, the number of states and branches in the FSM representing the RLL-NRZI-PR channel is at least twice as big as the corresponding numbers of Table 2.

With respect to the number of states and branches, Table 3 actually provides the most efficient way to represent a RLL- NRZI-PR channel. This is only possible because of the above metnioned special property of the (1,9) -RLL decoder FSM, that for a specific state the upcoming RLL codebits are the same.

Claims

Claims

1. A method for channel decoding a sequence of code words that is runlength-limited to within a minimum runlength of 1 and a maximum runlength of 9 and obeys an RMTR-limitation of 5 maximally allowable repetitions, the method characterized by steps of

- when a current state and the code word are as contained in a line of the following table, outputting a data word and transiting to a next state as contained in the line of the table.

Current Code Next Data state word state word

Sl 000 S7 11

Sl 001 S4 00

Sl 010 S6 00

Sl 100 S5 00

Sl 101 S3 00

S2 000 S8 11

S2 001 S4 01

S2 010 S6 01

S2 100 S5 01

S2 101 S3 01

S3 000 Sl 00

S3 001 S4 00

S3 010 S6 00

S4 000 Sl 10

S4 001 S4 10

S4 010 S6 10

S5 000 S2 00

S5 001 S4 01

S5 010 S6 01 S5 100 S5 01

S5 101 S3 01

S6 000 S2 10

S6 001 S4 11

S6 010 S6 11

S6 100 S5 11

S6 101 S3 11

S7 000 S9 00

S8 010 S6 00

S9 100 S5 11

S9 101 S3 11,

wherein 0 signifies a first binary value, 1 signifies a second binary value different from the first binary value, and Sl to S9 signify a first to a ninth state.

2. A method for channel encoding a sequence of data bits into a sequence of code bits that is runlength-limited, RMTR- limitation-obeying and finite-state-machine decodable, the method comprising steps of:

- generating, from the sequence of data bits, a sequence of interim bits by encoding the sequence of data bits with a finite-state-machine decodable first channel code that is runlength-limited with a minimum runlength and an internal maximum runlength;

- obtaining, from the sequence of interim bits, the sequence of code bits by sequentially searching, in the sequence of interim bits, a forbidden sequence in which a minimum runlength bit pattern is repeated more often than a maximum allowable number (r) , and by replacing the forbidden sequence by a replacement sequence selected from a set of replacement sequences all containing a maximum runlength pattern larger than the internal maximum runlength, the method characterized in that replacement sequences are selected such that they are decodable with a lookahead depth less than the maximum lookahead depth occurring in the set of replacement sequences .

3. A method according to claim 2, where the forbidden sequence comprises the bit sequence "010 101 010", and the replacement sequences comprise a bit sequence of "000 000 000".

4. A method according to claim 3, where the replacement sequences comprise bit sequences from the set ("001 000 000 000 101 0", "0 010 100 000 000 010", "00 100 000 000 010 10", "00 101 000 000 000 10") .

5. A method according to claim 2, where the data bits are organised in data words of a predetermined data word length, the code bits are organised in code words of a predetermined code word length larger than the data word length, the first channel code generates code words from data words, and where the predefined lookahead depth is equal to the code word length .

6. A method according to claim 5, where the data word length is

2, and the code word length is 3.

7. Apparatus for channel decoding digital data, characterised by being a finite state machine having 9 states and 30 state transitions and being equipped and configured to perform a decoding method according to claim 1.

8. Method for trellis decoding a sequence of readout samples from a storage medium employing a runlength-limited, RMTR- limitation-obeying and finite-state-machine decodable code, into a sequence of digital data bits, the method comprising steps of:

- using a combined trellis that models the concatenated effects of runlength encoding, replacement, NRZI precoding, and the PR channel, to convert candidate input infobits into candidate PR channel outputs,

- calculating distance criteria between the candidate PR channel outputs and the sequence of readout samples,

- using the calculated distance criteria for selecting as decoded input infobits those input infobits among the candidate input infobits, where the corresponding PR channel outputs have the smallest distance criterion.

9. A method according to claim 8, wherein the runlength limitation is d=l,k=9, the RMTR limitation is r=5, and the combined trellis is as described in Table 4.