WO2009103048A1 - Dual photo-diode cmos pixels - Google Patents

Dual photo-diode cmos pixels Download PDF

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Publication number
WO2009103048A1
WO2009103048A1 PCT/US2009/034211 US2009034211W WO2009103048A1 WO 2009103048 A1 WO2009103048 A1 WO 2009103048A1 US 2009034211 W US2009034211 W US 2009034211W WO 2009103048 A1 WO2009103048 A1 WO 2009103048A1
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well
photo
diode
deep
substrate
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PCT/US2009/034211
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French (fr)
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WO2009103048A4 (en
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Carlos Augusto
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Quantum Semiconductor Llc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H01L27/14647—Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes

Definitions

  • the present invention relates to CMOS Image Sensors (CIS), CMOS pixels, light-sensing regions, and photo-diodes.
  • CMOS light-sensing regions and photo-diodes of the present invention are compatible with know CMOS pixel architectures such as 3T Active Pixel Sensors (APS), 4T Pinned Photo-Diode APS, etc.
  • the present invention introduces a new design for the light-sensing region of the CMOS Pixel, using only the standard CMOS process steps, and which is compatible with each and all of aforementioned the CMOS pixel technologies.
  • the new light-sensing region comprises dual photo-diodes incorporating independently biased Wells and Deep-Wells.
  • One object of the invention is to provide a method of fabrication of CMOS pixels with dual photo-diodes, comprising Wells that are independently biased from adjacent Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on the same active area, and in which both photo-diodes are aligned vertically and electrically connected in parallel.
  • Another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and Deep-Wells that are independently biased from adjacent Wells and Deep- Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on the same active area, and in which both photo-diodes are aligned vertically and electrically connected in parallel.
  • Yet another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and that are independently biased from adjacent Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on an adjacent active area, and in which both photo-diodes are aligned vertically and in which the top photo-diode can be biased independently, including for avalanche operation.
  • Yet another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and Deep-Wells that are independently biased from adjacent Wells and Deep- Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on adjacent active area, and in which both photo-diodes are aligned vertically and in which the top photo-diode can be biased independently, including for avalanche operation.
  • FIG. 1 (Prior Art) - Schematic cross-section of the typical photo-diode region of a CMOS Pixel, applicable to Passive Power Pixels (PPS), 3-Transistor CMOS Active Pixel Sensor (CMOS 3T APS), and 3-Transistor CMOS Logarithmic Active Pixel Sensor.
  • PPS Passive Power Pixels
  • CMOS 3T APS 3-Transistor CMOS Active Pixel Sensor
  • CMOS Logarithmic Active Pixel Sensor 3-Transistor CMOS Logarithmic Active Pixel Sensor.
  • FIG. 2 (Prior Art) - Schematic cross-section of the typical pinned photo-diode region of a 4-Transistor Pinned Photo-Diode CMOS Active Pixel Sensor (CMOS 4T PPD APS).
  • CMOS 4T PPD APS 4-Transistor Pinned Photo-Diode CMOS Active Pixel Sensor
  • FIG. 3 (Prior Art) - Schematic cross-section of the photo-diode region of a Pixel with a SiGeC Avalanche Photo-Diode (APD).
  • FIG. 4 Schematic top view of the a portion of an APS pixel whose photo-diode comprises an independently biased N-WeIl, and in which the active has a serpentine shape between the edge of the gate and the edge of the N-WeIl implant.
  • said transistor is the Reset Transistor (RST) and in 4T PPD APS pixels, said transistor is the Transfer Gate transistor (TG).
  • FIG. 5 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes having in common an independently biased N- WeIl, wherein the top photo-diode can be biased independently from the bottom photo-diode, which is formed by the well-to-substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
  • FIG. 6 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, wherein the photo-diode incorporates an independently biased N-WeIl, which is formed by the well-to-substrate junction, wherein the active of the photo-diode region is separate from the active of the adjacent MOSFET, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
  • N-WeIl which is formed by the well-to-substrate junction
  • FIG. 7 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, wherein the photo-diode incorporates an independently biased N-WeIl, which is formed by the well-to-substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
  • FIG. 8 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel and having in common an independently biased N-WeIl, wherein the bottom photo-diode is formed by the well-to- substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
  • FIG. 9 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel, in which the top photo-diode is formed near the surface, between a p-type "surface pinning" implant, and a N-WeIl that is connected to a Deep-N-Well, whose junction with the p-Substrate forms the bottom photo-diode, wherein said N-WeIl is independently biased and overlaps the source/drain region of an adjacent NMOS, and wherein the N-WeIl together with the Deep-N-Well fully isolate from the substrate the P-WeIl on which the NMOS devices are made.
  • FIG. 10 Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel, in which the top photo-diode is formed near the surface, between a p-type "surface pinning" implant, and a N-WeIl that is connected to a Deep-N-Well, whose junction with the p-Substrate forms the bottom photo-diode, wherein said N-WeIl is independently biased and overlaps the source/drain region of an adjacent NMOS.
  • the current invention relates to the fabrication of CMOS photo-diode regions, whereby masked ion-implantation process steps, part of standard CMOS process flows, are used to form light-sensing regions that extend themselves from near the surface of the semiconductor substrate to depths longer than the absorption length of light in the visible spectrum. Because the coefficient of absorption of the semiconductor substrate decreases for longer wavelengths, the absorption length (inverse of the coefficient of absorption) becomes longer for longer wavelengths.
  • the junction depth of photo-diodes should not be too shallow compared to the absorption depth of the wavelengths of light that are to be sensed.
  • CMOS image sensor process technology uses the source/drain-to-well junctions of CMOS devices as photo-diodes, while a "Pinned Photo-Diode” technology requires additional customized implants to form photo-diodes, which are not much deeper than the standard source/drain-to-well junctions.
  • CMOS pixels The photo-diode region of CMOS pixels is essentially the same for a few different pixel architectures, such as the IT Passive Pixel Sensor (PPS), the 3-Transistor CMOS Active Pixel Sensor (CMOS 3T APS), and 3-Transistor CMOS Logarithmic Active Pixel Sensor.
  • PPS IT Passive Pixel Sensor
  • CMOS 3T APS 3-Transistor CMOS Active Pixel Sensor
  • FIG. 1 A schematic cross-section representation of such photo-diode region is shown in FIG. 1 (Prior Art).
  • the transistor "T" in FIG. 1 (Prior Art) is the Row-Select Transistor.
  • RST Reset Transistor
  • the transistor "T” in FIG. 1 (Prior Art) is no longer operated in the reset mode, but has its gate connected to the drain voltage supply, and is operated in the "weak inversion mode".
  • the photo-diode region of a 4-Transistor Pinned Photo-Diode Active Pixel Sensor (4T PPD APS), is the same for 5T PPD APS, but is different from that of a 3T APS pixel.
  • a schematic cross-section representation of a 4T PPD APS (and 5T PPD APS) photo-diode region is shown in FIG. 2 (Prior Art).
  • the "TG" transistor of FIG. 2 (Prior Art) is the transfer gate.
  • the present invention discloses a new CMOS pixel design, in which a N-WeIl is incorporated into the photo-diode of the CMOS pixel.
  • the present invention is applicable to all CMOS pixels: IT PPS, a 3T APS, 3T Logarithmic APS, 4T PPD APS, 5T PPD APS, etc.
  • CMOS pixels incorporate NMOS devices, rather than PMOS devices. This is due to the higher performance of electron-transport devices (photo-diode and transistors) over hole -transport devices.
  • electron-transport devices photo-diode and transistors
  • the description and exemplary implementations will assume pixels using electron- transport devices.
  • CMOS processing comprises junction- formation steps, part of the standard CMOS process flow of the simplest CMOS technologies, such as digital CMOS, that produce junctions that are much deeper than the aforementioned source/drain-to-well junctions, such as the N-Well-to-P-Substrate or P-Well-to-N- Substrate junction, depending on the starting substrate.
  • Well-to-Substrate junctions are then better suited for the photo-detection of longer wavelengths, such as the color red, and therefore improve the overall performance of image sensing across the entire range of the visible spectrum.
  • FIG. 3 (Prior Art) - Schematic cross-section of the photo-diode region of a 1 -Transistor Pixel with a comprising an epitaxial SiGeC films over the Well active region.
  • the N-WeIl (P-WeIl) implant into P-Substrate (N-Substrate) must be placed at a minimum distance from the channel of NMOS (PMOS) devices, due to the possible impact of the N- WeIl (P-WeIl) implant on the surface concentration in the channel, and therefore the threshold voltage (VT).
  • PMOS NMOS
  • VT threshold voltage
  • FIG. 4 with a schematic top view of the an pixel whose photo-diode comprises an independently biased N-WeIl (P-WeIl), and in which the active of the adjacent transistor has a serpentine shape between the edge of the gate of said transistor and the region in which the Well implant overlaps the source/drain junction.
  • the layout configuration shown in FIG. 4 is a key enabling factor to design smaller pixels comprising one or more independently biased N- Wells (P- Wells), since the simplest layout possible would place the edge of the N-WeIl (P-WeIl) implant on an active area.
  • P- Wells independently biased N- Wells
  • FIG. 5 A variation of the pixel cell presented in the aforementioned Prior Art, is shown in FIG. 5, wherein the epitaxial films are removed from the photo-diode, and the junction formed between the epitaxial film and the Well underneath it, is replaced by an ion- implanted junction into the substrate, inside the perimeter of the Well.
  • FIG. 6 A second variation of the pixel cell presented in the aforementioned Prior Art, is shown in FIG. 6, wherein the epitaxial films are removed from the top of the Well, and no other junction is formed over said Well. This is a case in which there is no advantage in keeping the isolation region between the Well and the source/drain region of the adjacent MOSFET, leading to the configuration depicted in FIG. 7, which is suitable for standard CMOS photo-diodes.
  • the configuration shown in FIG. 8 presents a novel pixel configuration for p-type substrates, comprising two buried photo-diodes, wherein a Pinned Photo-Diode is fabricated near the surface of the substrate and wherein a buried photo-diode is formed at the N-Well-to-P-Substrate junction.
  • This configuration differs from commonly used solutions for pinned photo-diodes because the top photo-diode junction is formed mainly over of the N-WeIl, rather than the P-WeIl on which the adjacent N-MOSFET is fabricated. This difference is very important for reducing leakage current (dark-current) and for reducing capacitance, which in turn is relevant for conversion of charge to voltage.
  • this configuration produces two photo-diodes electrically connected in parallel to the same adjacent transistor, one near the surface of the substrate, suitable for the sensing of shorter wavelengths, and the other buried deep into the substrate for the sensing of longer wavelengths.
  • a color filter positioned over each pixel determines which range of wavelengths reaches the photo-diodes and which contributes the most for the total photo-generated signal in each pixel.
  • the light-sensing region comprises two photo-diodes electrically connected in parallel, and in approximate vertical alignment, both positioned underneath the region onto which light is focused, by microlenses, for example.
  • the typical junction configuration of Pinned Photo-Diodes also produces what could be seen as two junctions/photo-diode connected in parallel, said two junctions/photo-diodes are formed at a distance from each other that is much shorter than the distance between the photo-diodes fabricated according to the present invention.
  • the "bottom buried photo-diode” is placed at a depth similar to that of standard CMOS field isolation (LOCOS or STI), while according to the present invention, the "bottom buried photo-diode” is formed:
  • the "bottom buried photo-diode" is not formed by said Deep-Well and a Well of the opposite polarity, but rather by the Deep- Well- to- Substrate junction, and that said Deep-Well is used in conjunction with a Well of the same polarity to (vertically) connect to the "top buried photo-diode" of the same light-sensing region.
  • the Well portion of the photo-diode is positioned mostly in an active area, and therefore the top portion of the semiconductor substrate also contributes to photo-absorption, which is not the case if the Well portion of the photo-diodes would be formed under field oxide.
  • the surface of the active region in which the Well photo-diode is formed is part of a pinned photo-diode, whose surface is terminated by a gate oxide.
  • the purpose of including a Deep-Well is not to electrically isolate the photo-diode and CMOS devices in a pixel, from other pixels and/or the substrate.
  • the purpose is to use a Deep-Well, as part of a photo- diode in a pixel, by connecting it to a Well which overlaps the sour/drain region - of the same polarity - of an adjacent MOSFET.
  • Said Well being preferably formed onto an active area, rather than a region covered with field oxide (LOCOS or STI).
  • Deep Well Implants (Deep-N-Well for P-Substrates or Deep-P-Well for N-Substrates) are part of standard CMOS processing.
  • the junction depth of a Deep-Well is several times deeper than that of the usual Well, which is helpful for longer wavelengths, for example in the Near-Infra-Red (NIR).
  • NIR Near-Infra-Red
  • CMOS photo-diodes and Pinned Photo- Diodes
  • adjacent photo-diode junctions are laterally isolated from each other by dielectric isolation, such as shallow trench isolation, Well-to-Substrate and/or Deep-Well-to-Substrate junctions, do not have dielectric isolation between them.
  • the spacing between adjacent pixels with Well-to- Substrate and/or Deep- Well-to-Substrate junctions as photo-diodes has to be larger than the respective lateral depletion regions, which can be more than 1 micron and 2 micron, respectively, given the low doping levels of said junctions.
  • the minimum distance between adjacent photo- diodes, which belong to adjacent pixels is the minimum distance between independently biased Wells
  • the minimum distance between adjacent photo-diodes, which belong to adjacent pixels is the minimum distance between independently biased Deep-Wells.
  • the lateral depletion width of the independently biased Deep-Wells can be shortened with an implant for a complementary Deep-Well.
  • Deep-N- Wells would part of the photo- diode junctions, and a Deep-P-Well would be implanted into the regions separating adjacent independently biased Deep-N- Wells. This would enable longer/deeper depletion regions between the Deep-N- Well and the p-substrate in the vertical direction, thus leading to an increased volume of photo- sensing material, resulting in more efficient absorption of the incoming light.
  • a "Complementary Deep-Well" is not part of standard CMOS process flows, it is a process step that is straightforward to develop and implement.
  • the photo-diodes for said shorter wavelengths can be made with shallower junctions, while photo-diodes for longer wavelengths, such as Red, can incorporate a Well-to-Substrate Junction, and/or photo-diodes incorporating a (Well+Deep-Well)-to-Substrate junction.
  • Such an arrangement optimizes the overall size for a pixel cell area that is capable of absorbing all the relevant wavelengths for color image sensing, and is more efficient that an alternative arrangement in which the photo-diodes for all wavelengths would e identical to those capable of efficient absorption of the longer wavelengths.
  • the length of the depletion regions of Wells and Deep- Wells can be further increased, especially in the vertical direction, without any modification to the process flow and/or process steps, through the application of a bias to the substrate: negative bias for p-type substrates, and positive bias for n-type substrates.
  • a bias to the substrate negative bias for p-type substrates, and positive bias for n-type substrates.
  • substrate bias is only possible when all CMOS devices are made on wells that are decoupled from the substrate: for p-type substrates, all NMOS would be made on P- Wells inside Deep-N- Wells, and for n-type substrates all PMOS would be made on N- Wells inside Deep-P-Wells.
  • the use of Deep-Wells and substrate bias also increase the sensing capability for NIR.
  • the photo-diodes of the current invention can be integrated with standard CMOS photo-diodes, and also with pinned photo-diodes, and are compatible with all types of pixel circuitry, such as the 3 T, 4T, 5T Active Pixel Sensors and all those derived from these.
  • the integration of a Deep-Well into a photo-diode can be implemented in at least two different configurations, with the main difference residing on the layout for the Well implant, which connects the Deep-Well with the source/drain region of a MOSFET.
  • the two options for the layout of the Well implant are:
  • the Well implant fully encloses the are of the photo-diode and/or pixel, by centering said implant on the line defining the perimeter of the Deep- We 11 implant, completely surrounding the pixel.
  • the width of the Well implant will be the minimum allowed by the design rules for the process technology being used.
  • This configuration is shown in FIG. 9, is compatible with the biasing of the substrate with voltages whose absolute value is larger than the absolute value of the voltages used for the CMOS devices, because said CMOS devices are decoupled from the substrate by Deep- Wells.
  • the Well implant does not enclose the entire area of the photo-diode and/or pixel, and together with the Deep-Well forms an structure whose cross-section resembles a "L" shape or an "inverted T” shape. This configuration is shown in FIG. 10, and allows a smaller pixel pitch than configuration #1.
  • CMOS process step can be adapted to further increase the efficiency of light absorption: the thinning of the substrate from the back-side and subsequent deposition of a metal layer (typically aluminum) for back-side contact to the substrate.
  • This process module can improve efficiency of optical absorption by thinning the substrate to the point at the which the back-side interface of the substrate with the metal contact is fairly close to the depletion region between the Deep-Wells and the substrate.
  • the metal contact on the back-side will reflect light back to the depletion regions. Electronic crosstalk is minimized by positioning the interface between substrate and metal as close as possible to the depletion regions.

Abstract

The present invention provides a method of forming CMOS pixels, with the light-sensing region comprising vertically aligned dual photo-diodes, in which the bottom photo-diode is formed either by a well-to-substrate junction, or by a deep-well-to-substrate junction, wherein said well and deep-well are independently biased from surrounding wells and deep-wells of the same polarity. Said independently biased well is a common region to the top and bottom photo-diodes and overlaps the source/drain region of a MOSFET formed on a well with the opposite polarity, that of the substrate. The photo-diodes can be electrically connected in parallel, or the top photo- diode can be biased separately from the bottom photo-diode, said bias can be such that avalanche mode operation is possible, including the single-photon detection (Geiger) mode.

Description

Dual Photo-Diode CMOS Pixels
Background of the Invention
The present invention relates to CMOS Image Sensors (CIS), CMOS pixels, light-sensing regions, and photo-diodes. The CMOS light-sensing regions and photo-diodes of the present invention are compatible with know CMOS pixel architectures such as 3T Active Pixel Sensors (APS), 4T Pinned Photo-Diode APS, etc.
The present invention introduces a new design for the light-sensing region of the CMOS Pixel, using only the standard CMOS process steps, and which is compatible with each and all of aforementioned the CMOS pixel technologies. The new light-sensing region comprises dual photo-diodes incorporating independently biased Wells and Deep-Wells.
The utilization of an independently biased N-WeIl as part of a photo-diode in a CMOS pixels was already introduced in WO 2002/33755, US Patent 6,943,051, and US Patent No.7,265,006.
Summary of the Invention
One object of the invention is to provide a method of fabrication of CMOS pixels with dual photo-diodes, comprising Wells that are independently biased from adjacent Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on the same active area, and in which both photo-diodes are aligned vertically and electrically connected in parallel.
Another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and Deep-Wells that are independently biased from adjacent Wells and Deep- Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on the same active area, and in which both photo-diodes are aligned vertically and electrically connected in parallel.
Yet another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and that are independently biased from adjacent Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on an adjacent active area, and in which both photo-diodes are aligned vertically and in which the top photo-diode can be biased independently, including for avalanche operation.
Yet another object of the invention is to provide a method of fabrication of CMOS pixels with dual photo- diodes, comprising Wells and Deep-Wells that are independently biased from adjacent Wells and Deep- Wells of the same polarity, and wherein said Well overlaps the source/drain region (of the same polarity) of an adjacent MOSFET made on adjacent active area, and in which both photo-diodes are aligned vertically and in which the top photo-diode can be biased independently, including for avalanche operation. Brief Description of the Drawing Figures
FIG. 1 (Prior Art) - Schematic cross-section of the typical photo-diode region of a CMOS Pixel, applicable to Passive Power Pixels (PPS), 3-Transistor CMOS Active Pixel Sensor (CMOS 3T APS), and 3-Transistor CMOS Logarithmic Active Pixel Sensor.
FIG. 2 (Prior Art) - Schematic cross-section of the typical pinned photo-diode region of a 4-Transistor Pinned Photo-Diode CMOS Active Pixel Sensor (CMOS 4T PPD APS).
FIG. 3 (Prior Art) - Schematic cross-section of the photo-diode region of a Pixel with a SiGeC Avalanche Photo-Diode (APD).
FIG. 4 - Schematic top view of the a portion of an APS pixel whose photo-diode comprises an independently biased N-WeIl, and in which the active has a serpentine shape between the edge of the gate and the edge of the N-WeIl implant. For 3T APS pixels said transistor is the Reset Transistor (RST) and in 4T PPD APS pixels, said transistor is the Transfer Gate transistor (TG).
FIG. 5 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes having in common an independently biased N- WeIl, wherein the top photo-diode can be biased independently from the bottom photo-diode, which is formed by the well-to-substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
FIG. 6 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, wherein the photo-diode incorporates an independently biased N-WeIl, which is formed by the well-to-substrate junction, wherein the active of the photo-diode region is separate from the active of the adjacent MOSFET, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
FIG. 7 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, wherein the photo-diode incorporates an independently biased N-WeIl, which is formed by the well-to-substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
FIG. 8 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel and having in common an independently biased N-WeIl, wherein the bottom photo-diode is formed by the well-to- substrate junction, and wherein said N-WeIl overlaps the source/drain region of an adjacent MOSFET.
FIG. 9 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel, in which the top photo-diode is formed near the surface, between a p-type "surface pinning" implant, and a N-WeIl that is connected to a Deep-N-Well, whose junction with the p-Substrate forms the bottom photo-diode, wherein said N-WeIl is independently biased and overlaps the source/drain region of an adjacent NMOS, and wherein the N-WeIl together with the Deep-N-Well fully isolate from the substrate the P-WeIl on which the NMOS devices are made.
FIG. 10 - Schematic cross-section of the light-sensing region of a CMOS Pixel according to the present invention, comprising 2 vertically aligned photo-diodes electrically connected in parallel, in which the top photo-diode is formed near the surface, between a p-type "surface pinning" implant, and a N-WeIl that is connected to a Deep-N-Well, whose junction with the p-Substrate forms the bottom photo-diode, wherein said N-WeIl is independently biased and overlaps the source/drain region of an adjacent NMOS. Detailed Description of the Invention
The current invention relates to the fabrication of CMOS photo-diode regions, whereby masked ion- implantation process steps, part of standard CMOS process flows, are used to form light-sensing regions that extend themselves from near the surface of the semiconductor substrate to depths longer than the absorption length of light in the visible spectrum. Because the coefficient of absorption of the semiconductor substrate decreases for longer wavelengths, the absorption length (inverse of the coefficient of absorption) becomes longer for longer wavelengths.
If the absorption length for a particular wavelength is deeper than the depletion region of the junctions forming the photo-diode, then the efficiency of collection and readout of the photo-generated charge carriers will be dramatically reduced, and at the same time, crosstalk will be increased. Therefore, the junction depth of photo-diodes should not be too shallow compared to the absorption depth of the wavelengths of light that are to be sensed.
Typical CMOS image sensor process technology uses the source/drain-to-well junctions of CMOS devices as photo-diodes, while a "Pinned Photo-Diode" technology requires additional customized implants to form photo-diodes, which are not much deeper than the standard source/drain-to-well junctions.
The photo-diode region of CMOS pixels is essentially the same for a few different pixel architectures, such as the IT Passive Pixel Sensor (PPS), the 3-Transistor CMOS Active Pixel Sensor (CMOS 3T APS), and 3-Transistor CMOS Logarithmic Active Pixel Sensor. A schematic cross-section representation of such photo-diode region is shown in FIG. 1 (Prior Art). For IT PPS pixels the transistor "T" in FIG. 1 (Prior Art) is the Row-Select Transistor. For 3T APS pixels, the transistor "T" in FIG. 1 (Prior Art) is the Reset Transistor (RST). For 3T Logarithmic APS, the transistor "T" in FIG. 1 (Prior Art) is no longer operated in the reset mode, but has its gate connected to the drain voltage supply, and is operated in the "weak inversion mode".
The photo-diode region of a 4-Transistor Pinned Photo-Diode Active Pixel Sensor (4T PPD APS), is the same for 5T PPD APS, but is different from that of a 3T APS pixel. A schematic cross-section representation of a 4T PPD APS (and 5T PPD APS) photo-diode region is shown in FIG. 2 (Prior Art). For both the 4T and 5T PPD APS pixels, the "TG" transistor of FIG. 2 (Prior Art) is the transfer gate.
The present invention discloses a new CMOS pixel design, in which a N-WeIl is incorporated into the photo-diode of the CMOS pixel. The present invention is applicable to all CMOS pixels: IT PPS, a 3T APS, 3T Logarithmic APS, 4T PPD APS, 5T PPD APS, etc.
Typically, CMOS pixels incorporate NMOS devices, rather than PMOS devices. This is due to the higher performance of electron-transport devices (photo-diode and transistors) over hole -transport devices. In this disclosure, the description and exemplary implementations will assume pixels using electron- transport devices. However, it is possible and straightforward to reverse the polarity of the photo-diodes, transistors, and substrate material, and obtain the same functionality.
CMOS processing comprises junction- formation steps, part of the standard CMOS process flow of the simplest CMOS technologies, such as digital CMOS, that produce junctions that are much deeper than the aforementioned source/drain-to-well junctions, such as the N-Well-to-P-Substrate or P-Well-to-N- Substrate junction, depending on the starting substrate. Well-to-Substrate junctions are then better suited for the photo-detection of longer wavelengths, such as the color red, and therefore improve the overall performance of image sensing across the entire range of the visible spectrum.
The utilization of an independently biased Well as part of a photo-diode in a CMOS pixel was introduced in Prior Art WO 2002/33755, US Patent 6,943,051, and US Patent No.7,265,006. In said Prior Art, the photo-diodes also comprised an epitaxial SiGeC epitaxial film, but the fundamental point is that they presented the concept of using an independently biased Well, connecting, underneath a portion of the isolation region defining the active area of the photo-diode, to a source/drain region - with the same polarity - of an adjacent MOSFET made on a Well of the opposite polarity. FIG. 3 (Prior Art) - Schematic cross-section of the photo-diode region of a 1 -Transistor Pixel with a comprising an epitaxial SiGeC films over the Well active region.
Also, within the same pixel, the N-WeIl (P-WeIl) implant into P-Substrate (N-Substrate) must be placed at a minimum distance from the channel of NMOS (PMOS) devices, due to the possible impact of the N- WeIl (P-WeIl) implant on the surface concentration in the channel, and therefore the threshold voltage (VT). However this can be solved with a suitable layout, as shown in FIG. 4, with a schematic top view of the an pixel whose photo-diode comprises an independently biased N-WeIl (P-WeIl), and in which the active of the adjacent transistor has a serpentine shape between the edge of the gate of said transistor and the region in which the Well implant overlaps the source/drain junction. The layout configuration shown in FIG. 4 is a key enabling factor to design smaller pixels comprising one or more independently biased N- Wells (P- Wells), since the simplest layout possible would place the edge of the N-WeIl (P-WeIl) implant on an active area.
An important reason for the isolation of the active area of the photo-diode, from that of the adjacent MOSFET, is that the standard practice for the monolithic integration with CMOS of epitaxial films (such as SiGe, SiGeC, etc.), requires the existence of such isolation structures to provide an etch stop marking layer for the patterning of the epitaxial films. Another reason is the fabrication of suicide and contacts to said epitaxial films over said isolation regions, rather than over the active areas.
Another important reason for the isolation of the active area of the photo-diode from that of the adjacent MOSFET, is to allow the application of voltage to the top region -near the substrate surface - of the photo- diode, when this region is doped with a polarity opposite to that of the Well that is formed on. This is of particular importance to enable the operation of the photo-diode in the avalanche mode, including the single-photon detection mode, also known as the Geiger mode.
A variation of the pixel cell presented in the aforementioned Prior Art, is shown in FIG. 5, wherein the epitaxial films are removed from the photo-diode, and the junction formed between the epitaxial film and the Well underneath it, is replaced by an ion- implanted junction into the substrate, inside the perimeter of the Well.
A second variation of the pixel cell presented in the aforementioned Prior Art, is shown in FIG. 6, wherein the epitaxial films are removed from the top of the Well, and no other junction is formed over said Well. This is a case in which there is no advantage in keeping the isolation region between the Well and the source/drain region of the adjacent MOSFET, leading to the configuration depicted in FIG. 7, which is suitable for standard CMOS photo-diodes.
The configuration shown in FIG. 8, presents a novel pixel configuration for p-type substrates, comprising two buried photo-diodes, wherein a Pinned Photo-Diode is fabricated near the surface of the substrate and wherein a buried photo-diode is formed at the N-Well-to-P-Substrate junction. This configuration differs from commonly used solutions for pinned photo-diodes because the top photo-diode junction is formed mainly over of the N-WeIl, rather than the P-WeIl on which the adjacent N-MOSFET is fabricated. This difference is very important for reducing leakage current (dark-current) and for reducing capacitance, which in turn is relevant for conversion of charge to voltage.
Furthermore, it must be noted that this configuration produces two photo-diodes electrically connected in parallel to the same adjacent transistor, one near the surface of the substrate, suitable for the sensing of shorter wavelengths, and the other buried deep into the substrate for the sensing of longer wavelengths. A color filter positioned over each pixel determines which range of wavelengths reaches the photo-diodes and which contributes the most for the total photo-generated signal in each pixel.
Therefore, according to the present invention, the light-sensing region comprises two photo-diodes electrically connected in parallel, and in approximate vertical alignment, both positioned underneath the region onto which light is focused, by microlenses, for example.
Although the typical junction configuration of Pinned Photo-Diodes also produces what could be seen as two junctions/photo-diode connected in parallel, said two junctions/photo-diodes are formed at a distance from each other that is much shorter than the distance between the photo-diodes fabricated according to the present invention. In typical Pinned Photo-Diodes, the "bottom buried photo-diode" is placed at a depth similar to that of standard CMOS field isolation (LOCOS or STI), while according to the present invention, the "bottom buried photo-diode" is formed:
(1) Well- to- Substrate junction, which is typically 4 to 5 times deeper than field isolation.
(2) Deep-Well- to-Substrate junction, which is typically 10 times deeper than field isolation.
It is important to note that in the present invention, in a photo-diode comprising a Deep-Well, the "bottom buried photo-diode" is not formed by said Deep-Well and a Well of the opposite polarity, but rather by the Deep- Well- to- Substrate junction, and that said Deep-Well is used in conjunction with a Well of the same polarity to (vertically) connect to the "top buried photo-diode" of the same light-sensing region.
In the present invention, the Well portion of the photo-diode is positioned mostly in an active area, and therefore the top portion of the semiconductor substrate also contributes to photo-absorption, which is not the case if the Well portion of the photo-diodes would be formed under field oxide. In the present invention, the surface of the active region in which the Well photo-diode is formed, is part of a pinned photo-diode, whose surface is terminated by a gate oxide. That provides a significantly better surface passivation than that available for Well photo-diodes formed under field oxide, wherein the bottom edge of a trench formed during Shallow Trench Isolation, and in which the light-sensing region comprises only one photo-diode, that which is formed by the Well-to-Substrate junction.
The purpose of including a Deep-Well is not to electrically isolate the photo-diode and CMOS devices in a pixel, from other pixels and/or the substrate. The purpose is to use a Deep-Well, as part of a photo- diode in a pixel, by connecting it to a Well which overlaps the sour/drain region - of the same polarity - of an adjacent MOSFET. Said Well being preferably formed onto an active area, rather than a region covered with field oxide (LOCOS or STI).
"Deep Well" Implants (Deep-N-Well for P-Substrates or Deep-P-Well for N-Substrates) are part of standard CMOS processing. The junction depth of a Deep-Well is several times deeper than that of the usual Well, which is helpful for longer wavelengths, for example in the Near-Infra-Red (NIR).
However, the utilization of deeper junctions for photo-diodes has a penalty in terms of the spacing between adjacent pixels (pixel pitch). Whereas in standard CMOS photo-diodes (and Pinned Photo- Diodes) adjacent photo-diode junctions are laterally isolated from each other by dielectric isolation, such as shallow trench isolation, Well-to-Substrate and/or Deep-Well-to-Substrate junctions, do not have dielectric isolation between them. For this reason, the spacing between adjacent pixels with Well-to- Substrate and/or Deep- Well-to-Substrate junctions as photo-diodes, has to be larger than the respective lateral depletion regions, which can be more than 1 micron and 2 micron, respectively, given the low doping levels of said junctions.
For photo-diodes using Well-to-Substrate junctions, the minimum distance between adjacent photo- diodes, which belong to adjacent pixels, is the minimum distance between independently biased Wells, and for photo-diodes using Deep-Well-to-Substrate junctions, the minimum distance between adjacent photo-diodes, which belong to adjacent pixels, is the minimum distance between independently biased Deep-Wells.
The lateral depletion width of the independently biased Deep-Wells can be shortened with an implant for a complementary Deep-Well. For example, on p-type substrates, Deep-N- Wells would part of the photo- diode junctions, and a Deep-P-Well would be implanted into the regions separating adjacent independently biased Deep-N- Wells. This would enable longer/deeper depletion regions between the Deep-N- Well and the p-substrate in the vertical direction, thus leading to an increased volume of photo- sensing material, resulting in more efficient absorption of the incoming light. Although a "Complementary Deep-Well" is not part of standard CMOS process flows, it is a process step that is straightforward to develop and implement.
Because the efficient absorption of shorter wavelengths (for example blue and green) do not require photo-diodes made with Wells or Deep-Wells, and given the penalty in pixel pitch when using such junctions, the photo-diodes for said shorter wavelengths can be made with shallower junctions, while photo-diodes for longer wavelengths, such as Red, can incorporate a Well-to-Substrate Junction, and/or photo-diodes incorporating a (Well+Deep-Well)-to-Substrate junction. Such an arrangement optimizes the overall size for a pixel cell area that is capable of absorbing all the relevant wavelengths for color image sensing, and is more efficient that an alternative arrangement in which the photo-diodes for all wavelengths would e identical to those capable of efficient absorption of the longer wavelengths.
The length of the depletion regions of Wells and Deep- Wells can be further increased, especially in the vertical direction, without any modification to the process flow and/or process steps, through the application of a bias to the substrate: negative bias for p-type substrates, and positive bias for n-type substrates. Naturally that the application of substrate bias is only possible when all CMOS devices are made on wells that are decoupled from the substrate: for p-type substrates, all NMOS would be made on P- Wells inside Deep-N- Wells, and for n-type substrates all PMOS would be made on N- Wells inside Deep-P-Wells. The use of Deep-Wells and substrate bias also increase the sensing capability for NIR.
The photo-diodes of the current invention can be integrated with standard CMOS photo-diodes, and also with pinned photo-diodes, and are compatible with all types of pixel circuitry, such as the 3 T, 4T, 5T Active Pixel Sensors and all those derived from these.
The integration of a Deep-Well into a photo-diode can be implemented in at least two different configurations, with the main difference residing on the layout for the Well implant, which connects the Deep-Well with the source/drain region of a MOSFET. The two options for the layout of the Well implant are:
(#1) The Well implant fully encloses the are of the photo-diode and/or pixel, by centering said implant on the line defining the perimeter of the Deep- We 11 implant, completely surrounding the pixel. Typically the width of the Well implant will be the minimum allowed by the design rules for the process technology being used. This configuration is shown in FIG. 9, is compatible with the biasing of the substrate with voltages whose absolute value is larger than the absolute value of the voltages used for the CMOS devices, because said CMOS devices are decoupled from the substrate by Deep- Wells.
(#2) The Well implant does not enclose the entire area of the photo-diode and/or pixel, and together with the Deep-Well forms an structure whose cross-section resembles a "L" shape or an "inverted T" shape. This configuration is shown in FIG. 10, and allows a smaller pixel pitch than configuration #1.
Another standard CMOS process step can be adapted to further increase the efficiency of light absorption: the thinning of the substrate from the back-side and subsequent deposition of a metal layer (typically aluminum) for back-side contact to the substrate. This process module can improve efficiency of optical absorption by thinning the substrate to the point at the which the back-side interface of the substrate with the metal contact is fairly close to the depletion region between the Deep-Wells and the substrate. The metal contact on the back-side will reflect light back to the depletion regions. Electronic crosstalk is minimized by positioning the interface between substrate and metal as close as possible to the depletion regions.

Claims

Claims
1. A method of forming CMOS Image Sensors, wherein the light-sensing region inside each pixel comprises 2 photo-diode junctions, vertically aligned and electrically connected in parallel, wherein the bottom photo-diode is formed by a well-to-substrate junction, and wherein the top photo-diode is formed near the surface of an active region, by at least one implant over said well, said well being independently biased from surrounding wells of the same polarity, wherein said well overlaps a portion of a source/drain region of an adjacent MOSFET, fabricated on the same active region, over a well with the same polarity of the substrate.
2. A method as claimed in claim 1, wherein the back- side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
3. A method of forming CMOS Image Sensors, wherein the light-sensing region comprises 2 photo-diode junctions, vertically aligned and electrically connected in parallel, wherein the bottom photo-diode is formed by a deep-well-to-substrate junction, and wherein the top photo- diode is formed near the surface of an active region, by at least one implant over a well with the same polarity and formed over said deep-well, said well and deep-well being independently biased from surrounding wells and deep-wells of the same polarity, wherein said well overlaps a portion of a source/drain region of an adjacent MOSFET, fabricated on the same active region, over a well with the same polarity of the substrate.
4. A method as claimed in claim 3, wherein the back- side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
5. A method as claimed in claim 3, wherein for each pixel, the well and deep-well part of the photo-diode, fully surround and electrically isolate from the substrate the well on which the adjacent in-pixel MOSFETs are made.
6. A method as claimed in claim 5, wherein the back- side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
7. A method of forming CMOS Image Sensors, wherein the light-sensing region inside each pixel comprises 2 vertically aligned photo-diode junctions, wherein the bottom photo-diode is formed by a well-to-substrate junction, and wherein the top photo-diode is formed near the surface of an active region, by at least one implant over said well, said well being independently biased from surrounding wells of the same polarity, wherein said well overlaps a portion of a source/drain region of an adjacent MOSFET, fabricated on the same active region, over a well with the same polarity of the substrate, and said top photo-diode is independently biased from said bottom photo-diode.
8. A method as claimed in claim 7, wherein the back-side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
9. A method of forming CMOS Image Sensors, wherein the light-sensing region comprises 2 vertically aligned photo-diode junctions, wherein the bottom photo-diode is formed by a deep- well-to-substrate junction, and wherein the top photo-diode is formed near the surface of an active region, by at least one implant over a well with the same polarity and formed over said deep-well, said well and deep-well being independently biased from surrounding wells and deep- wells of the same polarity, wherein said well overlaps a portion of a source/drain region of an adjacent MOSFET, fabricated on the same active region, over a well with the same polarity of the substrate, and said top photo-diode is independently biased from said bottom photo-diode.
10. A method as claimed in claim 9, wherein the back-side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
11. A method as claimed in claim 9, wherein for each pixel, the well and deep-well part of the photo-diode, fully surround and electrically isolate from the substrate the well on which the adjacent in-pixel MOSFETs are made.
12. A method as claimed in claim 11, wherein the back- side of the semiconductor substrate is thinned and electrically contacted by a light-reflecting metal.
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