WO2009091445A1 - Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices - Google Patents

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices Download PDF

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Publication number
WO2009091445A1
WO2009091445A1 PCT/US2008/084422 US2008084422W WO2009091445A1 WO 2009091445 A1 WO2009091445 A1 WO 2009091445A1 US 2008084422 W US2008084422 W US 2008084422W WO 2009091445 A1 WO2009091445 A1 WO 2009091445A1
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WIPO (PCT)
Prior art keywords
memory element
bitline
voltage
wordline
diode
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PCT/US2008/084422
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French (fr)
Inventor
Jun Liu
Original Assignee
Micron Technology, Inc.
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Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to EP21186092.9A priority Critical patent/EP3926632A3/en
Priority to EP14171745.4A priority patent/EP2787507B1/en
Priority to EP08870757.5A priority patent/EP2243138B1/en
Priority to KR1020107015584A priority patent/KR101136639B1/en
Priority to CN200880124714.6A priority patent/CN101911201B/en
Publication of WO2009091445A1 publication Critical patent/WO2009091445A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device

Definitions

  • Memory Cells Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
  • TECHNICAL FIELD Embodiments disclosed herein pertain to memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices.
  • BACKGROUND Resistive random access memories may use a material capable of being configured in one of two different resistive states to store information. When configured in one of the resistive states, the material may have a high resistance to electrical current. In contrast, when configured in the other resistive state, the material may have a low resistance to electrical current.
  • the resistive state in which the material is configured may be changed using electrical signals. For example, if the material is in a high-resistance state, the material may be configured to be in a low-resistance state by applying a voltage across the material.
  • the resistive state may be persistent. For example, once configured in a resistive state, the material may stay in the resistive state even if neither a current nor a voltage is applied to the material. Furthermore, the configuration of the material may be repeatedly changed from the high resistance state to the low resistance state or from the low resistance state to the high resistance state.
  • Fig. 1 is a chart illustrating voltage/current relationships.
  • Fig. 2 is chart illustrating other voltage/current relationships.
  • Fig. 3 is a schematic diagram of a memory cell.
  • Fig. 4 is a schematic diagram of a memory device.
  • Fig. 5 is a schematic diagram of a memory device illustrating a current.
  • Fig. 6 is a schematic diagram of a memory device illustrating another current.
  • Embodiments of the invention encompass memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. Example embodiments of such methods, memory cells, and memory devices are described with reference to Figs. 1-6.
  • Random access memories may use resistive states of a memory element to store one or more bits of information.
  • a memory element capable of being configured in either a high-resistance state or a low-resistance state may store one bit of information by associating a bit value of " 1" with the low- resistance state and a bit value of "0" with the high-resistance state.
  • bit value of "1" may be associated with the high-resistance state and a bit value of "0" may be associated with the low-resistance state.
  • the memory element may include a bipolar memory material.
  • a positive voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a high-resistance state to a low-resistance state.
  • a negative voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a low-resistance state to a high-resistance state.
  • a negative voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a high-resistance state to a low-resistance state and a positive voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a low-resistance state to a high-resistance.
  • a bipolar memory material may be configured in a first resistive state using a voltage having a first polarity and may be configured in a second resistive state using a voltage having a polarity opposite that of the first polarity.
  • bipolar memory material examples include ionic conducting chalcogenides, binary metal oxides, perovskite oxides, colossal magnetoresistives, and polymers.
  • Example ionic conducting chalcogenides that may be used as bipolar memory material include GeS, GeSe and Ag or Cu-doped GeS and GeSe.
  • Example binary metal oxides that may be used as bipolar memory material include HfO x , Nb 2 O 5 , Al 2 O 3 , WOx, Ta 2 O 5 , TiO x , ZrO x , Cu x O, and Ni x O.
  • Example ionic perovskite oxides that may be used as bipolar memory material include doped or undoped SrTiO 3 , SrZrO 3 , BaTiO 3 .
  • Example colossal magnetoresistives that may be used as bipolar memory material include Pr 1 ⁇ Ca x MnO 3 (PCMO), La 1-x Ca x MnO 3 (LCMO), and Ba 1 . xSr x TiO 3 .
  • Example polymers that may be used as bipolar memory material include Bengala Rose, AlQ 3 Ag, Cu-TCNQ, DDQ, TAPA, and fluorescine-based polymers. Of course, other materials may be used as bipolar memory material. The materials listed above are provided by way of example rather than as an exhaustive list of bipolar memory material. Referring to Fig.
  • a chart 100 depicts one example of a relationship 102 between voltages applied to a memory element initially in a high-resistance state and currents through the memory element resulting from the voltages.
  • the memory element may comprise one or more of the bipolar memory materials described above.
  • Chart 100 illustrates that as voltages applied to the memory element increase from -0.6 V to 0.2 V, no current, or a negligible amount of current, for example less than 1 micro amp, flows through the memory element. However, at a voltage substantially equal to a turn-on voltage 104, the memory element begins conducting current. As the voltage across the memory element is increased beyond turn-on voltage 104, the amount of current conducted by the memory element increases with the voltage without current clamping. The flattening of the current with voltage depicted in Fig. 1 results from current clamping of a measurement circuit.
  • chart 100 illustrates a change in the resistive state of the memory element.
  • the memory element is in a high-resistance state as evidenced by the fact that the memory element does not conduct current or conducts a negligible amount of current when voltages smaller than the turn-on voltage are applied to the memory element.
  • the memory element may have a resistance of about or above 10 9 ohms.
  • the memory element configures itself in a low-resistance state as evidenced by the fact that the memory element begins conducting current.
  • the memory element may be highly conductive and have a resistance of about a few thousand ohms.
  • a chart 200 depicts one example of a relationship 202 between voltages applied to a memory element initially in the low-resistance state described above and currents running through the memory element resulting from the voltages.
  • Chart 200 illustrates that currents resulting from voltages greater than about 0.25 V are substantially the same, which results from current clamping of a measurement circuit. Without the current clamping, the current increases with voltage. As the voltage is decreased below about 0.25 V, the current through the memory element accordingly decreases. As the voltage applied across the memory element becomes negative, the current through the memory element is also negative. However, when the voltage applied across the memory element is substantially equal to a turn-off voltage 204, the amount of current through the memory element is substantially zero. As the voltage is further decreased below the turn-off voltage, the current through the memory element remains substantially zero.
  • chart 200 illustrates a change in resistive state of the memory element.
  • the memory element is in the low-resistance state as evidenced by the fact that the memory element conducts current when voltages greater than turn-off voltage 204 are applied to the memory element.
  • the memory element configures itself in the high-resistance state described above as evidenced by the fact that the memory element stops conducting current or conducts only a negligible amount of current.
  • the memory element may remain in the high-resistance state as long as a voltage greater than or equal to turn-on voltage 104 is not applied to the memory element.
  • the memory element may remain in the high-resistance state even if no voltage is applied to the memory element. Accordingly, the high-resistance state of the memory element may be described as non-volatile since the high-resistance state might not change over time as long as a voltage greater than or equal to turn-on voltage 104 is not applied to the memory element. Similarly, in some cases, once configured in the low-resistance state, the memory element may remain in the low-resistance state as long as a voltage less than or equal to turn-off voltage 204 is not applied to the memory element. In fact, the memory element may remain in the low-resistance state even if no voltage is applied to the memory element. Accordingly, the low-resistance state of the memory element may also be described as non-volatile since the low- resistance state might not change over time as long as a voltage less than or equal to turn-off voltage 204 is not applied to the memory element.
  • the memory element may be used to store one bit information.
  • a memory element may represent a bit value of "0" when configured in the high-resistance state and may represent a bit value of "1" when configured in the low-resistance state.
  • the resistive state of the memory element may be repeatedly changed over time. Accordingly, the memory element may be in the high-resistance state representing a bit value of "0" at one moment in time and the memory element may be in a low-resistance state representing a bit value of "1” at another moment in time.
  • the representation of bit value with resistance states can be the opposite of that described above. Referring to Fig.
  • Memory cell 300 includes a memory element 302 having electrodes 306 and 304.
  • Memory element 302 may comprise a bipolar memory material such as one or more of the bipolar memory materials discussed above.
  • Memory cell 300 also includes a wordline 308 and two bitlines 314 and 316. Electrode 304 of memory element 302 is connected to a wordline 308.
  • Bitline 314 may be selectively electrically connected to memory element 302.
  • a diode 310 may be connected to bitline 314 and to electrode 306.
  • diode 310 When diode 310 is forward biased (e.g. , forward biased beyond a cut-in voltage of diode 310), diode 310 may conduct current from bitline 314 to memory element 302, thereby electrically connecting bitline 314 to memory element 302.
  • diode 310 when diode 310 is not forward biased (e.g., when diode 310 is reverse biased), diode 310 may hinder current from flowing from memory element 302 to bitline 314 or from bitline 314 to memory element 302 so that memory element 302 is not electrically connected to bitline 314.
  • bitline 316 may be selectively electrically connected to memory element 302.
  • a diode 312 may be connected to bitline 316 and to electrode 306.
  • diode 312 When diode 312 is forward biased (e.g. , forward biased beyond a cut-in voltage of diode 312), diode 312 may conduct current from memory element 302 to bitline 316 thereby electrically connecting memory element 302 to bitline 316.
  • diode 312 when diode 312 is not forward biased (e.g., when diode 312 is reverse biased), diode 312 may hinder current from flowing from bitline 316 to memory element 302 or from memory element 302 to bitline 316 so that memory element 302 is not electrically connected to bitline 316.
  • a memory cell may comprise one or more devices that selectively electrically connect a memory element to a first bitline and/or a second bitline instead of diodes.
  • memory element 300 may use a first transistor in place of diode 310 and a second transistor in place of diode 312. When turned on, the first transistor may allow current to flow between bitline 314 and memory element 302, electrically connecting bitline 314 and memory element 302. When turned off, the first transistor may hinder current from flowing between bitline 314 and memory element 302 thereby electrically disconnecting bitline 314 and memory element 302.
  • the second transistor may selectively electrically connect memory element 302 to bitline 316.
  • Devices other than diodes or transistors may alternatively be used to selectively electrically connect memory element 302 to bitlines 314 and 316.
  • Memory cell 300 may store a bit of information via a resistive state of memory element 302.
  • the bit may have a value of "0" or a value of "1.”
  • the value of the bit stored by memory cell 300 may be "0" and if memory element 302 is in a low-resistance state, the value of the bit stored by memory cell 300 may be "1.”
  • a convention in which a high-resislance state represents a bit value of " 1" and a low-resistance state represents a bit value of "0” may alternatively be used.
  • a read operation may be used to determine a value of a bit stored by memory cell 300.
  • a first positive voltage may be applied between wordline 308 and bitline 316 so that wordline 308 is at a higher potential than bitline 316 and so that diode 312 is forward biased.
  • the first positive voltage may be greater than a cut-in voltage of diode 312 but less than a sum of the cut-in voltage of diode 312 and the turn-off voltage (which was described above in relation to Fig. T) of memory element 302 so that the resistive state of memory element 302 is not altered.
  • a second positive voltage may be simultaneously applied between wordline 308 and bitline 314 so that wordline 308 is at a higher potential than bitline 314 and so that diode 310 is reverse biased.
  • the second voltage may be lower than a breakdown voltage of diode 310.
  • the first voltage and the second voltage may be substantially the same voltage.
  • memory element 302 If memory element 302 is configured in a low-resistance state, current may flow from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316. Based on the current, a memory device comprising memory cell 300 may determine that memory element 302 is in a low-resistance state and therefore the value stored by memory cell 300 is a "1." For example, the memory device may compare the current on bitline 316 with a reference current or the memory device may use the current on bitline 316 to create a voltage and may then compare the voltage with a reference voltage.
  • memory element 302 may hinder current from flowing from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316.
  • memory element 302 may restrict an amount of current flowing from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316 to a negligible amount of current that may be clearly distinguished from an amount of current allowed to flow when memory element 302 is in the low-resistance state.
  • the memory device comprising memory cell 300 may determine that memory element 302 is in the high-resistance state and therefore the value stored by memory cell 300 is a "0."
  • a first positive voltage may be applied between bitline 314 and wordline 308 so that bitline 314 is at a higher potential than wordline 308 and so that diode 310 is forward biased.
  • the first positive voltage may be greater than the cut-in voltage of diode 310 but less than a sum of the cut-in voltage of diode 310 and the turn-on voltage (which was described above in relation to Fig. 1) of memory element 302 so that the resistive state of memory element 302 is not altered.
  • a second positive voltage may simultaneously be applied between bitline 316 and wordline 308 so that bitline 316 is at a higher potential than wordline 308 and so that diode 312 is reverse biased.
  • the second voltage may be lower than a breakdown voltage of diode 312.
  • the first voltage and the second voltage may be substantially the same voltage.
  • memory element 302 If memory element 302 is configured in a low-resistance state, current may flow from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308. Based on the current on wordline 308, a memory device comprising memory cell 300 may determine that memory element 302 is in a low-resistance state and therefore the value stored by memory cell 300 is a " 1.”
  • memory element 302 may hinder current from flowing from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308.
  • memory element 302 may restrict an amount of current flowing from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308 to a negligible amount that may be clearly distinguished from an amount of current allowed to flow when memory element 302 is in the low- resistance state.
  • the memory device comprising memory cell 300 may determine that memory element 302 is in the high-resistance state and therefore the value stored by memory cell 300 is a "0.”
  • a bil value may be written to memory cell 300.
  • a first positive voltage may be applied between bitline 314 and wordline 308 so that bitline 314 is at a higher potential than wordline 308 and so that diode 310 is forward biased.
  • the first positive voltage may be greater than a sum of the cut-in voltage of diode 310 and the turn-on voltage of memory element 302.
  • the first voltage (or a current resulting from the first voltage) may re-configure memory element 302 to be in a low-resistance state. If memory element 302 is already in a low-resistance state, memory element 302 may remain in the low-resistance state.
  • memory element 302 may be configured in a low-resistance state corresponding with a bit value of "1."
  • a second positive voltage may be applied simultaneously with the first voltage.
  • the second positive voltage may be applied between bitline 316 and wordline 308 so that bitline 316 is at a higher potential than wordline 308 and so that diode 312 is reverse biased.
  • the second voltage may hinder current from flowing from bitline 314 to bitline 316.
  • the second voltage may be lower than a breakdown voltage of diode 312.
  • the first voltage may result from a first voltage pulse and the second voltage may result from a second voltage pulse.
  • the first voltage and the second voltage may be substantially the same voltage.
  • a bit value of "0" may be written to memory cell 300.
  • a first positive voltage may be applied between wordline 308 and bitline 316 so that wordline 308 is at a higher potential than bitline 316 and so that diode 312 is forward biased.
  • the first positive voltage may be greater than a sum of the cut-in voltage of diode 312 and the turn-off voltage of memory element 302. If memory element 302 is in a low-resistance state, the first voltage (or a current resulting from the first voltage) may re-configure memory element 302 to be in a high-resistance state.
  • memory element 302 may remain in the high-resistance state. Consequently, due to the first voltage, memory element 302 may be configured in a high-resistance state corresponding with a bit value of "0.”
  • a second positive voltage may be applied simultaneously with the first voltage.
  • the second positive voltage may be applied between wordline 308 and bitline 314 so that wordline 308 is at a higher potential than bitline 314 and so that diode 310 is reverse biased.
  • the second voltage may hinder current from flowing from bitline 316 to bitline 314.
  • the second voltage may be lower than a breakdown voltage of diode 310.
  • the first voltage may result from a first voltage pulse and the second voltage may result from a second voltage pulse.
  • the first voltage and the second voltage may be substantially the same voltage.
  • memory element 302 may be re-written using these methods millions of times without damaging memory element 302. Since memory element 302 may remain in a resistive state without a voltage or current being applied to memory element 302 as was discussed above in relation to Fig. 1 , memory element 302 may be said to preserve a bit value in a non-volatile manner. Accordingly, memory cell 300 may store a bit of information without having to be frequently refreshed or memory cell 300 may be refreshed at a rate lower than a rate used to refresh a volatile memory cell.
  • the memory device includes memory cell 300 as well as additional memory cells 402, 404, 406, 408, 410, 412, 414, and 416.
  • the memory device may store a plurality of bits. For example, the memory device may store one bit in each memory cell of the memory device.
  • the memory cells of the memory device may be arranged to share bitlines and wordlines.
  • memory cells 402, 408, and 412 share wordline 418; memory cells 404, 300, and 414 share wordline 308; and memory cells 406, 410, and 416 share wordline 420.
  • memory cells 402, 404, and 406 share bitlines 424 and 426; memory cells 408, 300, and 410 share bitlines 314 and 316; and memory cells 412, 414, and 416 share bitlines 428 and 430.
  • FIG. 5 a schematic diagram 500 illustrating a configuration of the memory device of Fig. 4 is illustrated.
  • the configuration may be used to write a bit value of " 1" to memory cell 300 or to read a bit of information from memory cell 300.
  • a first positive voltage is applied across bitline 314 and wordline 308.
  • a second positive voltage is applied across bitline 316 and wordline 308. Consequently, a current may flow from bitline 314 through memory cell 300 to wordline 308 as illustrated by arrow 502 and as was described above in relation to Fig. 3.
  • the first voltage is greater than a sum of the cut-in voltage of diode 310 and the turn-on voltage of memory element 302, a " 1" may be written to memory cell 300 as was described above in relation to Fig. 3.
  • the memory device may determine the value of a bit stored by memory cell 300 based on a current flowing from bitline 314 to wordline 308 as was described above in relation to Fig. 3.
  • bitlines and wordlines of the memory device may be configured with particular voltages.
  • bitlines 314 and 316 may be at a higher potential than wordline 308. Since memory cells 408 and 410 are also connected to bitlines 314 and 316, wordlines 418 and 420 may be configured to be at substantially the same potential as bitlines 314 and 316 to hinder current from flowing from bitline 314 and/or bitline 316 to wordline 418 and/or wordline 420.
  • bitlines 424 and 428 may be configured to be at substantially the same potential as wordline 308 to hinder current from flowing from bitline 424 to wordline 308 via memory cell 404 and to hinder current from flowing from bitline 428 to wordline 308 via memory cell 414.
  • bitlines 426 and 430 may be configured at a higher potential than wordline 308 so that current is hindered from flowing from bitline 426 through memory cell 404 to wordline 308 and from bitline 430 through memory cell 414 to wordline 308.
  • bitlines 424 and 426 and wordlines 418 and 420 may be configured with voltages causing the diodes of memory cells
  • bitlines 428 and 430 and wordlines 418 and 420 may be configured with voltages causing the diodes of memory cells 412 and 416 to be reverse biased.
  • FIG. 6 a schematic diagram 600 illustrating a configuration of the memory device of Fig. 4 is illustrated.
  • the configuration may be used to write a bit value of "0" to memory cell 300 or to read a bit of information from memory cell 300.
  • a first positive voltage is applied across wordline 308 and bitline 316.
  • a second positive voltage is applied across wordline 308 and bitline 314. Consequently, a current may flow from wordline 308 through memory cell 300 to bitline 316 as indicated by arrow 602 and as was described above in relation to Fig. 3.
  • the memory device may determine the value of a bit stored by memory cell 300 based on a current flowing from wordline 308 to bitline 316 as was described above in relation to Fig. 3. It may be desirable to ensure that values stored by memory cells 402, 404,
  • bitlines and wordlines of the memory device may be configured with particular voltages.
  • bitlines 314 and 316 may be at a lower potential than wordline 308. Since memory cells 408 and 410 are also connected to bitlines 314 and 316, wordlines 418 and 420 may be configured to be at substantially the same potential as bitlines 314 and 316 to hinder current from flowing from wordline 418 and/or wordline 420 to bitline 314 and/or bitline 316.
  • bitlines 426 and 430 may be configured to be at substantially the same potential as wordline 308 to hinder current from flowing from wordline 308 to bitline 426 via memory cell 404 and to hinder current from flowing from wordline 308 to bitline 430 via memory cell 414.
  • bitlines 424 and 428 may be configured at a lower potential than wordline 308 so that current is hindered from flowing from bitline 424 to wordline 308 through memory cell 404 and from bitline 428 to wordline 308 through memory cell 414.
  • bitlines 424 and 428 may be configured at the same potential as wordlines 418 and 420 to hinder current from flowing through left-hand diodes of memory cells 402, 406, 412, and 416.
  • bitlines 426 and 430 and wordlines 418 and 420 may be configured to reverse bias right-hand diodes of memory cells 402, 406, 412, and 416.
  • memory element 302 is configured so that memory element 302 changes to a low-resistance state when a voltage greater than the turn-on voltage of memory element 302 is applied between electrodes 306 and 304 so that electrode 306 is at a higher potential than electrode 304.
  • memory element 302 changes to a high-resistance state when a voltage greater than the turn-off voltage of memory element 302 is applied across electrodes 304 and 306 so that electrode 304 is at a higher potential than electrode 306.
  • memory element 302 may be reversed so that memory element 302 changes to a high-resistance state when a voltage greater than the turn-off voltage of memory element 302 is applied between electrodes 306 and 304 so that electrode 306 is at a higher potential than electrode 304.
  • memory element 302 may change to a low-resistance state when a voltage greater than the turn-on voltage of memory element 302is applied across electrodes 304 and 306 so that electrode 304 is at a higher potential than electrode 306.
  • memory devices may be constructed based on an understanding that the high-resistance state of memory element 302 corresponds to a bit value of "1” and that the low-resistance state of memory element 302 corresponds to a bit value of "0" without changing the principles of writing and reading memory cell 300.
  • a memory element having a high resistance state and a low resistance state.
  • a memory element may be configurable in more than two different resistive states.
  • Such a memory element may store more than one bit of information and may be used in a memory cell such as memory cell 300.
  • Each of a plurality of different programming voltages may correspond to a different one of a plurality of different resistive states of the memory element.
  • the methods of programming memory cell 300 described above may be adapted to program a memory element having more than one resistive state by applying one of the plurality of programming voltages to the memory element in order to configure the memory element in the resistive state corresponding to the applied programming voltage. Furthermore, the methods of reading memory cell 300 described above may be adapted to read the memory element by comparing a current resulting from a voltage applied to the memory element to a plurality of different reference currents to determine in which of the plurality of different resistive states the memory cell is configured.

Abstract

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Description

Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
TECHNICAL FIELD Embodiments disclosed herein pertain to memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices.
BACKGROUND Resistive random access memories may use a material capable of being configured in one of two different resistive states to store information. When configured in one of the resistive states, the material may have a high resistance to electrical current. In contrast, when configured in the other resistive state, the material may have a low resistance to electrical current. The resistive state in which the material is configured may be changed using electrical signals. For example, if the material is in a high-resistance state, the material may be configured to be in a low-resistance state by applying a voltage across the material.
The resistive state may be persistent. For example, once configured in a resistive state, the material may stay in the resistive state even if neither a current nor a voltage is applied to the material. Furthermore, the configuration of the material may be repeatedly changed from the high resistance state to the low resistance state or from the low resistance state to the high resistance state.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a chart illustrating voltage/current relationships.
Fig. 2 is chart illustrating other voltage/current relationships.
Fig. 3 is a schematic diagram of a memory cell.
Fig. 4 is a schematic diagram of a memory device.
Fig. 5 is a schematic diagram of a memory device illustrating a current.
Fig. 6 is a schematic diagram of a memory device illustrating another current.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
Embodiments of the invention encompass memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. Example embodiments of such methods, memory cells, and memory devices are described with reference to Figs. 1-6.
Random access memories may use resistive states of a memory element to store one or more bits of information. For example, a memory element capable of being configured in either a high-resistance state or a low-resistance state may store one bit of information by associating a bit value of " 1" with the low- resistance state and a bit value of "0" with the high-resistance state.
Alternatively, a bit value of "1" may be associated with the high-resistance state and a bit value of "0" may be associated with the low-resistance state.
The memory element may include a bipolar memory material. A positive voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a high-resistance state to a low-resistance state. Furthermore, a negative voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a low-resistance state to a high-resistance state.
Alternatively, a negative voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a high-resistance state to a low-resistance state and a positive voltage applied across the bipolar memory material may change the configuration of the bipolar memory material from a low-resistance state to a high-resistance. Accordingly, a bipolar memory material may be configured in a first resistive state using a voltage having a first polarity and may be configured in a second resistive state using a voltage having a polarity opposite that of the first polarity.
Examples of bipolar memory material include ionic conducting chalcogenides, binary metal oxides, perovskite oxides, colossal magnetoresistives, and polymers. Example ionic conducting chalcogenides that may be used as bipolar memory material include GeS, GeSe and Ag or Cu-doped GeS and GeSe. Example binary metal oxides that may be used as bipolar memory material include HfOx, Nb2O5, Al2O3, WOx, Ta2O5, TiOx, ZrOx, CuxO, and NixO. Example ionic perovskite oxides that may be used as bipolar memory material include doped or undoped SrTiO3, SrZrO3, BaTiO3.
Example colossal magnetoresistives that may be used as bipolar memory material include Pr1^CaxMnO3 (PCMO), La1-xCaxMnO3 (LCMO), and Ba1. xSrxTiO3. Example polymers that may be used as bipolar memory material include Bengala Rose, AlQ3Ag, Cu-TCNQ, DDQ, TAPA, and fluorescine-based polymers. Of course, other materials may be used as bipolar memory material. The materials listed above are provided by way of example rather than as an exhaustive list of bipolar memory material. Referring to Fig. 1 , a chart 100 depicts one example of a relationship 102 between voltages applied to a memory element initially in a high-resistance state and currents through the memory element resulting from the voltages. The memory element may comprise one or more of the bipolar memory materials described above. Chart 100 illustrates that as voltages applied to the memory element increase from -0.6 V to 0.2 V, no current, or a negligible amount of current, for example less than 1 micro amp, flows through the memory element. However, at a voltage substantially equal to a turn-on voltage 104, the memory element begins conducting current. As the voltage across the memory element is increased beyond turn-on voltage 104, the amount of current conducted by the memory element increases with the voltage without current clamping. The flattening of the current with voltage depicted in Fig. 1 results from current clamping of a measurement circuit.
Thus, chart 100 illustrates a change in the resistive state of the memory element. Initially, the memory element is in a high-resistance state as evidenced by the fact that the memory element does not conduct current or conducts a negligible amount of current when voltages smaller than the turn-on voltage are applied to the memory element. In this high-resistance state, the memory element may have a resistance of about or above 109 ohms. However, once a voltage greater than or equal to turn-on voltage 104 is applied to the memory element, the memory element configures itself in a low-resistance state as evidenced by the fact that the memory element begins conducting current. In this low-resistance state, the memory element may be highly conductive and have a resistance of about a few thousand ohms.
Referring to Fig. 2, a chart 200 depicts one example of a relationship 202 between voltages applied to a memory element initially in the low-resistance state described above and currents running through the memory element resulting from the voltages. Chart 200 illustrates that currents resulting from voltages greater than about 0.25 V are substantially the same, which results from current clamping of a measurement circuit. Without the current clamping, the current increases with voltage. As the voltage is decreased below about 0.25 V, the current through the memory element accordingly decreases. As the voltage applied across the memory element becomes negative, the current through the memory element is also negative. However, when the voltage applied across the memory element is substantially equal to a turn-off voltage 204, the amount of current through the memory element is substantially zero. As the voltage is further decreased below the turn-off voltage, the current through the memory element remains substantially zero.
Thus, chart 200 illustrates a change in resistive state of the memory element. Initially, the memory element is in the low-resistance state as evidenced by the fact that the memory element conducts current when voltages greater than turn-off voltage 204 are applied to the memory element. However, once a voltage less than or equal to turn-off voltage 204 is applied to the memory element, the memory element configures itself in the high-resistance state described above as evidenced by the fact that the memory element stops conducting current or conducts only a negligible amount of current. In some cases, once configured in the high-resistance state, the memory element may remain in the high-resistance state as long as a voltage greater than or equal to turn-on voltage 104 is not applied to the memory element. The memory element may remain in the high-resistance state even if no voltage is applied to the memory element. Accordingly, the high-resistance state of the memory element may be described as non-volatile since the high-resistance state might not change over time as long as a voltage greater than or equal to turn-on voltage 104 is not applied to the memory element. Similarly, in some cases, once configured in the low-resistance state, the memory element may remain in the low-resistance state as long as a voltage less than or equal to turn-off voltage 204 is not applied to the memory element. In fact, the memory element may remain in the low-resistance state even if no voltage is applied to the memory element. Accordingly, the low-resistance state of the memory element may also be described as non-volatile since the low- resistance state might not change over time as long as a voltage less than or equal to turn-off voltage 204 is not applied to the memory element.
Since the high-resistance state and the low-resistance state may be non- volatile, the memory element may be used to store one bit information. For example, a memory element may represent a bit value of "0" when configured in the high-resistance state and may represent a bit value of "1" when configured in the low-resistance state. Furthermore, the resistive state of the memory element may be repeatedly changed over time. Accordingly, the memory element may be in the high-resistance state representing a bit value of "0" at one moment in time and the memory element may be in a low-resistance state representing a bit value of "1" at another moment in time. Similarly, the representation of bit value with resistance states can be the opposite of that described above. Referring to Fig. 3, a memory cell 300 is illustrated. Memory cell 300 includes a memory element 302 having electrodes 306 and 304. Memory element 302 may comprise a bipolar memory material such as one or more of the bipolar memory materials discussed above. Memory cell 300 also includes a wordline 308 and two bitlines 314 and 316. Electrode 304 of memory element 302 is connected to a wordline 308.
Bitline 314 may be selectively electrically connected to memory element 302. For example, a diode 310 may be connected to bitline 314 and to electrode 306. When diode 310 is forward biased (e.g. , forward biased beyond a cut-in voltage of diode 310), diode 310 may conduct current from bitline 314 to memory element 302, thereby electrically connecting bitline 314 to memory element 302. In contrast, when diode 310 is not forward biased (e.g., when diode 310 is reverse biased), diode 310 may hinder current from flowing from memory element 302 to bitline 314 or from bitline 314 to memory element 302 so that memory element 302 is not electrically connected to bitline 314. Similarly, bitline 316 may be selectively electrically connected to memory element 302. For example, a diode 312 may be connected to bitline 316 and to electrode 306. When diode 312 is forward biased (e.g. , forward biased beyond a cut-in voltage of diode 312), diode 312 may conduct current from memory element 302 to bitline 316 thereby electrically connecting memory element 302 to bitline 316. In contrast, when diode 312 is not forward biased (e.g., when diode 312 is reverse biased), diode 312 may hinder current from flowing from bitline 316 to memory element 302 or from memory element 302 to bitline 316 so that memory element 302 is not electrically connected to bitline 316.
In some configurations, a memory cell may comprise one or more devices that selectively electrically connect a memory element to a first bitline and/or a second bitline instead of diodes. For example, in one configuration, memory element 300 may use a first transistor in place of diode 310 and a second transistor in place of diode 312. When turned on, the first transistor may allow current to flow between bitline 314 and memory element 302, electrically connecting bitline 314 and memory element 302. When turned off, the first transistor may hinder current from flowing between bitline 314 and memory element 302 thereby electrically disconnecting bitline 314 and memory element 302.
Similarly, the second transistor may selectively electrically connect memory element 302 to bitline 316. Devices other than diodes or transistors may alternatively be used to selectively electrically connect memory element 302 to bitlines 314 and 316.
Memory cell 300 may store a bit of information via a resistive state of memory element 302. In one configuration, the bit may have a value of "0" or a value of "1." For example, according to one convention, if memory element 302 is in a high-resistance state, the value of the bit stored by memory cell 300 may be "0" and if memory element 302 is in a low-resistance state, the value of the bit stored by memory cell 300 may be "1." Of course, a convention in which a high-resislance state represents a bit value of " 1" and a low-resistance state represents a bit value of "0" may alternatively be used.
A read operation may be used to determine a value of a bit stored by memory cell 300. According to one read operation, a first positive voltage may be applied between wordline 308 and bitline 316 so that wordline 308 is at a higher potential than bitline 316 and so that diode 312 is forward biased. The first positive voltage may be greater than a cut-in voltage of diode 312 but less than a sum of the cut-in voltage of diode 312 and the turn-off voltage (which was described above in relation to Fig. T) of memory element 302 so that the resistive state of memory element 302 is not altered. A second positive voltage may be simultaneously applied between wordline 308 and bitline 314 so that wordline 308 is at a higher potential than bitline 314 and so that diode 310 is reverse biased. The second voltage may be lower than a breakdown voltage of diode 310. In some cases, the first voltage and the second voltage may be substantially the same voltage.
If memory element 302 is configured in a low-resistance state, current may flow from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316. Based on the current, a memory device comprising memory cell 300 may determine that memory element 302 is in a low-resistance state and therefore the value stored by memory cell 300 is a "1." For example, the memory device may compare the current on bitline 316 with a reference current or the memory device may use the current on bitline 316 to create a voltage and may then compare the voltage with a reference voltage.
In contrast, if memory element 302 is configured in a high-resistance state, memory element 302 may hinder current from flowing from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316. Alternatively, memory element 302 may restrict an amount of current flowing from wordline 308 through memory element 302 and forward-biased diode 312 to bitline 316 to a negligible amount of current that may be clearly distinguished from an amount of current allowed to flow when memory element 302 is in the low-resistance state. Based on the lack of current, or the very small amount of current, the memory device comprising memory cell 300 may determine that memory element 302 is in the high-resistance state and therefore the value stored by memory cell 300 is a "0."
Another method of reading memory cell 300 may alternatively be used. According to this method, a first positive voltage may be applied between bitline 314 and wordline 308 so that bitline 314 is at a higher potential than wordline 308 and so that diode 310 is forward biased. The first positive voltage may be greater than the cut-in voltage of diode 310 but less than a sum of the cut-in voltage of diode 310 and the turn-on voltage (which was described above in relation to Fig. 1) of memory element 302 so that the resistive state of memory element 302 is not altered. A second positive voltage may simultaneously be applied between bitline 316 and wordline 308 so that bitline 316 is at a higher potential than wordline 308 and so that diode 312 is reverse biased. The second voltage may be lower than a breakdown voltage of diode 312. In some cases, the first voltage and the second voltage may be substantially the same voltage.
If memory element 302 is configured in a low-resistance state, current may flow from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308. Based on the current on wordline 308, a memory device comprising memory cell 300 may determine that memory element 302 is in a low-resistance state and therefore the value stored by memory cell 300 is a " 1."
In contrast, if memory element 302 is configured in a high-resistance state, memory element 302 may hinder current from flowing from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308. Alternatively, memory element 302 may restrict an amount of current flowing from bitline 314 through forward-biased diode 310 and memory element 302 to wordline 308 to a negligible amount that may be clearly distinguished from an amount of current allowed to flow when memory element 302 is in the low- resistance state. Based on the lack of current, or the very small amount of current, the memory device comprising memory cell 300 may determine that memory element 302 is in the high-resistance state and therefore the value stored by memory cell 300 is a "0." In addition to reading a bit value from memory cell 300, a bil value may be written to memory cell 300. To write a bit value of "1" to memory cell 300, a first positive voltage may be applied between bitline 314 and wordline 308 so that bitline 314 is at a higher potential than wordline 308 and so that diode 310 is forward biased. The first positive voltage may be greater than a sum of the cut-in voltage of diode 310 and the turn-on voltage of memory element 302. If memory element 302 is in a high-resistance state, the first voltage (or a current resulting from the first voltage) may re-configure memory element 302 to be in a low-resistance state. If memory element 302 is already in a low-resistance state, memory element 302 may remain in the low-resistance state.
Consequently, due to the first voltage, memory element 302 may be configured in a low-resistance state corresponding with a bit value of "1."
A second positive voltage may be applied simultaneously with the first voltage. The second positive voltage may be applied between bitline 316 and wordline 308 so that bitline 316 is at a higher potential than wordline 308 and so that diode 312 is reverse biased. The second voltage may hinder current from flowing from bitline 314 to bitline 316. The second voltage may be lower than a breakdown voltage of diode 312.
The first voltage may result from a first voltage pulse and the second voltage may result from a second voltage pulse. In some cases, the first voltage and the second voltage may be substantially the same voltage.
Alternatively, a bit value of "0" may be written to memory cell 300. To write a bit value of "0" to memory cell 300, a first positive voltage may be applied between wordline 308 and bitline 316 so that wordline 308 is at a higher potential than bitline 316 and so that diode 312 is forward biased. The first positive voltage may be greater than a sum of the cut-in voltage of diode 312 and the turn-off voltage of memory element 302. If memory element 302 is in a low-resistance state, the first voltage (or a current resulting from the first voltage) may re-configure memory element 302 to be in a high-resistance state. If memory element 302 is already in a high-resistance state, memory element 302 may remain in the high-resistance state. Consequently, due to the first voltage, memory element 302 may be configured in a high-resistance state corresponding with a bit value of "0."
A second positive voltage may be applied simultaneously with the first voltage. The second positive voltage may be applied between wordline 308 and bitline 314 so that wordline 308 is at a higher potential than bitline 314 and so that diode 310 is reverse biased. The second voltage may hinder current from flowing from bitline 316 to bitline 314. The second voltage may be lower than a breakdown voltage of diode 310.
The first voltage may result from a first voltage pulse and the second voltage may result from a second voltage pulse. In some cases, the first voltage and the second voltage may be substantially the same voltage.
The methods of writing a "0" and writing a "1 " to memory cell 300 may be repeatedly used so that memory cell 300 stores different bit values over time. In some cases, memory element 302 may be re-written using these methods millions of times without damaging memory element 302. Since memory element 302 may remain in a resistive state without a voltage or current being applied to memory element 302 as was discussed above in relation to Fig. 1 , memory element 302 may be said to preserve a bit value in a non-volatile manner. Accordingly, memory cell 300 may store a bit of information without having to be frequently refreshed or memory cell 300 may be refreshed at a rate lower than a rate used to refresh a volatile memory cell.
Referring to Fig. 4, a schematic diagram 400 of a portion of a memory device is illustrated. The memory device includes memory cell 300 as well as additional memory cells 402, 404, 406, 408, 410, 412, 414, and 416. The memory device may store a plurality of bits. For example, the memory device may store one bit in each memory cell of the memory device.
The memory cells of the memory device may be arranged to share bitlines and wordlines. In diagram 400, memory cells 402, 408, and 412 share wordline 418; memory cells 404, 300, and 414 share wordline 308; and memory cells 406, 410, and 416 share wordline 420. Furthermore, in diagram 400, memory cells 402, 404, and 406 share bitlines 424 and 426; memory cells 408, 300, and 410 share bitlines 314 and 316; and memory cells 412, 414, and 416 share bitlines 428 and 430.
Referring to Fig. 5, a schematic diagram 500 illustrating a configuration of the memory device of Fig. 4 is illustrated. The configuration may be used to write a bit value of " 1" to memory cell 300 or to read a bit of information from memory cell 300. According to the configuration, a first positive voltage is applied across bitline 314 and wordline 308. A second positive voltage is applied across bitline 316 and wordline 308. Consequently, a current may flow from bitline 314 through memory cell 300 to wordline 308 as illustrated by arrow 502 and as was described above in relation to Fig. 3. If the first voltage is greater than a sum of the cut-in voltage of diode 310 and the turn-on voltage of memory element 302, a " 1" may be written to memory cell 300 as was described above in relation to Fig. 3.
Alternatively, if the first voltage is greater than the cut-in voltage of diode 310 but less than a sum of the cut-in voltage of the diode and the turn-on voltage of memory element 302, the memory device may determine the value of a bit stored by memory cell 300 based on a current flowing from bitline 314 to wordline 308 as was described above in relation to Fig. 3.
It may be desirable to ensure that values stored by memory cells 402, 404, 406, 408, 410, 412, 414, and 416 are not disturbed while writing or reading memory cell 300. To avoid disturbances, bitlines and wordlines of the memory device may be configured with particular voltages.
For example, when writing a "1" into memory cell 300, bitlines 314 and 316 may be at a higher potential than wordline 308. Since memory cells 408 and 410 are also connected to bitlines 314 and 316, wordlines 418 and 420 may be configured to be at substantially the same potential as bitlines 314 and 316 to hinder current from flowing from bitline 314 and/or bitline 316 to wordline 418 and/or wordline 420.
Furthermore, it may be desirable to hinder currents from flowing from memory cells 404 and 414 onto wordline 308 so that a current on wordline 308 may be correctly attributed to memory cell 300. To do so, bitlines 424 and 428 may be configured to be at substantially the same potential as wordline 308 to hinder current from flowing from bitline 424 to wordline 308 via memory cell 404 and to hinder current from flowing from bitline 428 to wordline 308 via memory cell 414. In addition, bitlines 426 and 430 may be configured at a higher potential than wordline 308 so that current is hindered from flowing from bitline 426 through memory cell 404 to wordline 308 and from bitline 430 through memory cell 414 to wordline 308.
Other memory cells not connected to either wordline 308 or bitlines 314 and 316 (i.e., memory cells 402, 406, 412, and 416) may be configured to hinder consumption of current. For example, bitlines 424 and 426 and wordlines 418 and 420 may be configured with voltages causing the diodes of memory cells
402 and 406 to be reverse biased. Similarly, bitlines 428 and 430 and wordlines 418 and 420 may be configured with voltages causing the diodes of memory cells 412 and 416 to be reverse biased.
Referring to Fig. 6, a schematic diagram 600 illustrating a configuration of the memory device of Fig. 4 is illustrated. The configuration may be used to write a bit value of "0" to memory cell 300 or to read a bit of information from memory cell 300. According to the configuration, a first positive voltage is applied across wordline 308 and bitline 316. A second positive voltage is applied across wordline 308 and bitline 314. Consequently, a current may flow from wordline 308 through memory cell 300 to bitline 316 as indicated by arrow 602 and as was described above in relation to Fig. 3. If the first voltage is greater than a sum of the cut-in voltage of diode 312 and the turn-off voltage of memory element 302, a "0" may be written to memory cell 300 as was described above in relation to Fig. 3. Alternatively, if the first voltage is greater than the cut-in voltage of diode 312 but less than a sum of the cut-in voltage of diode and the turn-off voltage of memory element 302, the memory device may determine the value of a bit stored by memory cell 300 based on a current flowing from wordline 308 to bitline 316 as was described above in relation to Fig. 3. It may be desirable to ensure that values stored by memory cells 402, 404,
406, 408, 410, 412, 414, and 416 are not disturbed while writing or reading memory cell 300. To avoid disturbances, bitlines and wordlines of the memory device may be configured with particular voltages.
For example, when writing a "0" into memory cell 300, bitlines 314 and 316 may be at a lower potential than wordline 308. Since memory cells 408 and 410 are also connected to bitlines 314 and 316, wordlines 418 and 420 may be configured to be at substantially the same potential as bitlines 314 and 316 to hinder current from flowing from wordline 418 and/or wordline 420 to bitline 314 and/or bitline 316.
Furthermore, it may be desirable to hinder currents from flowing from wordline 308 into memory cells 404 and 414. To do so, bitlines 426 and 430 may be configured to be at substantially the same potential as wordline 308 to hinder current from flowing from wordline 308 to bitline 426 via memory cell 404 and to hinder current from flowing from wordline 308 to bitline 430 via memory cell 414. In addition, bitlines 424 and 428 may be configured at a lower potential than wordline 308 so that current is hindered from flowing from bitline 424 to wordline 308 through memory cell 404 and from bitline 428 to wordline 308 through memory cell 414.
Other memory cells not connected to either wordline 308 or bitlines 314 and 316 (i.e., memory cells 402, 406, 412, and 416) may be configured to hinder consumption of current as is illustrated in Fig. 6. For example, bitlines 424 and 428 may be configured at the same potential as wordlines 418 and 420 to hinder current from flowing through left-hand diodes of memory cells 402, 406, 412, and 416. Furthermore, bitlines 426 and 430 and wordlines 418 and 420 may be configured to reverse bias right-hand diodes of memory cells 402, 406, 412, and 416.
The above discussion has assumed that memory element 302 is configured so that memory element 302 changes to a low-resistance state when a voltage greater than the turn-on voltage of memory element 302 is applied between electrodes 306 and 304 so that electrode 306 is at a higher potential than electrode 304. Similarly, the above discussion has assumed that memory element 302 changes to a high-resistance state when a voltage greater than the turn-off voltage of memory element 302 is applied across electrodes 304 and 306 so that electrode 304 is at a higher potential than electrode 306.
However, memory element 302 may be reversed so that memory element 302 changes to a high-resistance state when a voltage greater than the turn-off voltage of memory element 302 is applied between electrodes 306 and 304 so that electrode 306 is at a higher potential than electrode 304. In this configuration, memory element 302 may change to a low-resistance state when a voltage greater than the turn-on voltage of memory element 302is applied across electrodes 304 and 306 so that electrode 304 is at a higher potential than electrode 306.
Furthermore, the above discussion has assumed that a high-resistance state of memory element 302 corresponds to a bit value of "0" and that a low- resistance state of memory element 302 corresponds to a bit value of "1." However, as was mentioned above, memory devices may be constructed based on an understanding that the high-resistance state of memory element 302 corresponds to a bit value of "1" and that the low-resistance state of memory element 302 corresponds to a bit value of "0" without changing the principles of writing and reading memory cell 300.
The above discussion has referred to a memory element having a high resistance state and a low resistance state. However, in some embodiments of the invention, a memory element may be configurable in more than two different resistive states. Such a memory element may store more than one bit of information and may be used in a memory cell such as memory cell 300. Each of a plurality of different programming voltages may correspond to a different one of a plurality of different resistive states of the memory element.
The methods of programming memory cell 300 described above may be adapted to program a memory element having more than one resistive state by applying one of the plurality of programming voltages to the memory element in order to configure the memory element in the resistive state corresponding to the applied programming voltage. Furthermore, the methods of reading memory cell 300 described above may be adapted to read the memory element by comparing a current resulting from a voltage applied to the memory element to a plurality of different reference currents to determine in which of the plurality of different resistive states the memory cell is configured.

Claims

CLAIMS:
1. A memory cell comprising: a wordline; a first bitline; a second bitline; and a memory element electrically connected to the wordline and selectively electrically connected to the first bitline and to the second bitline, the memory element storing information via a resistive state of the memory element; wherein the memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
2. The memory cell of claim 1 wherein : the memory cell further comprises a first diode and a second diode ; the memory element comprises a first electrode connected to the first bitline via the first diode and to the second bitline via the second diode and a second electrode connected to the wordline; and the memory element is electrically connected to the first bitline via the first diode when the first diode is forward biased and is electrically disconnected from the first bitline when the first diode is not forward biased; and the memory element is electrically connected to the second bitline via the second diode when the second diode is forward biased and is electrically disconnected from the second bitline when the second diode is not forward biased.
3. The memory cell of claim 1 wherein the memory element comprises at least one of an ionic conducting chalcogenide, a binary metal oxide, a perovskite oxide, a colossal magnetoresistive, or a polymer.
4. The memory cell of claim 1 wherein the memory element is configured to store the information in a non-volatile manner in the absence of a voltage or a current.
5. A memory cell programming method comprising: providing a memory cell comprising a wordline, first and second bitlines, and a memory element, the memory element being electrically connected to the wordline and selectively electrically connected to the first and second bitlines ; using the memory element, storing information via a first resistive state of the memory element; applying a first voltage across the wordline and the first bitline effective to electrically disconnect the first bitline from the memory element; and applying a second voltage across the wordline and the second bitline effective to electrically connect the second bitline to the memory element and to configure the memory element in a different second resistive state.
6. The method of claim 5 further comprising: providing a first diode connected to a first electrode of the memory element and to the first bitline, the first diode being reverse biased due to the first voltage and the first voltage being less than a breakdown voltage of the first diode; and providing a second diode connected to the first electrode of the memory element and to the second bitline; wherein: a second electrode of the memory element is connected to the wordline; the memory element is highly conductive of current between the second electrode and the first electrode when the memory element is in the first resistive state; and the memory element is highly resistive of current between the second electrode and the first electrode when the memory element is in the second resistive state.
7. The method of claim 6 wherein the applied second voltage is greater than a sum of a turn-off voltage, of the memory element and a cut-in voltage of the. second diode.
8. The method of claim 5 wherein the applied first voltage is substantially the same as the applied second voltage.
9. The method of claim 5 further comprising subsequent to the applying of the first voltage and the applying of the second voltage: applying a third voltage across the second bitline and the wordline effective to electrically disconnect the second bitline from the memory element; and applying a fourth voltage across the first bitline and the wordline effective to electrically connect the first bitline to the memory element and to configure the memory element in the first resistive state.
10. The method of claim 9 wherein the applied third voltage is substantially the same as the applied fourth voltage.
1 1. A memory cell reading method comprising: providing a memory cell comprising a wordline, first and second bitlines, and a memory element electrically connected to the wordline and selectively electrically connected to the first and second bitlines, the memory element being disposed to be selectively configured in any of a plurality of different resistive states ; applying a first voltage across the wordline and the first bitline effective to electrically disconnect the first bitline from the memory element; applying a second voltage across the wordline and the second bitline effective to cause a current to flow from the wordline through the memory element to the second bitline; and based on the current, determining that the memory element is configured in a particular one of the plurality of different resistive states.
12. The method of claim 11 wherein the particular one of the plurality of different resistive states is associated with a value of a bit of information.
13. The method of claim 11 wherein the memory element is disposed to be selectively configured in either a high resistance state or a low resistance state.
14. The method of claim 11 further comprising: providing a first diode connected to a first electrode of the memory element and to the first bitline; and providing a second diode connected to the first electrode of the memory element and to the second bitline; wherein the applied second voltage is greater than a cut-in voltage of the second diode but less than a sum of the cut-in voltage of the second diode and a turn-off voltage of the memory element and the memory element comprises a second electrode connected to the wordline.
15. The method of claim 11 wherein the determining comprises comparing the current to a reference current.
16. The method of claim 11 wherein the determining comprises determining that the current is very small or immeasurable and that the memory element is in a high resistance state.
17. A memory device comprising: a first bitline; a second bitline; a memory element disposed to be selectively and reversibly configured in one of two different resistive states ; a first diode connected between the first bitline and a first electrode of the memory element; a second diode connected between the second bitline and the first electrode of the memory element; and a wordline connected to a second electrode of the memory element.
18. The device of claim 17 wherein the first diode is configured to conduct current from the first bitline to the first electrode when the first diode is forward biased and the second diode is configured to conduct current from the first electrode to the second bitline when the second diode is forward biased.
19. The device of claim 17 wherein the memory element comprises a first memory element, the wordline comprises a first wordline, and the memory device further comprises : a second memory element disposed to be selectively and reversibly configured in one of two different resistive states; a second wordline connected to a second electrode of the second memory element; a third diode connected between the first bitline and a first electrode of the second memory element; and a fourth diode connected between the second bitline and the first electrode of the second memory element.
20. The device of claim 19 wherein the memory device is configured to: convey the resistive state of the first memory element via a first current flowing from the first wordline through the first memory element to the second bitline; and hinder a second current from flowing from the second wordline through the second memory element to the second bitline while the resistive state of the first memory element is being conveyed by the first current.
21. The device of claim 19 wherein the memory device is configured to: change the resistive state of the first memory element via a first voltage between the first bitline and the first wordline; and hinder a second voltage between the first bitline and the second wordline from changing the resistive state of the second memory element while the first voltage is being applied between the first bitline and the first wordline.
22. A memory cell operating method comprising: providing a memory cell comprising a wordline, first and second bitlines, a memory element, and first and second diodes, the memory element being electrically connected to the wordline and selectively electrically connected to the first bitline via the first diode when the first diode is forward biased and selectively electrically connected to the second bitline via the second diode when the second diode is forward biased; applying a first voltage across the wordline and the first bitline effective to electrically disconnect the first bitline from the memory element; while the first voltage is being applied, applying a second voltage across the wordline and the second bitline effective to electrically connect the second bitline to the memory element and to configure the memory element in a high resistance state; while the first voltage is being applied but the second voltage is not being applied, applying a third voltage across the wordline and the second bitline; determining, based on a lack of current flowing from the wordline through the memory element and the second diode to the second bitline, that the memory element is configured in the high resistance state; applying a fourth voltage across the second bitline and the wordline effective to electrically disconnect the second bitline from the memory element; while the fourth voltage is being applied, applying a fifth voltage across the first bitline and the wordline effective to electrically connect the first bitline to the memory element and to configure the memory element in a low resistance state; while the first voltage is being applied but the second voltage is not being applied and subsequent to the memory element being configured in the low resistance state, applying the third voltage across the wordline and the second bitline effective to cause a current to flow from the wordline through the memory element and the second diode to the second bitline; and based on the current, determining that the memory element is configured in the low resistance state.
23. The method of claim 22 wherein the applied second voltage is larger than the third voltage.
24. The method of claim 22 wherein the memory element comprises at least one of an ionic conducting chalcogenide, a binary metal oxide, a perovskite oxide, a colossal magnetoresistive, or a polymer.
25. The method of claim 22 wherein the applied third voltage is greater than a cut-in voltage of the second diode but less than a sum of the cut-in voltage of the second diode and a turn-off voltage of the memory element.
PCT/US2008/084422 2008-01-15 2008-11-21 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices WO2009091445A1 (en)

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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768812B2 (en) 2008-01-15 2010-08-03 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US8034655B2 (en) 2008-04-08 2011-10-11 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8211743B2 (en) * 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US8134137B2 (en) 2008-06-18 2012-03-13 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US8014185B2 (en) * 2008-07-09 2011-09-06 Sandisk 3D Llc Multiple series passive element matrix cell for three-dimensional arrays
US7733685B2 (en) * 2008-07-09 2010-06-08 Sandisk 3D Llc Cross point memory cell with distributed diodes and method of making same
US7910407B2 (en) 2008-12-19 2011-03-22 Sandisk 3D Llc Quad memory cell and method of making same
US7923812B2 (en) * 2008-12-19 2011-04-12 Sandisk 3D Llc Quad memory cell and method of making same
US8461566B2 (en) * 2009-11-02 2013-06-11 Micron Technology, Inc. Methods, structures and devices for increasing memory density
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8289763B2 (en) 2010-06-07 2012-10-16 Micron Technology, Inc. Memory arrays
US8351242B2 (en) 2010-09-29 2013-01-08 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8526213B2 (en) 2010-11-01 2013-09-03 Micron Technology, Inc. Memory cells, methods of programming memory cells, and methods of forming memory cells
US8796661B2 (en) 2010-11-01 2014-08-05 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cell
US8502185B2 (en) * 2011-05-31 2013-08-06 Crossbar, Inc. Switching device having a non-linear element
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8488365B2 (en) 2011-02-24 2013-07-16 Micron Technology, Inc. Memory cells
US8537592B2 (en) 2011-04-15 2013-09-17 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
JP2013069928A (en) * 2011-09-22 2013-04-18 Toshiba Corp Nonvolatile semiconductor storage device
US9514814B1 (en) * 2015-08-13 2016-12-06 Arm Ltd. Memory write driver, method and system
CN110619907B (en) * 2019-08-28 2021-06-04 中国科学院上海微系统与信息技术研究所 Synapse circuit, synapse array and data processing method based on synapse circuit
JP2021047937A (en) * 2019-09-17 2021-03-25 キオクシア株式会社 Semiconductor storage device
RU2744246C1 (en) * 2019-12-10 2021-03-04 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Device for switching memristor
RU2737794C1 (en) * 2019-12-10 2020-12-03 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Method to control operation of memristor and device for implementation thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020196695A1 (en) * 2001-05-30 2002-12-26 Stmicroelectronics S.R.L. Column multiplexer for semiconductor memories
US6693846B2 (en) * 2002-05-24 2004-02-17 Infineon Technologies Ag Command controller for an integrated circuit memory device and test circuitry thereof
US20060062049A1 (en) * 2004-09-17 2006-03-23 Seok-Heon Lee Methods for programming user data and confirmation information in nonvolatile memory devices

Family Cites Families (295)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1266513A (en) * 1969-05-19 1972-03-08
AU562641B2 (en) * 1983-01-18 1987-06-18 Energy Conversion Devices Inc. Electronic matrix array
US4715685A (en) * 1985-03-04 1987-12-29 Energy Conversion Devices, Inc. Liquid crystal display having potential source in a diode ring
JPH01130552A (en) * 1987-11-17 1989-05-23 Sharp Corp High resistant element
US4964080A (en) 1990-03-09 1990-10-16 Intel Corporation Three-dimensional memory cell with integral select transistor
US5057888A (en) * 1991-01-28 1991-10-15 Micron Technology, Inc. Double DRAM cell
US6432767B2 (en) 1995-12-05 2002-08-13 Hitachi, Ltd. Method of fabricating semiconductor device
US6271131B1 (en) * 1998-08-26 2001-08-07 Micron Technology, Inc. Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers
US6197628B1 (en) * 1998-08-27 2001-03-06 Micron Technology, Inc. Ruthenium silicide diffusion barrier layers and methods of forming same
US6034882A (en) 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US7157314B2 (en) * 1998-11-16 2007-01-02 Sandisk Corporation Vertically stacked field programmable nonvolatile memory and method of fabrication
US6635914B2 (en) * 2000-09-08 2003-10-21 Axon Technologies Corp. Microelectronic programmable device and methods of forming and programming the same
US6218696B1 (en) 1999-06-07 2001-04-17 Infineon Technologies North America Corp. Layout and wiring scheme for memory cells with vertical transistors
US20040124407A1 (en) * 2000-02-11 2004-07-01 Kozicki Michael N. Scalable programmable structure, an array including the structure, and methods of forming the same
US7247876B2 (en) * 2000-06-30 2007-07-24 Intel Corporation Three dimensional programmable device and method for fabricating the same
US6451646B1 (en) * 2000-08-30 2002-09-17 Micron Technology, Inc. High-k dielectric materials and processes for manufacturing them
KR100451096B1 (en) 2000-09-19 2004-10-02 엔이씨 일렉트로닉스 가부시키가이샤 Non-volatile semiconductor memory device with magnetic memory cell array
KR100751736B1 (en) 2000-11-01 2007-08-27 도꾸리쯔교세이호징 가가꾸 기쥬쯔 신꼬 기꼬 Point contact array, not circuit, and electronic circuit using the same
US6534357B1 (en) * 2000-11-09 2003-03-18 Micron Technology, Inc. Methods for forming conductive structures and structures regarding same
US6646297B2 (en) 2000-12-26 2003-11-11 Ovonyx, Inc. Lower electrode isolation in a double-wide trench
US6524867B2 (en) * 2000-12-28 2003-02-25 Micron Technology, Inc. Method for forming platinum-rhodium stack as an oxygen barrier
US6440753B1 (en) 2001-01-24 2002-08-27 Infineon Technologies North America Corp. Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines
JP4818519B2 (en) 2001-02-06 2011-11-16 ルネサスエレクトロニクス株式会社 Magnetic storage
US7102150B2 (en) * 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6905937B2 (en) * 2001-06-28 2005-06-14 Sharp Laboratories Of America, Inc. Methods of fabricating a cross-point resistor memory array
US7193267B2 (en) * 2001-06-28 2007-03-20 Sharp Laboratories Of America, Inc. Cross-point resistor memory array
US6825058B2 (en) * 2001-06-28 2004-11-30 Sharp Laboratories Of America, Inc. Methods of fabricating trench isolated cross-point memory array
US6693821B2 (en) * 2001-06-28 2004-02-17 Sharp Laboratories Of America, Inc. Low cross-talk electrically programmable resistance cross point memory
US6747286B2 (en) 2001-06-30 2004-06-08 Ovonyx, Inc. Pore structure for programmable device
US6567301B2 (en) 2001-08-09 2003-05-20 Hewlett-Packard Development Company, L.P. One-time programmable unit memory cell based on vertically oriented fuse and diode and one-time programmable memory using the same
US6946712B2 (en) * 2001-11-07 2005-09-20 Kabushiki Kaisha Toshiba Magnetic memory device using SOI substrate
US20030143853A1 (en) * 2002-01-31 2003-07-31 Celii Francis G. FeRAM capacitor stack etch
JP2003273252A (en) * 2002-03-12 2003-09-26 Mitsubishi Electric Corp Semiconductor memory device
US6778421B2 (en) * 2002-03-14 2004-08-17 Hewlett-Packard Development Company, Lp. Memory device array having a pair of magnetic bits sharing a common conductor line
US6687147B2 (en) 2002-04-02 2004-02-03 Hewlett-Packard Development Company, L.P. Cubic memory array with diagonal select lines
JP4047615B2 (en) * 2002-04-03 2008-02-13 株式会社ルネサステクノロジ Magnetic storage
CN1459398A (en) 2002-05-21 2003-12-03 日本精工股份有限公司 Steering wheel column device
US6757188B2 (en) 2002-05-22 2004-06-29 Hewlett-Packard Development Company, L.P. Triple sample sensing for magnetic random access memory (MRAM) with series diodes
US6952043B2 (en) * 2002-06-27 2005-10-04 Matrix Semiconductor, Inc. Electrically isolated pillars in active devices
TWI233204B (en) 2002-07-26 2005-05-21 Infineon Technologies Ag Nonvolatile memory element and associated production methods and memory element arrangements
US6970375B2 (en) 2002-08-02 2005-11-29 Unity Semiconductor Corporation Providing a reference voltage to a cross point memory array
US7067862B2 (en) * 2002-08-02 2006-06-27 Unity Semiconductor Corporation Conductive memory device with conductive oxide electrodes
US6917539B2 (en) * 2002-08-02 2005-07-12 Unity Semiconductor Corporation High-density NVRAM
US6834008B2 (en) * 2002-08-02 2004-12-21 Unity Semiconductor Corporation Cross point memory array using multiple modes of operation
US6753561B1 (en) * 2002-08-02 2004-06-22 Unity Semiconductor Corporation Cross point memory array using multiple thin films
US6859382B2 (en) 2002-08-02 2005-02-22 Unity Semiconductor Corporation Memory array of a non-volatile ram
US6785159B2 (en) * 2002-08-29 2004-08-31 Micron Technology, Inc. Combination etch stop and in situ resistor in a magnetoresistive memory and methods for fabricating same
US7184301B2 (en) * 2002-11-27 2007-02-27 Nec Corporation Magnetic memory cell and magnetic random access memory using the same
JP2006511965A (en) 2002-12-19 2006-04-06 マトリックス セミコンダクター インコーポレイテッド Improved method for fabricating high density non-volatile memory
US7005350B2 (en) * 2002-12-31 2006-02-28 Matrix Semiconductor, Inc. Method for fabricating programmable memory array structures incorporating series-connected transistor strings
DE10261457B3 (en) * 2002-12-31 2004-03-25 Infineon Technologies Ag Integrated circuit with transistor array of vertical FET selection transistors has array diagnosis test structure with two offset word, bit line combs alternately connecting different word, bit lines
JP2004220740A (en) 2003-01-17 2004-08-05 Seiko Epson Corp Ferroelectric storage device
DE10306281B4 (en) 2003-02-14 2007-02-15 Infineon Technologies Ag Arrangement and method for the production of vertical transistor cells and transistor-controlled memory cells
US6958273B2 (en) 2003-03-21 2005-10-25 Silicon Storage Technology, Inc. Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby
US6753562B1 (en) * 2003-03-27 2004-06-22 Sharp Laboratories Of America, Inc. Spin transistor magnetic random access memory device
US7233024B2 (en) * 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
JP4445398B2 (en) 2003-04-03 2010-04-07 株式会社東芝 Phase change memory device
US7459715B2 (en) 2003-04-03 2008-12-02 Kabushiki Kaisha Toshiba Resistance change memory device
US6806531B1 (en) 2003-04-07 2004-10-19 Silicon Storage Technology, Inc. Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation
US7001846B2 (en) * 2003-05-20 2006-02-21 Sharp Laboratories Of America, Inc. High-density SOI cross-point memory array and method for fabricating same
US7291878B2 (en) 2003-06-03 2007-11-06 Hitachi Global Storage Technologies Netherlands B.V. Ultra low-cost solid-state memory
TW589753B (en) * 2003-06-03 2004-06-01 Winbond Electronics Corp Resistance random access memory and method for fabricating the same
US7416911B2 (en) * 2003-06-24 2008-08-26 California Institute Of Technology Electrochemical method for attaching molecular and biomolecular structures to semiconductor microstructures and nanostructures
KR100507205B1 (en) 2003-07-15 2005-08-10 현대자동차주식회사 Knocking sensor mounting position determining method
US7050346B2 (en) * 2003-07-29 2006-05-23 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and electric device with the same
US7029924B2 (en) * 2003-09-05 2006-04-18 Sharp Laboratories Of America, Inc. Buffered-layer memory cell
US6955992B2 (en) 2003-09-30 2005-10-18 Sharp Laboratories Of America, Inc. One mask PT/PCMO/PT stack etching process for RRAM applications
JPWO2005041303A1 (en) * 2003-10-23 2007-04-26 松下電器産業株式会社 RESISTANCE CHANGE ELEMENT, ITS MANUFACTURING METHOD, MEMORY INCLUDING THE ELEMENT, AND DRIVE METHOD FOR THE MEMORY
US7098438B1 (en) * 2003-11-19 2006-08-29 Raytheon Company Method and apparatus for resetting a high speed latch circuit
US7009278B2 (en) * 2003-11-24 2006-03-07 Sharp Laboratories Of America, Inc. 3d rram
US6937507B2 (en) * 2003-12-05 2005-08-30 Silicon Storage Technology, Inc. Memory device and method of operating same
JP4567963B2 (en) 2003-12-05 2010-10-27 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device
US6849891B1 (en) 2003-12-08 2005-02-01 Sharp Laboratories Of America, Inc. RRAM memory cell electrodes
US7002197B2 (en) * 2004-01-23 2006-02-21 Hewlett-Packard Development Company, L.P. Cross point resistive memory array
US7138687B2 (en) * 2004-01-26 2006-11-21 Macronix International Co., Ltd. Thin film phase-change memory
US7538338B2 (en) 2004-09-03 2009-05-26 Unity Semiconductor Corporation Memory using variable tunnel barrier widths
US7082052B2 (en) 2004-02-06 2006-07-25 Unity Semiconductor Corporation Multi-resistive state element with reactive metal
US20060171200A1 (en) * 2004-02-06 2006-08-03 Unity Semiconductor Corporation Memory using mixed valence conductive oxides
US7050316B1 (en) * 2004-03-09 2006-05-23 Silicon Storage Technology, Inc. Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements
US7476945B2 (en) * 2004-03-17 2009-01-13 Sanyo Electric Co., Ltd. Memory having reduced memory cell size
DE102004020297B4 (en) 2004-04-26 2007-06-21 Infineon Technologies Ag Process for producing resistively switching memory components
DE102004026003B3 (en) * 2004-05-27 2006-01-19 Infineon Technologies Ag Resistive memory cell arrangement
JP4377751B2 (en) 2004-06-10 2009-12-02 シャープ株式会社 Cross-point structure semiconductor memory device and manufacturing method thereof
KR100614240B1 (en) 2004-06-10 2006-08-18 삼성전자주식회사 Semiconductor devices including a field effect transistor and methods of the same
US7187201B1 (en) * 2004-06-24 2007-03-06 Xilinx, Inc. Programmable logic device suitable for implementation in molecular electronics
US7091091B2 (en) 2004-06-28 2006-08-15 Promos Technologies Inc. Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer
KR20070028604A (en) 2004-06-30 2007-03-12 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Method for manufacturing an electric device with a layer of conductive material contacted by nanowire
US20060002330A1 (en) 2004-07-01 2006-01-05 Lila Madour Method and system for providing network access to protocol for carrying authentication for network access (PANA) mobile terminals and point-to-point protocol (PPP) mobile terminals packet data network
US7791141B2 (en) 2004-07-09 2010-09-07 International Business Machines Corporation Field-enhanced programmable resistance memory cell
JP2006032729A (en) 2004-07-16 2006-02-02 Matsushita Electric Ind Co Ltd Nonvolatile memory and its manufacturing method
JP4827074B2 (en) 2004-07-22 2011-11-30 シャープ株式会社 High density SOI crosspoint memory array and method for manufacturing the same
US7180160B2 (en) * 2004-07-30 2007-02-20 Infineon Technologies Ag MRAM storage device
US20080008642A1 (en) 2004-08-24 2008-01-10 Osaka University Process For Producing Aluminum Nitride Crystal And Aluminum Nitride Crystal Obtained Thereby
KR100568543B1 (en) 2004-08-31 2006-04-07 삼성전자주식회사 Method of forming a phase change memory device having a small area of contact
FR2875995B1 (en) 2004-09-24 2014-10-24 Oberthur Card Syst Sa METHOD FOR MOUNTING AN ELECTRONIC COMPONENT ON A SUPPORT, PREFERABLY MOU, AND ELECTRONIC ENTITY THUS OBTAINED, SUCH AS A PASSPORT
US7205238B2 (en) * 2004-10-21 2007-04-17 Sharp Laboratories Of America, Inc. Chemical mechanical polish of PCMO thin films for RRAM applications
US7189626B2 (en) 2004-11-03 2007-03-13 Micron Technology, Inc. Electroless plating of metal caps for chalcogenide-based memory devices
US7035141B1 (en) * 2004-11-17 2006-04-25 Spansion Llc Diode array architecture for addressing nanoscale resistive memory arrays
US20060108667A1 (en) 2004-11-22 2006-05-25 Macronix International Co., Ltd. Method for manufacturing a small pin on integrated circuits or other devices
WO2006070693A1 (en) 2004-12-27 2006-07-06 Nec Corporation Switching element, switching element driving method, switching element manufacturing method, rewritable logic integrated circuit, and memory element
US7046550B1 (en) * 2005-01-18 2006-05-16 International Business Machines Corporation Cross-point memory architecture with improved selectivity
US7208372B2 (en) * 2005-01-19 2007-04-24 Sharp Laboratories Of America, Inc. Non-volatile memory resistor cell with nanotip electrode
KR100682926B1 (en) 2005-01-31 2007-02-15 삼성전자주식회사 Nonvolatile memory device using resistance material and fabrication method of the same
DE102005005938B4 (en) 2005-02-09 2009-04-30 Qimonda Ag Resistive memory element with shortened erase time, method of manufacture and memory cell arrangement
WO2006087798A1 (en) 2005-02-18 2006-08-24 Fujitsu Limited Storage element matrix, method for manufacturing such storage element matrix and semiconductor storage device using such storage element matrix
FR2882828B1 (en) * 2005-03-03 2007-04-06 Saint Gobain METHOD FOR SUPPLYING AN ELECTROCOMMANDABLE DEVICE HAVING VARIABLE OPTICAL AND / OR ENERGY PROPERTIES
JP2006267411A (en) 2005-03-23 2006-10-05 Victor Co Of Japan Ltd Liquid crystal display device and liquid crystal display method
KR100697282B1 (en) 2005-03-28 2007-03-20 삼성전자주식회사 Resistive memory cell, method for forming the same and resistive memory array using the same
US7154774B2 (en) * 2005-03-30 2006-12-26 Ovonyx, Inc. Detecting switching of access elements of phase change memory cells
US8031509B2 (en) 2008-12-19 2011-10-04 Unity Semiconductor Corporation Conductive metal oxide structures in non-volatile re-writable memory devices
US7323349B2 (en) * 2005-05-02 2008-01-29 Sharp Laboratories Of America, Inc. Self-aligned cross point resistor memory array
US9196615B2 (en) * 2005-05-09 2015-11-24 Nantero Inc. Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
US7782650B2 (en) * 2005-05-09 2010-08-24 Nantero, Inc. Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
US7585724B2 (en) 2005-05-10 2009-09-08 Elite Semiconductor Memory Technology, Inc. FLASH memory device and method of manufacture
KR100655447B1 (en) 2005-06-07 2006-12-08 삼성전자주식회사 Non-volatile memory device having a floating gate and methods of forming the same
US7238994B2 (en) 2005-06-17 2007-07-03 Macronix International Co., Ltd. Thin film plate phase change ram circuit and manufacturing method
US7514288B2 (en) 2005-06-17 2009-04-07 Macronix International Co., Ltd. Manufacturing methods for thin film fuse phase change ram
US7321130B2 (en) 2005-06-17 2008-01-22 Macronix International Co., Ltd. Thin film fuse phase change RAM and manufacturing method
US7167397B2 (en) * 2005-06-21 2007-01-23 Intel Corporation Apparatus and method for programming a memory array
US20070010082A1 (en) * 2005-07-05 2007-01-11 Cay-Uwe Pinnow Structure and method for manufacturing phase change memories with particular switching characteristics
US7446010B2 (en) * 2005-07-18 2008-11-04 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal (MSM) back-to-back Schottky diode
KR20080040715A (en) * 2005-07-22 2008-05-08 콸콤 인코포레이티드 Support structure for mems device and methods therefor
US7521705B2 (en) 2005-08-15 2009-04-21 Micron Technology, Inc. Reproducible resistance variable insulating memory devices having a shaped bottom electrode
JP4309877B2 (en) 2005-08-17 2009-08-05 シャープ株式会社 Semiconductor memory device
US20070048990A1 (en) * 2005-08-30 2007-03-01 Sharp Laboratories Of America, Inc. Method of buffer layer formation for RRAM thin film deposition
KR100630437B1 (en) * 2005-08-31 2006-10-02 삼성전자주식회사 Non-volatile organic resistance random access memory device and method for manufacturing the same
KR100665227B1 (en) * 2005-10-18 2007-01-09 삼성전자주식회사 Phase change memory device and fabricating method for the same
US7236389B2 (en) * 2005-11-17 2007-06-26 Sharp Laboratories Of America, Inc. Cross-point RRAM memory array having low bit line crosstalk
US7666526B2 (en) 2005-11-30 2010-02-23 The Trustees Of The University Of Pennsylvania Non-volatile resistance-switching oxide thin film devices
US8106375B2 (en) 2005-11-30 2012-01-31 The Trustees Of The University Of Pennsylvania Resistance-switching memory based on semiconductor composition of perovskite conductor doped perovskite insulator
US20070132049A1 (en) 2005-12-12 2007-06-14 Stipe Barry C Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
PL204873B1 (en) 2005-12-15 2010-02-26 Wagony & Sacute Widnica Spo & Mechanism of the hinged unloading traps in railway wagons
JP4054347B2 (en) 2005-12-16 2008-02-27 シャープ株式会社 Nonvolatile semiconductor memory device
CN101461071B (en) 2005-12-20 2012-01-18 Nxp股份有限公司 A vertical phase change memory cell and methods for manufacturing thereof
KR100655082B1 (en) 2005-12-23 2006-12-08 삼성전자주식회사 Phase-change memory cell and method of fabricating the same
US7531825B2 (en) 2005-12-27 2009-05-12 Macronix International Co., Ltd. Method for forming self-aligned thermal isolation cell for a variable resistance memory array
US7560337B2 (en) * 2006-01-09 2009-07-14 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
KR101186293B1 (en) * 2006-01-19 2012-09-27 삼성전자주식회사 Resistive RAM comprising varistor and method of operating the same
JP2007201081A (en) 2006-01-25 2007-08-09 Elpida Memory Inc Semiconductor memory device
US7456421B2 (en) 2006-01-30 2008-11-25 Macronix International Co., Ltd. Vertical side wall active pin structures in a phase change memory and manufacturing methods
JP2007213639A (en) * 2006-02-07 2007-08-23 Renesas Technology Corp Nonvolatile semiconductor memory
KR100723420B1 (en) 2006-02-20 2007-05-30 삼성전자주식회사 Non volatile memory device comprising amorphous alloy metal oxide layer
KR100707212B1 (en) 2006-03-08 2007-04-13 삼성전자주식회사 Nanowire memory device and method of manufacturing the same
KR100745764B1 (en) 2006-03-09 2007-08-02 삼성전자주식회사 Method of manufacturing nanowire memory device and system of controlling nanowire formation using in the method
KR101176543B1 (en) 2006-03-10 2012-08-28 삼성전자주식회사 Resistance Random Memory Device
US8395199B2 (en) * 2006-03-25 2013-03-12 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US20070246795A1 (en) 2006-04-20 2007-10-25 Micron Technology, Inc. Dual depth shallow trench isolation and methods to form same
KR101213702B1 (en) * 2006-04-21 2012-12-18 삼성전자주식회사 Non-volatile memory device having a pair of fins between which a void is defined
US7606055B2 (en) 2006-05-18 2009-10-20 Micron Technology, Inc. Memory architecture and cell design employing two access transistors
KR101206034B1 (en) 2006-05-19 2012-11-28 삼성전자주식회사 Nonvolatile memory device using oxygen-deficient metal oxide layer and the fabrication method
KR100833903B1 (en) 2006-06-13 2008-06-03 광주과학기술원 Non-volatile Memory Device And Manufacturing Method And Apparatus Therefor
KR101159075B1 (en) 2006-06-27 2012-06-25 삼성전자주식회사 Variable resistance random access memory device comprising n+ interfacial layer
KR100818271B1 (en) 2006-06-27 2008-03-31 삼성전자주식회사 Threshold switching operation method of nonvolitile memory device induced by pulse voltage
US7569459B2 (en) 2006-06-30 2009-08-04 International Business Machines Corporation Nonvolatile programmable resistor memory cell
KR101374491B1 (en) 2006-07-04 2014-03-14 바스프 에스이 Electrochemical production of sterically hindered amines
US7932548B2 (en) * 2006-07-14 2011-04-26 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US7696077B2 (en) * 2006-07-14 2010-04-13 Micron Technology, Inc. Bottom electrode contacts for semiconductor devices and methods of forming same
JP2008028228A (en) * 2006-07-24 2008-02-07 Seiko Epson Corp Variable resistance element and resistance random access memory
US7807995B2 (en) 2006-07-27 2010-10-05 Panasonic Corporation Nonvolatile semiconductor memory apparatus and manufacturing method thereof
KR101309111B1 (en) * 2006-07-27 2013-09-17 삼성전자주식회사 Method for forming of poly-Si pattern and multi-layer cross point resistive memory device comprising poly-Si pattern and method for manufacturing the same
KR100749740B1 (en) * 2006-08-01 2007-08-17 삼성전자주식회사 Phase-change memory device and method of manufacturing the same
US7515454B2 (en) * 2006-08-02 2009-04-07 Infineon Technologies Ag CBRAM cell and CBRAM array, and method of operating thereof
US7727908B2 (en) * 2006-08-03 2010-06-01 Micron Technology, Inc. Deposition of ZrA1ON films
JP4344372B2 (en) * 2006-08-22 2009-10-14 シャープ株式会社 Semiconductor memory device and driving method thereof
KR100755409B1 (en) 2006-08-28 2007-09-04 삼성전자주식회사 Method of programing in resist memory device
WO2008029446A1 (en) 2006-09-05 2008-03-13 Fujitsu Limited Writing method of nonvolatile semiconductor storage apparatus
US7553758B2 (en) 2006-09-18 2009-06-30 Samsung Electronics Co., Ltd. Method of fabricating interconnections of microelectronic device using dual damascene process
JP2008078404A (en) * 2006-09-21 2008-04-03 Toshiba Corp Semiconductor memory and manufacturing method thereof
US8058643B2 (en) 2006-09-29 2011-11-15 The Board Of Trustees Of The Leland Stanford Junior University Electrochemical memory with internal boundary
US7751163B2 (en) * 2006-09-29 2010-07-06 Qimonda Ag Electric device protection circuit and method for protecting an electric device
KR100772904B1 (en) 2006-10-02 2007-11-05 삼성전자주식회사 Semiconductor memory device using variable resistive element and mabufacturing method thereof
KR100819099B1 (en) * 2006-10-02 2008-04-03 삼성전자주식회사 Variable resistive semiconductor memory device
KR100858083B1 (en) 2006-10-18 2008-09-10 삼성전자주식회사 Phase change memory device having increased contact area between lower electrode contact layer and phase change layer and method of manufacturing the same
US10134985B2 (en) * 2006-10-20 2018-11-20 The Regents Of The University Of Michigan Non-volatile solid state resistive switching devices
US20080102278A1 (en) * 2006-10-27 2008-05-01 Franz Kreupl Carbon filament memory and method for fabrication
KR100827661B1 (en) 2006-10-31 2008-05-07 삼성전자주식회사 Phase change memory devices having dual lower electrodes and methods fabricating the same
US7639523B2 (en) 2006-11-08 2009-12-29 Symetrix Corporation Stabilized resistive switching memory
US7872900B2 (en) 2006-11-08 2011-01-18 Symetrix Corporation Correlated electron memory
KR100827697B1 (en) * 2006-11-10 2008-05-07 삼성전자주식회사 Semiconductor memory device having three dimension structure and cell array structure
KR101196392B1 (en) 2006-11-28 2012-11-02 삼성전자주식회사 Non-volatile Memory Device and method of fabricating the same
US7864568B2 (en) 2006-12-07 2011-01-04 Renesas Electronics Corporation Semiconductor storage device
US7557424B2 (en) * 2007-01-03 2009-07-07 International Business Machines Corporation Reversible electric fuse and antifuse structures for semiconductor devices
US8675571B2 (en) 2007-01-04 2014-03-18 Nokia Corporation Apparatus, methods and computer program products providing a common signaling entry for a modular control channel structure
JP5091491B2 (en) 2007-01-23 2012-12-05 株式会社東芝 Nonvolatile semiconductor memory device
KR100881292B1 (en) * 2007-01-23 2009-02-04 삼성전자주식회사 Resistive semiconductor memory device having three dimension stack structure and method for controlling the same
KR100885184B1 (en) 2007-01-30 2009-02-23 삼성전자주식회사 Memory Devices Having Resistance Property Capable Of Being Independently Controlled By Electric And Magnetic Fields And Methods Of Operating The Same
US7800093B2 (en) * 2007-02-01 2010-09-21 Qimonda North America Corp. Resistive memory including buried word lines
JP2008192995A (en) 2007-02-07 2008-08-21 Matsushita Electric Ind Co Ltd Resistance change element, method of manufacturing the same, and resistance change memory using the same
US20080185687A1 (en) 2007-02-07 2008-08-07 Industry-University Cooperation Foundation Hanyang University Memory device and method for fabricating the same
US7906175B2 (en) 2007-02-21 2011-03-15 Air Liquide Electronics U.S. Lp Methods for forming a ruthenium-based film on a substrate
US7382647B1 (en) 2007-02-27 2008-06-03 International Business Machines Corporation Rectifying element for a crosspoint based memory array architecture
KR100852206B1 (en) 2007-04-04 2008-08-13 삼성전자주식회사 Resist random access memory device and method for manufacturing the same
US7723786B2 (en) 2007-04-11 2010-05-25 Ronald Kakoschke Apparatus of memory array using FinFETs
US7569844B2 (en) 2007-04-17 2009-08-04 Macronix International Co., Ltd. Memory cell sidewall contacting side electrode
US7755076B2 (en) * 2007-04-17 2010-07-13 Macronix International Co., Ltd. 4F2 self align side wall active phase change memory
CN100521278C (en) 2007-04-19 2009-07-29 复旦大学 Preparing method for RRAM to avoid forming phenomenon using CuxO as storage medium
US7990754B2 (en) 2007-06-01 2011-08-02 Panasonic Corporation Resistance variable memory apparatus
US7459716B2 (en) * 2007-06-11 2008-12-02 Kabushiki Kaisha Toshiba Resistance change memory device
JP4280302B2 (en) 2007-06-22 2009-06-17 パナソニック株式会社 Variable resistance nonvolatile memory device
US8513637B2 (en) * 2007-07-13 2013-08-20 Macronix International Co., Ltd. 4F2 self align fin bottom electrodes FET drive phase change memory
TWI402980B (en) * 2007-07-20 2013-07-21 Macronix Int Co Ltd Resistive memory structure with buffer layer
KR101344346B1 (en) 2007-07-25 2013-12-24 삼성전자주식회사 Phase change memory devices and methods of forming the same
JP5088036B2 (en) 2007-08-06 2012-12-05 ソニー株式会社 Storage element and storage device
US7772580B2 (en) * 2007-08-10 2010-08-10 Qimonda Ag Integrated circuit having a cell with a resistivity changing layer
JP2009059735A (en) 2007-08-29 2009-03-19 Elpida Memory Inc Semiconductor storage device
TW200913249A (en) 2007-09-04 2009-03-16 Ind Tech Res Inst Phase-change memory and fabrication method thereof
US7838861B2 (en) 2007-09-17 2010-11-23 Qimonda Ag Integrated circuits; methods for manufacturing an integrated circuit and memory module
JP2009081251A (en) 2007-09-26 2009-04-16 Panasonic Corp Resistance change element, production method thereof, and resistance change memory
US8665629B2 (en) * 2007-09-28 2014-03-04 Qimonda Ag Condensed memory cell structure using a FinFET
KR20090055874A (en) 2007-11-29 2009-06-03 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
JP4466738B2 (en) 2008-01-09 2010-05-26 ソニー株式会社 Storage element and storage device
JP2009168867A (en) 2008-01-11 2009-07-30 Hitachi Displays Ltd Display device
US7768812B2 (en) 2008-01-15 2010-08-03 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
JP5049814B2 (en) 2008-02-14 2012-10-17 株式会社東芝 Data writing method for nonvolatile semiconductor memory device
US7742324B2 (en) 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
KR100978911B1 (en) * 2008-02-28 2010-08-31 삼성전자주식회사 Semiconductor Device And Method Of Forming The Same
JP2009212202A (en) 2008-03-03 2009-09-17 Elpida Memory Inc Phase change memory device and fabrication method thereof
US8343813B2 (en) 2009-04-10 2013-01-01 Intermolecular, Inc. Resistive-switching memory elements having improved switching characteristics
US7960216B2 (en) 2008-05-10 2011-06-14 Intermolecular, Inc. Confinement techniques for non-volatile resistive-switching memories
CN101546602B (en) 2008-03-27 2014-05-14 三星电子株式会社 Nonvolatile memory device using variable resistance element
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8034655B2 (en) 2008-04-08 2011-10-11 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
KR20090108804A (en) 2008-04-14 2009-10-19 윤진수 Method of manufacturing food including kimchi powder
DE102008019860B4 (en) 2008-04-15 2010-10-07 Technische Universität Dresden Apparatus, method and use of the method for generating switchable temporary magnetism in oxidic materials by means of electric fields
KR20090109804A (en) 2008-04-16 2009-10-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
US8098520B2 (en) 2008-04-25 2012-01-17 Seagate Technology Llc Storage device including a memory cell having multiple memory layers
JP2009267219A (en) 2008-04-28 2009-11-12 Hitachi Ltd Semiconductor memory device and manufacturing method thereof
US7969806B2 (en) 2008-04-28 2011-06-28 Qimonda Ag Systems and methods for writing to a memory
US8551809B2 (en) 2008-05-01 2013-10-08 Intermolecular, Inc. Reduction of forming voltage in semiconductor devices
US8053364B2 (en) 2008-05-01 2011-11-08 Intermolecular, Inc. Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer
US8129704B2 (en) 2008-05-01 2012-03-06 Intermolecular, Inc. Non-volatile resistive-switching memories
US8062918B2 (en) 2008-05-01 2011-11-22 Intermolecular, Inc. Surface treatment to improve resistive-switching characteristics
US8211743B2 (en) 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US8284596B2 (en) 2008-06-09 2012-10-09 Qimonda Ag Integrated circuit including an array of diodes coupled to a layer of resistance changing material
US8114468B2 (en) 2008-06-18 2012-02-14 Boise Technology, Inc. Methods of forming a non-volatile resistive oxide memory array
US8134137B2 (en) 2008-06-18 2012-03-13 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US7795109B2 (en) 2008-06-23 2010-09-14 Qimonda Ag Isolation trenches with conductive plates
KR101407362B1 (en) 2008-06-23 2014-06-16 삼성전자주식회사 Phase change memory
JP2010009669A (en) 2008-06-26 2010-01-14 Toshiba Corp Semiconductor memory device
KR20100001260A (en) 2008-06-26 2010-01-06 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
US7732235B2 (en) 2008-06-30 2010-06-08 Sandisk 3D Llc Method for fabricating high density pillar structures by double patterning using positive photoresist
US9343665B2 (en) * 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
JP5100555B2 (en) 2008-07-30 2012-12-19 株式会社東芝 Semiconductor memory device
CN101350360B (en) 2008-08-29 2011-06-01 中国科学院上海微系统与信息技术研究所 Three-dimensional stacking non-phase-change caused resistance conversion storage apparatus and manufacturing method thereof
KR20100032572A (en) * 2008-09-18 2010-03-26 주식회사 하이닉스반도체 Resistive memory device and method for manufacturing the same
KR101424138B1 (en) 2008-09-19 2014-08-04 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
JP4733233B2 (en) 2008-09-19 2011-07-27 パナソニック株式会社 Manufacturing method of current suppressing element
US8063394B2 (en) 2008-10-08 2011-11-22 Qimonda Ag Integrated circuit
US8687402B2 (en) 2008-10-08 2014-04-01 The Regents Of The University Of Michigan Silicon-based nanoscale resistive device with adjustable resistance
KR20100041155A (en) 2008-10-13 2010-04-22 삼성전자주식회사 Resistive memory device
US7897955B2 (en) * 2008-11-03 2011-03-01 Seagate Technology Llc Programmable resistive memory cell with filament placement structure
US8022547B2 (en) 2008-11-18 2011-09-20 Seagate Technology Llc Non-volatile memory cells including small volume electrical contact regions
US20100135061A1 (en) * 2008-12-02 2010-06-03 Shaoping Li Non-Volatile Memory Cell with Ferroelectric Layer Configurations
US20100140578A1 (en) 2008-12-05 2010-06-10 Seagate Technology Llc Non volatile memory cells including a composite solid electrolyte layer
WO2010068221A1 (en) 2008-12-12 2010-06-17 Hewlett-Packard Development Company, L.P. Memristive device
KR20100076274A (en) * 2008-12-26 2010-07-06 주식회사 하이닉스반도체 Phase changeable memory device and method of manufacturing the same
KR20100078808A (en) 2008-12-30 2010-07-08 삼성전자주식회사 Resistive memory device
TWI401796B (en) * 2008-12-30 2013-07-11 Ind Tech Res Inst Conductive bridging random access memory device and method of manufacturing the same
KR101583717B1 (en) 2009-01-13 2016-01-11 삼성전자주식회사 Methods for fabricating resistive random access memory devices
WO2010082922A1 (en) 2009-01-13 2010-07-22 Hewlett-Packard Development Company, L.P. Memristor having a triangular shaped electrode
WO2010082923A2 (en) 2009-01-13 2010-07-22 Hewlett-Packard Development Company, L.P. Programmable bipolar electronic device
JP2010165803A (en) 2009-01-14 2010-07-29 Toshiba Corp Method of manufacturing semiconductor memory device, and semiconductor memory device
US8614432B2 (en) 2009-01-15 2013-12-24 Hewlett-Packard Development Company, L.P. Crystalline silicon-based memristive device with multiple mobile dopant species
US8471234B2 (en) 2009-01-20 2013-06-25 Hewlett-Packard Development Company, L.P. Multilayer memristive devices
US8487291B2 (en) * 2009-01-30 2013-07-16 Seagate Technology Llc Programmable metallization memory cell with layered solid electrolyte structure
US8134138B2 (en) * 2009-01-30 2012-03-13 Seagate Technology Llc Programmable metallization memory cell with planarized silver electrode
WO2010087854A1 (en) 2009-01-30 2010-08-05 Hewlett-Packard Development Company, L.P. Memristive transistor memory
TWI394231B (en) * 2009-02-03 2013-04-21 Nanya Technology Corp Non-volatile memory cell and fabrication method thereof
JP2010192569A (en) 2009-02-17 2010-09-02 Toshiba Corp Nonvolatile semiconductor memory device and method for manufacturing the same
JP2010192646A (en) 2009-02-18 2010-09-02 Toshiba Corp Semiconductor device and method of manufacturing the same
US8021897B2 (en) 2009-02-19 2011-09-20 Micron Technology, Inc. Methods of fabricating a cross point memory array
WO2010101340A1 (en) 2009-03-05 2010-09-10 광주과학기술원 Resistance change memory device with three-dimensional structure, and device array, electronic product and manufacturing method therefor
WO2010104918A1 (en) 2009-03-10 2010-09-16 Contour Semiconductor, Inc. Three-dimensional memory array comprising vertical switches having three terminals
US8410559B2 (en) 2009-03-19 2013-04-02 International Business Machines Corporation Selectively self-assembling oxygen diffusion barrier
JP4810581B2 (en) 2009-03-25 2011-11-09 株式会社東芝 Nonvolatile memory device
US8420478B2 (en) 2009-03-31 2013-04-16 Intermolecular, Inc. Controlled localized defect paths for resistive memories
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US8199576B2 (en) 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US7983065B2 (en) 2009-04-08 2011-07-19 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
JP2010263211A (en) 2009-05-04 2010-11-18 Samsung Electronics Co Ltd Laminated memory element
CN102026154B (en) 2009-09-23 2014-11-05 中兴通讯股份有限公司 Media modifying method and system
WO2011051785A2 (en) 2009-10-30 2011-05-05 Synopsys, Inc. Routing method for flip chip package and apparatus using the same
WO2011059095A1 (en) 2009-11-16 2011-05-19 株式会社上原Ｏｔｅｃ研究所 Device for treating plastic
CN101703051B (en) 2009-12-03 2012-10-17 湖南化工研究院 Insecticidal composition containing cyanogen insect amide and molosultap and application thereof
TWI492432B (en) 2009-12-17 2015-07-11 Hitachi Ltd Semiconductor memory device and manufacturing method thereof
US8048755B2 (en) 2010-02-08 2011-11-01 Micron Technology, Inc. Resistive memory and methods of processing resistive memory
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
WO2012021168A1 (en) 2010-08-09 2012-02-16 Ck Technologies, Inc. Cable / harness test connector
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
KR20140043050A (en) 2010-12-14 2014-04-08 쌘디스크 3디 엘엘씨 Three dimensional non-volatile storage with dual gated vertical select devices
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8537592B2 (en) 2011-04-15 2013-09-17 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020196695A1 (en) * 2001-05-30 2002-12-26 Stmicroelectronics S.R.L. Column multiplexer for semiconductor memories
US6693846B2 (en) * 2002-05-24 2004-02-17 Infineon Technologies Ag Command controller for an integrated circuit memory device and test circuitry thereof
US20060062049A1 (en) * 2004-09-17 2006-03-23 Seok-Heon Lee Methods for programming user data and confirmation information in nonvolatile memory devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2243138A4 *

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US20160211019A1 (en) 2016-07-21
EP3926632A2 (en) 2021-12-22
US20100271863A1 (en) 2010-10-28
US20210005259A1 (en) 2021-01-07
US10790020B2 (en) 2020-09-29
US9343145B2 (en) 2016-05-17
US20120057391A1 (en) 2012-03-08

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