WO2009087162A3 - Rotate then operate on selected bits facility and instructions therefore - Google Patents

Rotate then operate on selected bits facility and instructions therefore Download PDF

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Publication number
WO2009087162A3
WO2009087162A3 PCT/EP2009/050109 EP2009050109W WO2009087162A3 WO 2009087162 A3 WO2009087162 A3 WO 2009087162A3 EP 2009050109 W EP2009050109 W EP 2009050109W WO 2009087162 A3 WO2009087162 A3 WO 2009087162A3
Authority
WO
WIPO (PCT)
Prior art keywords
operand
rotate
operate
facility
instructions
Prior art date
Application number
PCT/EP2009/050109
Other languages
French (fr)
Other versions
WO2009087162A2 (en
Inventor
Dan Greiner
Timothy Slegel
Joachim Von Buttlar
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to CN200980101991.XA priority Critical patent/CN101911015B/en
Priority to KR1020107015044A priority patent/KR101231556B1/en
Priority to JP2010541776A priority patent/JP5357181B2/en
Priority to EP20090701244 priority patent/EP2243076A2/en
Publication of WO2009087162A2 publication Critical patent/WO2009087162A2/en
Publication of WO2009087162A3 publication Critical patent/WO2009087162A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029Logical and Boolean instructions, e.g. XOR, NOT
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30185Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342Extension of operand address space

Abstract

In a method of operating a computer, a rotate-then-operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated byan amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is '0' the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is '1', in addition to the inserted bits,the bits other than the selected portion of the rotated first operand are saved in the second register.
PCT/EP2009/050109 2008-01-11 2009-01-07 Rotate then operate on selected bits facility and instructions therefore WO2009087162A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200980101991.XA CN101911015B (en) 2008-01-11 2009-01-07 Reduced the dependent method of Computer Architecture and device by processor instruction
KR1020107015044A KR101231556B1 (en) 2008-01-11 2009-01-07 Rotate then operate on selected bits facility and instructions therefore
JP2010541776A JP5357181B2 (en) 2008-01-11 2009-01-07 Computer system, operating method thereof, and computer program
EP20090701244 EP2243076A2 (en) 2008-01-11 2009-01-07 Rotate then operate on selected bits facility and instructions therefore

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/972,679 US7895419B2 (en) 2008-01-11 2008-01-11 Rotate then operate on selected bits facility and instructions therefore
US11/972,679 2008-01-11

Publications (2)

Publication Number Publication Date
WO2009087162A2 WO2009087162A2 (en) 2009-07-16
WO2009087162A3 true WO2009087162A3 (en) 2009-09-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/050109 WO2009087162A2 (en) 2008-01-11 2009-01-07 Rotate then operate on selected bits facility and instructions therefore

Country Status (6)

Country Link
US (3) US7895419B2 (en)
EP (1) EP2243076A2 (en)
JP (1) JP5357181B2 (en)
KR (1) KR101231556B1 (en)
CN (1) CN101911015B (en)
WO (1) WO2009087162A2 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7895419B2 (en) * 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US9026424B1 (en) * 2008-10-27 2015-05-05 Juniper Networks, Inc. Emulation of multiple instruction sets
US8473567B2 (en) * 2010-03-29 2013-06-25 Intel Corporation Generating a packet including multiple operation codes
US9361109B2 (en) 2010-05-24 2016-06-07 Qualcomm Incorporated System and method to evaluate a data value as an instruction
GB2485774A (en) * 2010-11-23 2012-05-30 Advanced Risc Mach Ltd Processor instruction to extract a bit field from one operand and insert it into another with an option to sign or zero extend the field
US8683261B2 (en) * 2011-07-20 2014-03-25 International Business Machines Corporation Out of order millicode control operation
CN104011652B (en) * 2011-12-30 2017-10-27 英特尔公司 packing selection processor, method, system and instruction
US9459864B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Vector string range compare
US9588762B2 (en) 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
US9459868B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a dynamically determined memory boundary
US9710266B2 (en) 2012-03-15 2017-07-18 International Business Machines Corporation Instruction to compute the distance to a specified memory boundary
US9459867B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a specified memory boundary indicated by the instruction
US9454366B2 (en) 2012-03-15 2016-09-27 International Business Machines Corporation Copying character data having a termination character from one memory location to another
US9268566B2 (en) 2012-03-15 2016-02-23 International Business Machines Corporation Character data match determination by loading registers at most up to memory block boundary and comparing
US9715383B2 (en) 2012-03-15 2017-07-25 International Business Machines Corporation Vector find element equal instruction
US9280347B2 (en) 2012-03-15 2016-03-08 International Business Machines Corporation Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
US9454367B2 (en) * 2012-03-15 2016-09-27 International Business Machines Corporation Finding the length of a set of character data having a termination character
US8874933B2 (en) * 2012-09-28 2014-10-28 Intel Corporation Instruction set for SHA1 round processing on 128-bit data paths
US8953785B2 (en) 2012-09-28 2015-02-10 Intel Corporation Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
US9665368B2 (en) * 2012-09-28 2017-05-30 Intel Corporation Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register
US20150052330A1 (en) * 2013-08-14 2015-02-19 Qualcomm Incorporated Vector arithmetic reduction
US20150186137A1 (en) * 2013-12-27 2015-07-02 Tal Uliel Systems, apparatuses, and methods for vector bit test
US9639671B2 (en) * 2014-05-27 2017-05-02 Assured Information Security, Inc. Secure execution of encrypted program instructions
US9317719B2 (en) * 2014-09-04 2016-04-19 Intel Corporation SM3 hash algorithm acceleration processors, methods, systems, and instructions
CN105522826B (en) * 2014-10-16 2017-06-23 珠海艾派克微电子有限公司 Check value production method, consumable chip and the consumption material box including the consumable chip
GB2573121B (en) * 2018-04-24 2020-09-30 Subsea 7 Norway As Injecting fluid into a hydrocarbon production line or processing system
WO2020092257A1 (en) * 2018-10-29 2020-05-07 Cryptography Research, Inc. Constant time secure arithmetic-to-boolean mask conversion
CN112905528A (en) * 2021-02-09 2021-06-04 深圳市众芯诺科技有限公司 Intelligent household chip based on Internet of things

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2317469A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Data processing system register control
WO1999014665A2 (en) * 1997-09-17 1999-03-25 Sony Electronics Inc. Digital signal processor particularly suited for decoding digital audio
US20030037085A1 (en) * 2001-08-20 2003-02-20 Sandbote Sam B. Field processing unit

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825895A (en) 1973-05-14 1974-07-23 Amdahl Corp Operand comparator
US3982229A (en) * 1975-01-08 1976-09-21 Bell Telephone Laboratories, Incorporated Combinational logic arrangement
US4713750A (en) 1983-03-31 1987-12-15 Fairchild Camera & Instrument Corporation Microprocessor with compact mapped programmable logic array
US4569016A (en) * 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
US4578750A (en) 1983-08-24 1986-03-25 Amdahl Corporation Code determination using half-adder based operand comparator
US4785393A (en) 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
US5113523A (en) 1985-05-06 1992-05-12 Ncube Corporation High performance computer system
JPS6382513A (en) 1986-09-26 1988-04-13 Toshiba Corp Barrel shifter
US5859994A (en) 1992-08-10 1999-01-12 Intel Corporation Apparatus and method for modifying instruction length decoding in a computer processor
WO1994027215A1 (en) 1993-05-07 1994-11-24 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US6067613A (en) 1993-11-30 2000-05-23 Texas Instruments Incorporated Rotation register for orthogonal data transformation
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US5751614A (en) * 1994-03-08 1998-05-12 Exponential Technology, Inc. Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU
US5781457A (en) * 1994-03-08 1998-07-14 Exponential Technology, Inc. Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5748950A (en) 1994-09-20 1998-05-05 Intel Corporation Method and apparatus for providing an optimized compare-and-branch instruction
EP0730220A3 (en) 1995-03-03 1997-01-08 Hal Computer Systems Inc Method and apparatus for rapid execution of control transfer instructions
US5732242A (en) 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
US5822606A (en) * 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
TW380237B (en) * 1996-09-23 2000-01-21 Advanced Risc Mach Ltd Data processing system register control
JP3790607B2 (en) 1997-06-16 2006-06-28 松下電器産業株式会社 VLIW processor
US6223256B1 (en) 1997-07-22 2001-04-24 Hewlett-Packard Company Computer cache memory with classes and dynamic selection of replacement algorithms
US6112293A (en) 1997-11-17 2000-08-29 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US20020147969A1 (en) 1998-10-21 2002-10-10 Richard A. Lethin Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method
US6446197B1 (en) 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions
US6763327B1 (en) 2000-02-17 2004-07-13 Tensilica, Inc. Abstraction of configurable processor functionality for operating systems portability
US6738895B1 (en) 2000-08-31 2004-05-18 Micron Technology, Inc. Method and system for substantially registerless processing
US7165101B2 (en) 2001-12-03 2007-01-16 Sun Microsystems, Inc. Transparent optimization of network traffic in distributed systems
US7493480B2 (en) 2002-07-18 2009-02-17 International Business Machines Corporation Method and apparatus for prefetching branch history information
US8335810B2 (en) 2006-01-31 2012-12-18 Qualcomm Incorporated Register-based shifts for a unidirectional rotator
US7895419B2 (en) * 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US20090182982A1 (en) 2008-01-11 2009-07-16 International Business Machines Corporation Rotate Then Insert Selected Bits Facility and Instructions Therefore

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2317469A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Data processing system register control
WO1999014665A2 (en) * 1997-09-17 1999-03-25 Sony Electronics Inc. Digital signal processor particularly suited for decoding digital audio
US20030037085A1 (en) * 2001-08-20 2003-02-20 Sandbote Sam B. Field processing unit

Also Published As

Publication number Publication date
CN101911015B (en) 2016-01-20
JP2011509476A (en) 2011-03-24
US9135004B2 (en) 2015-09-15
EP2243076A2 (en) 2010-10-27
WO2009087162A2 (en) 2009-07-16
US20150006860A1 (en) 2015-01-01
US20100299506A1 (en) 2010-11-25
US20090182981A1 (en) 2009-07-16
US7895419B2 (en) 2011-02-22
CN101911015A (en) 2010-12-08
KR20100113076A (en) 2010-10-20
KR101231556B1 (en) 2013-02-08
US8838943B2 (en) 2014-09-16
JP5357181B2 (en) 2013-12-04

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