WO2009065224A8 - Data channel test apparatus and method thereof - Google Patents

Data channel test apparatus and method thereof Download PDF

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Publication number
WO2009065224A8
WO2009065224A8 PCT/CA2008/002051 CA2008002051W WO2009065224A8 WO 2009065224 A8 WO2009065224 A8 WO 2009065224A8 CA 2008002051 W CA2008002051 W CA 2008002051W WO 2009065224 A8 WO2009065224 A8 WO 2009065224A8
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WO
WIPO (PCT)
Prior art keywords
data channel
devices
controller
series
test apparatus
Prior art date
Application number
PCT/CA2008/002051
Other languages
French (fr)
Other versions
WO2009065224A1 (en
Inventor
Hong Beom Pyeon
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Publication of WO2009065224A1 publication Critical patent/WO2009065224A1/en
Publication of WO2009065224A8 publication Critical patent/WO2009065224A8/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls

Abstract

A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.
PCT/CA2008/002051 2007-11-23 2008-11-21 Data channel test apparatus and method thereof WO2009065224A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US98987907P 2007-11-23 2007-11-23
US60/989,879 2007-11-23
US12/028,335 US7913128B2 (en) 2007-11-23 2008-02-08 Data channel test apparatus and method thereof
US12/028,335 2008-02-08

Publications (2)

Publication Number Publication Date
WO2009065224A1 WO2009065224A1 (en) 2009-05-28
WO2009065224A8 true WO2009065224A8 (en) 2010-01-14

Family

ID=40667081

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2008/002051 WO2009065224A1 (en) 2007-11-23 2008-11-21 Data channel test apparatus and method thereof

Country Status (2)

Country Link
US (2) US7913128B2 (en)
WO (1) WO2009065224A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7925949B2 (en) * 2008-10-15 2011-04-12 Micron Technology, Inc. Embedded processor
US9476938B2 (en) * 2013-09-27 2016-10-25 Novachips Canada Inc. Method and apparatus for testing surface mounted devices
KR102401093B1 (en) * 2015-09-17 2022-05-24 에스케이하이닉스 주식회사 Semiconductor memory and memory system using the same
KR20180024961A (en) * 2016-08-31 2018-03-08 에스케이하이닉스 주식회사 Method for control of distortion in exposure mask
CN113452538B (en) * 2020-03-26 2022-12-13 华为技术有限公司 Control device, execution device, device management method, and device management system
US11841396B1 (en) * 2021-03-22 2023-12-12 Marvell Asia Pte Ltd United states test controller for system-on-chip validation

Family Cites Families (122)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4174536A (en) * 1977-01-21 1979-11-13 Massachusetts Institute Of Technology Digital communications controller with firmware control
DE3586523T2 (en) * 1984-10-17 1993-01-07 Fujitsu Ltd SEMICONDUCTOR MEMORY ARRANGEMENT WITH A SERIAL DATA INPUT AND OUTPUT CIRCUIT.
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
NL192801C (en) * 1986-09-10 1998-02-03 Philips Electronics Nv A method for testing a carrier with a plurality of digitally operating integrated circuits, an integrated circuit suitable for mounting on a carrier thus to be tested, and a carrier provided with several such integrated circuits.
DE3886038T2 (en) 1988-07-13 1994-05-19 Philips Nv Storage device which contains a static RAM memory adapted for carrying out a self-test and integrated circuit which contains such a device as built-in static RAM memory.
WO1990010903A1 (en) * 1989-03-15 1990-09-20 Oki Electric Industry Co., Ltd. Serial data receiving circuit
US5126808A (en) * 1989-10-23 1992-06-30 Advanced Micro Devices, Inc. Flash EEPROM array with paged erase architecture
US5185722A (en) * 1989-11-22 1993-02-09 Sharp Kabushiki Kaisha Semiconductor memory device having a memory test circuit
US5175819A (en) * 1990-03-28 1992-12-29 Integrated Device Technology, Inc. Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer
US5315130A (en) * 1990-03-30 1994-05-24 Tactical Fabs, Inc. Very high density wafer scale device architecture
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US5132635A (en) * 1991-03-05 1992-07-21 Ast Research, Inc. Serial testing of removable circuit boards on a backplane bus
US5430859A (en) 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
KR950000761B1 (en) * 1992-01-15 1995-01-28 삼성전자 주식회사 Apparatus for synchronizing serial input signals
JP3088180B2 (en) * 1992-03-26 2000-09-18 日本電気アイシーマイコンシステム株式会社 Serial input interface circuit
GB9217728D0 (en) 1992-08-20 1992-09-30 Texas Instruments Ltd Method of testing interconnections between integrated circuits in a circuit
KR960000616B1 (en) * 1993-01-13 1996-01-10 삼성전자주식회사 Non-volatile semiconductor memory device
JPH06275069A (en) * 1993-03-20 1994-09-30 Hitachi Ltd Serial memory
US5365484A (en) * 1993-08-23 1994-11-15 Advanced Micro Devices, Inc. Independent array grounds for flash EEPROM array with paged erase architechture
JPH0793219A (en) * 1993-09-20 1995-04-07 Olympus Optical Co Ltd Information processor
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5452259A (en) * 1993-11-15 1995-09-19 Micron Technology Inc. Multiport memory with pipelined serial input
US5526311A (en) * 1993-12-30 1996-06-11 Intel Corporation Method and circuitry for enabling and permanently disabling test mode access in a flash memory device
US5404460A (en) * 1994-01-28 1995-04-04 Vlsi Technology, Inc. Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus
US5596724A (en) * 1994-02-04 1997-01-21 Advanced Micro Devices Input/output data port with a parallel and serial interface
DE4429433C1 (en) * 1994-08-19 1995-10-26 Siemens Ag Address association method for modular stored program controller
US5473566A (en) * 1994-09-12 1995-12-05 Cirrus Logic, Inc. Memory architecture and devices, systems and methods utilizing the same
KR0142367B1 (en) * 1995-02-04 1998-07-15 김광호 Erase verifying circuit for nonvolatile semiconductor memory having dolumn redundancy
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
JP3361648B2 (en) * 1995-03-15 2003-01-07 富士通株式会社 Semiconductor memory device having data compression test function and test method therefor
US5594694A (en) * 1995-07-28 1997-01-14 Micron Quantum Devices, Inc. Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell
US5835935A (en) * 1995-09-13 1998-11-10 Lexar Media, Inc. Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory
JP3693721B2 (en) * 1995-11-10 2005-09-07 Ｎｅｃエレクトロニクス株式会社 Microcomputer with built-in flash memory and test method thereof
TW307869B (en) * 1995-12-20 1997-06-11 Toshiba Co Ltd Semiconductor memory
KR100211760B1 (en) * 1995-12-28 1999-08-02 윤종용 Data i/o path control circuit of semiconductor memory device having multi-bank structure
KR0170723B1 (en) * 1995-12-29 1999-03-30 김광호 Semiconductor memory device having duale bank
US5828899A (en) * 1996-01-04 1998-10-27 Compaq Computer Corporation System for peripheral devices recursively generating unique addresses based on the number of devices connected dependent upon the relative position to the port
JPH09231740A (en) * 1996-02-21 1997-09-05 Nec Corp Semiconductor memory
US5777488A (en) * 1996-04-19 1998-07-07 Seeq Technology, Inc. Integrated circuit I/O node useable for configuration input at reset and normal output at other times
US5941974A (en) * 1996-11-29 1999-08-24 Motorola, Inc. Serial interface with register selection which uses clock counting, chip select pulsing, and no address bits
KR100243335B1 (en) * 1996-12-31 2000-02-01 김영환 Daisy chain type memory device having refresh circuit
KR100272037B1 (en) * 1997-02-27 2000-12-01 니시무로 타이죠 Non volatile simiconductor memory
US5900021A (en) * 1997-04-04 1999-05-04 United Memories, Inc. Pad input select circuit for use with bond options
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
GB2329792A (en) 1997-08-20 1999-03-31 Nokia Telecommunications Oy Identification signals enable a transceiver module to correctly configure itself to an attached functional module
JPH1166841A (en) * 1997-08-22 1999-03-09 Mitsubishi Electric Corp Semiconductor storage device
KR100240873B1 (en) 1997-08-26 2000-01-15 윤종용 Serial interface unit having the same register for reception/transmission
US6049901A (en) * 1997-09-16 2000-04-11 Stock; Mary C. Test system for integrated circuits using a single memory for both the parallel and scan modes of testing
US5926422A (en) * 1997-10-02 1999-07-20 Texas Instruments Incorporated Integrated circuit memory device having current-mode data compression test mode
JP4039532B2 (en) * 1997-10-02 2008-01-30 株式会社ルネサステクノロジ Semiconductor integrated circuit device
US5937425A (en) * 1997-10-16 1999-08-10 M-Systems Flash Disk Pioneers Ltd. Flash file system optimized for page-mode flash technologies
US6148364A (en) * 1997-12-30 2000-11-14 Netlogic Microsystems, Inc. Method and apparatus for cascading content addressable memory devices
US6002638A (en) * 1998-01-20 1999-12-14 Microchip Technology Incorporated Memory device having a switchable clock output and method therefor
WO1999045460A2 (en) 1998-03-02 1999-09-10 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US6085290A (en) * 1998-03-10 2000-07-04 Nexabit Networks, Llc Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM)
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
US6438604B1 (en) 1998-10-05 2002-08-20 Canon Kabushiki Kaisha Digital video network interface
US5995417A (en) * 1998-10-20 1999-11-30 Advanced Micro Devices, Inc. Scheme for page erase and erase verify in a non-volatile memory array
JP4601737B2 (en) 1998-10-28 2010-12-22 株式会社東芝 Memory embedded logic LSI
JP2000149564A (en) * 1998-10-30 2000-05-30 Mitsubishi Electric Corp Semiconductor memory device
US6185708B1 (en) * 1998-11-27 2001-02-06 Advantest Corp. Maintenance free test system
US6304921B1 (en) * 1998-12-07 2001-10-16 Motorola Inc. System for serial peripheral interface with embedded addressing circuit for providing portion of an address for peripheral devices
KR100284742B1 (en) * 1998-12-28 2001-04-02 윤종용 Memory device with the minimum number of I / O sense amplifiers
DE19918095C1 (en) * 1999-04-21 2000-10-12 Siemens Ag Solenoid valve control circuit for inlet and outlet valves in internal combustion engine cylinder
US6680904B1 (en) 1999-12-27 2004-01-20 Orckit Communications Ltd. Bi-directional chaining of network access ports
US20050160218A1 (en) 2004-01-20 2005-07-21 Sun-Teck See Highly integrated mass storage device with an intelligent flash controller
US6442098B1 (en) * 2000-02-08 2002-08-27 Alliance Semiconductor High performance multi-bank compact synchronous DRAM architecture
US6816933B1 (en) 2000-05-17 2004-11-09 Silicon Laboratories, Inc. Serial device daisy chaining method and apparatus
US6535948B1 (en) 2000-05-31 2003-03-18 Agere Systems Inc. Serial interface unit
US6317350B1 (en) * 2000-06-16 2001-11-13 Netlogic Microsystems, Inc. Hierarchical depth cascading of content addressable memory devices
US6754807B1 (en) 2000-08-31 2004-06-22 Stmicroelectronics, Inc. System and method for managing vertical dependencies in a digital signal processor
US6317352B1 (en) * 2000-09-18 2001-11-13 Intel Corporation Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
US6853557B1 (en) 2000-09-20 2005-02-08 Rambus, Inc. Multi-channel memory architecture
FR2816751A1 (en) 2000-11-15 2002-05-17 St Microelectronics Sa Flash memory erasable by page and method for data storaage, comprising array with counter and sectors, and circuits for reading page address and incrementing counter
ITRM20010104A1 (en) 2001-02-27 2002-08-27 Micron Technology Inc DATA COMPRESSION READING MODE FOR TESTING MEMORIES.
JP4115676B2 (en) * 2001-03-16 2008-07-09 株式会社東芝 Semiconductor memory device
US6732221B2 (en) 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US6996644B2 (en) 2001-06-06 2006-02-07 Conexant Systems, Inc. Apparatus and methods for initializing integrated circuit addresses
DE10130785C2 (en) * 2001-06-26 2003-04-30 Infineon Technologies Ag Memory chip and device for testing a memory chip
KR100413762B1 (en) 2001-07-02 2003-12-31 삼성전자주식회사 Semiconductor memory device having adjustable banks and method thereof
JP3802377B2 (en) * 2001-07-27 2006-07-26 Ｎｅｃエレクトロニクス株式会社 Flip-flop and scan path circuit
US6928501B2 (en) 2001-10-15 2005-08-09 Silicon Laboratories, Inc. Serial device daisy chaining method and apparatus
US6763426B1 (en) 2001-12-27 2004-07-13 Cypress Semiconductor Corporation Cascadable content addressable memory (CAM) device and architecture
US6938188B1 (en) * 2002-01-29 2005-08-30 Advanced Digital Information Corporation Method for verifying functional integrity of computer hardware, particularly data storage devices
US7073022B2 (en) 2002-05-23 2006-07-04 International Business Machines Corporation Serial interface for a data storage array
US7062601B2 (en) 2002-06-28 2006-06-13 Mosaid Technologies Incorporated Method and apparatus for interconnecting content addressable memory devices
KR100499686B1 (en) 2002-07-23 2005-07-07 주식회사 디지털웨이 Portable flash memory extended memory capacity
CA2396632A1 (en) 2002-07-31 2004-01-31 Mosaid Technologies Incorporated Cam diamond cascade architecture
KR100487539B1 (en) 2002-09-02 2005-05-03 삼성전자주식회사 Nonvolatile semiconductor memory device for connecting to serial advanced techonology attachement cable
US6799133B2 (en) * 2002-09-24 2004-09-28 Analog Devices, Inc. Test mode control circuit for reconfiguring a device pin of an integrated circuit chip
EP1424635B1 (en) 2002-11-28 2008-10-29 STMicroelectronics S.r.l. Non volatile memory device architecture, for instance a flash kind, having a serial communication interface
KR100493884B1 (en) 2003-01-09 2005-06-10 삼성전자주식회사 Control apparatus and method for xip(execution in place) in serial flash memory and flash memory chip using the same
US20040199721A1 (en) 2003-03-12 2004-10-07 Power Data Communication Co., Ltd. Multi-transmission interface memory card
US7127629B2 (en) * 2003-06-03 2006-10-24 Intel Corporation Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
US7200787B2 (en) * 2003-06-03 2007-04-03 Intel Corporation Memory channel utilizing permuting status patterns
US7194581B2 (en) * 2003-06-03 2007-03-20 Intel Corporation Memory channel with hot add/remove
US7340537B2 (en) * 2003-06-04 2008-03-04 Intel Corporation Memory channel with redundant presence detect
US7165153B2 (en) * 2003-06-04 2007-01-16 Intel Corporation Memory channel with unidirectional links
US7386768B2 (en) * 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
JP4156986B2 (en) 2003-06-30 2008-09-24 株式会社東芝 Nonvolatile semiconductor memory device
US20050015213A1 (en) * 2003-07-15 2005-01-20 Kevin Somervill Method and apparatus for testing an electronic device
US7085966B2 (en) * 2003-09-25 2006-08-01 International Business Machines Corporation Methods and arrangements for repairing ports
US7177211B2 (en) * 2003-11-13 2007-02-13 Intel Corporation Memory channel test fixture and method
US7143207B2 (en) * 2003-11-14 2006-11-28 Intel Corporation Data accumulation between data path having redrive circuit and memory device
US7219294B2 (en) * 2003-11-14 2007-05-15 Intel Corporation Early CRC delivery for partial frame
US7447953B2 (en) * 2003-11-14 2008-11-04 Intel Corporation Lane testing with variable mapping
US7212423B2 (en) * 2004-05-31 2007-05-01 Intel Corporation Memory agent core clock aligned to lane
US7383399B2 (en) * 2004-06-30 2008-06-03 Intel Corporation Method and apparatus for memory compression
US7254763B2 (en) 2004-09-01 2007-08-07 Agere Systems Inc. Built-in self test for memory arrays using error correction coding
KR100705221B1 (en) 2004-09-03 2007-04-06 에스티마이크로일렉트로닉스 엔.브이. Flash memory device and method of erasing the flash memory cell using the same
US6950325B1 (en) 2004-10-07 2005-09-27 Winbond Electronics Corporation Cascade-connected ROM
US7395476B2 (en) * 2004-10-29 2008-07-01 International Business Machines Corporation System, method and storage medium for providing a high speed test interface to a memory subsystem
US7139673B1 (en) 2004-11-05 2006-11-21 Xilinx, Inc. Method of and circuit for verifying a data transfer protocol
US7366931B2 (en) * 2004-12-30 2008-04-29 Intel Corporation Memory modules that receive clock information and are placed in a low power state
US20070022349A1 (en) * 2005-07-07 2007-01-25 Agilent Technologies, Inc. Test apparatus with tester channel availability identification
US7516349B2 (en) * 2005-12-29 2009-04-07 Intel Corporation Synchronized memory channels with unidirectional links
US7508724B2 (en) 2006-11-30 2009-03-24 Mosaid Technologies Incorporated Circuit and method for testing multi-device systems
DE112007003412T5 (en) 2007-03-23 2010-01-21 Advantest Corp. Tester and electronic device
US7890811B2 (en) * 2007-06-29 2011-02-15 Intel Corporation Method and apparatus for improved memory reliability, availability and serviceability

Also Published As

Publication number Publication date
US8392767B2 (en) 2013-03-05
US7913128B2 (en) 2011-03-22
US20090265589A2 (en) 2009-10-22
US20110154137A1 (en) 2011-06-23
WO2009065224A1 (en) 2009-05-28
US20090138768A1 (en) 2009-05-28

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