WO2009055103A4 - Low-power source-synchronous signaling - Google Patents

Low-power source-synchronous signaling Download PDF

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Publication number
WO2009055103A4
WO2009055103A4 PCT/US2008/069250 US2008069250W WO2009055103A4 WO 2009055103 A4 WO2009055103 A4 WO 2009055103A4 US 2008069250 W US2008069250 W US 2008069250W WO 2009055103 A4 WO2009055103 A4 WO 2009055103A4
Authority
WO
WIPO (PCT)
Prior art keywords
signal
timing
timing signal
data
circuitry
Prior art date
Application number
PCT/US2008/069250
Other languages
French (fr)
Other versions
WO2009055103A3 (en
WO2009055103A2 (en
Inventor
Jared L Zerbe
Frederick Ware
Original Assignee
Rambus Inc
Jared L Zerbe
Frederick Ware
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Jared L Zerbe, Frederick Ware filed Critical Rambus Inc
Priority to EP08841143A priority Critical patent/EP2223227B1/en
Priority to US12/738,610 priority patent/US8793525B2/en
Publication of WO2009055103A2 publication Critical patent/WO2009055103A2/en
Publication of WO2009055103A3 publication Critical patent/WO2009055103A3/en
Publication of WO2009055103A4 publication Critical patent/WO2009055103A4/en
Priority to US14/445,014 priority patent/US9536589B2/en
Priority to US15/389,407 priority patent/US10418089B2/en
Priority to US16/549,992 priority patent/US11195570B2/en
Priority to US17/521,379 priority patent/US11749336B2/en
Priority to US18/222,808 priority patent/US20240021236A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

Claims

AMENDED CLAIMS received by the International Bureau on 18 June 2009.
1. A method of operation within a digital system, the method compri sing: receiving a data signal over each one of at least two parallel data links; receiving a timing signal on a dedicated link; distributing a sampling signal based on the timing signal using a timing signal distribution network within an IC device to each of a plurality of samplers, at least one sampler per external data link, to responsive Iy sample the associated data signal; obtaining a reference that represents the timing of the data signals, independent of the timing signal distribution network, and comparing the reference and the sampling signal; and adjusting one of (1) the relation between the timing signal and the data signals or (2) the relation between the sampling signal and the data signals to compensate for relative delay imparted by the timing signal distribution network.
2. The method according to claim 1 wherein the IC device is a first IC device and the system further includes a second IC device coupled to the first IC device, the second IC device generating the timing signal and providing the timing signal via the dedicated link, and wherein the comparing includes providing an error signal to the second IC device to generate an adjustment to one of (1) the timing signal, (2) the sampling signal, or (3) transmit timing for the data signals to provide the compensation.
47
3. The method according to claim 2 wherein the error signal provides an indication of whether one of the reference signal or the sampling signal is early or late relative to the data signal,
4. The method according to claim 2 wherein the system includes a backchannei coupling the second IC device to the first IC device, and wherein the error signal is transmitted over the backchaπnel from the first JC device to the second IC device.
5. The method according to claim 2 wherein the timing signal comprises a strobe signal.
6. The method according to claim 1 wherein the digital system comprises a memory system.
7. The method according to claim 6 wherein the system further supports a steep mode of operation and a normal mode of operation, and wherein the method further comprises upon exiting the sleep mode of operation, adjusting the phase of the timing signal on a transient basis.
8. The method according to claim 1 wherein the adjusting one of (1) the relation between the timing signal and the data signals or (2) the relation between the sampling signal and the data signals to compensate for relative delay imparted by the timing signal distribution network further includes compensating for drift.
48
9. The method according to claim 1 wherein receiving a timing signal comprises receiving multiple timing references, and the IC device includes a mixer circuit with a programmable input, wherein the adjusting comprises setting a mixer value via the programmable input.
10. The method according to claim 1 and further comprising: receiving a phase clock, and wherein the deriving the source synchronous timing reference includes comparing the phase clock to the sampling clock.
11. The method according to claim 1 and further comprising: processing at least one of the data signals to obtain a recovered clock, wherein the comparing includes comparing the recovered clock with the distributed sampling signal to obtain a phase error.
12. A method of operation within an integrated circuit (IC) device, the method comprising: transmitting data to a recipient over each one of at least two parallel external data links; and transmitting a timing signal to the recipient on a dedicated external link, wherein the transmitting is intermittent, including periods of active communication and idle periods; and upon cessation of an idle period, using a phase correction circuit to adjust the phase of the timing signal on a transient basis.
49
13. The method according to claim 12 wherein the idle period comprises one of a sleep mode or a shutdown mode, and wherein using a phase correction circuit upon cessation of the idle period comprises exiting the one of a sleep mode or shutdown mode.
14. The method according to claim 13 wherein using a phase correction circuit comprises (1) generating a delay control value as part of a normal mode of operation; (2) generating a corrective value to compensate for deterministic phase drift, and (3) summing the delay control value and the corrective value to adjust the phase of the timing signal on a transient basis.
15. The method according to claim 14 wherein generating a corrective value comprises determining the phase difference count value, and sizing the corrective value proportionally with a phase difference count value.
16. The method according to claim 14 wherein generating a corrective value comprises arithmetically computing the corrective value based at least in part on a phase difference count value.
17. The method according to claim 14 wherein generating a corrective value comprises retrieving a corrective value from a lookup table, the count value based at least in part on a phase difference count value.
50
18. The method according to claim 14 wherein generating a corrective value comprises storing programmable values in a memory, and retrieving at least one of the programmable values based on a phase difference count value.
19. The method according to claim 18 wherein the programmable values comprise coefficients of polynomial expressions.
20. An apparatus comprising: distribution circuitry to distribute a sampling signal based on a timing signal, a plurality of samplers coupled to the distribution circuitry to receive the timing signal, and to responsively sample an associated data signal received via a respective data link; timing circuitry to provide a reference that represents the timing of the data signals, independent of the timing signal distribution circuitry; a comparator to compare the reference and the sampling signal; and adjustment circuitry to modify one of (1) the relation between the timing signal and the data signals or (2) the relation between the sampling signal and the data signals to compensate for relative delay imparted by the timing signal distribution circuitry.
21. The apparatus of claim 20 wherein the adjustment circuitry is disposed in a memory controller to modify the timing signal relative to the data signal to compensate for relative delay imparted by the timing signal distribution circuitry.
22. The apparatus of claim 20 wherein the adjustment circuitry is disposed in a memory controller to modify the transmit timing of the data signal.
23. The apparatus of claim 20 wherein the comparator includes error signal generation circuitry to output an error signal based on the comparison between the reference and the sampling signal.
24. The apparatus of claim 23 wherein the timing circuitry is employed on a second IC device, and wherein the apparatus further includes a first IC device, the first IC device having a backchannei transmit circuit to transmit the error signal to the second IC device.
25. The apparatus of claim 20 wherein: the timing circuitry provides multiple timing references; the apparatus further includes a mixer circuit with a programmable input; and the adjustment circuitry sets a mixer value into the programmable input, to modify the one of the timing signal or the sampling signal using the mixer circuit.
26. The apparatus of claim 20 wherein: one of the plurality of samplers samples a specific data signal in accordance with the sampling clock; the IC device further comprises a second receiver that also samples the specific data signal in accordance with a time-shifted version of the sampling clock; and the comparator is coupled to the one of the plurality of samplers and to the second receiver to compare respective outputs, the comparator generating a value that indicates whether the sampling clock is early or late relative to the timing reference based on the respective outputs.
52
27. The apparatus of claim 20 embodied as a DRAM integrated circuit.
28. An integrated circuit (IC) device comprising: a set of first transmit circuits to each transmit data to a recipient over respective parallel external data links; and a second transmit circuit to transmit a timing signal to the recipient on a dedicated external link, wherein the transmitting of each signal is intermittent, including periods of active communication and idle periods; and a phase correction circuit to, upon cessation of an idle period, adjust the phase of the timing signal on a transient basis.
29. The IC device of claim 28 and further including mode control circuitry to support at least one of a sleep mode or a shutdown mode, and wherein the mode control circuitry, upon cessation of the idle period, controls exiting of the one of a sleep mode or shutdown mode.
30. The IC device of claim 28 wherein the phase correction circuit generates a delay control value based on a phase difference count value, and wherein the phase correction circuit includes a transient control circuit to generate a corrective value to compensate for phase drift attributable to the idle period, the delay control value and corrective value summed via a summing circuit to adjust the timing signal.
31 The IC device of claim 30 wherein the generated corrective value is proportional to the phase difference count value.
53
32. The IC device of claim 30 wherein the transient control circuit comprises an arithmetic computation circuit to arithmetically compute the corrective value.
33. The IC device of claim 30 wherein the transient control circuit comprises a lookup table to store a plurality of corrective values based on possible values of the phase difference count, and wherein the corrective value is retrieved from the lookup table based on the actual phase difference count value.
34. The IC device according to claim 30 wherein the transient control circuit includes memory to store a plurality of programmable values, one of the plurality of programmable values retrieved from the memory for use as the corrective value.
35. The IC device according to claim 34 wherein the programmable values comprise coefficients of polynomial expressions.
36. An apparatus comprising: means for receiving a data signal over each one of at least two parallel data links; means for receiving a timing signal on a dedicated link; means for distributing a sampling signal based on the timing signal using a timing signal distribution network within the apparatus to each of a plurality of samplers, at least one sampler per data link, to responsively sample the associated data signal; means for obtaining a reference that represents the timing of the data signals, independent of the timing signal distribution network;
54 means for comparing the reference and the sampling signal; and means for adjusting one of (1) the relation between the timing signal and the data signals or (2) the relation between the sampling signal and the data signals to compensate for relative delay imparted by the timing signal distribution network.
37. An integrated circuit (IC) device comprising: means for transmitting data to a recipient over each one of at least two parallel external data links; and means for transmitting a timing signal to the recipient on a dedicated external link, wherein the transmitting of each signal is intermittent, including periods of active communication and idle periods; and means for adjusting the phase of the timing signal on a transient basis, upon cessation of an idle period.
38. A system comprising; a second integrated circuit (IC) device to transmit a data signal over each of at least two parallel data links and to transmit a timing signal on a dedicated timing link; and a first IC device coupled to the second IC device via the links and to receive the data signals and to receive the timing signal on the dedicated timing link, the first IC device including distribution circuitry to distribute a sampling signal based on the timing signal to a plurality of samplers, at least one sampler per data link, to responsively sample a respective data signal,
55 timing derivation circuitry to derive a source synchronous timing reference that represents the timing of the data signals, independent of the timing signal distribution circuitry, a comparator to compare the source synchronous timing reference and the sampling signal, and adjustment circuitry to modify one of (1) the relation between the timing signal and the data signals or (2) the relation between the sampling signal and the data signals to compensate for relative delay imparted by the timing signal distribution network.
39. The system of claim 38 wherein the second IC device comprises a DRAM controller IC and wherein the first 1C device comprises a DRAM memory IC-
40. The system of claim 38 wherein the comparator includes error generation circuitry to generate an error signal based on the comparison of the timing reference to the sampling signal.
41. The system of claim 40 and further comprising: a backchannel that conveys the error signal from the first IC device to the second IC device.
56
PCT/US2008/069250 2007-10-22 2008-07-03 Low-power source-synchronous signaling WO2009055103A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP08841143A EP2223227B1 (en) 2007-10-22 2008-07-03 Low-power source-synchronous signaling
US12/738,610 US8793525B2 (en) 2007-10-22 2008-07-03 Low-power source-synchronous signaling
US14/445,014 US9536589B2 (en) 2007-10-22 2014-07-28 Low-power source-synchronous signaling
US15/389,407 US10418089B2 (en) 2007-10-22 2016-12-22 Low-power source-synchronous signaling
US16/549,992 US11195570B2 (en) 2007-10-22 2019-08-23 Low-power source-synchronous signaling
US17/521,379 US11749336B2 (en) 2007-10-22 2021-11-08 Low-power source-synchronous signaling
US18/222,808 US20240021236A1 (en) 2007-10-22 2023-07-17 Low-power source-synchronous signaling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98177707P 2007-10-22 2007-10-22
US60/981,777 2007-10-22

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/738,610 A-371-Of-International US8793525B2 (en) 2007-10-22 2008-07-03 Low-power source-synchronous signaling
US14/445,014 Continuation US9536589B2 (en) 2007-10-22 2014-07-28 Low-power source-synchronous signaling

Publications (3)

Publication Number Publication Date
WO2009055103A2 WO2009055103A2 (en) 2009-04-30
WO2009055103A3 WO2009055103A3 (en) 2009-06-11
WO2009055103A4 true WO2009055103A4 (en) 2009-08-06

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US (6) US8793525B2 (en)
EP (1) EP2223227B1 (en)
WO (1) WO2009055103A2 (en)

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US20100271092A1 (en) 2010-10-28

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