WO2009045091A2

WO2009045091A2 - A vertical thin polysilicon substrate isfet

Info

Publication number: WO2009045091A2
Application number: PCT/MY2008/000116
Authority: WO
Inventors: Mohd Ismahadi Syono; Rozina Abdul Rani
Original assignee: Mimos Berhad
Priority date: 2007-10-05
Filing date: 2008-09-29
Publication date: 2009-04-09
Also published as: WO2009045091A3

Abstract

The present invention generally relates to a vertical thin polysilicon substrate ISFET for the measurement of hydrogen ions (pH) and other ion activity in solution characterized in that wherein the present invention comprises of a method of making polysilicon vertical ISFET which is fully CMOS compatible and wherein the substrate is the polysilicon which is vertically sandwiched between a source and a drain and wherein a very high drive current is possible to achieve due to the thin polysilicon material and wherein the sandwiched structure is designed to ensure excellent noise isolation and wherein the gate lies on the same surface level as the drain and hence a very large area for better gate sensitivity is possible.

Description

A VERTICAL THIN POLYSILICON SUBSTRATE ISFET

FIELD OF THE INVENTION

This present invention relates to chemical or electrochemical sensors based technology and more particularly the present invention relates to the construction of such devices for the measurement of hydrogen ions (pH) and other ion activity in solution.

BACKGROUND OF THE INVENTION

The prior art devices typically use contacts on the front side (the chemically or electrochemically responsive side) of the ISFET. Thus, protection is required for the circuit leads or circuit elements to isolate them from the environment. In some cases this protection has been attempted by providing contact from the back of the device. This has been done, for example, by making contact with the source and drain by way of holes which have been laser machined all the way through the device or by migrating aluminum through the device. These methods all have the disadvantage of producing either a disrupted front surface or a region which is not mechanically strong, In this connection, it should be pointed out that a planar front surface is desirable in order to avoid susceptibility to contamination which can cause a fouling of the gate membrane.

It is an object of this invention to provide a method and means for providing an ISFET probe having protected contacts while maintaining a planar front surface which is mechanically strong. It is also the objective of the present invention to provide a highly isolated vertical ISFET sensor for better SNR.

SUMMARY OF THE INVENTION

The present invention generally relates to a vertical thin polysilicon substrate ISFET for the measurement of hydrogen ions (pH) and other ion activity in solution characterized in that wherein the present invention comprises of a method of making polysilicon vertical ISFET which is fully CMOS compatible and wherein the substrate is the polysilicon which is vertically sandwiched between a source and a drain. A very high drive current is possible to achieve due to the thin polysilicon material and wherein the sandwiched structure is designed to ensure excellent noise isolation and wherein the gate lies on the same surface level as the drain and hence a very large area for better gate sensitivity is possible. Substrate leakage is eliminated by reducing substrate leakage to zero using existing CMOS line and making a very compact ISFET.

The features of the present invention is that it is fully CMOS compatible, it is almost a planar shaped like member, it consist of a very high drive current, an excellent noise isolation thru very thin substrate (polysilicon) and a built-in connectivity to source, drain & substrate.

The method of operation of the present invention is that wherein when the ISFET is immersed in a solution, H⁺ ions will be trapped by silicon hydroxyl ions and wherein this would induce an inversion channel in the polysilicon with the closed loop circuit completed by the reference electrode. The output voltage can be read off the reference electrode by using a constant current-constant voltage readout circuit. A very high and stable current can be generated between source and drain. The method according to the present invention comprises of the following steps:

(i) Implanting a low voltage with a high dose of n+ implant to create a

Source on a p type wafer - (Figure 2)

(ii) Growing very thin polysilicon. Threshold adjust implant (p type) if necessary - (Figure 2)

(iii) Depositing a thin oxide layer as gate oxide - (Figure 2)

(iv) Growing LPCVD nitride as sensing gate material and protection layer for ISFET - (Figure 2) (v) Pattern and etch nitride and oxide to create contact to Drain - Mask 1 (Figure 3)

(vi) Deposit TiN and Tungsten or inert metal as both contact to drain and as a reference electrode - (Figure 4)

(vii) Patterning and etching of metal layer - Mask 2 (Figure 4)

(viii) Depositing PECVD nitride as insulator to Drain - (Figure 5)

(ix) Patterning and etching of PECVD nitride - Mask 3 (Figure 5)

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 shows a diagrammatic view of the present invention.

Figure 2 shows the important steps of the fabrication flow according to the present invention.

Figure 3 shows the important steps of the fabrication flow according to the present invention.

Figure 4 shows the important steps of the fabrication flow according to the present invention.

Figure 5 shows the important steps of the fabrication flow according to the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention would be described with reference made to the accompanied drawings but not limited thereto to the scope of the invention.

The present invention generally describes a method of making polysilicon vertical ISFET which is fully CMOS compatible. According to the present invention as the substrate is the polysilicon which is vertically sandwiched between a source and a drain, a very high drive current is possible to achieve due to the thin polysilicon material. The sandwiched structure according to the present invention is also designed to ensure excellent noise isolation. According to the present invention the gate lies on the same surface level as the drain and hence a very large area for better gate sensitivity is possible.

In the prior art, normal ISFET are susceptible to substrate leakage. However, in the present invention this problem is eliminated by reducing substrate (polysilicon layer) leakage to zero using existing CMOS line and making a very compact ISFET

Some of the main features of the present invention is as follow:-

- Fully CMOS compatible

- Almost planar shaped like member

- Consist of a very high drive current - Excellent noise isolation thru very thin substrate and trench isolation

- Built-in connectivity to source, drain & substrate

Now the method of operation of the present invention would be described. When the ISFET is immersed in a solution, H⁺ ions will be trapped by silicon nitride hydroxyl ions, This would induce an inversion channel with assistance from biasing the reference electrode. A very high current can be generated between source and drain. The method according to the present invention comprises of the following steps :-

Step 1: Implanting a low voltage with a high dose of n+ implant to create a Source on a p type wafer

Step 2: Growing very thin polysilicon. Threshold adjust implant (p type) if necessary

Step 3: Depositing a thin oxide layer as gate oxide

Step 4: Growing LPCVD nitride as sensing gate material and protection layer for ISFET

Step 5: Pattern and etch nitride and oxide to create contact to Drain - Mask 1

Step 6: Deposit TiN and Tungsten or inert metal as both contact to drain and as a reference electrode

Step 7: Patterning and etching of metal layer - Mask 2

Step 8: Depositing PECVD nitride as insulator to Drain

Step 9: Patterning and etching of PECVD nitride - Mask 3

Claims

1. A vertical thin polysilicon substrate ISFET for the measurement of hydrogen ions (pH) and other ion activity in solution characterized in that wherein the present invention comprises of a method of making polysilicon vertical

ISFET which is fully CMOS compatible and wherein the substrate is the polysilicon which is vertically sandwiched between a source and a drain and wherein a very high drive current is possible to achieve due to the thin polysilicon material and wherein the sandwiched structure is designed to ensure excellent noise isolation and wherein the gate lies on the same surface level as the drain and hence a very large area for better gate sensitivity is possible.

2. A vertical thin polysilicon substrate ISFET as claimed in Claim 1 wherein substrate leakage is eliminated by reducing substrate (polysilicon) leakage to zero using existing CMOS line and making a very compact ISFET.

3. A vertical thin polysilicon substrate ISFET claimed in Claim 1 wherein the features of the present invention is that it is fully CMOS compatible, it is almost a planar shaped like member, it consist of a very high drive current, an excellent noise isolation thru very thin substrate and a built-in connectivity to source, drain & substrate.

4. A vertical thin polysilicon substrate ISFET claimed in Claim 1 wherein the method of operation of the present invention is that wherein when the ISFET is immersed in a solution, H⁺ ions will be trapped by silicon hydroxyl ions and wherein this would induce an inversion channel in the polysilicon with the closed loop circuit completed by the reference electrode. The output voltage can be read off the reference electrode by using a constant current- constant voltage readout circuit. A very high and stable current can be generated between source and drain.

5. A vertical thin polysilicon substrate ISFET claimed in Claim 1 wherein the method according to the present invention comprises of the following steps;

(i) Implanting a low voltage with a high dose of n+ implant to create a Source on a p type wafer

(ii) Growing a very thin polysilicon. With threshold adjust implant (p type) if necessary

(iii) Depositing a thin oxide layer as gate oxide

(iv) Growing LPCVD nitride as sensing gate material and protection layer for ISFET

(v) Patterning and etching of nitride and oxide layers to create contact to

Drain - Mask 1

(vi) Depositing Titanium Nitride and Tungsten or inert metal as both contact to drain and as a reference electrode

(vii) Patterning and etching of metal layer - Mask 2

(viii) Depositing PECVD nitride as insulator to Drain

(ix) Patterning and etching of PECVD nitride - Mask 3