WO2009037614A3 - Circuit with a plurality of processors connected to a plurality of memory circuits via a network - Google Patents

Circuit with a plurality of processors connected to a plurality of memory circuits via a network Download PDF

Info

Publication number
WO2009037614A3
WO2009037614A3 PCT/IB2008/053633 IB2008053633W WO2009037614A3 WO 2009037614 A3 WO2009037614 A3 WO 2009037614A3 IB 2008053633 W IB2008053633 W IB 2008053633W WO 2009037614 A3 WO2009037614 A3 WO 2009037614A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory circuits
shared memory
processors
data object
messages
Prior art date
Application number
PCT/IB2008/053633
Other languages
French (fr)
Other versions
WO2009037614A2 (en
Inventor
Marco Jan Gerrit Bekooij
Den Brand Jan Willem Van
Original Assignee
Nxp Bv
Marco Jan Gerrit Bekooij
Den Brand Jan Willem Van
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Marco Jan Gerrit Bekooij, Den Brand Jan Willem Van filed Critical Nxp Bv
Publication of WO2009037614A2 publication Critical patent/WO2009037614A2/en
Publication of WO2009037614A3 publication Critical patent/WO2009037614A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)

Abstract

A plurality of computer programs is executed concurrently with a plurality of processors (10) that are coupled to a plurality of shared memory circuits (14) via a communication network (12). A data object is stored distributed over the plurality of shared memory circuits (14), in respective memory portions of the shared memory circuits (14). Access to a data object by different ones of the processors (10) during a program execution period is made mutually exclusive by executing acquire and release instructions of a semaphore flag for the data object. Write operation records for the write instructions are buffered in buffers (34) in the processors. Messages are transmitted via a communication network (12), comprising the write operation records from the buffers, to those of the shared memory circuits (14) where the parts are stored that are addressed by the write operations. Processing of the messages is signaled by the shared memory circuits (14) back to the processors (10). Each processor (10) verifies prior to clearing the semaphore flag in response to the release instruction that signals have been received that all previous messages to all shared memories that store data from the data object have been processed.
PCT/IB2008/053633 2007-09-18 2008-09-09 Circuit with a plurality of processors connected to a plurality of memory circuits via a network WO2009037614A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07116624.3 2007-09-18
EP07116624 2007-09-18

Publications (2)

Publication Number Publication Date
WO2009037614A2 WO2009037614A2 (en) 2009-03-26
WO2009037614A3 true WO2009037614A3 (en) 2009-05-22

Family

ID=40382028

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/053633 WO2009037614A2 (en) 2007-09-18 2008-09-09 Circuit with a plurality of processors connected to a plurality of memory circuits via a network

Country Status (1)

Country Link
WO (1) WO2009037614A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180157735A1 (en) * 2015-06-04 2018-06-07 Siemens Aktiengesellschaft Method and system for clustering engineering data in a multidisciplinary engineering system
CN114281557A (en) * 2020-09-27 2022-04-05 中兴通讯股份有限公司 Data acquisition and reporting method, system, chip, CPU and storage medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060230411A1 (en) * 2005-04-12 2006-10-12 Microsoft Corporation Resource accessing with locking

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060230411A1 (en) * 2005-04-12 2006-10-12 Microsoft Corporation Resource accessing with locking

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MONCHIERO ET AL: "Efficient Synchronization for Embedded On-Chip Multiprocessors", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 14, no. 10, 1 October 2006 (2006-10-01), pages 1049 - 1062, XP011142360, ISSN: 1063-8210 *
RADULESCU A ET AL: "An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATEDCIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 24, no. 1, 1 January 2005 (2005-01-01), pages 4 - 17, XP002343901, ISSN: 0278-0070 *

Also Published As

Publication number Publication date
WO2009037614A2 (en) 2009-03-26

Similar Documents

Publication Publication Date Title
US10942737B2 (en) Method, device and system for control signalling in a data path module of a data stream processing engine
US8006015B2 (en) Device and method for managing access requests
WO2006015868A3 (en) Global memory system for a data processor comprising a plurality of processing elements
CN102473169B (en) Dynamic system reconfiguration
JP6062506B2 (en) Computation resource pipeline in general-purpose graphics processing equipment
TW200627266A (en) Processor, method, and data processing system employing a variable store gather window
WO2005081105A3 (en) Methods and apparatus for task management in a multi-processor system
JP2019028865A (en) Information processing apparatus, information processing method, and information processing program
TW200416594A (en) Improved computing architecture and related system and method
TW200741550A (en) Methods and arrangements to dynamically modify the number of active processors in a multi-node system
JP2013512509A5 (en)
CN102662634B (en) Memory access and execution device for non-blocking transmission and execution
US20120266029A1 (en) Arrangement for processing trace data information, integrated circuits and a method for processing trace data information
WO2008127610A3 (en) Application interface on multiple processors
JPH0235559A (en) Double buffering subsystem
US20090106533A1 (en) Data processing apparatus
JP2013512511A5 (en)
WO2022001128A1 (en) Fpga board memory data reading method and apparatus, and medium
US8527671B2 (en) DMA engine
WO2009037614A3 (en) Circuit with a plurality of processors connected to a plurality of memory circuits via a network
CN106326184A (en) CPU (Central Processing Unit), GPU (Graphic Processing Unit) and DSP (Digital Signal Processor)-based heterogeneous computing framework
US6427181B1 (en) Method of and apparatus for processing information, and providing medium
US8228101B2 (en) Source-synchronous clocking
US20170308487A1 (en) Data transfer control system, data transfer control method, and program storage medium
CN104951268A (en) Method for implementing extended high-performance graphics card based on CPCI

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08807581

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08807581

Country of ref document: EP

Kind code of ref document: A2