WO2009035858A2 - Imager die package and methods of packaging an imager die on a temporary carrier - Google Patents

Imager die package and methods of packaging an imager die on a temporary carrier Download PDF

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Publication number
WO2009035858A2
WO2009035858A2 PCT/US2008/074594 US2008074594W WO2009035858A2 WO 2009035858 A2 WO2009035858 A2 WO 2009035858A2 US 2008074594 W US2008074594 W US 2008074594W WO 2009035858 A2 WO2009035858 A2 WO 2009035858A2
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WO
WIPO (PCT)
Prior art keywords
imager
die
imager die
dice
encapsulant
Prior art date
Application number
PCT/US2008/074594
Other languages
French (fr)
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WO2009035858A3 (en
Inventor
Steven Oliver
Warren M. Farnworth
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Micron Technology, Inc.
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Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020107005048A priority Critical patent/KR101170224B1/en
Publication of WO2009035858A2 publication Critical patent/WO2009035858A2/en
Publication of WO2009035858A3 publication Critical patent/WO2009035858A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device

Definitions

  • Embodiments of the present invention relate generally to packaging of optically interactive microelectronic devices. More specifically, embodiments of the present invention relate to an imager die package sealed within an encapsulant and to methods of packaging an imager die.
  • Microelectronic imagers are well known to those having skill in the electronics/photonics art, as they are used in digital cameras, wireless devices with picture capabilities, and many other applications.
  • Cellular telephones and Personal Digital Assistants (PDAs) for example, are incorporating microelectronic imagers for capturing and sending pictures.
  • PDAs Personal Digital Assistants
  • the growth rate of microelectronic imagers has been steadily increasing as they become smaller and produce better images with higher pixel counts.
  • Microelectronic imagers include image sensors that use Charged Coupled Device (CCD) systems, Complementary Metal-Oxide Semiconductor (CMOS) systems, or other solid state systems.
  • CCD image sensors have been widely used in digital cameras and other applications.
  • CMOS image sensors are quickly becoming very popular because they have low production costs, high yields, and small sizes.
  • CMOS image sensors, as well as CCD image sensors are accordingly "packaged" to protect the delicate components and to provide external electrical contacts.
  • Optically interactive microelectronic devices require packaging that provides protection from other environmental conditions while allowing light or other forms of radiation to pass through to a surface where sensing circuitry is located.
  • One problem with conventional packaging techniques of microelectronic devices is that the final packages produced allow for the exposure of the image sensor to amounts of unwanted peripheral light.
  • FIG. 1 is a top view of a semiconductor imager wafer having an array of multiple discrete imager die attached thereon, according to an embodiment of the invention
  • FIG. 2 is a cross-sectional view of an imager wafer according to an embodiment of the invention.
  • FIGS. 3(a) and (b) are cross-sectional views of an imager wafer with an attached glass layer according to an embodiment of the invention:
  • FIG. 3(c) is a cross-sectional view of an imager wafer with an attached lens-carrying substrate according to other embodiments of the invention
  • FIG. 4 is a cross-sectional view of an imager wafer with an attached glass layer after a dicing operation according to an embodiment of the invention
  • FIG. 5 is a cross-sectional view of a reconstructed wafer including a plurality of imager die attached to a temporary carrier according to an embodiment of the invention
  • FIG. 5(a) is a cross-sectional view of a reconstructed wafer, including a plurality of imager die on a temporary carrier, positioned within a cavity of a mold according to embodiments of the present invention
  • FIG. 6 is a cross-sectional view of a reconstructed wafer including a plurality of encapsulated imager die in accordance with an embodiment of the invention
  • FIG. 7 is a cross-sectional view of a plurality of singulated imager die packages in accordance with an embodiment of the invention.
  • FIGS. 8(a) and (b) are cross-sectional views of an imager die package in accordance with an embodiment of the invention.
  • FIG. 9 is a cross-sectional view of a plurality of lenses according to an embodiment of the invention.
  • FIG. 10 is a cross-sectional view of a plurality of lenses attached to an imager wafer in accordance with an embodiment of the invention;
  • FIG. 11 is a cross-sectional view of an imager die with at least one lens attached thereto according to an embodiment of the invention.
  • FIG. 12 is a cross-sectional view of a plurality of imager die attached to a temporary carrier in accordance with an embodiment of the invention.
  • FIG. 13 is a cross-sectional view of a reconstructed wafer including a plurality of encapsulated imager die according to an embodiment of the invention.
  • FIG. 14 is a cross-sectional view of a final imager die package in accordance with an embodiment of the invention.
  • FIG. 15 is an illustration of a system including an imager die package according to an embodiment of the invention.
  • Embodiments of the invention include methods for packaging imager die and imager die packages.
  • An imager die packaging method may utilize a temporary carrier during an encapsulation process.
  • the carrier may include a high temperature compatible film frame tape and an ultraviolet-releasable adhesive.
  • An embodiment of the invention includes a method of packaging an imager die.
  • the method includes cutting through a thickness of a fabrication substrate between adjacent imager die carried by the fabrication substrate to form a plurality of individual imager die.
  • the method further includes securing a plurality of known good die characterized from the plurality of individual imager die to a temporary carrier and at least partially encapsulating the plurality of known good die on the temporary carrier to reconstruct a wafer.
  • the method also includes singulating the at least partially encapsulated plurality of known good die from the wafer.
  • a temporary carrier includes an ultraviolet-sensitive adhesive on a surface of a film formed from a material configured to withstand relatively high process temperatures, (e.g.. temperatures of about 9O 0 C or greater).
  • Another embodiment of the invention includes an imager die package comprising a fabrication substrate having an active surface and a back side with an imager die having an image sensor formed on the active surface.
  • the package further includes at least one conductive interconnect extending from the active surface to the back side of the fabrication substrate.
  • the package may comprise an encapsulant formed at least partially around the fabrication substrate including the imager die.
  • the invention includes an electronic system comprising a processor-based device operably coupled to an imager die package according to an embodiment of the invention.
  • Another embodiment of the invention includes a known good die wafer comprising a plurality of known good imager die.
  • Each known good die is fabricated on an active surface of one fabrication substrate of a plurality and a back side of each fabrication substrate includes circuit traces thereon.
  • the known good die wafer further includes a first plurality of discrete conductive elements respectively formed on the circuit traces and an encapsulant at least partially formed around each known good imager die of the plurality.
  • FIGS. 1-8 The fabrication of an imager die package according to an embodiment of the present invention is illustrated by FIGS. 1-8.
  • a semiconductor wafer 110 is illustrated at a preliminary processing stage.
  • the wafer construction is subdivided into a plurality of die regions 218 which are separated from one another, and bounded, by streets 142.
  • Each of the die regions 218 is, conventionally, processed identically to form a plurality of identical die.
  • Each die region 218 includes an active surface 111 having an image sensitive area 112 that comprises sensing circuitry reactive to light or other forms of radiation.
  • FIG. 2 illustrates a cross-sectional view of a through wafer interconnect (TWI) wafer 216 taken along line 2 of FIG. 1.
  • TWI through wafer interconnect
  • the term "through wafer interconnect” may be used herein to describe a substrate having vias extending therethrough and lined or filled with conductive material for forming interconnects for connecting circuitry on one side of a portion of the substrate to circuitry on the other side thereof, or to external circuitry.
  • TWI wafer 216 includes a first surface 210 and a second surface 212.
  • TWI wafer 216 may comprise a fabrication substrate 232 having a plurality of die regions 218 formed on an active surface thereof, and each die region 218 may comprise imager die 226.
  • Imager die 226 may each comprise an image sensor 225, such as, but not limited to, a CMOS imager.
  • fabrication substrate 232 may comprise a full or partial wafer of semiconductive material (e.g., silicon, gallium arsenide, indium phosphide, etc.), a silicon-on-insulator (SOI) type substrate (e.g.. silicon-on-ceramic (SOC), silicon-on-glass (SOG), silicon-on-sapphire (SOS), etc.). or any other bulk or large-scale substrate upon which a plurality of semiconductor device components may be fabricated.
  • SOI silicon-on-insulator
  • SOC silicon-on-ceramic
  • SOG silicon-on-glass
  • SOS silicon-on-sapphire
  • TWI wafer 216 may include a plurality of standoffs 242 secured to fabrication substrate 232 and comprising of. for example, a photopolymerized material. Standoffs 242 may be configured to provide spacing between imager die 226 and a subsequently attached layer, such as a cover glass or a lens. TWJ wafer 216 may also comprise at least one conductive interconnect 236 located between adjacent die and extending from the active surface 234 to a back side 235 of fabrication substrate 232 and in contact with a redistribution layer (RDL). RDL may be in the form of conductive traces 238 formed at the second surface 212 of TWI wafer 216.
  • RDL redistribution layer
  • TWI wafer 216 may comprise a first plurality of discrete conductive elements 240 conventionally formed or disposed on and respectively in contact with conductive traces 238.
  • first plurality of discrete conductive elements 240 may comprise solder balls, or bumps, studs, pillars or columns formed or covered with a conductive material, or formed of a conductor-filled material.
  • solder balls, or bumps, studs, pillars or columns formed or covered with a conductive material, or formed of a conductor-filled material may be used in the present invention.
  • FIG. 3(a) illustrates an embodiment of a TWI wafer 216 with a glass layer 310 or sheet of another suitable transparent material attached.
  • Glass layer 310 may be of a size sufficient to cover the array of imager die active surfaces 111 (see FIG. 1) and is attached to and peripherally supported about each die region 218 by the plurality of standoffs 242.
  • Glass layer 310 may be formed of an at least partially optically transparent material such as borosilicate glass (BSG). Other types of glass which allow the passage of a desired range of wavelengths of light or other forms of electromagnetic radiation may also be used.
  • Glass layer 310 may comprise cuts 312 in the form of notches that may be formed before or after glass layer 310 is attached to TWI wafer 216.
  • cuts 312 are configured to minimize the peripheral light received by image sensor 225 and, therefore, increase the quality of image sensor 225.
  • Cuts 312 may be formed by a scoring blade (not shown) wherein the groove depth of cuts 312 may depend on the size of the scoring blade and the depth of penetration of the scoring blade into glass layer 310. Additionally. the angle at which cuts 312 are formed in glass layer 310 may depend, in part, on the shape of the scoring blade.
  • the shape of cuts 312 is not limited to a cut having angled or beveled edges, as depicted but, rather, cuts 312 may have a generally square or rectangular shape, as illustrated in FIG 3(b).
  • standoffs 242 may be configured to withstand some compressive force as applied by the scoring blade.
  • a substrate 310' formed from glass or another suitable transparent material that carries a plurality of lenses 311 ' or other optical elements may be positioned over TWI wafer 216, as shown in FIG. 3(c).
  • Each lens 31 1 ' is aligned over an image sensor 225 of a die region 218.
  • additional standoffs 242' may be formed or positioned around each lens 311 ' to facilitate further processing in accordance with teachings of the present invention (e.g., prevent encapsulant from contacting each lens 311'.
  • glass layer 310 (or lens 311 '-bearing glass substrate 310') to the plurality of standoffs 242, glass layer 310, standoffs 242, and fabrication substrate 232 may be cut by way of a dicing operation carried out to form a plurality of individualized imager die regions 218 (See FIG. 4).
  • Cutting of glass layer 310 may be accomplished, in some embodiments, using a resinoid blade saw.
  • Cutting of fabrication substrate 232 may be accomplished, in a more specific embodiment, using a diamond plated nickel saw.
  • fabrication substrate 232, standoffs 242 and glass layer 310 may be cut by a "stealth" dicing process wherein the fabrication substrate 232, standoffs 242 and glass layer 310 are weakened at an internal region by one or more lasers and thereafter the glass layer 310, standoffs 242 and fabrication substrate 232 are stretched and broken at the weakened internal region.
  • the stealth dicing process is developed by Hamamatsu Photonics K. K.. Shizuoka. Japan.
  • An alternative dicing process may be effected using a water-jet-guided laser available from Synova S. A., Lausanne, Switzerland.
  • the imager singulation process may be achieved by a jet singulation system wherein a jet stream of an abrasive slurry is used to singulate component parts.
  • the jet singulation system may be made by Towa Intercon Technology, Inc., of Morgan Hill, California.
  • individual imager die Prior to or after the dicing operation is completed, individual imager die may be tested to ascertain which of the imager die are operational and meet qualitative performance standards and are thus deemed "good," and which are defective.
  • the imager die that are good can be considered to be "known good die” (KGD).
  • the KGD may be placed on a temporary carrier 410 (See FIG. 5).
  • FIG. 5 illustrates KGD 510 populated on a temporary carrier 410.
  • temporary carrier 410 comprises a film frame tape or a glass carrier.
  • Temporary carrier 410 may comprise a high temperature compatible polyethylene terephthalate (PET) material that may withstand relatively high process temperatures (i.e., temperatures above about 90 0 C).
  • PET polyethylene terephthalate
  • temporary carrier 410 may comprise a pressure sensitive adhesive.
  • temporary carrier 410 may comprise an ultraviolet-sensitive adhesive which loses adhesive strength when irradiated with a select wavelength of light, normally UV light. Use of an ultraviolet-type tape may be desirable since, when irradiated, it loses its adherent properties and thus reduces stress on the dice during a subsequent pick-and-place operation.
  • Ultraviolet sensitive tapes are commercially available from Furukawa Electric Company, Ltd. of Japan.
  • KGD 510 are placed facedown on temporary carrier 410, and, therefore.
  • FIG. 5 is shown inverted relative to FIGS. 2-4.
  • KGD 510 may be positioned on temporary carrier 410 to provide for a desired gap width 450 and. thereafter.
  • KGD 510 may be encapsulated with an encapsulant 512 to form wafer 610.
  • Encapsulant 512 may comprise any conventional compound known for use in encapsulating semiconductor chips that exhibits low moisture uptake and good dimensional stability.
  • Encapsulant 512 may also be selected to have a coefficient of thermal expansion (CTE) that is compatible with those of substrate 232 and KGD 510.
  • CTE coefficient of thermal expansion
  • encapsulation of KGD 510 may be effected by a molding process or a dam and fill process.
  • Molding processes known in the art may include injection molding. transfer molding, and compression molding.
  • Injection molding is a process wherein an encapsulant is injected at high pressure into a mold cavity containing the device to be encapsulated.
  • a compression molding process may include placing an encapsulant into a mold cavity containing the device to be encapsulated and thereafter applying pressure and heat.
  • Transfer molding differs from compression molding in that instead of applying pressure to the pre-placed compound, the encapsulant material is preheated and then transferred into a molding cavity under pressure, containing the device to be encapsulated.
  • Dam and fill is a two-step process wherein a dam is dispensed around a device within a cavity and, thereafter. the cavity may be filled with an encapsulant to encapsulate the device.
  • encapsulant 512 contemplated for use in the present invention include, but are not limited to, thermoset and thermoplastic curable compounds such as silicon-filled polymers or liquid crystal polymers.
  • a surface of a mold cavity may be configured to receive portions of discrete conductive elements 240 that protrude from each KGD 510 to prevent encapsulant from completely covering the discrete conductive elements 240.
  • discrete conductive elements 240 may be partially received by a compressible, conformable element 522 (e.g., a polytetrafluoroethylene film, such as the material sold under the trademark TEFLON ® by E.I. duPont Nemours & Co. of Wilmington, Delaware) that lines at least a portion of a surface of a mold cavity 550.
  • a compressible, conformable element 522 e.g., a polytetrafluoroethylene film, such as the material sold under the trademark TEFLON ® by E.I. duPont Nemours & Co. of Wilmington, Delaware
  • portions of discrete conductive elements 240 that protrude from each KGD 510 within mold cavity 550 are received by compressible, conformable element 552, shielding the received portions of discrete conductive elements 240 from encapsulant 512 as encapsulant 512 is introduced into mold cavity 550. Therefore, upon completion of the mold process and removal of the resulting wafer 610 from mold cavity 550, portions of discrete conductive elements 240 may protrude from an outer surface of encapsulant 512.
  • the distance that discrete conductive elements 240 protrude from the outer surface of the encapsulant may be defined by a depth that discrete conductive elements 240 are received and, thus, in embodiments where a compressible, conformable element 552 is used, by a thickness of compressible, conformable element 552.
  • a mold cavity is not configured to receive discrete conductive elements 240, as well as in embodiments where dam and fill or other encapsulation processes are used, it may be necessary to expose conductive elements 240 through encapsulant 512.
  • wafer 610 may be subjected to appropriate processing to form a substantially planarized surface 612 extending across the first plurality of discrete conductive elements 240 and encapsulant 512.
  • the processing may further provide for the at least partial exposure of the first plurality of discrete conductive elements 240.
  • the formation of the substantially planarized surface 612 can be accomplished with any suitable method, and may be accomplished by back grinding or another mechanical planarization process such as chemical mechanical planarization (CMP). Appropriate control of the planarization process may be required to prevent the smearing of any conductive material of the first plurality of discrete conductive elements 240, which may result in shorting of one conductive element 240 to an adjacent one.
  • CMP chemical mechanical planarization
  • a second plurality of discrete conductive elements 620 may be formed or disposed on, and bonded to, the first plurality of discrete conductive elements 240.
  • the second plurality of discrete conductive elements 620 may provide for subsequent attachment to a carrier substrate or other higher-level circuit assembly, as shown in FIG. 6.
  • FIG. 6 also depicts removal of wafer 610 from temporary carrier 410. Cleaning of adhesive from wafer 610 may be required after separation of wafer 610 from temporary carrier 410. Cleaning methods known in the art, such as. a plasma cleaning technique, may be effected.
  • wafer 610 may then be placed on a dicing tape 710 and singulated by performing a dicing operation through encapsulant 512 and, therefore, resulting in a final packaged die 810/810", as shown in FIGS. 8(a) and (b).
  • Final packaged die 810/810" provide for. as a result of cuts 312 (see FIGS. 3(a) and (b)), regions 822 that extend laterally over non-imaging regions on the active surface of the final packaged die 810/810".
  • These laterally extending regions 822 of encapsulant, or packaging material prevent at least some unwanted, or stray, light from reaching the image sensor 225 and are, therefore, also referred to herein as "lateral light blocking elements.
  • Imager die packages may be formed in a manner similar to that of that described above, except the imager die are not covered with a glass layer. Instead, "known good lenses' * (KGL) are identified or qualified, and are subsequently placed over known good imager die. KGD, comprising known good imagers with KGL assembled therewith may then be placed on a temporary carrier, with standoffs that completely circumscribe the periphery of each image sensor 225 contacting the temporary carrier. These assemblies may then be encapsulated by molding or dam and fill processes and, thereafter, singulated to form final die packages.
  • KGL known good lenses' *
  • FIG. 9 illustrates a plurality of lenses 900A-E formed from a glass substrate 904. Lenses 900A-E may be individually qualified by methods known in the art to ascertain known good lenses. After testing, a dicing operation may be performed along dicing lines 902 resulting in a plurality of individual lenses. As shown in FIG. 10, a plurality of known good lenses 900' may thereafter be individually placed over a plurality of known good imager die 910 located on a TWI wafer 960. As described above in reference to FIGS. 1-8 and TWI wafer 216. TWI wafer 960, as illustrated in FIGS.
  • 10-14 may comprise a fabrication substrate 908 and at least one conductive interconnect 236' located between adjacent image die 910 and extending from active surface 912 to a back side 913 of fabrication substrate 908 and in contact with an RDL.
  • the RDL may be in the form of conductive traces 238' formed on the second surface 212' of TWI wafer 960.
  • TWI wafer 960 may also comprise a first plurality of discrete conductive elements 240' formed on and in contact with conductive traces 238'.
  • the plurality of known good lenses 900' may be respectively peripherally supported on and attached to a plurality of standoffs 242 located on the active surface 912 of fabrication substrate 908. wherein at least one known good lens 900' may be placed over one known good imager die 910.
  • Standoffs 242/242' may be configured to provide support for attached known good lenses 900' and to provide a selected vertical spacing between stacked known good lenses 9007900" or between known good lenses 900' and TWI wafer 960. Standoffs 242' may also be configured to seal against a temporary earner 410 and to prevent encapsulant from contacting known good lenses 9007900". Implementing the configuration described in FIGS. 9 and 10 may improve the yield of an imager die package by ensuring bad lenses are not placed over good imagers and, therefore, decrease the amount of wasted material and component parts. Furthermore, this configuration may ensure that good lenses are not placed over bad imagers.
  • KGD 510' may include at least one additional known good lens 900" and corresponding standoffs 242" (shown by dashed lines) stacked over known good lens 900' in order to achieve a desired focus onto imager die 910.
  • KGD 510' may be placed face-down on a temporary carrier 410', such as a film frame tape or glass carrier, with standoffs 242' positioned against and secured to temporary carrier 410' to prevent encapsulant from contacting known good lenses 9007900".
  • KGD 510' are shown inverted relative to FIGS. 10 and 11.
  • KGD 510' may be encapsulated with encapsulant 512', thus resulting in reconstructed wafer 930, as illustrated in FIG. 13.
  • encapsulant 512' may comprise any conventional compound known for use in encapsulating semiconductors. Encapsulation processes may include a molding or dam and fill process as known in the art.
  • reconstructed wafer 930 may be subjected to appropriate processing to form a substantially planarized surface 950 extending across first set of discrete conductive elements 240' and encapsulant 512'.
  • the processing may further provide for the at least partial exposure of the first plurality of discrete conductive elements 240'.
  • a second plurality of discrete conductive elements 620' such as balls, bumps, columns, or pins of conductive material (e.g., solder, another metal, a conductor-filled polymer, etc.), may be bonded to the first plurality of discrete conductive elements 240'.
  • the second plurality of discrete conductive elements 620' provides for subsequent attachment to a carrier substrate or other higher-level circuit assembly.
  • one discrete element of the second plurality may be operably coupled to one discrete element of the first plurality.
  • at least a portion of the first plurality of discrete conductive elements 240' may remain exposed during a compression molding process and, therefore, neither a planarizing process nor a second plurality of discrete conductive elements may be required.
  • FIG. 15 A processor based system 1060 which includes an imager die package 810/8107810" in accordance with an embodiment of the present invention is illustrated in FIG. 15.
  • a system 1060 may include a computer system, camera system, scanner, machine vision system, vehicle na ⁇ igation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, each of which may be configured to utilize an embodiment of the present invention.
  • a processor based system 1060 such as a computer system, for example, generally comprises a central processing unit (CPU) 962, for example, a microprocessor that may communicate with and input/output (I/O) device 964 over a bus 966.
  • the imager die package 810/8107810" may also communicate with the system 1060 over bus 966.
  • the system 1060 also includes random access memory (RAM) 968, and. in the case of a computer system, may include peripheral devices such as a floppy disk drive 970 and a compact disk (CD) ROM drive 972 which also communicate with CPU 962 over bus 966.
  • CPU 962, imager die package 810/8107810" and memory 968 may be integrated on a single IC chip.

Abstract

Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated, face down on a high temperature-compatible temporary carrier, the KGD on the temporary carrier are encapsulated and thereafter removed as a reconstructed wafer from the temporary carrier. Furthermore, a first plurality of discrete conductive elements on a back side of the reconstructed wafer may be partially exposed and, optionally, a second plurality of discrete conductive elements may be applied to the first plurality of discrete conductive elements. The encapsulated KGD are then singulated.

Description

IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER
PRIORITY CLAIM This application claims the benefit of the filing date of United States Patent
Application Serial No. 11/851.787, filed September 7, 2007, titled "Imager Die Package and Methods of Packaging an Imager Die on a Temporary Carrier."
TECHNICAL FIELD Embodiments of the present invention relate generally to packaging of optically interactive microelectronic devices. More specifically, embodiments of the present invention relate to an imager die package sealed within an encapsulant and to methods of packaging an imager die.
BACKGROUND
Microelectronic imagers are well known to those having skill in the electronics/photonics art, as they are used in digital cameras, wireless devices with picture capabilities, and many other applications. Cellular telephones and Personal Digital Assistants (PDAs), for example, are incorporating microelectronic imagers for capturing and sending pictures. The growth rate of microelectronic imagers has been steadily increasing as they become smaller and produce better images with higher pixel counts.
Microelectronic imagers include image sensors that use Charged Coupled Device (CCD) systems, Complementary Metal-Oxide Semiconductor (CMOS) systems, or other solid state systems. CCD image sensors have been widely used in digital cameras and other applications. CMOS image sensors are quickly becoming very popular because they have low production costs, high yields, and small sizes. CMOS image sensors, as well as CCD image sensors, are accordingly "packaged" to protect the delicate components and to provide external electrical contacts. Optically interactive microelectronic devices require packaging that provides protection from other environmental conditions while allowing light or other forms of radiation to pass through to a surface where sensing circuitry is located. One problem with conventional packaging techniques of microelectronic devices is that the final packages produced allow for the exposure of the image sensor to amounts of unwanted peripheral light.
Furthermore, the materials and structures involved in conventional semiconductor packaging techniques require fabrication processes that can be time consuming and require several precision assembly steps. Each assembly step increases the opportunity for contamination or damage to the imaging device itself, raising defect levels and slowing production time to avoid such damage and contamination. Additionally, if the package design or fabrication approach necessitates that all of the imager die located on a wafer be packaged regardless of whether a significant number of die are defective, a substantial waste of material results. Due to the extremely cost-competitive nature of the semiconductor industry, improvements in product yield and production time are of value, especially when considered in terms of the high volume of components being manufactured.
There is a need for methods to both improve the quality, and decrease the cost, of an imaging device. Specifically, there is a need for providing a method that enables low-cost, high volume encapsulated packaging of imager die while providing a high quality imaging device.
BRIEF DESCRIPTION OF THE DRAWINGS In the drawings:
FIG. 1 is a top view of a semiconductor imager wafer having an array of multiple discrete imager die attached thereon, according to an embodiment of the invention;
FIG. 2 is a cross-sectional view of an imager wafer according to an embodiment of the invention;
FIGS. 3(a) and (b) are cross-sectional views of an imager wafer with an attached glass layer according to an embodiment of the invention:
FIG. 3(c) is a cross-sectional view of an imager wafer with an attached lens-carrying substrate according to other embodiments of the invention; FIG. 4 is a cross-sectional view of an imager wafer with an attached glass layer after a dicing operation according to an embodiment of the invention: FIG. 5 is a cross-sectional view of a reconstructed wafer including a plurality of imager die attached to a temporary carrier according to an embodiment of the invention;
FIG. 5(a) is a cross-sectional view of a reconstructed wafer, including a plurality of imager die on a temporary carrier, positioned within a cavity of a mold according to embodiments of the present invention;
FIG. 6 is a cross-sectional view of a reconstructed wafer including a plurality of encapsulated imager die in accordance with an embodiment of the invention;
FIG. 7 is a cross-sectional view of a plurality of singulated imager die packages in accordance with an embodiment of the invention;
FIGS. 8(a) and (b) are cross-sectional views of an imager die package in accordance with an embodiment of the invention;
FIG. 9 is a cross-sectional view of a plurality of lenses according to an embodiment of the invention; FIG. 10 is a cross-sectional view of a plurality of lenses attached to an imager wafer in accordance with an embodiment of the invention;
FIG. 11 is a cross-sectional view of an imager die with at least one lens attached thereto according to an embodiment of the invention;
FIG. 12 is a cross-sectional view of a plurality of imager die attached to a temporary carrier in accordance with an embodiment of the invention;
FIG. 13 is a cross-sectional view of a reconstructed wafer including a plurality of encapsulated imager die according to an embodiment of the invention;
FIG. 14 is a cross-sectional view of a final imager die package in accordance with an embodiment of the invention; and FIG. 15 is an illustration of a system including an imager die package according to an embodiment of the invention.
MODE(S) FOR CARRYING OUT THE INVENTION Embodiments of the invention include methods for packaging imager die and imager die packages. An imager die packaging method may utilize a temporary carrier during an encapsulation process. In a specific embodiment, the carrier may include a high temperature compatible film frame tape and an ultraviolet-releasable adhesive.
An embodiment of the invention includes a method of packaging an imager die. The method includes cutting through a thickness of a fabrication substrate between adjacent imager die carried by the fabrication substrate to form a plurality of individual imager die. The method further includes securing a plurality of known good die characterized from the plurality of individual imager die to a temporary carrier and at least partially encapsulating the plurality of known good die on the temporary carrier to reconstruct a wafer. The method also includes singulating the at least partially encapsulated plurality of known good die from the wafer. In a particular embodiment, a temporary carrier includes an ultraviolet-sensitive adhesive on a surface of a film formed from a material configured to withstand relatively high process temperatures, (e.g.. temperatures of about 9O0C or greater).
Another embodiment of the invention includes an imager die package comprising a fabrication substrate having an active surface and a back side with an imager die having an image sensor formed on the active surface. The package further includes at least one conductive interconnect extending from the active surface to the back side of the fabrication substrate. Furthermore, the package may comprise an encapsulant formed at least partially around the fabrication substrate including the imager die.
According to yet another embodiment, the invention includes an electronic system comprising a processor-based device operably coupled to an imager die package according to an embodiment of the invention.
Another embodiment of the invention includes a known good die wafer comprising a plurality of known good imager die. Each known good die is fabricated on an active surface of one fabrication substrate of a plurality and a back side of each fabrication substrate includes circuit traces thereon. The known good die wafer further includes a first plurality of discrete conductive elements respectively formed on the circuit traces and an encapsulant at least partially formed around each known good imager die of the plurality.
Referring in general to the accompanying drawings, various aspects of the present invention are illustrated to show the structure and methods of packaging an imager die. Common elements of the illustrated embodiments are designated with like numerals. It should be understood that the figures presented are not meant to be illustrative of actual views of any particular portion of the actual device structure, but are merely schematic representations which are employed to more clearly and fully depict the invention. It should be further understood that while depicted and described in the context of an image sensor, the package embodiments and methods presented herein would work well for enclosing other types of optically interactive devices, such as, but not limited to, CCD and CMOS image sensors, electrically erasable programmable read-only memory (EPROM), and photodiodes, as well as light-emitting devices including semiconductor lasers and light-emitting diodes.
The fabrication of an imager die package according to an embodiment of the present invention is illustrated by FIGS. 1-8. Referring to FIG. 1, a semiconductor wafer 110 is illustrated at a preliminary processing stage. The wafer construction is subdivided into a plurality of die regions 218 which are separated from one another, and bounded, by streets 142. Each of the die regions 218 is, conventionally, processed identically to form a plurality of identical die. Each die region 218 includes an active surface 111 having an image sensitive area 112 that comprises sensing circuitry reactive to light or other forms of radiation.
FIG. 2 illustrates a cross-sectional view of a through wafer interconnect (TWI) wafer 216 taken along line 2 of FIG. 1. The term "through wafer interconnect" may be used herein to describe a substrate having vias extending therethrough and lined or filled with conductive material for forming interconnects for connecting circuitry on one side of a portion of the substrate to circuitry on the other side thereof, or to external circuitry. TWI wafer 216 includes a first surface 210 and a second surface 212. TWI wafer 216 may comprise a fabrication substrate 232 having a plurality of die regions 218 formed on an active surface thereof, and each die region 218 may comprise imager die 226. Imager die 226 may each comprise an image sensor 225, such as, but not limited to, a CMOS imager. By way of example only, fabrication substrate 232 may comprise a full or partial wafer of semiconductive material (e.g., silicon, gallium arsenide, indium phosphide, etc.), a silicon-on-insulator (SOI) type substrate (e.g.. silicon-on-ceramic (SOC), silicon-on-glass (SOG), silicon-on-sapphire (SOS), etc.). or any other bulk or large-scale substrate upon which a plurality of semiconductor device components may be fabricated.
TWI wafer 216 may include a plurality of standoffs 242 secured to fabrication substrate 232 and comprising of. for example, a photopolymerized material. Standoffs 242 may be configured to provide spacing between imager die 226 and a subsequently attached layer, such as a cover glass or a lens. TWJ wafer 216 may also comprise at least one conductive interconnect 236 located between adjacent die and extending from the active surface 234 to a back side 235 of fabrication substrate 232 and in contact with a redistribution layer (RDL). RDL may be in the form of conductive traces 238 formed at the second surface 212 of TWI wafer 216. In addition, TWI wafer 216 may comprise a first plurality of discrete conductive elements 240 conventionally formed or disposed on and respectively in contact with conductive traces 238. For example only, and not by way of limitation, first plurality of discrete conductive elements 240 may comprise solder balls, or bumps, studs, pillars or columns formed or covered with a conductive material, or formed of a conductor-filled material. The above description represents only one example of a TWI wafer and any other configurations known in the art are within the scope of the present invention.
FIG. 3(a) illustrates an embodiment of a TWI wafer 216 with a glass layer 310 or sheet of another suitable transparent material attached. Glass layer 310 may be of a size sufficient to cover the array of imager die active surfaces 111 (see FIG. 1) and is attached to and peripherally supported about each die region 218 by the plurality of standoffs 242. Glass layer 310 may be formed of an at least partially optically transparent material such as borosilicate glass (BSG). Other types of glass which allow the passage of a desired range of wavelengths of light or other forms of electromagnetic radiation may also be used. Glass layer 310 may comprise cuts 312 in the form of notches that may be formed before or after glass layer 310 is attached to TWI wafer 216. As described in more detail below, cuts 312 are configured to minimize the peripheral light received by image sensor 225 and, therefore, increase the quality of image sensor 225. Cuts 312 may be formed by a scoring blade (not shown) wherein the groove depth of cuts 312 may depend on the size of the scoring blade and the depth of penetration of the scoring blade into glass layer 310. Additionally. the angle at which cuts 312 are formed in glass layer 310 may depend, in part, on the shape of the scoring blade. The shape of cuts 312 is not limited to a cut having angled or beveled edges, as depicted but, rather, cuts 312 may have a generally square or rectangular shape, as illustrated in FIG 3(b). In the event the cuts 312 are formed after glass layer 310 has been attached to wafer 110, standoffs 242 may be configured to withstand some compressive force as applied by the scoring blade.
In other embodiments, instead of a glass layer 310, a substrate 310' formed from glass or another suitable transparent material that carries a plurality of lenses 311 ' or other optical elements may be positioned over TWI wafer 216, as shown in FIG. 3(c). Each lens 31 1 ' is aligned over an image sensor 225 of a die region 218. In embodiments where lenses 311 ' protrude from an outer surface of glass substrate 310', additional standoffs 242' may be formed or positioned around each lens 311 ' to facilitate further processing in accordance with teachings of the present invention (e.g., prevent encapsulant from contacting each lens 311'.
Subsequent to attaching glass layer 310 (or lens 311 '-bearing glass substrate 310') to the plurality of standoffs 242, glass layer 310, standoffs 242, and fabrication substrate 232 may be cut by way of a dicing operation carried out to form a plurality of individualized imager die regions 218 (See FIG. 4). Cutting of glass layer 310 may be accomplished, in some embodiments, using a resinoid blade saw. Cutting of fabrication substrate 232 may be accomplished, in a more specific embodiment, using a diamond plated nickel saw. In another embodiment of the present invention, fabrication substrate 232, standoffs 242 and glass layer 310 may be cut by a "stealth" dicing process wherein the fabrication substrate 232, standoffs 242 and glass layer 310 are weakened at an internal region by one or more lasers and thereafter the glass layer 310, standoffs 242 and fabrication substrate 232 are stretched and broken at the weakened internal region. The stealth dicing process is developed by Hamamatsu Photonics K. K.. Shizuoka. Japan. An alternative dicing process may be effected using a water-jet-guided laser available from Synova S. A., Lausanne, Switzerland. In other embodiments, the imager singulation process may be achieved by a jet singulation system wherein a jet stream of an abrasive slurry is used to singulate component parts. The jet singulation system may be made by Towa Intercon Technology, Inc., of Morgan Hill, California. Prior to or after the dicing operation is completed, individual imager die may be tested to ascertain which of the imager die are operational and meet qualitative performance standards and are thus deemed "good," and which are defective. The imager die that are good can be considered to be "known good die" (KGD). Upon determining the KGD, the KGD may be placed on a temporary carrier 410 (See FIG. 5).
FIG. 5 illustrates KGD 510 populated on a temporary carrier 410. According to some embodiments, temporary carrier 410 comprises a film frame tape or a glass carrier. Temporary carrier 410 may comprise a high temperature compatible polyethylene terephthalate (PET) material that may withstand relatively high process temperatures (i.e., temperatures above about 900C). In addition, temporary carrier 410 may comprise a pressure sensitive adhesive. Furthermore, temporary carrier 410 may comprise an ultraviolet-sensitive adhesive which loses adhesive strength when irradiated with a select wavelength of light, normally UV light. Use of an ultraviolet-type tape may be desirable since, when irradiated, it loses its adherent properties and thus reduces stress on the dice during a subsequent pick-and-place operation. Ultraviolet sensitive tapes are commercially available from Furukawa Electric Company, Ltd. of Japan.
As shown, KGD 510 are placed facedown on temporary carrier 410, and, therefore. FIG. 5 is shown inverted relative to FIGS. 2-4. KGD 510 may be positioned on temporary carrier 410 to provide for a desired gap width 450 and. thereafter. KGD 510 may be encapsulated with an encapsulant 512 to form wafer 610. Encapsulant 512 may comprise any conventional compound known for use in encapsulating semiconductor chips that exhibits low moisture uptake and good dimensional stability. Encapsulant 512 may also be selected to have a coefficient of thermal expansion (CTE) that is compatible with those of substrate 232 and KGD 510. For example only, and not by way of limitation, encapsulation of KGD 510 may be effected by a molding process or a dam and fill process. Molding processes known in the art may include injection molding. transfer molding, and compression molding. Injection molding is a process wherein an encapsulant is injected at high pressure into a mold cavity containing the device to be encapsulated. A compression molding process may include placing an encapsulant into a mold cavity containing the device to be encapsulated and thereafter applying pressure and heat. Transfer molding differs from compression molding in that instead of applying pressure to the pre-placed compound, the encapsulant material is preheated and then transferred into a molding cavity under pressure, containing the device to be encapsulated. Dam and fill is a two-step process wherein a dam is dispensed around a device within a cavity and, thereafter. the cavity may be filled with an encapsulant to encapsulate the device. Examples of encapsulant 512 contemplated for use in the present invention include, but are not limited to, thermoset and thermoplastic curable compounds such as silicon-filled polymers or liquid crystal polymers.
In embodiments where molding processes are used, a surface of a mold cavity may be configured to receive portions of discrete conductive elements 240 that protrude from each KGD 510 to prevent encapsulant from completely covering the discrete conductive elements 240. In one such embodiment, shown in FIG. 5(a), discrete conductive elements 240 may be partially received by a compressible, conformable element 522 (e.g., a polytetrafluoroethylene film, such as the material sold under the trademark TEFLON® by E.I. duPont Nemours & Co. of Wilmington, Delaware) that lines at least a portion of a surface of a mold cavity 550. Upon being confined within mold cavity 550, portions of discrete conductive elements 240 that protrude from each KGD 510 within mold cavity 550 are received by compressible, conformable element 552, shielding the received portions of discrete conductive elements 240 from encapsulant 512 as encapsulant 512 is introduced into mold cavity 550. Therefore, upon completion of the mold process and removal of the resulting wafer 610 from mold cavity 550, portions of discrete conductive elements 240 may protrude from an outer surface of encapsulant 512. The distance that discrete conductive elements 240 protrude from the outer surface of the encapsulant may be defined by a depth that discrete conductive elements 240 are received and, thus, in embodiments where a compressible, conformable element 552 is used, by a thickness of compressible, conformable element 552. In embodiments where a mold cavity is not configured to receive discrete conductive elements 240, as well as in embodiments where dam and fill or other encapsulation processes are used, it may be necessary to expose conductive elements 240 through encapsulant 512. In such embodiments, wafer 610 may be subjected to appropriate processing to form a substantially planarized surface 612 extending across the first plurality of discrete conductive elements 240 and encapsulant 512. The processing may further provide for the at least partial exposure of the first plurality of discrete conductive elements 240. The formation of the substantially planarized surface 612 can be accomplished with any suitable method, and may be accomplished by back grinding or another mechanical planarization process such as chemical mechanical planarization (CMP). Appropriate control of the planarization process may be required to prevent the smearing of any conductive material of the first plurality of discrete conductive elements 240, which may result in shorting of one conductive element 240 to an adjacent one. After planarizing surface 612, a second plurality of discrete conductive elements 620 (e.g., solder balls, pins, pillars, columns, etc.) may be formed or disposed on, and bonded to, the first plurality of discrete conductive elements 240. The second plurality of discrete conductive elements 620 may provide for subsequent attachment to a carrier substrate or other higher-level circuit assembly, as shown in FIG. 6.
FIG. 6 also depicts removal of wafer 610 from temporary carrier 410. Cleaning of adhesive from wafer 610 may be required after separation of wafer 610 from temporary carrier 410. Cleaning methods known in the art, such as. a plasma cleaning technique, may be effected.
As illustrated in FIG. 7, wafer 610 may then be placed on a dicing tape 710 and singulated by performing a dicing operation through encapsulant 512 and, therefore, resulting in a final packaged die 810/810", as shown in FIGS. 8(a) and (b). Final packaged die 810/810" provide for. as a result of cuts 312 (see FIGS. 3(a) and (b)), regions 822 that extend laterally over non-imaging regions on the active surface of the final packaged die 810/810". These laterally extending regions 822 of encapsulant, or packaging material, prevent at least some unwanted, or stray, light from reaching the image sensor 225 and are, therefore, also referred to herein as "lateral light blocking elements. ' Consequently, the accuracy of an image detected by image sensor 225 may be enhanced in embodiments of final packaged die 810/810" with laterally extending regions 822. Imager die packages, according to another embodiment of the present invention, may be formed in a manner similar to that of that described above, except the imager die are not covered with a glass layer. Instead, "known good lenses'* (KGL) are identified or qualified, and are subsequently placed over known good imager die. KGD, comprising known good imagers with KGL assembled therewith may then be placed on a temporary carrier, with standoffs that completely circumscribe the periphery of each image sensor 225 contacting the temporary carrier. These assemblies may then be encapsulated by molding or dam and fill processes and, thereafter, singulated to form final die packages. One variant of the second embodiment is shown in FIGS. 9-14. FIG. 9 illustrates a plurality of lenses 900A-E formed from a glass substrate 904. Lenses 900A-E may be individually qualified by methods known in the art to ascertain known good lenses. After testing, a dicing operation may be performed along dicing lines 902 resulting in a plurality of individual lenses. As shown in FIG. 10, a plurality of known good lenses 900' may thereafter be individually placed over a plurality of known good imager die 910 located on a TWI wafer 960. As described above in reference to FIGS. 1-8 and TWI wafer 216. TWI wafer 960, as illustrated in FIGS. 10-14 may comprise a fabrication substrate 908 and at least one conductive interconnect 236' located between adjacent image die 910 and extending from active surface 912 to a back side 913 of fabrication substrate 908 and in contact with an RDL. The RDL may be in the form of conductive traces 238' formed on the second surface 212' of TWI wafer 960. TWI wafer 960 may also comprise a first plurality of discrete conductive elements 240' formed on and in contact with conductive traces 238'. The plurality of known good lenses 900' may be respectively peripherally supported on and attached to a plurality of standoffs 242 located on the active surface 912 of fabrication substrate 908. wherein at least one known good lens 900' may be placed over one known good imager die 910. Standoffs 242/242' may be configured to provide support for attached known good lenses 900' and to provide a selected vertical spacing between stacked known good lenses 9007900" or between known good lenses 900' and TWI wafer 960. Standoffs 242' may also be configured to seal against a temporary earner 410 and to prevent encapsulant from contacting known good lenses 9007900". Implementing the configuration described in FIGS. 9 and 10 may improve the yield of an imager die package by ensuring bad lenses are not placed over good imagers and, therefore, decrease the amount of wasted material and component parts. Furthermore, this configuration may ensure that good lenses are not placed over bad imagers.
After placing known good lenses 9007900" over known good imager die 910, the imager die 910 with the known good lenses 9007900" attached thereto may be singulated by a dicing operation resulting in a plurality of KGD 510'. As described above, and illustrated in FlG. 11, KGD 510' may include at least one additional known good lens 900" and corresponding standoffs 242" (shown by dashed lines) stacked over known good lens 900' in order to achieve a desired focus onto imager die 910.
Referring to FIG. 12, KGD 510' may be placed face-down on a temporary carrier 410', such as a film frame tape or glass carrier, with standoffs 242' positioned against and secured to temporary carrier 410' to prevent encapsulant from contacting known good lenses 9007900". As the KGD 510' are placed face down on temporary carrier 410', KGD 510' are shown inverted relative to FIGS. 10 and 11. Once attached to temporary carrier 410', KGD 510' may be encapsulated with encapsulant 512', thus resulting in reconstructed wafer 930, as illustrated in FIG. 13. As described above, encapsulant 512' may comprise any conventional compound known for use in encapsulating semiconductors. Encapsulation processes may include a molding or dam and fill process as known in the art.
Thereafter, reconstructed wafer 930 may be subjected to appropriate processing to form a substantially planarized surface 950 extending across first set of discrete conductive elements 240' and encapsulant 512'. The processing may further provide for the at least partial exposure of the first plurality of discrete conductive elements 240'. After planarizing surface 950, a second plurality of discrete conductive elements 620', such as balls, bumps, columns, or pins of conductive material (e.g., solder, another metal, a conductor-filled polymer, etc.), may be bonded to the first plurality of discrete conductive elements 240'. The second plurality of discrete conductive elements 620' provides for subsequent attachment to a carrier substrate or other higher-level circuit assembly. As shown in FIG. 14, one discrete element of the second plurality may be operably coupled to one discrete element of the first plurality. As described above, in an embodiment of the invention using a compression molding encapsulation process, at least a portion of the first plurality of discrete conductive elements 240' may remain exposed during a compression molding process and, therefore, neither a planarizing process nor a second plurality of discrete conductive elements may be required.
Subsequent to encapsulation, temporary carrier 410' may be removed and a dicing operation through encapsulation material 512' may be performed, resulting in a final packaged die 810", as shown in FIG. 14. A processor based system 1060 which includes an imager die package 810/8107810" in accordance with an embodiment of the present invention is illustrated in FIG. 15. Without being limiting, such a system 1060 may include a computer system, camera system, scanner, machine vision system, vehicle na\ igation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, each of which may be configured to utilize an embodiment of the present invention.
A processor based system 1060, such as a computer system, for example, generally comprises a central processing unit (CPU) 962, for example, a microprocessor that may communicate with and input/output (I/O) device 964 over a bus 966. The imager die package 810/8107810" may also communicate with the system 1060 over bus 966. The system 1060 also includes random access memory (RAM) 968, and. in the case of a computer system, may include peripheral devices such as a floppy disk drive 970 and a compact disk (CD) ROM drive 972 which also communicate with CPU 962 over bus 966. CPU 962, imager die package 810/8107810" and memory 968 may be integrated on a single IC chip.
Specific embodiments have been shown by way of example in the drawings and have been described in detail herein; however, the invention may be susceptible to N arious modifications and alternative forms. It should be understood that the im ention is not intended to be limited to the particular forms disclosed. Rather, the im ention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Claims

What is claimed is:
L A method of packaging an imager die. comprising: positioning at least one optical element over at least one image sensor of at least one imager die of a plurality of imager dice carried by a fabrication substrate; singulating the imager dice from other imager dice; securing a plurality of imager dice to a temporary carrier with optical elements over the plurality of imager dice secured to or positioned adjacent to the temporary carrier; at least partially encapsulating the plurality of imager dice on the temporary carrier to form a reconstructed wafer; and singulating at least partially encapsulated imager dice from the reconstructed wafer.
2. The method of claim 1, wherein positioning at least one optical element comprises positioning at least one of a transparent layer and a substrate carrying a plurality of lenses over the fabrication substrate.
3. The method of claim 2, wherein singulating the plurality of imager dice includes forming cuts in the transparent layer or the substrate carrying the plurality of lenses with surfaces of the cuts extend laterally over at least portions of the plurality of imager dice.
4. The method of claim 3, wherein singulating the known good dice comprises forming cuts with an upper region that is wider than a lower region thereof.
5. The method of claim 1, further comprising: testing the plurality of imager die to ascertain known good dice.
6. The method of claim 1. further comprising: preventing encapsulant from covering at least end portions of discrete conductive elements protruding from the plurality of imager dice.
7. The method of claim 1, further comprising: at least partially exposing portions of discrete conductive elements embedded within encapsulant.
8. The method of claim 1 , further comprising: removing the reconstructed wafer from the temporary carrier.
9. An imager die package, comprising: an imager die comprising an image sensor on an active surface of the imager die; at least one contact on a back side of the imager die; an optical element over the image sensor; and an encapsulant surrounding the imager die and including an lateral light blocking element that extends laterally over a portion of the active surface of the imager die.
10. The imager die package of claim 9, wherein the encapsulant covers the back side of the imager die.
11. The imager die package of claim 10, wherein at least one discrete conductive element protruding from the at least one contact includes an end protruding from the encapsulant.
12. The imager die package of claim 10, wherein at least one discrete conductive element protruding from the at least one contact is completely surrounded by encapsulant.
13. The imager die package of claim 9, wherein the lateral light blocking element extends laterally substantially to a location above an outer periphery of the imager sensor.
14. The imager die package of claim 9, wherein the optical element comprises a layer of transparent material with a beveled or notched edge and the lateral light blocking element comprises encapsulant covering surfaces of the beveled or notched edge that are at least partially laterally extending.
15. A film frame tape, comprising: a substantially planar substrate; and an ultraviolet-sensitive adhesive material on the substantially planar substrate, the ultraviolet-sensitive adhesive material being configured to release an adhered object upon exposure of the ultraviolet-sensitive adhesive material to ultraviolet radiation.
16. An electronic device, comprising: a processor-based device; and an imager die package operably coupled to the processor-based device and comprising: an imager die comprising an image sensor on an active surface of the imager die; at least one contact on a back side of the imager die; an optical element over the image sensor; and an encapsulant surrounding the imager die and including an lateral light blocking element that extends laterally over a portion of the active surface of the imager die.
17. A collection of known good imagers, comprising: a plurality of imagers residing in a single plane; optical elements over image sensors of the plurality of imagers; and encapsulant between adjacent imagers and securing the plurality of imagers to each other.
18. The collection of claim 17, wherein the plurality of imagers consists of known good imagers.
19. The collection of claim 18, wherein the optical elements comprise lenses.
20. The collection of claim 17, wherein encapsulant extends at least partially laterally over active surfaces of the plurality of imagers.
21. An imager process assembly, comprising: a carrier; and a plurality of imager assemblies secured to the carrier, each imager assembly including: an imager die including an image sensor at an active surface of the imager die; and an optical element over the image sensor, the optical element being secured to or positioned adjacent to the carrier.
22. The imager process assembly of claim 21 , further comprising encapsulant between adjacent imager assemblies of the plurality of imager assemblies.
23. A method of packaging an imager die, comprising: dicing through a thickness of a fabrication substrate between adjacent imager die of a plurality of imager dice carried by the fabrication substrate to form a plurality of individual imager die; securing a plurality of known good imager die qualified from the plurality of individual imager die to a temporary carrier; encapsulating at least partially the plurality of known good die on the temporary carrier to form a reconstructed wafer; and singulating the at least partially encapsulated plurality of known good die from the reconstructed wafer.
24. The method of claim 23, further comprising positioning at least one optical element over the at least one imager die of a plurality of imager dice carried by the fabrication substrate prior to dicing through a thickness of the fabrication substrate.
25. A method of packaging an imager die, comprising: attaching at least one optical element over an active surface of a wafer including a plurality of imager dice, each imager die positioned on the active surface; dicing the wafer between adjacent imager die resulting in a plurality of individual imager die; securing at least one imager die of the plurality of individual imager die to a temporary carrier; forming a reconstructed wafer by at least partially encapsulating the at least one imager die on the temporary carrier; and singulating the at least partially encapsulated at least one imager die from the reconstructed wafer.
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