WO2009033081A1

WO2009033081A1 - Systems and methods for simultaneously transmitting a plurality of frequency multiplexed channels

Info

Publication number: WO2009033081A1
Application number: PCT/US2008/075474
Authority: WO
Inventors: Laurence Fish; Ian Lerner; Roswell Roberts; Lowell Teschmacher; Fred Harris; Dragan Vuletic; Wade Lowdermilk
Original assignee: X-Digital Systems
Priority date: 2007-09-07
Filing date: 2008-09-05
Publication date: 2009-03-12

Abstract

A method for simultaneously transmitting a plurality of frequency multiplexed channels is described. A plurality of multimedia channels are is received. The multimedia channels are decoded. The multimedia channels are modulated. The modulated channels are transmitted, simultaneously, through an analog cable infrastructure.

Description

SYSTEMS AND METHODS FOR SIMULTANEOUSLY TRANSMITTING A PLURALITY OF FREQUENCY MULTIPLEXED

CHANNELS

RELATED APPLICATIONS

[000 1] This application is related to and claims priority from U.S. Patent Application Serial No. 60/970915 filed September 7, 2007, for DIGITAL MOD ULATION SYSTEMS AND METHODS OF USE, with inventors Larry Fish, Ian .erner, Roswell Roberts, Lowell Teschmacher, Fred Harris, Dragan Vuletic, and Wade Lowdermilk, which is incorporated herein by reference.

TECHNICAL FIELD

[000 2] The present disclosure relates generally to radio frequency transmitters. More specifically, the present disclosure relates to systems and methods for simultaneously transmitting a plurality of frequency multiplexed chan nels.

BACKGROUND

[000 3] Multiple forms of media are being used to convey information to customers, consumers, etc. Multimedia describes these multiple forms of media, such as text, audio, still images, animation, video, interactivity, etc. Multiple forms media may be combined to convey the information, such as text together with audio, graphics together with animation, etc. [0004] Satellites may be used to convey some forms of multimedia. For exam ple, high-quality stereo audio signals may be compressed and transmitted from a satellite as a multi-channel Motion Picture Experts Group Layer-3 (MP3) signal. The compressed MP3 may be transmitted to a cable head end where the multiple channels are demodulated. The MP3 streams may be decoded and then remodulated as channelized analog frequency modulated (FM) signals for inser tion in a cable distribution plant.

[0005] In addition, digital television signals are transmitted from satellites as multi -channel MPEG compressed video signals. The compressed signals may be transmitted to a cable head end where the multiple channels may be demodulated. Similar to audio streams, the MPEG video streams may be decoded and then remodulated as channelized analog National Television Standards Committee (NTSC) or Phase Alternating Lines (PAL) television signals. These channelized analog signals may be inserted in a cable distribution system.

[0006] In the examples provided above, analog modulators are used to modulate the multimedia streams into channelized analog signals. The hardware for multi-channel analog modulators may require a large amount of space. For example, equipment bays that house the analog modulators are extre mely large in size and require a significant amount of processing power to operate. As such, benefits may be realized by providing digital signal processing (DSP) techniques to replace legacy multi-channel analog modulators. Specifically, benefits may be realized by providing system and methods for simultaneously transmitting a plurality of frequency multiplexed channels that have been digitally modulated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating one embodiment of a digital modulator in accordance with the present systems and methods;

[0008] Figure 2 is a block diagram illustrating another embodiment of a digital modulator field programmable gate array;

[0009] Figure 3 is a block diagram illustrating a further embodiment of a pulse-code modulation (PCM) interface ;

[0010] Figure 4 is a block diagram illustrating one embodiment of a first-in first out (FIFO) channel vector that is provided to a FIFO channel;

[0011] Figure 5 is a flow diagram illustrating one embodiment of a method for reading vectors from the FIFO channel;

[0012] Figure 6 is a block diagram illustrating one embodiment of a modulator engine;

[0013] Figure 7 is a flow diagram illustrating one embodiment of modulating multiple channel time division multiplexed (TDM) streams to a single channel;

[0014] Figure 8 is a block diagram illustrating one embodiment of a dBx encoder; [0015] Figure 9 is a block diagram illustrating one embodiment of a resampler;

[00 16] Figure 10 is a block diagram illustrating one embodiment of an upsampler;

[00 17] Figure 11 is a block diagram illustrating one embodiment of two channelizers that are incorporated as part of the modulator engine;

[00 18] Figure 12 is a flow diagram illustrating one embodiment of a method for simultaneously transmitting a plurality of frequency multiplexed channels; and

[00 19] Figure 13 illustrates various components that may be used in a computing device.

BRIEF SUMMARY OF SOME ASPECTS OF THE INVENTION

[00 20] The technology of the present application provides systems, apparatuses, and methods to multiplex a plurality of streams (channels) of mutimedia data using a single digital multiplexer. Aspects of the technology of the present application include simultaneously transmitting a plurality of frequency multiplexed channels by receiving a plurality of multimedia channels. Decoding the plurality of multimedia channels and modulating, digitally, the multimedia channels that are transmitted simultaneously over a distribution infrastructure.

[00 21] Other aspects of the technology of the present application includes a digtal modulation device that is configured to transmit a plurality of frequency mutiplexed channels. The digital modulator includes a processor having a memory. Instructions stored in the memory are executable by the digital modulation device to receive a plurality of multimedia channels. The plurality of multimedia channels are decoded. The decoded plurality of multimedia channels are modulated, digitally, into multimedia channels and transmitted simultaneously over a distribution infrastructure.

[00 22] Other aspects of the technology of the present application include a digital modulation device that is configured to transmit a plurality of frequency multiplexed channels. The digital modulator includes a processor having amemory. Instructions stored in the memory are executable by the digital modulation device to receive a plurality of multimedia channels. The plurality of multimedia channels are decoded. The decoded plurality of multimedia channels are modulated, digitally, into multimedia channels and transmitted simultaneously over a distribution infrastructure.

DETAILED DESCRIPTION

[00 23] The technology of the present application provides systems, apparatuses, and methods that may convert, replace, or be in the alternative to legacy cable infrastructure. For example, multiple dwelling unit (MDU) locations, resorts, hotels, and the like typically have legacy cable infrastructure. The technology provided herein may be used to convert the legacy cable infrastructure to a hybrid satellite reception/analog cable distribution system. In one embodiment, the present systems and methods may be implemented using multiple satellite receivers, transport demultiplexers, multiple digital signal processor (DSP) based decoders, and a multi-channel digital modulator. The digital modulator may be implemented as a field programmable gate array (FP GA) device or other complex programmable logic devices (CPLDs). The digital modulator may receive digital pulse-code modulation (PCM) samples (or streams) and modulate a number of carriers in a continuous frequency band. For example, the digital modulator may modulate, in one prototype embodiment, up to 200 analog carriers in a continuous frequency band from 18 Megahertz ( MHz) to 80 MHz for an audio plant. Multimedia streams having more data to transmit, such as video transmission, may not be able to modulate as many carriers. The present systems and methods improve the existing analog equipment by replacing, for example, 200 single channel units with one DSP device. In other words, legacy systems provide a multiplixer for each channel. Thus, legacy systems provide 200 modulators to provide 200 channels. Conversely, as explained further below, the technology of the present application provides a signal modulator for 200 channels.

[00 24] In one embodiment, each modulated carrier is made up of three channels with three PCM streams. In one configuration, the three channels that make up a modulated carrier are audio channels that carry audio data. In another configuration, the channels are video channels that carry video data. In still another configuration, the channels are audio and video channels. In yet another embodiment, the channels may carry any other form of multimedia data. The output of the digital modulator, which may be implemented as a FPGA, may feed a high speed digital-to-analog converter (DAC). The DAC may generate a waveform for the modulated frequency spectrum. A more detailed description of these systems and methods is provided below. In addition, although the description below describes the transmission of audio data, the present system and methods may be used to modulate and transmit other types of data, such as video data, audio and video data, or any other type of multimedia data. [0025] Figure 1 is a block diagram illustrating one embodiment of a digital modulator 102 in accordance with the present systems and methods. As previously explained, the digital modulator 102 may be implemented as a FPGA and may be installed on a printed circuit board (PCB) by way of a high density cornector.

[0026] The digital modulator 102 may include an analog-to-digital converter (ADC) interface 104. The ADC interface 104 may provide a way for live samples to be brought into the modulator FPGA 102. In one configuration, the live samples are audio samples. In another configuration, the live samples are video samples, audio and video samples, or any other type of multimedia. In one exemplary embodiment, two ADCs (not shown) may reside on the PCB and com municate with the digital modulator 102 via the ADC interface 104. [0027] In this exemplary embodiment, each of these two ADCs may receive a master clock, a sample clock, and left/right clocks as input. The two ADCs output a serial stream of encoded data, such as PCM encoded data, and the ADC interface 104 may drive the clocks in order to obtain a 32-bit left/right serial sample stream from the two ADCs. In one embodiment, the ADC interface 104 drives the clocks with a frequency of 48 kilohertz (kHz) in order to obtain the 32- bit left/right serial sample stream. The 32-bit left/right stream may be converted from serial to parallel format and 16 bits of left data and 16 bits of right data may be extracted. One, or both, of the 16 bit samples may be passed to a PCM interface 108 for routing to a modulator engine 112. The modulator engine 112 may further process the 16 bit sample(s), as will be described below. [0028] The digital modulator 102 also may include a host interface 106 that is used to program the digital modulator 102. For example, if the modulator is constructed from FPGAs, the host interface 106 downloads for a new program tha is imprinted on the FPGA using flash memory or the like. The host interface 106 may receive programming instructions for the digital modulator 102 from a cervral processing unit (CPU) (not shown) that is on the PCB. In one embodiment, the host interface 106 includes a 15 bit address bus, a 16 bit data bus a chip select, and read/write strobes. The 16 bit data bus may be asynchronous. The host interface 106 may be used to program a set of internal registers (not shown) in order to configure the modulation engine 112. Details regarding the configuration of the modulation engine 112 will be discussed below.

[0029] The digital modulator 102 may further include the PCM interface 108 mentioned above. The PCM interface 108 facilitates a plurality of digital signal processor (DSP) serial sample streams to be input to the digital modulator 102 for processing and modulation. The serial sample streams may be received fron ADCs on the PCB via the ADC interface 104, as previously explained. Further details regarding the PCM interface 108 will be described below, in particular, in relation to Figure 3.

[0030] In one embodiment, the digital modulator 102 also includes a motherboard DAC interface 110. A single PCM stream (such as an audio stream) may be selected by the PCM interface 108 and directed to the motherboard DAC interface 110. The selected single stream may be observed live via the motherboard DAC interface 110. The output of the motherboard DAC interface 110 may be a serial stream that represents the 16 bit left sample and the 16 bit right sample previously described. In addition, the output may be provided with a 3 MHz sample clock and a 48 kHz left/right clock. [0031] The modulator engine 112 may receive a plurality of carrier channel vectors for each of the sample streams extracted from the PCM interface 108. For example, the modulator engine 112 may receive 200 carrier channel vectors and create a single waveform that includes all of the carrier channel vectors (i.e. all 200 carriers are modulated and transmitted with a single waveform). [0032] Figure 2 is a block diagram illustrating another embodiment of a digital modulator 202. In this exemplary embodiment, digital modulator is constructed as a field programmable gate array in accordance with the technology of the present systems and methods. The digital modulator 202 may receive channels by satellite through a conventional downconverter or the like as is generally known in the art. Digital modulator 202 may receive channels through other conventional transmission mechanisms as well, such as a conventional radio frequency broadcast. Channels may include radio channels, Motion Picture Experts Group (MPEG) channels, etc. The digital modulator 202 may decode the channels, modulate the decoded channels, and transmit the channels through an analog cable infrastructure.

[0033] The digital modulator 202 may include a PCM interface 208, as previously described. In one embodiment, the interface 208 accepts serial PCM streams of radio channels sampled at 48 kHz from DSP based decoders 222. Decoders 222 in this exemplary embodiment are audio decoders. In another embodiment, the PCM interface 208 may accept serial PCM streams of other multimedia channels from DSP based decoders. The PCM streams may be parallelized and stored in different memory locations for each channel. In addition, channel configuration bits 246 may be added to each channel. Channel configuration bits 246 may be obtained from a host interface 206. Details regarding the configuration bits are provided below. [0034] The PCM interface 208 may organize the received channel streams as a multiple channel time division multiplexed (TDM) stream. The TDM stream may be input to a modulator engine 212. In one embodiment, a frame of the TDM stream 238 may be input to the engine 212 at a frequency rate of 48 kHz. [0035] In another configuration, a single channel (such as a radio channel) may be generated locally by a first analog-to-digital converter (ADC) 224 and a second ADC 226. The first and second ADC 224, 226 may be on the PCB (not shown). Samples 230, 232 of the channel may be passed to the PCM interface 208 via an ADC interface 204 as an ADC stream 234. In one embodiment, the PCM interface 208 may replace samples from a channel received from a satellite by either of the ADC samples 230, 232 in the ADC stream 234. [0036] The modulator 202 may further include a motherboard DAC interface 21 ( that interfaces the modulator 202 with a motherboard DAC 216. The motherboard DAC 216 may test received PCM streams 228. For example, a PCM test stream 236 may be sent to a motherboard DAC 216 via the motherboard DAC interface 210. Samples 240 included in the PCM test stream 236 may include left and right audio samples at a sample frequency rate of 48 kHz frequency.

[0037] The modulator engine 212 may represent a multiple channel digital transmitter. In one exemplary embodiment, the modulator engine 212 represents a 200 radio channel digital transmitter. Other embodiments may provide a digital transmitter that transmits more or less channels. For example, a video digital transmitter may transmit less channels. Inputs to the modulator engine 212 may be the multiple channel TDM input stream 238. The TDM stream 238 may be read from a data interface inside the PCM interface module 208. The engine 238 may convert the TDM input stream 238 to a frequency division multiplexed (FDM) stream. The FDM output 242 may be passed to a DAC 218 on the PCB for further processing. The modulator engine 212 also may include a port to receive engine configuration bits 248 from a host interface 206. The engine configuration bits 248 may be used for fine tuning various parameters of the modulator engine 212. [0038] The digital modulator 202, which may be a FPGA or other CPLD₁ may include a system clock interface 214. In one embodiment, engine clocks 250 used by the modulator engine 212 are DAC clocks 244 that are acquired from the DAC 218 via the system clock interface 214. Using DAC clocks 244 as the engine clocks 250 helps synchronize the modulator engine 212 and the DAC 218.

[0039] In a further embodiment, the digital modulator 202 also includes a host interface 206. Communications between the modulator engine 212 and a user may be performed via a motherboard CPU 220 and the host interface 206. For example, a host address 252 may be provided to the modulator engine 212 from the CPU 220 via the host interface 206. In addition, host data 254 may be passed between the engine 212 and CPU 220 via the interface 206. [0040] The host interface 206 may include an array of addressable registers, which may be accessed over an external address and data bus. Among the registers, some examples may include access points to channel configurations 246 that are communicated to the PCM interface 208. Another example may include access points to engine configurations 248 that are passed to the modulator engine 212. Further examples may include a reset register that provides reset signals 256 and a status register that provides status signals 258. More details regarding the configurations 246, 248 and signals 256, 258 are described below.

[0041] Figure 3 is a block diagram illustrating an embodiment of an exemplary PCM interface 308. In one configuration, the PCM interface 308 allows multiple DSP serial sample streams 322A-N to be input to the digital modulator 102 for processing and modulation. For example, the PCM interface 308 may allow 64

DSP serial sample streams to be input into the digital modulator 102 in order to be processed and modulated. The PCM interface 308 may receive the multiple

DSP streams 322A-N and convert them from serial to a 16-bit parallel format through a serial-to-parallel converter 320. The serial streams 322A-N may be converted by implementing a front end shift register as a group of shift register look-up (SRL) primitives for each of the multiple streams 322A-N. The SRL may shift each sample stream 322A-N by an amount representing its bit position in a final 16-bit vector.

[0042] In one embodiment, a final 16-bit vector for each of the multiple streams 322A-N is stored in a flip-flop based holding register (not shown). For example, a final vector may be stored in a holding register every 16 cycles of a 12.288 MHz system clock. The content 332 of these multiple holding registers may be written into a first block random access memory (BRAM) 328 and a second BRAM 330.

[0043] The PCM interface 308 also may support two external PCM channel formatted streams 324A and 324B. In one embodiment, the two external streams are PCM audio channel formatted streams. The external streams 324A and 324B may be TDM streams and may be stored in the same way as the multiple DSP streams 322A-N described above. In one embodiment, in order to route the external streams 324A and 324B to the modulator engine 112, a particular bit of a control register (not shown) is set. In one embodiment, bit five of the control register may be set in order to enable the external streams 324A and 324B to be routed to the modulator engine 112.

[0044] As previously explained, the PCM interface 308 may include a first BRAM 338 and a second BRAM 330. Multiple BRAMs allow for a snap shot of contiguous samples, such as audio samples, video samples, audio and video samples, or any other type of multimedia samples. For example, while one snap she is stored in the first BRAM 328, the other snap shot may be read out of the second BRAM 330. Data that is extracted from a BRAM may be located at any address. As such, in order to avoid a situation where the data being read is simultaneously being written, a separate BRAM is used for writing and reading. The write address for the BRAM may be generated by a BRAM storage control module (not shown) and the read address 338 may be generated by a multiplexer (MUX) map module 334.

[0045] In one embodiment, the MUX map module 334 extracts data from the currently active BRAM 328, 330 and routes the data 342 to a first-in-first-out (FOFO) channel 340. The FIFO channel 340 may be an n-channel queue buffer. The FIFO channel 340 may then route data 344 to the modulation engine 112. The data that is extracted from a BRAM may be dictated by a mapping function of the MUX map module 334. The read address 338 for an active carrier channel may be provided to a BRAM 328, 330. The BRAM may store carrier configuration data. For example, each of the multiple carriers may be configured for PCM channels, level, and modulation. [0046] In one aspect, a configuration vector that includes three PCM channel addresses may be used to extract data from the first BRAM 328 or the second BRAM 330. The read address 338 (provided by the MUX map module 334) may be a configuration vector with the three PCM channel addresses. Each of the channel addresses are multiplexed in time and may be applied to the BRAM 328, 330. In one embodiment, each of the three PCM channel addresses correspond to a 16-bit stream. The first stream that may be extracted may be 16 bits of SCA data. The second stream extracted may be 16 bits of right audio data, and the third extracted stream may be 16 bits of left audio data The extracted streams 336A, 336B passed from the BRAMs 328, 330 may be stored in a temporary holding register (not shown).

[0047] Figure 4 is a block diagram illustrating one embodiment of a FIFO channel vector 400 that is provided to the FIFO channel 340 from the MUX map 334. After a certain portion of the data, or streams , is returned 336A, 336B from the BRAM 328, 330, 11 bits of carrier configuration information and one bit indicating the end of a packet may be concatenated to the returned data 336A, 3368. The portion of data may be 48 bits. The resultant 60 bits may form the FIFO channel vector 400.

[0048] In the case of audio streams, the vector 400 may include 16 bits of SCA data 418, 16 bits of right data 416, 16 bits of left data 414, and 11 bits of carrier configuration data 402, 404, 406, 408, 410, 412. In one embodiment, four bits of the carrier configuration data is carrier attenuation data 412. In addition, one bit of the configuration data may be mode data 410. For example, for audio streams, the mode data 410 may indicate whether the mode is mono or stereo. Further, the carrier configuration data may include two bits of SCA configuration data 408, 2 bits of right configuration data 406, and two bits of left configuration data 404. The left, right, and SCA configuration data 404, 406, 408 ma include modulation and carrier enable controls.

[0049] In one embodiment, the carrier configuration data further includes a packet end single bit 402 that is used by the modulator engine 112 as a tracking bit. In other words, the end of packet bit 402 may be used for error detection if the modulator engine 112 reads too many or too few sample streams. Multiple earner channel vectors (such as the vector 400) may be written into the FIFO channel 340 in a contiguous block. The FIFO channel 340 may be sized such that it 340 may not overflow as long as the modulator engine 112 reads each of the multiple vectors at a predetermined frequency. For example, the modulator engine 112 may read 200 vectors from the FIFO channel 340 at a rate of 48 kHz. [0050] Figure 5 is a flow diagram illustrating one embodiment of a method 500 for reading vectors from the FIFO channel 340. In one configuration, the method 500 is implemented by the modulation engine 112. The operational steps provided herein are described in a particular order but the operational steps may be performed in the described order or other orders. Moreover, more, less, or other operational steps may be included that are not specifically described herein. Further, certain steps provided herein may be separated into several steps or several steps provided may be combined into a single step. [0051] The method 500 may begin and a decision 502 may be made as to whether the FIFO channel 340 is empty. If the FIFO channel is empty, the me iod 500 may return and continue to determine whether the FIFO channel 340 is empty. If it is determined 502 that the FIFO channel 340 is not empty, dat may be read 504. The data may include a 60 bit vector, as previously described. In one embodiment, the data may be read in a non-continuous fashion. In one aspect, each channel vector stored in the FIFO channel 340 may be read out at a frequency rate of 48 kHz.

[0052] A second determination 506 may be made as to whether a read count has been reached. If the read count has not been reached, the method 500 continues to read 504 the data until the read count has been reached. A third determination 508 may be made as to whether a flag bit is set. If the flag bit is set, the method 500 may return to determine 502 whether the FIFO channel is empty. If the flag bit is not set, the FIFO channel may be reset 510. In other words, if the flag bit is not set at the end of reading the data (i.e. vectors) from the FIFO channel 340, the channel 340 may be reset 510 and cleared. A clean snap shot of audio, video, etc. may be present on a subsequent data read from the BRAMs 328, 330.

[0053] Figure 6 is a block diagram illustrating one embodiment of a modulator engine 612 in accordance with the present systems and methods. As illustrated, the nodulator engine 612 may receive data and other information from various sources. For example, the modulator engine 612 may include a transmitter/receiver 660 that receives data 674 from a PCM interface 608. In one embodiment, the data 674 may be read from the FIFO channel 640 that resides in the PCM interface 608. The data 674 may include multiple vectors associated with carrier channels as previously described. The transmitter/receiver 660 may transmit data 676 to an output section 662, which out| uts the data 678 to a DAC 618. The DAC 618 may reside on the PCB (not shown). In one embodiment, the output data 678 may be 200 vectors, each including 60 bits, as previously explained. In other embodiments, the output data may be more or less than 200 vectors. The DAC 618 may generate a single waveform that carries each of the 200 vectors over a frequency spectrum. The spectrum may be in the range of 18 MHz to 80 MHz.

[0054] The modulator engine 612 may further include a configuration interface 664 to pass configuration signals 680 to control registers within the modulator engine 612. The configuration signals 680 may be received from a host interface 606. In one embodiment, a clock signal 632 may be used to receive control data into the control registers of the modulator engine 612. The clock signal 632 may be the same clock that is used to drive output registers of the host interface 606 that store information about the configuration of the engine 612.

[0055] The configuration interface 664 also may receive a configuration address signal 634. The address signal 634 may be a vector that includes an address of the currently written control. In addition, a configuration value signal 636 may be a vector that includes a value of the currently written control. The configuration interface 664 may further receive an enable signal 638. The enable signal 638 may define a clock period when the data on the address signal 634 and the value signal 636 are valid.

[0056] The engine 612 may also receive clock signals 682, 684 from a system clock interface 614. In one embodiment, a first clock signal 682 is at a frequency of about 150 MHz and may be used for clocking most of the engine 612 For example, the first clock signal 682 may be used to clock the rate at which data 674 is read out of the FIFO channel 640 in the PCM interface 608. A second clock signal 684 may be at a frequency of about 225 MHz and may be used for clocking the output section of the engine 612. In one embodiment, the output signal 678 of the engine 612 is clocked at about the same frequency as the DAC618.

[0057] In one embodiment, the host interface 606 may send/receive reset signals to/from the modulator engine 612. For example, an error reset signal 696 may be a signal to reset a starved flag 698 produced by a starvation detection module 668. A starved signal 698 may be generated if prolonged periods of FIFO channel 640 data writes exist. In other words, the starved signal 698 may be generated if the pause between generating two frames of sync signals 692 is longer than a standard time frame. In addition, the error reset signal 696 may be a signal to reset an underflow signal 694 provided by an underflow detection module 670. In one configuration, an underflow signal 694 may be generated if a FIFO empty signal 686 is received by the underflow detection module 670 and the last data read from the FIFO channel 640 is not the 200th radio channel. The underflow signal 694 may be passed to the host interface 606.

[0058] The host interface 606 may also send a modulator engine reset signal 690 to the engine 612. The reset signal 690 may be applied to the engine's 612 input interface on the transmitter 660. The reading of data from the FIFO chanel 640 may be stopped when the reset signal 690 is received. The reset signal 690 may be held high for a certain number of clock periods until data from a previous state is propagated through the modulator engine 612. [0059 In another embodiment, a flush reset signal 688 may be provided to the transmitter 660 of the modulator engine 612. The flush reset signal 688 may be used to clear the states of one or more infinite impulse response (MR) filters (not shown) that may be included in the modulator engine 612. The flush signal 688 may be necessary because a faulty write to an HR filter may lead to instability. Unstable filters may not return to stable states from an input. Filter instability also may be caused by input signals that are too high, or by transfer function denominator gains in filters with a fixed point format. Another cause of filter instability may be the reset of the DAC 618, because the clocks 682, 684 of the engine 612 may be derived from the DAC clock.

[0060] In one configuration, a data bus 674 includes data that is read from the FIFO channel 640 in the PCM interface 608. Each signal of data that is read from the FIFO 640 may include left, right, and SCA samples from one of 200 TDM radio channels, as well as controls defining characteristics of that particular channel. The modulator engine 612 may read an input data stream from the FIFO channel 640 over the data bus 674. The stream may be split to left, right, and SCA sample and control bits that manage the channel characteristics. The FIFO channel 640 may be read in frames including 200 data samples. Each data sample may correspond to the same time sample of a different radio channel. The start of a frame read may be defined by a frame sync signal 692. After the reading of data has begun, the data may be read from the FIFO channel 640 every 15 periods of a 150 MHz clock. In one embodiment, the data may be read 200 times.

[0061] In addition, an empty signal 686 may be passed from the FIFO channel 640 to the underflow detection module 670. The empty signal 686 may indicate when the FIFO channel 640 does not include data to be read by the modulator engine 612.

[0062] The transmitter 660 may provide a read enable signal 684 to the FIFO channel 640. As previously mentioned, the enable signal 684 may be generated every 15 periods of the first clock signal 682 (i.e., 150 MHz) for 200 times after a frame sync signal 692 occurrence. In other words, the enable signal 684 may be generated 200 times after the frame that includes one sample of each channel has been sampled. The frame sync signal 692 may be the internal signal for the modulator engine 612. The sync signal 692 may be generated with some delay after the falling edge of the empty signal 686. Writes and reads to/from the FIFO channel 640 may be done in bursts that include 200 data samples. The falling edge of the empty signal 686 may be used to detect the start of the next data burst if the data samples are correctly written and read from the FIFO channel 640 with sufficient time between the frames.

[0063] In another embodiment, the engine 612 includes a version constant module 666 that generates an engine version signal 630. The version signal 630 indicates the current version of the modulator engine 612. The version information may be passed to the host interface 606. In addition, the engine 612 may include a frame start module 672 that receives the empty signal 686 and the engine reset signal 690 and generates the frame sync signal 692. [0064] Figure 7 is a flow diagram illustrating one embodiment of modulating multiple channel TDM streams to a single channel. The operations illustrated in Figure 7 may be performed by the modulator engine 112. In one embodiment, an input stream 702 from the FIFO channel 340 may be divided into multiple streams by a first MUX 704. The first MUX 704 may divide the input stream 702 into a left stream 710, a right stream 708, and an SCA stream 706. In another embodiment, test signals from a Direct Digital Synthesizer (DDS) (not shown) may be used instead of the input stream 702. The DDS may generate three independent sine waves that may be used as left samples, right samples, and SCA samples of a designated channel. The rest of the channels may be set to zero.

[0065] In addition to the input stream 702 including data samples, the stream 702 may also include channel configuration bits. These bits may include mono/stereo mode bits. A channel mode may define the branch inputs for that particular channel. For example, in the case of a channel in the mono mode, a base branch 716 may be fed with a left sample 710. A Sub branch 714 may be fed with a right sample 708. In the case of a channel in the stereo mode (as illustrated in Figure 7), the base branch 716 may be fed with the sum of the left sample 710 and the right sample 708. In one embodiment, the time between samples in the base branch 716 may be 15 clock cycles. The Sub branch 714 may be fed the difference of the left sample 708 and the right sample 710. The summing and subtracting of the left and right samples may be executed by a second MUX 712.

[0066] In one embodiment, SCA samples that feed the SCA branch 706 are unaltered. The Sub branch 714 and the SCA branch 706 may be interleaved into a 400 channel TDM stream before being encoded by a dBX encoder 718. The time between samples in the interleaved Sub branch 714 and the interleaved SCA branch 70 may be 7 clock cycles processing for each sample. [0067] In one aspect, the base branch 716 may be filtered by a pre-emphasis first HR filter 720. The pre-emphasis filter may be a first order floating point HR filter. The first HR filter 720 may be a differentiator with zeros at 75 microseconds (μs). The base branch may then pass through a first band limiting low pass filter (LPF) 726. The band limiting filter may be implemented as a sixth order floating point HR filter. The filter structure may be three cascaded second order filters. The band limiting LPF 726 may pass frequencies of about 7.5 or 14 kHz depending on the channel mode (Ae. mono or stereo mode). In order to protect a receiver from over-modulation, a limiter may be implemented as part of the band limiting LPF 726 for the base branch 716. In one configuration, the base branch 716 may pass through a phase HR compensation filter, and then the base branch 716 may be resampled by a first resampler 738. [0068] In one embodiment, a variable delay 744 may be added to the signal in order to introduce latency to the base signal. The variable delay 744 may also facilitate the matching of the phases for the base and sub signals. The introduced latency may be set as a fixed value through engine configuration ports. In one embodiment, samples may be incrementally written to memory, wrapping after the last memory address. The first address of a frame that is being currently written to memory may be saved. A fixed delay, which may be a multiple of 200, is added to the saved value and may be used as a first address for the next frame reading.

[0069] The encoded Sub branch 714 and the encoded SCA branch 706 may be filtered by a second low pass band limiting filter (LPF) 722 and a third band limiting LPF 724, respectively. The second LPF 722 may pass Sub samples at about 7.5 or 14 kHz depending on the channel mode. The third LPF 724 may pas SCA samples at about 7.5 kHz regardless of the channel mode. The Sub branch 714 and SCA branch 706 may pass through a second and third pre- emphasis UR filter 728, 730, respectively. The second and third HR 728, 730 may include zeros at 50 μs.

[0070] The branches 714, 706 may also pass through a second and third phase and magnitude HR compensation filter 734, 736, respectively. In one embodiment, the compensation filters 732, 734, 736 may be used to provide a flat spectrum of a transfer function and stereo signal separation for a modulator- receiver system. The base branch 716 and the interleaved Sub brand 714 and SCA branch 706 may be compensated. The base branch compensation filter 732 may be a fourth order all-pass HR filter fitting the phase characteristics of the different processing branches (i.e., base branch, Sub branch, and SCA branch). The base compensation filter 732 may be implemented as two cascaded sections of a standard second order floating point filter. In one embodiment, the Sub branch and the SCA branch may each include a standard first order floating point compensation filter 734, 736 for magnitude compensation, and an all-pass filter of the same structure as the base branch compensation filter 732. [0071] Following the compensation to the phase and magnitude, the Sub branch 714 and the SCA branch 706 may be resampled by a second and third resampler 740, 742, respectively. Details regarding the resamplers 738, 740, 742 are provided below.

[0072] In one embodiment, the Sub branch 714 and the SCA branch 706 may each pass through a DDS 746. The DDS 746 that processes the Sub branch 714 may operate at 30 or 32 kHz, and the DDS 746 that processes the SCA branch 706 may operate at 70 or 80 kHz. In addition, the Sub branch 714 and the SCA branch 706 may be filtered by a first and second bandpass filter (BPF) 748, 750, respectively. The first BPF 748 may pass Sub samples of between about 30 and 32 kHz, depending on the mode of the channel. The second BPF 750 may pass SCA samples between about 75 and 80 kHz regardless of the channel mode. [0073] A summer 752 may sum together the SCA branch 706, the Sub branch 714, and the base branch 716. After the base branch 716, Sub branch 714 and the SCA branch 716 have been summed, the channels may be encoded and sampled by an upsampler 754 and then processed by a DDS 746. Details regarding the upsampler 754 are provided below. The output of the flow diagram illustrated in Figure 7 may be an FM encoded single channel 756. [0074] Figure 8 is a block diagram illustrating one embodiment of a dBx encoder 818. In one configuration, the dBx encoder 818 represents a magnitude compression device. A feedback loop characterizes the output signal gain and may be used to attenuate an input signal 802 and provide magnitude compression. By compressing the magnitude of the signal over the channel, the dBy encoder 818 raises the signal-to-noise ratio for low-level signals. [0075] In one embodiment, the input signal 802 is passed through a fixed pre- emphasis HR filter 804. The filter 804 may be a high-pass filter to flatten the spectral magnitude of the input signal 802. In one embodiment, the input signal 802 is the Sub branch 714 and/or the SCA branch 706 of an audio signal. In another embodiment, the input signal 802 is a video signal or any other type of multimedia signal.

[0076] The filtered input signal may be multiplied 806 with a processed feedback signal 822. The multiplied signal may be saturated by a limiter 808. The limiter 808 may protect an output signal 824 and the feedback signal 822 from over-modulation. In one embodiment, the feedback signal 822 passes through a gain control band-pass filter (BPF) 820. Frequencies in the range of about 35 Hz - 2 kHz may be passed through the BPF 820. The filtered signal may provide a prediction of the average signal magnitude. [0077] The filtered signal may be further processed by an exponentially weighted root mean square (ERMS) module 814. A square function 818 may first square the filtered signal and the a leaky integrator filter (LPF) 816 may further filter the signal. A square root of the signal may then be obtained. The square root function may be incorporated in a gain function module 812. In one embodiment, the gain function 812 represents a set of two functions that occur in a loop, using a single memory bank. Further a synchronization register bank 810 provides values for the channel selected in the input branch channel 802. The sync register bank 810 may synchronize the input branch channel 802 and feedback channel 822 processing.

[0078] Figure 9 is a block diagram illustrating one embodiment of a resampler 938 that may be used for the base branch 716, the Sub branch 714, and the SCA branch 706. The resampler 938 may change the sampling frequency rate by synchronizing the receive rate of data samples to the DAC clock. The output signal 920 of the resampler 938 may have a rate of 293 kHz and may be tied to 512 cycles of the 150 MHz clock. In one embodiment, 200 multiplexed channels may allow for approximately 2.5 cycles per sample throughput. The resampler 938 may provide four parallel channels 916 at the output in order to provide for 10 cycles per sample throughput.

[0079] In one embodiment, input data 902 may be provided to a synchronization FIFO 906. The input data 902 may be provided at a frequency rate of 48 kHz and may be divided by a time division demultiplexer 904 into four separate channels 908. Each of the channels 908 may be written into four separate memory locations 910 that may be used for upsampling filter inputs by an upsampler 912. The upsampler 912 may be an eight channel upsampler. In one embodiment, each memory location 910 may store 50 channels, with 16 samples for each channel.

[0030] A bank linearization medium access control (MAC) module 914 may perform filter bank linearization by calculating outputs with two adjacent banks provided by a bank pointer 936. Further, the bank linearization MAC 914 may apply first order interpolation on outputs depending on the pointer's 936 remainder.

[0031] The resampler 938 may also include one or more controls 934. The controls 934 may generate a context switch every 10 cycles. For example, control logic 924 may generate read/write signals 922 every 10 cycles. In one embodiment, a data pointer 932 and a bank pointer 936 may be generated by a pointers generator 930 every 512 cycles at the sampled rate. The bank pointer 936 may indirectly define an output to input ratio and may be calculated according to a fill percentage of memories that are storing the input data 902. In one embodiment, 16 samples of each channel are stored, as such, parameters of a Pl regulator 926 may be selected to provide a stable resampling ratio. [0032] The resampler 938 may further include multiple coefficients 940, 942 thai are arranged in multiple banks, such as the coefficient banks ROM 944. For example, the resampler 938 may include 2344 coefficients arranged in 293 banks. The coefficient banks ROM 944 may store the coefficients. The stored bank coefficients may be passed 940, 942 to the upsampler 912. The output from the upsampler 912 may be provided to the bank linearization MAC 914 and four channels 916 may be the output from the linearization MAC 914. The four channels 916 may be multiplexed by a time division multiplexer 918 in order to prc luce an output 920 signal with a frequency rate of 293 kHz. [0083] Figure 10 is a block diagram illustrating one embodiment of an upsampler 1054. In one example, an input signal 1002 is at a frequency of 293 kHz. The input signal 1002 may be the summation of the base branch 716, the Su branch 714, and the SCA branch 706. The signal 1002 may be demultiplexed by a time division demultiplexer 1004. For example, data processing of the input 1002 may be parallelized into four branches 1008. Each branch may handle multiple radio channels. As an example, each branch may handle 50 radio channels.

[0084] In one embodiment, the multiple branches 1008 are saved in memory 1010 on a synchronous FIFO 1006. The memory 1010 may be similar to the memory 910 previously described in relation to the resampler. In one configuration, ten samples of each branch (i.e., channel) 1008 may be stored in the memory 1010. Samples from each of the four channels 1008 may be retrieved and filtered through a channel upsampler 1012. [0085] In one embodiment, each branch 1008 includes two channel upsampler filters, both with coefficients from a different coefficient bank. The output 1018 of the channel upsampler 1012 provides two channels corresponding to each single channel that was input to the υpsampler 1012. For example, a first branch "chO" that is input to the upsampler 1012 may be associated with a "chO even" branch and a "chO odd" branch at the output 1018 of the upsampler 1012.

[0086] A channel reorder and multiplex memory module 1014 may reorder and multiplex the multiple channels at the output 1018 of the upsampler. The resultant output signal 1016 may have a frequency twice the frequency of the input signal 1002. For example, the frequency of the output signal 1016 may be 586 kHz (assuming the frequency of the input signal 1002 is 293 kHz). The output 1016 may represent samples at a frequency rate of 586 kHz. The samples may be arranged in groups of two adjacent samples per channel. In order to provide a TDM stream as the output 1016, the samples may be reordered (by the channel reorder and multiplex memory module 1014). In one embodiment, the samples are reordered by storing the samples into memory at alternating address locations.

[0087] Figure 11 is a block diagram illustrating one embodiment of two channelizers 1100 that are incorporated as part of the modulator engine 112. The channelizers 1100 may convert a channels' structure from a time multiplex channel to a frequency multiplex channel. In one embodiment, the bandwidth of a channel is twice as large as the channel spacing. As such, a single channelizer may accommodate every second channel. Hence, two channelizes 1100 may be used. Each of the two channelizers 1100 may perform 1:128 upsampling. The FDM output 1034 of the channelizers 1100 may be interleaved by shifting the output 1130 of the second channelizer by 293 kHz and then adding 1132 the output 1136 of the first channelizer. The output 1130 of the second channelizer may be shifted by an upconverter 1128. [0088] In one embodiment, a TDM channel input 1102 is provided to a splitter

110 that splits the TDM channel 1102 into even 1106 and odd 1108 channels. Time division demultiplexers 1110A, 1110B may demultiplex the even 1106 and odd 108 channels, respectively, into a plurality of even demultiplexed channels

1112 and odd demultiplexed channels 1114. The demultiplexed channels 1112, 1114 may be saved in channel alignment memory 1138A, 1138B. The alignement memory 1138A, 1138B may be implemented as ping-pong block RAMs. In one embodiment, the alignment memory 1138A₁ 1138B performs channel reorder, assigning each channel to its matching frequency. Unused channels may be set to zero.

[0089] A first Fourier transform module 1120 may retrieve even channels 1118 from a channel alignment memory 1138A. In addition, a second Fourier transform 1122 retrieves odd channels 1118 from memory 1138B. Each of the Fou er transform modules 1120, 1122 performs an inverse Fourier transform on 128 input channels 1116, 1118. The transform modules 1120, 1122 may operate in bursts. As such, memory may be inserted before the transform modules 1120, 1122 (i.e., channel alignment memory 1138A, 1138B) and after the nodules 1120, 1122 (e.g. an FFT store 1124A, 1124B). The FFT store memory 1124A, 1124B may also be implemented as ping-pong block RAMs. [0090] In one embodiment, a first FFT channel filtering module 1126A and a second FFT channel filtering module 1126B shape the spectrum of each multiplexed channel stored in the FFT stores 1124A₁ 1124B. The Fourier transform modules 1120, 1122 may upsample the input signal 128 times. As such , FFT filtering may be performed with 1:128 upsampling by the channel filtering modules 1126A, 1126B. The filter bandwidth may be selected according to the widest expected spectrum of a final FDM modulated signal. [0091] The outputs 1136, 1130 of the filtering modules 1126A, 1126B may represent FDM signals with 586 kHz spacing between two adjacent channels. As previously explained, in order to interleave the output signals 1136, 1130, the second output 1130 (that includes odd number channels) is shifted by 293 kHz. Shifting may be accomplished by the upconverter 1128, which performs complex multiplication of the second output signal 1130 and a unit signal (not shown) rotating at 293 kHz. The unit signal may be generated by two look-up tables (not shown) with cosine and sine samples at 293 kHz. The first and second outputs 1136, 1130 may be added 132 to form a single 200 channel baseband FDM 1134 signal. The 200 channel baseband FDM signal may be frequency shifted to the 20-80 MHz band.

[0092] In one embodiment, in order to frequency shift the 200 channel baseband FDM signal 1134, the sample rate may be increased by a factor of three. Data signals may be registered in order to cross from a clock domain of 150 MHz to 225 MHz. The output of the 150 MHz clock domain may be registered twice, with a throughput of two cycles per sample. The signal may also be read at the 225 MHz clock domain and registered twice in order to prevent level ambiguity.

[0093] Once the clock domain is crossed from 150 MHz to 225 MHz, the baseband FDM signal 1134 may be passed to a 1:3 upsampler that represents an upsampling filter operating at 225 MHz. The 1:3 upsampler may be implemented as a direct FIR filter with multiple filter banks. After the signal has been upsampled, an upconverter may upconvert (or shift) the 200 channels of the baseband FDM signal 1134 from baseband to the desired radio frequency (RF) band. The shift value may represent the frequency of the 100th channel in the baseband FDM signal 1134.

[0094] Figure 12 is a flow diagram illustrating one embodiment of a method 1200 for simultaneously transmitting a plurality of frequency multiplexed channels. In one configuration, the method 1200 may simultaneously transmit up to 200 radio channels. The method 1200 may be implemented by a digital modulation system, such as the modulator 102 described herein. [0095] In one embodiment, a plurality of multimedia channels may be received 1202. The channels may be received 1202 from one or more satellites. The multimedia channels may include audio, video, or any other type of multimedia data. The plurality of multimedia channels may be decoded 1204 and each of the channels may be modulated 1206 as described herein. A waveform may be generated to simultaneously transmit each of the modulated channels 1208. In one embodiment, the waveform is used to transmit 1208 the modulated channels through an analog cable infrastructure. [OO 6] Figure 13 illustrates various components that may be used in a computing device 1302. One or more computing devices 1302 may be used to implement the various systems and methods described herein. The illustrated components may be located within the same physical structure or in separate housings or structures. Thus, the term computer or computer system is used to mean one or more broadly defined computing devices 1302 unless it is expressly stated otherwise. Computing devices 1302 include the broad range of digital computers including microcontrollers, hand-held computers, personal computers, servers, mainframes, supercomputers, minicomputers, workstations, and any variation or related device thereof. The computing device 1302 may include a digital modulation system, such as the modulator 102 described herein. [0097] The computing device 1302 may include a processor 1304 which controls operation of the computing device 1302. The processor 1304 may also be referred to as a central processing unit (CPU). Memory 1306, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 1304. A portion of the memory 1308 may also include non-volatile random access memory (NVRAM). The processor 1304 typically performs logical and arithmetic operations based on program instructions stored within the memory 1306. The instructions in the memory 1306 may be executable to implement the methods described herein. [0098] The computing device 1302 may also include a housing 1308 that may include a transmitter 1310 and a receiver 1312 to allow transmission and reception of data between the computing device 1302 and a remote location. The transmitter 1310 and receiver 1312 may be combined into a transceiver 1314. An antenna 1316 may be attached to the housing 1308 and electrically coupled to the transceiver 1314. The computing device 1302 may also include (not shown) multiple transmitters, multiple receivers, multiple transceivers and/or multiple antenna.

[0099] The computing device 1302 may also include a signal detector 1318 that may be used to detect and quantify the level of signals received by the transceiver 1314. The signal detector 1318 may detect such signals as total energy, pilot energy per pseudonoise (PN) chips, power spectral density, and other signals. The computing device 1302 may also include a digital signal processor (DSP) 1320 for use in processing signals.

[00100] The various components of the computing device 1302 may be coupled together by a bus system 1322 which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, the various busses are illustrated in FIG. 13 as the bus system 1322. Figure 13 illustrates only one possible configuration of a computing device 1302. Various other architectures and components may be used.

[100101] As used herein, the term "determining" encompasses a wide variety of actions and, therefore, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, "determining" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, "determining" can include resolving, selecting, choosing, establishing and the like. [00102] The phrase "based on" does not mean "based only on," unless expressly specified otherwise. In other words, the phrase "based on" describes both "based only on" and "based at least on."

[00103] The various illustrative logical blocks, modules and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSF and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core or any other such configuration. [00104] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs and across multiple storage media. An exemplary storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. [00105] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is required for proper operation of the embodiment that is being described, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. [00106] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions on a computer-readable medium. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. [00107] Software or instructions may also be transmitted over a transmission medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL₁ or wireless technologies such as infrared, radio, and microwave are included in the definition of transmission medium. [00108] Functions such as executing, processing, performing, running, determining, notifying, sending, receiving, storing, requesting, and/or other functions may include performing the function using a web service. Web services may include software systems designed to support interoperable machine-to-machine interaction over a computer network, such as the Internet. Web services may include various protocols and standards that may be used to exchange data between applications or systems. For example, the web services may include messaging specifications, security specifications, reliable messaging specifications, transaction specifications, metadata specifications, XML specifications, management specifications, and/or business process specifications. Commonly used specifications like SOAP, WSDL, XML, and/or other specifications may be used. [00109] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the systems, methods, and apparatus described herein without departing from the scope of the claims. [00110] What is claimed is:

Claims

1. A method for simultaneously transmitting a plurality of frequency multiplexed channels, comprising: receiving a plurality of multimedia channels; decoding the multimedia channels; modulating, digitally, the multimedia channels; and transmitting, simultaneously, the modulated channels through an analog cable infrastructure.

2. The method of claim 1, further comprising modulating the multimedia channels in a continuous frequency band.

3. The method of claim 2, wherein the continuous frequency band comprises 18 Megahertz (MHz) to 80 MHz.

4. The method of claim 1 , wherein the multimedia channels are audio radio channels received from satellites.

5. The method of claim 1 , wherein the multimedia channels are video channels received from satellites.

6. The method of claim 1 , wherein receiving a plurality of multimedia channels comprises receiving serial pulse-code modulation (PCM) streams of radio channels.

7. The method of claim 6, further comprising receiving the PCM streams of radio channels at a frequency rate of 48 kilohertz (kHz).

8. The method of claim 6, further comprising organizing the received PCM streams of radio channels as a multiple time division multiplexed (TDM) stream.

9. The method of claim 8, further comprising converting the TDM stream into a frequency division multiplexed (FDM) stream at a baseband frequency.

10. The method of claim 9, further comprising shifting the frequency of the FDM stream to a frequency band of 20 MHz to 80 MHz.

11. A digital modulation device that is configured to simultaneously transmit a plurality of frequency multiplexed channels, the digital modulation device comprising: a processor; memory in electronic communication with the processor; instructions stored in the memory, the instructions being executable to: receive a plurality of multimedia channels; decode the multimedia channels; modulate, digitally, the multimedia channels; and transmit, simultaneously, the modulated channels through an analog cable infrastructure.

12. The device of claim 11, wherein the instructions are further executable to modulate the multimedia channels in a continuous frequency band.

13. The device of claim 12, wherein the continuous frequency band comprises 18 Megahertz (MHz) to 80 MHz.

14. The device of claim 11, wherein the multimedia channels are audio radio channels received from satellites.

15. The device of claim 11, wherein the multimedia channels are video channels received from satellites.

16. The device of claim 11, wherein the instructions are further executable to receiver serial pulse-code modulation (PCM) streams of radio channels.

17. The device of claim 16, wherein the instructions are further executable to receive the PCM streams of radio channels at a frequency rate of 48 kilohertz (kHz).

18. The device of claim 16, wherein the instructions are further executable to organize the received PCM streams of radio channels as a multiple time division multiplexed (TDM) stream.

19. The device of claim 18, wherein the instructions are further executable to convert the TDM stream into a frequency division multiplexed (FDM) stream at a baseband frequency.

20. A computer-readable medium comprising executable instructions for: receiving a plurality of multimedia channels; decoding the multimedia channels; modulating, digitally, the multimedia channels; and transmitting, simultaneously, the modulated channels through an analog cable infrastructure.