WO2009032488A1 - Improved low k porous sicoh dielectric and integration with post film formation treatment - Google Patents

Improved low k porous sicoh dielectric and integration with post film formation treatment Download PDF

Info

Publication number
WO2009032488A1
WO2009032488A1 PCT/US2008/072955 US2008072955W WO2009032488A1 WO 2009032488 A1 WO2009032488 A1 WO 2009032488A1 US 2008072955 W US2008072955 W US 2008072955W WO 2009032488 A1 WO2009032488 A1 WO 2009032488A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric film
dielectric
pores
groups
layer
Prior art date
Application number
PCT/US2008/072955
Other languages
French (fr)
Inventor
Stephen M. Gates
Alfred Grill
Son Nguyen
Satyanarayana V. Nitta
Thomas M. Shaw
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/846,182 external-priority patent/US20090061237A1/en
Priority claimed from US11/846,250 external-priority patent/US20090061649A1/en
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO2009032488A1 publication Critical patent/WO2009032488A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor dielectric film as well as a method of fabricating such a film. More particularly, the present invention relates to a porous dielectric material comprising atoms of at least Si, C, O and H (hereinafter p-SiCOH dielectric) which has a low dielectric constant (k of about 2.7 or less), enhanced post processing stability and improved film properties as compared with prior art p-SiCOH dielectrics. The present invention also relates to a method of fabricating such a p-SiCOH dielectric as well as the use of the same as a dielectric in various semiconductor structures, including, for example, interconnect structures.
  • p-SiCOH dielectric porous dielectric material comprising atoms of at least Si, C, O and H
  • VLSI very large scale integration
  • ULSI chips are carried out by plasma enhanced chemical or physical vapor deposition techniques.
  • PECVD plasma enhanced chemical vapor deposition
  • Such low k dielectrics are also referred to as C doped oxides or organosilicate glass (OSG).
  • porous SiCOH For porous SiCOH (“p-SiCOH”) dielectrics, post treatment in oxidizing ambients (including, for example, oxygen and water) increases the film's stress by increasing the formation of tetrahedral strain.
  • the increased tetrahedral strain is caused by increased Si-O- Si bonding in the p-SiCOH dielectric film.
  • the formation of Si-O-Si bonding is increased in such dielectric films by the presence of Si-OH and Si-H bonding in the as-deposited film or after performing a high-energy (including, for example, ultra-violet (UV), electron-beam (E- beam) and/or thermal) post deposition treatment step.
  • a high-energy including, for example, ultra-violet (UV), electron-beam (E- beam) and/or thermal
  • Si-OH and Si-H bonds in p-SiCOH films are readily oxidized by oxygen and water in an ambient to form Si-O-Si bonding due to a low activation energy needed for the formation of such Si-O-Si bonding.
  • p-SiCOH dielectrics become more porous with lower k values, the surface area and the absorption of oxygen/water increase significantly and become more susceptible to oxidation thus forming an increased number of strained Si-O-Si bonds to be present in the dielectric film.
  • the formation of Si-O-Si bonds increases the film's stress and crack velocity to levels which are not acceptable in semiconductor interconnect structures.
  • a p-SiCOH dielectric film in which the film's stress and crack velocity are not significantly increased as compared to prior art p- SiCOH dielectrics. That is, a p-SiCOH dielectric film is needed in which the content of Si-O- Si bonding in the film is decreased by decreasing the content of Si-OH and Si-H bonding in the p-SiCOH dielectric film.
  • the present invention provides a porous SiCOH (p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized.
  • the inventive porous SiCOH dielectric film has less Si-O-Si bonding as compared to prior art p- SiCOH dielectric films.
  • a stable p-SiOCH dielectric film is provided in which the amount of Si-OH (silanol) and/or Si-H groups at least within the pores has been reduced to about 0.01 atomic % or less.
  • the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films.
  • a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking -(CH x )- chains wherein x is 1, 2 or 3 therein.
  • the inventive dielectric film comprises elements of Si, C, H and O, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pores, wherein said multiplicity of nano-sized pores include additional crosslinking -(CH x )- chains, wherein x is 1, 2 or 3 that bond with at least one Si bond that originated from the reaction between a post treatment double bond precursor with some of the Si-OH groups and/or Si-H groups (i.e., Si bonding groups) normally present in said pores prior to the treatment.
  • the inventive dielectric film typically has a hydrocarbon content (saturated and unsaturated) within said pores and on a surface thereof that is from about 0.1 to about 10 wt. %, with a hydrocarbon content in the range from about 0.5 to about 2 wt. % being more typical.
  • the inventive dielectric film can be further characterized as having more branching C-group bonding -(CH x )- chains, wherein x is 1, 2 or 3 on the surface and within the pores as compared with prior art p-SiCOH dielectric materials.
  • the increased branching C-group bonding can be evidenced by additional hydrocarbon (on the order of about 1 atomic % C or higher) being presented in the film, as measured by Electron Spectroscopy for Chemical Analysis (ESCA), Rutherford Back Scattering (RBS), Time-of-Flight Secondary Ion Mass Spectroscopy (TOF SIMS), or FTIR as measured of carbon concentration or C-H bonding change before and after post-treatment.
  • ESA Electron Spectroscopy for Chemical Analysis
  • RBS Rutherford Back Scattering
  • TOF SIMS Time-of-Flight Secondary Ion Mass Spectroscopy
  • FTIR measured of carbon concentration or C-H bonding change before and after post-treatment.
  • the -(CH x )- chains are also present on the surface of the film as well as within the pores.
  • the presence of these chains on the surface of the dielectric film provides a film that is less sensitive to moisture as compared with prior art films not including the -(CH x )- chains since the presence of the -(CH x )- chains on the surface of the dielectric material removes the silanol groups (i.e., Si-OH) present on the surface of the dielectric film.
  • the inventive p-SiCOH dielectric film is more hydrophobic than prior art SiCOH dielectric films.
  • the present invention also provides a method of forming such a p-SiCOH dielectric film.
  • the applicants have determined that one can reduce or minimize the stress change and make the p-SiCOH dielectric film more stable and more hydrophobic by selecting an appropriate annealing ambient that has the ability to reduce oxidation of the dielectric film and thus minimize or reduce the formation of Si-OH (and to a lesser extent Si-H) groups on the surface of the dielectric film.
  • the present invention it has been determined that by annealing in an ambient that includes a gas that contains at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond produces the inventive p-SiCOH dielectric film.
  • the bonding formation utilizing such an ambient gas produces flexible and stabilized crosslinking -(CH x )- chains at least within the pores of the SiCOH dielectric film. Subsequently, the film stress will be reduced and the film's stability will be improved.
  • the presence of the at least one C- C double bond and/or the at least one C-C triple bond in the annealing ambient also minimizes the impact of residual oxygen in the ambient during annealing and reduces/eliminates the formation of Si-OH and/or Si-H bonding on the surface of the dielectric film forming various bridging bonds.
  • the inventive method comprises:
  • forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pore;
  • the -(CH x )- chains bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups and Si-H groups originally present in said pores.
  • the annealing step may include a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal and/or a microwave anneal.
  • UV ultraviolet
  • the pores contain the bonding Si-OH groups and/or the Si-H groups prior to the annealing step.
  • these bonding groups are generated during initial stages of said annealing process during pore formation and then they are removed during subsequent stages of the annealing process.
  • the gaseous ambient employed in the annealing step is an unsaturated hydrocarbon.
  • the gaseous ambient comprises a compound having an organosilicon group (Rl, R2, R3)-Si-OH with silanol group bonding wherein Rl, R2, R3 are identical or different and are a hydrocarbon, vinyl or diene radical.
  • the annealing in the aforementioned gaseous ambient occurs during a high-energy post deposition processing step that removes labile organic groups thus forming a porous dielectric material.
  • the annealing in the above gaseous ambient may occur after a high energy post deposition processing step that removes the labile organic groups.
  • the treating in the aforementioned ambient may occur during and after a high-energy post deposition processing step that removes the organic labile groups.
  • the annealing step of the present invention reduces both Si-OH and Si-H bond formation within the pores and on the surface of the p-SiCOH film, increases the film's hydrophobicity, enhances the films stability and reduces the film's stress by reducing the formation of Si-O-Si crosslinking bonds.
  • the present invention also relates to electronic structures, in which the p-SiCOH dielectric film of the present invention may be used as an interconnect (i.e., interlevel or intralevel) dielectric, a capping layer, and/or as a hard mask/polish-stop layer.
  • interconnect i.e., interlevel or intralevel
  • the electronic structures of the present invention include a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, the second layer of insulating material being in intimate contact with the first layer of insulating material, the first region of conductor being in electrical communication with the first region of metal, and a second region of conductor being in electrical communication with the first region of conductor and being embedded in a third layer of insulating material, the third layer of insulating material being in intimate contact with the second layer of insulating material.
  • each of the insulating layers can comprise the inventive p-SiCOH dielectric film which has a reduced content of Si-O-Si bonding.
  • the electronic structure may further include a dielectric cap layer situated in-between the first layer of insulating material and the second layer of insulating material, and may further include a dielectric cap layer situated in-between the second layer of insulating material and the third layer of insulating material.
  • the electronic structure may further include a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material.
  • the dielectric cap itself can comprise the inventive p-SiCOH dielectric film.
  • the electronic structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layer of insulating material.
  • the electronic structure may further include a dielectric layer on top of the second layer of insulating material for use as a RIE hard mask/polish-stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask/polish-stop layer.
  • the electronic structure may further include a first dielectric RIE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RIE diffusion barrier layer on top of the first dielectric polish-stop layer a second dielectric RIE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer.
  • the dielectric RIE hard mask/polish-stop layer may be comprised of the inventive p-SiCOH dielectric film as well.
  • the present invention also relates to the use of the inventive SiCOH dielectric film in other electronic structures including a structure including at least two conductors and an optoelectronic sensing structure, for use in detection of light.
  • FIGS. 1A-1C are pictorial representations (through cross sectional views) depicting the basic processing steps in which a p-SiCOH dielectric film having reduced Si-OH content and thus reduced Si-O-Si bonding is formed on a surface of a substrate.
  • FIG. 2 is an enlarged, cross-sectional view of an electronic device of the present invention that includes the inventive p-SiCOH dielectric film as both the intralevel dielectric layer and the interlevel dielectric layer.
  • FIG. 3 is an enlarged, cross-sectional view of the electronic structure of FIG. 2 having an additional diffusion barrier dielectric cap layer deposited on top of the inventive p-SiCOH dielectric film.
  • FIG. 4 is an enlarged, cross-sectional view of the electronic structure of FIG. 3 having an additional RIE hard mask/polish-stop dielectric cap layer and a dielectric cap diffusion barrier layer deposited on top of the polish-stop layer.
  • FIG. 5 is an enlarged, cross-sectional view of the electronic structure of FIG. 4 having additional RIE hard mask/polish-stop dielectric layers deposited on top of the p-SiCOH dielectric film of the present invention.
  • FIG. 6 is a pictorial representation (through a cross sectional view) illustrating an electronic structure including at least two conductors and the inventive p-SiCOH dielectric material.
  • FIGS. 7A-7B are pictorial representations (through cross sectional views) illustrating electronic structures including a sensing element and the inventive p-SiCOH dielectric material.
  • the present invention which describes a p-SiCOH dielectric film having a reduced content of Si-OH and Si-H bondings, and increased -(CH x )- bondings within the pores and on the surface of the film, a method of fabricating the same and electronic structures containing the inventive p-SiCOH dielectric film, will now be described in greater detail.
  • a SiCOH dielectric film 12 is formed on a surface of a substrate 10 such as shown, for example, in FIG. IA.
  • substrate when used in conjunction with substrate 10 includes, a semiconducting material, an insulating material, a conductive material or any combination thereof, including multilayered structures.
  • substrate 10 may be a semiconducting material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors.
  • the semiconductor substrate 10 may also include a layered substrate such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on- insulators (SGOIs).
  • a layered substrate such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on- insulators (SGOIs).
  • the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers.
  • the substrate 10 is a conductive material
  • the substrate 10 may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal suicide, a metal nitride and combinations thereof, including multilayers.
  • the substrate 10 includes a combination of a semiconducting material and an insulating material, a combination of a semiconducting material and a conductive material or a combination of a semiconducting material, an insulating material and a conductive material.
  • An example of a substrate that includes a combination of the above is an interconnect structure.
  • the SiCOH dielectric film 12 is typically deposited using plasma enhanced chemical vapor deposition (PECVD). In addition to PECVD, the present invention also contemplates that the SiCOH dielectric film 12 can be formed utilizing chemical vapor deposition (CVD), high-density plasma (HDP) deposition, pulsed PECVD, spin-on application, or other related methods.
  • the thickness of the SiCOH dielectric film 12 deposited may vary; typical ranges for the deposited SiCOH dielectric film 12 are from about 50 nm to about 1 ⁇ m, with a thickness from 100 to about 500 nm being more typical.
  • the SiCOH dielectric film is deposited using the processing techniques disclosed in co-assigned U.S. Patent Nos. 6,147,009, 6,312,793, 6,441,491, 6,437,443, 6,541,398, 6,479,110 B2, and 6,497,963 as well as in U.S. Patent Application Publication Nos. 2005/0156285 Al, 2005/0245096 Al, 2005/ 0194619 Al and 2006/0165891 Al, the contents of each of which are incorporated herein by reference.
  • the SiCOH dielectric film 12 is formed by providing at least a first precursor (liquid, gas or vapor) comprising atoms of Si, C, O, and H, and an inert carrier such as He or Ar, into a reactor, preferably the reactor is a PECVD reactor, and then depositing a film derived from said first precursor onto a suitable substrate utilizing conditions that are effective in forming a SiCOH dielectric material.
  • a first precursor liquid, gas or vapor
  • an inert carrier such as He or Ar
  • the present invention yet further provides for mixing the first precursor with an oxidizing agent such as O 2 , CO 2 or a combination thereof, thereby stabilizing the reactants in the reactor and improving the uniformity of the SiCOH dielectric film 12 deposited on the substrate 10.
  • a second precursor gas, liquid or vapor
  • a third precursor gas, liquid or gas
  • Ge may also be used.
  • the first precursor is selected from silane (SiH 4 ) derivatives having the molecular formula SiRR'R"R'" where R,R',R", and R'" may or may not be identical and are selected from H, alkyl, and alkoxy, preferably methyl, ethyl, methoxy, and ethoxy.
  • Preferred precursors include: diethoxydimethylsilane, diethoxymethylsilane (DEMS), ethoxyltrimethylsilane, ethoxydimethylsilane, dimethoxydimethylsilane, dimethoxymethylsilane, triethoxysilane, and trimethoxymethylsilane.
  • the first precursor is selected from organosilicon molecules with ring structures comprising SiCOH components such as 1, 3, 5, 7-tetramethylcyclotetrasiloxane ("TMCTS” or “C 4 Hi 6 O 4 Si 4 "), and octamethylcyclotetrasiloxane (OMCTS).
  • TCTS 1, 3, 5, 7-tetramethylcyclotetrasiloxane
  • O 4 Si 4 octamethylcyclotetrasiloxane
  • the second precursor employed in the present application is an organic compound that is selected from:
  • R , R , R 3 , R 4 , R 5 and R may or may not be identical and are selected from hydrogen, alkyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. Additionally, other atoms such as S, Si, or other halogens may be contained in the second precursor molecule.
  • ethylene oxide propylene oxide, cyclopentene oxide, isobutylene oxide, 2,2,3-trimethyloxirane, butadienemonoxide, bicycloheptadiene (BCHD), l,2-epoxy-5-hexene, 2-methyl-2-vinyloxirane, 1-isopropyl- cyclohexa-l,3-diene and tertbutylmethylether.
  • the second precursor may be selected from the group consisting of hydrocarbon molecules with ring structures, preferably with more than one ring present in the molecule or with branched chains attached to the ring.
  • species containing fused rings at least one of which contains a heteroatom, preferentially oxygen.
  • the most suitable are those that include a ring of a size that imparts significant ring strain, namely rings of 3 or 4 atoms and/or 7 or more atoms.
  • molecules containing branched tertiary butyl (t- butyl) and isopropyl (i-propyl) groups attached to a hydrocarbon ring; the ring may be saturated or unsaturated (containing C C double bonds).
  • the above second precursors include labile functional groups that can be readily removed from the dielectric film during a subsequent processing (i.e., curing) step.
  • a separate porogen material can be added during the formation of the p-SiCOH dielectric film.
  • the third precursor which can optionally be used is formed from germane hydride or any other reactant comprising a source of Ge.
  • the SiCOH film 12 may be deposited using a method the includes the step of providing a parallel plate reactor, which has a conductive area of a substrate chuck between about 85 cm 2 and about 1600 cm 2 , and a gap between the substrate and a top electrode between about 1 cm and about 12 cm.
  • a high frequency RF power is applied to one of the electrodes at a frequency from about 0.45 MHz to about 200 MHz.
  • an additional low frequency power can be applied to one of the electrodes.
  • the conditions used for the deposition step may vary depending on the desired final dielectric constant of the SiCOH dielectric film 12.
  • the conditions used for providing a stable dielectric material comprising elements of Si, C, O, H that has a dielectric constant of about 2.7 or less include: setting the substrate temperature at a temperature from about 200 0 C to about 425 0 C; setting the high frequency RF power density within a range from about 0.1 W/cm 2 to about 1.5 W/cm 2 ; setting the first liquid precursor flow rate within a range from about 100 mg/min to about 5000 mg/min, optionally setting the second liquid precursor flow rate within a range from about 50 mg/min to about 10,000 mg/min; optionally setting the third liquid precursor flow rate within a range from about 25 mg/min to about 4000 mg/min; optionally setting the inert carrier gases such as helium (or/and argon) flow rate within a range from about 50 seem to about 5000 seem; setting the reactor pressure at a pressure within a range from about 1000
  • an ultra low frequency power may be added to the plasma within a range from about 30 W to about 400 W.
  • the RF power applied to the substrate chuck may also change by a factor of X.
  • an oxidizing agent When employed in the present invention, it is flown into the PECVD reactor at a flow rate within a range from about 10 seem to about 1000 seem.
  • organosilicon gas phase precursors such as trimethylsilane
  • the organosilicon gas phase precursors such as trimethylsilane
  • the dielectric film 12 formed at this point of the present invention contains a matrix of a hydrogenated oxidized silicon carbon material (SiCOH) comprising atoms of Si, C, O and H in a covalently bonded tri-dimensional network and having a dielectric constant of not more than about 3.6 prior to curing. After UV or E-beam curing, the film will have some pores and the dielectric constant of the film is about 2.7 or less.
  • the tri-dimensional network may include a covalently bonded tri-dimensional structure comprising Si-O, Si-C, Si-H, C-H and C-C bonds.
  • the dielectric film 12 may comprise F and N and may optionally have the Si atoms partially substituted by Ge atoms.
  • the deposited film is subjected to a high energy post deposition processing step that forms a porous SiCOH dielectric film 12' (See FIG. IB).
  • the as deposited film can be processed using a high energy source to stabilize the film, remove labile functional groups and improve its properties (electrical, mechanical, adhesive).
  • Suitable energy sources that can be used for the post processing step include thermal, chemical, ultraviolet (UV) light, electron beam (E-beam), microwave, and plasma. Combinations of the aforementioned energy sources can also be used in the present invention.
  • the thermal energy source includes any source such as, for example, a heating element or a lamp, that can heat the deposited dielectric material to a temperature from about 300° to about 500 0 C. More preferably, the thermal energy source is capable of heating the deposited dielectric material to a temperature from about 350° to about 43O 0 C.
  • This thermal treatment process can be carried out for various time periods, with a time period from about 1 minute to about 300 minutes being typical.
  • the thermal treatment step is typically performed in the presence of an inert gas such as He and Ar.
  • the thermal treatment step may include a rapid thermal anneal, a furnace anneal, a laser anneal or a spike anneal.
  • the UV light treatment step is performed utilizing a source that can generate light having a wavelength from about 500 to about 150 nm, to irradiate the substrate while the wafer temperature is maintained at a temperature from about 25° to about 500 0 C, with temperatures from about 300° to about 450 0 C being preferred. Radiation with less than 370 nm is of insufficient energy to dissociate or activate important bonds, so the wavelength range 150-370 nm is a preferred range. Using literature data and absorbance spectra measured on as deposited films, the inventors have found that less than 170 nm radiation may not be favored due to degradation of the SiCOH film.
  • the energy range 310-370 nm is less useful than the range 150-310 nm, due to the relatively low energy per photon from 310-370 nm.
  • optimum overlap with the absorbance spectrum of the as deposited film and minimum degradation of the film properties may be optionally used to select a most effective region of the UV spectrum for changing the SiCOH properties.
  • the electron beam treatment step is performed utilizing a source that is capable of generating a uniform electron flux over the wafer, with energies from about 0.5 to about 25 keV and current densities from about 0.1 to about 100 micro Amp/cm 2 (preferably about 1 to about 5 microAmp/cm 2 ), while the wafer temperature is maintained at a temperature from about 25° to about 500 0 C, with temperatures from about 300° to about 45O 0 C being preferred.
  • the preferred dose of electrons used in the electron beam treatment step is from about 50 to about 500 microcoulombs/cm , with about 100 to about 300 microcoulombs/cm being most preferred.
  • the SiCOH dielectric film 12 after curing comprises between about 5 and about 40 atomic percent of Si; between about 5 and about 45 atomic percent of C; between 0 and about 60 atomic percent of O; and between about 10 and about 55 atomic percent of H.
  • the SiCOH dielectric film 12 is thermally stable above 350°C .
  • the SiCOH film 12 preferably has a thickness of not more than 1.3 micrometers and a crack propagation velocity in water of less than 10 "9 meters per second.
  • the inventive second post treatment including either plasma, thermal, UV or E-beam in an ambient that includes a gas that contains at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond is used.
  • thermal treatment including annealing at a temperature range from about 300° to about 45O 0 C for a duration from about 1 to about 120 minutes in an ambient gas that includes one of ethylene (C 2 H 4 ), acetylene (C 2 H 2 ), propylene (C 3 H 6 ), and butene (C 4 H 8 ) as well as an organic gas compound that is selected from one of the following formula:
  • R 1 , R 2 , R 3 , R 4 are either saturated hydrocarbon groups (-CH 3 , -C 2 H 5 , and etc.), or hydrogen can be used in the present invention.
  • the plasma treatment step which includes the above mentioned hydrocarbon gas including at least one C-C double bond and/or at least one C-C triple bond is performed utilizing a source that is capable of generating atomic hydrogen (H), and optionally CH 3 or other hydrocarbon radicals. Downstream plasma sources are preferred over direct plasma exposure.
  • the wafer temperature is maintained at a temperature from about 25° to about 500 0 C, with temperatures from about 300° to about 45O 0 C being preferred.
  • the plasma treatment step is performed by introducing a gas into a reactor that can generate a plasma and thereafter it is converted into a plasma.
  • the gas that can be used for the plasma treatment includes at least one of the above mentioned hydrocarbons containing at least one C-C double bond and/or at least one C-C triple bond and an inert gas such as Ar, N, He, Xe or Kr, with He being preferred; hydrogen or related sources of atomic hydrogen, methane, methylsilane, related sources OfCH 3 groups, and mixtures thereof.
  • the flow rate of the plasma treatment gas may vary depending on the reactor system being used.
  • the chamber pressure can range anywhere from about 0.05 to about 20 torr, but the preferred range of pressure operation is from about 1 to about 10 torr.
  • the plasma treatment step occurs for a period of time, which is typically from about Vi to about 10 minutes, although longer times may be used within the invention.
  • An RF or microwave power source is typically used to generate the above plasma.
  • the RF power source may operate at either the high frequency range (on the order of about 100 W or greater); the low frequency range (less than about 250 W) or a combination thereof may be employed.
  • the high frequency power density can range anywhere from about 0.1 to about 2.0 W/cm 2 but the preferred range of operation is from about 0.2 to about 1.0 W/cm 2 .
  • the low frequency power density can range anywhere from about 0.1 to about 1.0 W/cm 2 but the preferred range of operation is from about 0.2 to about 0.5 W/cm 2 .
  • the chosen power levels must be low enough to avoid significant sputter etching of the exposed dielectric surface (less than 5 nanometers removal).
  • UV and E-beam treatment processes it is possible to use the same hydrocarbon ambient (double and triple bond hydrocarbon gases) and temperature (about 200° to about 450 0 C range) as used in the thermal process.
  • first and second inventive post deposition processes into a single two-step post treatment process which includes 1) a first step post-treatment in inert ambient (Ar, He) to remove porogen and form pores, and 2) a second step post-treatment in the inventive double/triple bond hydrocarbon gases to removal any remain Si-H and Si-OH and to form cross-linking -(CH x )- bonding in the pores and film's surface
  • the above high energy first and second inventive post deposition processes provide a p-SiCOH dielectric film 12' on the surface of substrate 10.
  • the p-SiCOH dielectric film 12' has a multiplicity of nano-sized pores therein.
  • the nano-sized pores include at least one of Si-OH groups and Si-H groups therein.
  • the nano-sized pores have a pore size from about 0.3 to about 10 nm, with a pore size from about 0.8 to about 2 nm being more preferred.
  • the second post treatment step which is a separate step of treating the p-SiCOH dielectric film in a gaseous ambient that includes at least one C-C double bond, at least one C-C- triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, is employed after the high energy post deposition step.
  • treating in the aforementioned gaseous ambient occurs during the high energy post deposition step that removes labile organic groups that forms a porous dielectric material.
  • the treating in the aforementioned ambient may occur during and after the high energy post deposition treatment step that removes the organic labile groups.
  • FIG. 1C illustrates a treated p-SiCOH dielectric film 12" of the present invention.
  • the treating in the aforementioned ambient forms crosslinking -(CH x )- chains, wherein x is 1, 2, or 3 that bond with at least one Si-bonds, which originally came from Si-OH groups and Si-H groups also present in said pores before the post treatment.
  • the amount of Si-O-H and Si-H bonds within the pores of the dielectric film are reduced due to the reaction between the double and/or triple hydrocarbon gases with the Si- OH and Si-H in the pore.
  • the amount of Si-O-H and Si-H bonds on the surface of the dielectric film are also reduced and making the film hydrophobic.
  • the second annealing step may include a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal and/or a microwave anneal.
  • the conditions for each of the anneals is the same as mentioned above, expect that a gaseous ambient including at least one C-C- double and/or triple bond is employed.
  • the anneal ambient is an unsaturated hydrocarbon.
  • the unsaturated hydrocarbon contains from about 2 to about 24, preferably 2 to 5, carbon atoms.
  • the carbon atoms may be straight chained or branched.
  • suitable unsaturated hydrocarbons include, but are not limited to ethylene, propylene, butylene, ethane, butane, and acetylene.
  • the annealing ambient comprises a compound having an organosilicon group (R) 3 -Si-OH with one silanol group bonding wherein R is the same or different and is a saturated hydrocarbon, or vinyl or diene group.
  • organosilanes include, but are not limited to divinyl methyl silanol, and diethyl vinyl silanol.
  • the above ambients may be used alone or mixed together or used in the presence of another gas including an inert gas such as Ar, and/or He.
  • the amount of gaseous ambient including at least one C-C double/triple bond present during the annealing ambient may vary depending on the type of annealing process used, as well as the surface area of the p-SiCOH dielectric being annealed.
  • the annealing ambient pressure typically ranges from about 1 torr to about 760 torr, and the preferred range is from about 5 to about 100 torr.
  • the flow rates of the hydrocarbon gases range from about 10 to about 1000 seem for the ambient employed.
  • the annealing step of the present invention reduces both Si-OH and Si-H bond formation within the pores and on the surface of the p-SiCOH film, increases the film's hydrophobicity, enhances the films stability and reduces the film's stress by crosslinking Si- R-Si bonding formation.
  • FIGS. 2-7B Electronic devices which can contain the inventive p-SiCOH dielectric film are shown in FIGS. 2-7B. It should be noted that the devices shown in FIGS. 2-7B are merely illustrative examples of the present invention, while an infinite number of other devices may also be formed by the present invention novel methods.
  • an electronic device 30 built on a silicon substrate 32 is shown.
  • an insulating material layer 34 is first formed with a first region of metal 36 embedded therein.
  • a p-SiCOH dielectric film 38 of the present invention is formed on top of the first layer of insulating material 34 and the first region of metal 36.
  • the first layer of insulating material 34 may be suitably formed of silicon oxide, silicon nitride, doped varieties of these materials, or any other suitable insulating materials.
  • the p-SiCOH dielectric film 38 is then patterned in a photolithography process followed by etching and a conductor layer 40 is deposited thereon.
  • a second layer of the inventive p-SiCOH film 44 is formed by a overlying the first p-SiCOH dielectric film 38 and the first conductor layer 40.
  • the conductor layer 40 may be a deposit of a metallic material or a nonmetallic conductive material. For instance, a metallic material of aluminum or copper, or a nonmetallic material of nitride or polysilicon.
  • the first conductor 40 is in electrical communication with the first region of metal 36.
  • a second region of conductor 50 is then formed after a photolithographic process on the p-SiCOH dielectric film 44 is conducted followed by etching and then a deposition process for the second conductor material.
  • the second region of conductor 50 may also be a deposit of either a metallic material or a nonmetallic material, similar to that used in depositing the first conductor layer 40.
  • the second region of conductor 50 is in electrical communication with the first region of conductor 40 and is embedded in the second layer of the SiCOH dielectric film 44.
  • the second layer of the p-SiCOH dielectric film 44 is in intimate contact with the first layer of p-SiCOH dielectric material 38.
  • the first layer of the p-SiCOH dielectric film 38 is an intralevel dielectric material
  • the second layer of the p-SiCOH dielectric film 44 is both an intralevel and an interlevel dielectric. Based on the low dielectric constant of the inventive p-SiCOH dielectric films, superior insulating property can be achieved by the first insulating layer 38 and the second insulating layer 44.
  • FIG. 3 shows a present invention electronic device 60 similar to that of electronic device 30 shown in FIG. 2, but with an additional dielectric cap layer 62 deposited between the first insulating material layer 38 and the second insulating material layer 44.
  • the dielectric cap layer 62 can be suitably formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-nitride (SiCN), silicon carbo-oxide (SiCO), Silicon Carbo-oxynitride (SiCON) and their hydrogenated compounds.
  • the additional dielectric cap layer 62 functions as a diffusion barrier layer for preventing diffusion of the first conductor layer 40 into the second insulating material layer 44 or into the lower layers, especially into layers 34 and 32.
  • FIG. 4 Another alternate embodiment of the present invention electronic device 70 is shown in FIG. 4.
  • two additional dielectric cap layers 72 and 74 which act as a RIE mask and CMP (chemical mechanical polishing) polish stop layer are used.
  • the first dielectric cap layer 72 is deposited on top of the first low k insulating material layer 38 and used as a RIE mask and CMP stop, so the first conductor layer 40 and layer 72 are approximately co-planar after CMP.
  • the function of the second dielectric layer 74 is similar to layer 72, however layer 74 is utilized in planarizing the second conductor layer 50.
  • the polish stop layer 74 can be deposited of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-oxide (SiCO), Silicon Carbo- oxynitride (SiCON) and their hydrogenated compounds.
  • a preferred polish stop layer composition is SiCH or SiCOH for layers 72 or 74.
  • the SiCOH layer may include the inventive p-SiCOH dielectric film.
  • a second dielectric layer can be added on top of the second p-SiCOH dielectric film 44 for the same purposes.
  • FIG. 5 Still another alternate embodiment of the present invention electronic device 80 is shown in FIG. 5.
  • an additional layer 82 of dielectric material is deposited and thus dividing the second insulating material layer 44 into two separate layers 84 and 86.
  • the intralevel and interlevel dielectric layer 44 formed of the inventive p-SiCOH material is therefore divided into an interlayer dielectric layer 84 and an intralevel dielectric layer 86 at the boundary between via 92 and interconnect 94.
  • An additional diffusion barrier layer 96 is further deposited on top of the upper dielectric layer 74.
  • the additional benefit provided by this alternate embodiment electronic structure 80 is that dielectric layer 82 acts as an RIE etch stop providing superior interconnect depth control.
  • the composition of layer 82 is selected to provide etch selectivity with respect to layer 86.
  • Still other alternate embodiments may include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate which has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of the insulating material wherein the second layer of insulating material is in intimate contact with the first layer of insulating material, and the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, wherein the third layer of insulating material is in intimate contact with the second layer of insulating material, a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material and a second dielectric cap layer on top of the third layer of insulating material, wherein the first and the second dielectric cap layers are formed of a material that includes atoms of Si
  • Still other alternate embodiments of the present invention include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor that is in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, and a diffusion barrier layer formed of the dielectric film of the present invention deposited on at least one of the second and third layers of insulating material.
  • Still other alternate embodiments include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a reactive ion etching (RIE) hard mask/polish stop layer on top of the second layer of insulating material, and a diffusion barrier layer on top of the RIE hard mask/polish stop layer, wherein the RIE hard mask/polish stop layer and the diffusion barrier layer are formed of the p-SiCOH dielectric film of
  • Still other alternate embodiments include an electronic structure which has layers of insulating materials as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a first RIE hard mask, polish stop layer on top of the second layer of insulating material, a first diffusion barrier layer on top of the first RIE hard mask/polish stop layer, a second RIE hard mask/polish stop layer on top of the third layer of insulating material, and a second diffusion barrier layer on top of the second RIE hard
  • Still other alternate embodiments of the present invention includes an electronic structure that has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure similar to that described immediately above but further includes a dielectric cap layer which is formed of the p-SiCOH dielectric material of the present invention situated between an interlevel dielectric layer and an intralevel dielectric layer.
  • an electronic structure containing at least two metallic conductor elements (labeled as reference numerals 97 and 101) and a p-SiCOH dielectric material (labeled as reference numeral 98).
  • metal contacts 95 and 102 are used to make electrical contact to conductors 97 and 101.
  • the inventive p-SiCOH dielectric 98 provides electrical isolation and low capacitance between the two conductors.
  • the electronic structure is made using a conventional technique that is well known to those skilled in the art such as described, for example, in U.S. Patent No. 6,737,727, the entire content of which is incorporated herein by reference.
  • the at least two metal conductor elements are patterned in a shape required for a function of a passive or active circuit element including, for example, an inductor, a resistor, a capacitor, or a resonator.
  • the inventive p-SiCOH dielectric can be used in an electronic sensing structure wherein the optoelectronic sensing element (detector) shown in FIG. 7A or 7B is surrounded by a layer of the inventive SiCOH dielectric material.
  • the electronic structure is made using a conventional technique that is well known to those skilled in the art. Referring to FIG. 7 A, a p-i-n diode structure is shown which can be a high speed Si based photodetector for IR signals.
  • the n+ substrate is 110, and atop this is an intrinsic semiconductor region 112, and within region 112 p+ regions 114 are formed, completing the p-i-n layer sequence.
  • Layer 116 is a dielectric (such as SiO 2 ) used to isolate the metal contacts 118 from the substrate. Contacts 118 provide electrical connection to the p+ regions.
  • the entire structure is covered by the inventive SiCOH dielectric material, 120. This material is transparent in the IR region, and serves as a passivation layer.
  • FIG. 7B A second optical sensing structure is shown in FIG. 7B, this is a simple p-n junction photodiode, which can be a high speed IR light detector.
  • the metal contact to substrate is 122, and atop this is an n-type semiconductor region 124, and within this region p+ regions 126 are formed, completing the p-n junction structure.
  • Layer 128 is a dielectric (such as SiO 2 ) used to isolate the metal contacts 130 from the substrate. Contacts 130 provide electrical connection to the p+ regions.
  • the entire structure is covered by the inventive p-SiCOH dielectric material, 132. This material is transparent in the IR region, and serves as a passivation layer.

Abstract

A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more -(CHx) and less Si-O-H and Si-H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si-OH (silanol) and Si-H groups at least within the pores has been reduced by about 90 % or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking -(CHx)- chains wherein x is 1,2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C-C double bond and/or at least one C-C triple bond.

Description

IMPROVED LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
Field of the Invention
[0001] The present invention relates to a semiconductor dielectric film as well as a method of fabricating such a film. More particularly, the present invention relates to a porous dielectric material comprising atoms of at least Si, C, O and H (hereinafter p-SiCOH dielectric) which has a low dielectric constant (k of about 2.7 or less), enhanced post processing stability and improved film properties as compared with prior art p-SiCOH dielectrics. The present invention also relates to a method of fabricating such a p-SiCOH dielectric as well as the use of the same as a dielectric in various semiconductor structures, including, for example, interconnect structures.
Background of the Invention
[0002] The continuous shrinking in dimensions of electronic devices utilized in ultra large scale integrated (ULSI) circuits in recent years has resulted in increasing the resistance of the interconnect metallization as well as increasing the capacitance of the intralayer and interlayer dielectric. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) insulators, and particularly those with a dielectric constant significantly lower than silicon oxide, are needed to reduce the capacitance.
[0003] Most of the fabrication steps of very large scale integration ("VLSI") and ULSI chips are carried out by plasma enhanced chemical or physical vapor deposition techniques. The ability to fabricate a low k dielectric by a plasma enhanced chemical vapor deposition (PECVD) technique using previously installed and available processing equipment simplifies its integration in the manufacturing process, reduces manufacturing cost, and creates less hazardous waste. U.S. Patent Nos. 6,147,009 and 6,497,963 assigned to the common assignee of the present invention, which are incorporated herein by reference in their entirety, describe a low dielectric constant material consisting of elements of Si, C, O and H atoms having a dielectric constant not more than 3.6 and which exhibits very low crack propagation velocities. Such low k dielectrics are also referred to as C doped oxides or organosilicate glass (OSG).
[0004] U.S. Patent Nos. 6,312,793, 6,441,491 and 6,479,110 B2, assigned to the common assignee of the present invention and incorporated herein by reference in their entirety, describe a multiphase low k dielectric material that consists of a matrix composed of elements of Si, C, O and H atoms, a phase composed mainly of C and H and having a dielectric constant of not more than 3.2.
[0005] U.S. Patent Application Publication Nos. 2005/0156285 Al and 2005/0245096 Al, assigned to the common assignee of the present invention, and incorporated herein by reference in their entirety, describe means for improving the stability and/or physical properties such as tensile strength, elastic modulus, hardness cohesive strength and crack velocity in water of SiCOH dielectric materials.
[0006] U.S. Patent Application Publication Nos. 2005/0194619 Al and 2006/0165891 A, assigned to the common assignee of the present invention and incorporated herein by reference in their entirety, provide a low dielectric material with increased cohesive strength that includes atoms of Si, C, O and H, in which a fraction of the C atoms are bonded as Si- CH3 functional groups and another fraction of the C atoms are bonded as Si-R-Si, wherein R is phenyl, -(CH2)n- where n is greater than or equal to one, HC=CH, C=CH2, C≡C or a [S]n linkage wherein n is as defined above.
[0007] For porous SiCOH ("p-SiCOH") dielectrics, post treatment in oxidizing ambients (including, for example, oxygen and water) increases the film's stress by increasing the formation of tetrahedral strain. The increased tetrahedral strain is caused by increased Si-O- Si bonding in the p-SiCOH dielectric film. The formation of Si-O-Si bonding is increased in such dielectric films by the presence of Si-OH and Si-H bonding in the as-deposited film or after performing a high-energy (including, for example, ultra-violet (UV), electron-beam (E- beam) and/or thermal) post deposition treatment step. [0008] Thermodynamically, Si-OH and Si-H bonds in p-SiCOH films are readily oxidized by oxygen and water in an ambient to form Si-O-Si bonding due to a low activation energy needed for the formation of such Si-O-Si bonding. As p-SiCOH dielectrics become more porous with lower k values, the surface area and the absorption of oxygen/water increase significantly and become more susceptible to oxidation thus forming an increased number of strained Si-O-Si bonds to be present in the dielectric film. The formation of Si-O-Si bonds, in turn, increases the film's stress and crack velocity to levels which are not acceptable in semiconductor interconnect structures.
[0009] In view of the above, there is a need for providing a p-SiCOH dielectric film in which the film's stress and crack velocity are not significantly increased as compared to prior art p- SiCOH dielectrics. That is, a p-SiCOH dielectric film is needed in which the content of Si-O- Si bonding in the film is decreased by decreasing the content of Si-OH and Si-H bonding in the p-SiCOH dielectric film.
Summary of the Invention
[0010] The present invention provides a porous SiCOH (p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized. In other terms, the inventive porous SiCOH dielectric film has less Si-O-Si bonding as compared to prior art p- SiCOH dielectric films. Moreover, a stable p-SiOCH dielectric film is provided in which the amount of Si-OH (silanol) and/or Si-H groups at least within the pores has been reduced to about 0.01 atomic % or less. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking -(CHx)- chains wherein x is 1, 2 or 3 therein.
[0011] In general terms, the inventive dielectric film comprises elements of Si, C, H and O, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pores, wherein said multiplicity of nano-sized pores include additional crosslinking -(CHx)- chains, wherein x is 1, 2 or 3 that bond with at least one Si bond that originated from the reaction between a post treatment double bond precursor with some of the Si-OH groups and/or Si-H groups (i.e., Si bonding groups) normally present in said pores prior to the treatment.
[0012] The inventive dielectric film typically has a hydrocarbon content (saturated and unsaturated) within said pores and on a surface thereof that is from about 0.1 to about 10 wt. %, with a hydrocarbon content in the range from about 0.5 to about 2 wt. % being more typical.
[0013] The inventive dielectric film can be further characterized as having more branching C-group bonding -(CHx)- chains, wherein x is 1, 2 or 3 on the surface and within the pores as compared with prior art p-SiCOH dielectric materials. The increased branching C-group bonding can be evidenced by additional hydrocarbon (on the order of about 1 atomic % C or higher) being presented in the film, as measured by Electron Spectroscopy for Chemical Analysis (ESCA), Rutherford Back Scattering (RBS), Time-of-Flight Secondary Ion Mass Spectroscopy (TOF SIMS), or FTIR as measured of carbon concentration or C-H bonding change before and after post-treatment.
[0014] In some embodiments of the present invention, the -(CHx)- chains are also present on the surface of the film as well as within the pores. The presence of these chains on the surface of the dielectric film provides a film that is less sensitive to moisture as compared with prior art films not including the -(CHx)- chains since the presence of the -(CHx)- chains on the surface of the dielectric material removes the silanol groups (i.e., Si-OH) present on the surface of the dielectric film. Hence, the inventive p-SiCOH dielectric film is more hydrophobic than prior art SiCOH dielectric films.
[0015] The present invention also provides a method of forming such a p-SiCOH dielectric film. In particular, the applicants have determined that one can reduce or minimize the stress change and make the p-SiCOH dielectric film more stable and more hydrophobic by selecting an appropriate annealing ambient that has the ability to reduce oxidation of the dielectric film and thus minimize or reduce the formation of Si-OH (and to a lesser extent Si-H) groups on the surface of the dielectric film. In the present invention it has been determined that by annealing in an ambient that includes a gas that contains at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond produces the inventive p-SiCOH dielectric film. In particular, the bonding formation utilizing such an ambient gas produces flexible and stabilized crosslinking -(CHx)- chains at least within the pores of the SiCOH dielectric film. Subsequently, the film stress will be reduced and the film's stability will be improved. The presence of the at least one C- C double bond and/or the at least one C-C triple bond in the annealing ambient also minimizes the impact of residual oxygen in the ambient during annealing and reduces/eliminates the formation of Si-OH and/or Si-H bonding on the surface of the dielectric film forming various bridging bonds.
[0016] In general terms, the inventive method comprises:
[0017] forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pore;
[0018] annealing said dielectric film in the presence of a gaseous ambient that includes at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, wherein said annealing forms crosslinking - (CHx)- chains, wherein x is 1, 2 or 3, that react with at least some active bonding Si-OH groups and Si-H groups present in said pores.
[0019] That is, the -(CHx)- chains bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups and Si-H groups originally present in said pores.
[0020] The annealing step may include a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal and/or a microwave anneal.
[0021] In some embodiments, the pores contain the bonding Si-OH groups and/or the Si-H groups prior to the annealing step. In yet other embodiments, these bonding groups are generated during initial stages of said annealing process during pore formation and then they are removed during subsequent stages of the annealing process.
[0022] In some embodiments of the present invention, the gaseous ambient employed in the annealing step is an unsaturated hydrocarbon. In other embodiments of the present invention, the gaseous ambient is an organosilicon compound with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups. In yet another embodiment of the present invention, the gaseous ambient comprises a compound having an organosilicon group (Rl, R2, R3)-Si-OH with silanol group bonding wherein Rl, R2, R3 are identical or different and are a hydrocarbon, vinyl or diene radical.
[0023] In some embodiments of the present invention, the annealing in the aforementioned gaseous ambient occurs during a high-energy post deposition processing step that removes labile organic groups thus forming a porous dielectric material. In yet another embodiment of the present invention, the annealing in the above gaseous ambient may occur after a high energy post deposition processing step that removes the labile organic groups. In yet another embodiment of the present invention, the treating in the aforementioned ambient may occur during and after a high-energy post deposition processing step that removes the organic labile groups.
[0024] The annealing step of the present invention reduces both Si-OH and Si-H bond formation within the pores and on the surface of the p-SiCOH film, increases the film's hydrophobicity, enhances the films stability and reduces the film's stress by reducing the formation of Si-O-Si crosslinking bonds.
[0025] The present invention also relates to electronic structures, in which the p-SiCOH dielectric film of the present invention may be used as an interconnect (i.e., interlevel or intralevel) dielectric, a capping layer, and/or as a hard mask/polish-stop layer.
[0026] Specifically, the electronic structures of the present invention include a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, the second layer of insulating material being in intimate contact with the first layer of insulating material, the first region of conductor being in electrical communication with the first region of metal, and a second region of conductor being in electrical communication with the first region of conductor and being embedded in a third layer of insulating material, the third layer of insulating material being in intimate contact with the second layer of insulating material. In the above structure, each of the insulating layers can comprise the inventive p-SiCOH dielectric film which has a reduced content of Si-O-Si bonding.
[0027] The electronic structure may further include a dielectric cap layer situated in-between the first layer of insulating material and the second layer of insulating material, and may further include a dielectric cap layer situated in-between the second layer of insulating material and the third layer of insulating material. The electronic structure may further include a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material.
[0028] In some embodiments, the dielectric cap itself can comprise the inventive p-SiCOH dielectric film.
[0029] The electronic structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layer of insulating material. The electronic structure may further include a dielectric layer on top of the second layer of insulating material for use as a RIE hard mask/polish-stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask/polish-stop layer. The electronic structure may further include a first dielectric RIE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RIE diffusion barrier layer on top of the first dielectric polish-stop layer a second dielectric RIE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer. The dielectric RIE hard mask/polish-stop layer may be comprised of the inventive p-SiCOH dielectric film as well. [0030] The present invention also relates to the use of the inventive SiCOH dielectric film in other electronic structures including a structure including at least two conductors and an optoelectronic sensing structure, for use in detection of light.
Brief Description of the Drawings
[0031] FIGS. 1A-1C are pictorial representations (through cross sectional views) depicting the basic processing steps in which a p-SiCOH dielectric film having reduced Si-OH content and thus reduced Si-O-Si bonding is formed on a surface of a substrate.
[0032] FIG. 2 is an enlarged, cross-sectional view of an electronic device of the present invention that includes the inventive p-SiCOH dielectric film as both the intralevel dielectric layer and the interlevel dielectric layer.
[0033] FIG. 3 is an enlarged, cross-sectional view of the electronic structure of FIG. 2 having an additional diffusion barrier dielectric cap layer deposited on top of the inventive p-SiCOH dielectric film.
[0034] FIG. 4 is an enlarged, cross-sectional view of the electronic structure of FIG. 3 having an additional RIE hard mask/polish-stop dielectric cap layer and a dielectric cap diffusion barrier layer deposited on top of the polish-stop layer.
[0035] FIG. 5 is an enlarged, cross-sectional view of the electronic structure of FIG. 4 having additional RIE hard mask/polish-stop dielectric layers deposited on top of the p-SiCOH dielectric film of the present invention.
[0036] FIG. 6 is a pictorial representation (through a cross sectional view) illustrating an electronic structure including at least two conductors and the inventive p-SiCOH dielectric material. [0037] FIGS. 7A-7B are pictorial representations (through cross sectional views) illustrating electronic structures including a sensing element and the inventive p-SiCOH dielectric material.
Detailed Description of the Invention
[0038] The present invention, which describes a p-SiCOH dielectric film having a reduced content of Si-OH and Si-H bondings, and increased -(CHx)- bondings within the pores and on the surface of the film, a method of fabricating the same and electronic structures containing the inventive p-SiCOH dielectric film, will now be described in greater detail.
[0039] In accordance with the method of the present invention, a SiCOH dielectric film 12 is formed on a surface of a substrate 10 such as shown, for example, in FIG. IA. The term "substrate" when used in conjunction with substrate 10 includes, a semiconducting material, an insulating material, a conductive material or any combination thereof, including multilayered structures. Thus, for example, substrate 10 may be a semiconducting material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors. The semiconductor substrate 10 may also include a layered substrate such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on- insulators (SGOIs). When substrate 10 is an insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers. When the substrate 10 is a conductive material, the substrate 10 may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal suicide, a metal nitride and combinations thereof, including multilayers.
[0040] In some embodiments, the substrate 10 includes a combination of a semiconducting material and an insulating material, a combination of a semiconducting material and a conductive material or a combination of a semiconducting material, an insulating material and a conductive material. An example of a substrate that includes a combination of the above is an interconnect structure. [0041] The SiCOH dielectric film 12 is typically deposited using plasma enhanced chemical vapor deposition (PECVD). In addition to PECVD, the present invention also contemplates that the SiCOH dielectric film 12 can be formed utilizing chemical vapor deposition (CVD), high-density plasma (HDP) deposition, pulsed PECVD, spin-on application, or other related methods. The thickness of the SiCOH dielectric film 12 deposited may vary; typical ranges for the deposited SiCOH dielectric film 12 are from about 50 nm to about 1 μm, with a thickness from 100 to about 500 nm being more typical.
[0042] Typically, the SiCOH dielectric film is deposited using the processing techniques disclosed in co-assigned U.S. Patent Nos. 6,147,009, 6,312,793, 6,441,491, 6,437,443, 6,541,398, 6,479,110 B2, and 6,497,963 as well as in U.S. Patent Application Publication Nos. 2005/0156285 Al, 2005/0245096 Al, 2005/ 0194619 Al and 2006/0165891 Al, the contents of each of which are incorporated herein by reference.
[0043] Specifically, the SiCOH dielectric film 12 is formed by providing at least a first precursor (liquid, gas or vapor) comprising atoms of Si, C, O, and H, and an inert carrier such as He or Ar, into a reactor, preferably the reactor is a PECVD reactor, and then depositing a film derived from said first precursor onto a suitable substrate utilizing conditions that are effective in forming a SiCOH dielectric material. The present invention yet further provides for mixing the first precursor with an oxidizing agent such as O2, CO2 or a combination thereof, thereby stabilizing the reactants in the reactor and improving the uniformity of the SiCOH dielectric film 12 deposited on the substrate 10.
[0044] In addition to the first precursor, a second precursor (gas, liquid or vapor) comprising atoms of C, H, and optionally O, F and N can be used. Optionally, a third precursor (gas, liquid or gas) comprising Ge may also be used.
[0045] The first precursor is selected from silane (SiH4) derivatives having the molecular formula SiRR'R"R'" where R,R',R", and R'" may or may not be identical and are selected from H, alkyl, and alkoxy, preferably methyl, ethyl, methoxy, and ethoxy. Preferred precursors include: diethoxydimethylsilane, diethoxymethylsilane (DEMS), ethoxyltrimethylsilane, ethoxydimethylsilane, dimethoxydimethylsilane, dimethoxymethylsilane, triethoxysilane, and trimethoxymethylsilane. In some embodiments, the first precursor is selected from organosilicon molecules with ring structures comprising SiCOH components such as 1, 3, 5, 7-tetramethylcyclotetrasiloxane ("TMCTS" or "C4Hi6O4Si4"), and octamethylcyclotetrasiloxane (OMCTS).
[0046] The second precursor employed in the present application is an organic compound that is selected from:
Figure imgf000013_0001
alkenes:
Ri ≡E— Rz alkynes:
ethers: ; and
oxiranes:
Figure imgf000013_0002
[0047] where R , R , R3, R4, R5 and R may or may not be identical and are selected from hydrogen, alkyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. Additionally, other atoms such as S, Si, or other halogens may be contained in the second precursor molecule. Of these species, the most suitable are ethylene oxide, propylene oxide, cyclopentene oxide, isobutylene oxide, 2,2,3-trimethyloxirane, butadienemonoxide, bicycloheptadiene (BCHD), l,2-epoxy-5-hexene, 2-methyl-2-vinyloxirane, 1-isopropyl- cyclohexa-l,3-diene and tertbutylmethylether.
[0048] In some embodiments, the second precursor may be selected from the group consisting of hydrocarbon molecules with ring structures, preferably with more than one ring present in the molecule or with branched chains attached to the ring. Especially useful, are species containing fused rings, at least one of which contains a heteroatom, preferentially oxygen. Of these species, the most suitable are those that include a ring of a size that imparts significant ring strain, namely rings of 3 or 4 atoms and/or 7 or more atoms. Particularly attractive, are members of a class of compounds known as oxabicyclics, such as cyclopentene oxide ("CPO'Or "CsH8O"). Also useful are molecules containing branched tertiary butyl (t- butyl) and isopropyl (i-propyl) groups attached to a hydrocarbon ring; the ring may be saturated or unsaturated (containing C=C double bonds).
[0049] It is noted that the above second precursors include labile functional groups that can be readily removed from the dielectric film during a subsequent processing (i.e., curing) step. In some embodiments, a separate porogen material can be added during the formation of the p-SiCOH dielectric film.
[0050] The third precursor which can optionally be used is formed from germane hydride or any other reactant comprising a source of Ge.
[0051] The SiCOH film 12 may be deposited using a method the includes the step of providing a parallel plate reactor, which has a conductive area of a substrate chuck between about 85 cm2 and about 1600 cm2, and a gap between the substrate and a top electrode between about 1 cm and about 12 cm. A high frequency RF power is applied to one of the electrodes at a frequency from about 0.45 MHz to about 200 MHz. Optionally, an additional low frequency power can be applied to one of the electrodes.
[0052] The conditions used for the deposition step may vary depending on the desired final dielectric constant of the SiCOH dielectric film 12. Broadly, the conditions used for providing a stable dielectric material comprising elements of Si, C, O, H that has a dielectric constant of about 2.7 or less include: setting the substrate temperature at a temperature from about 200 0C to about 4250C; setting the high frequency RF power density within a range from about 0.1 W/cm2 to about 1.5 W/cm2; setting the first liquid precursor flow rate within a range from about 100 mg/min to about 5000 mg/min, optionally setting the second liquid precursor flow rate within a range from about 50 mg/min to about 10,000 mg/min; optionally setting the third liquid precursor flow rate within a range from about 25 mg/min to about 4000 mg/min; optionally setting the inert carrier gases such as helium (or/and argon) flow rate within a range from about 50 seem to about 5000 seem; setting the reactor pressure at a pressure within a range from about 1000 mTorr to about 7000 mTorr; and setting the high frequency RF power within a range from about 75 W to about 1000 W. Optionally, an ultra low frequency power may be added to the plasma within a range from about 30 W to about 400 W. When the conductive area of the substrate chuck is changed by a factor of X, the RF power applied to the substrate chuck may also change by a factor of X.
[0053] When an oxidizing agent is employed in the present invention, it is flown into the PECVD reactor at a flow rate within a range from about 10 seem to about 1000 seem.
[0054] While liquid precursors are used in the above example, it is known in the art that the organosilicon gas phase precursors (such as trimethylsilane) can also be used for the deposition.
[0055] The dielectric film 12 formed at this point of the present invention contains a matrix of a hydrogenated oxidized silicon carbon material (SiCOH) comprising atoms of Si, C, O and H in a covalently bonded tri-dimensional network and having a dielectric constant of not more than about 3.6 prior to curing. After UV or E-beam curing, the film will have some pores and the dielectric constant of the film is about 2.7 or less. The tri-dimensional network may include a covalently bonded tri-dimensional structure comprising Si-O, Si-C, Si-H, C-H and C-C bonds. The dielectric film 12 may comprise F and N and may optionally have the Si atoms partially substituted by Ge atoms.
[0056] After deposition of the SiCOH dielectric film, the deposited film is subjected to a high energy post deposition processing step that forms a porous SiCOH dielectric film 12' (See FIG. IB). Specifically, the as deposited film can be processed using a high energy source to stabilize the film, remove labile functional groups and improve its properties (electrical, mechanical, adhesive). Suitable energy sources that can be used for the post processing step include thermal, chemical, ultraviolet (UV) light, electron beam (E-beam), microwave, and plasma. Combinations of the aforementioned energy sources can also be used in the present invention.
[0057] The thermal energy source includes any source such as, for example, a heating element or a lamp, that can heat the deposited dielectric material to a temperature from about 300° to about 5000C. More preferably, the thermal energy source is capable of heating the deposited dielectric material to a temperature from about 350° to about 43O0C. This thermal treatment process can be carried out for various time periods, with a time period from about 1 minute to about 300 minutes being typical. The thermal treatment step is typically performed in the presence of an inert gas such as He and Ar. The thermal treatment step may include a rapid thermal anneal, a furnace anneal, a laser anneal or a spike anneal.
[0058] The UV light treatment step is performed utilizing a source that can generate light having a wavelength from about 500 to about 150 nm, to irradiate the substrate while the wafer temperature is maintained at a temperature from about 25° to about 5000C, with temperatures from about 300° to about 4500C being preferred. Radiation with less than 370 nm is of insufficient energy to dissociate or activate important bonds, so the wavelength range 150-370 nm is a preferred range. Using literature data and absorbance spectra measured on as deposited films, the inventors have found that less than 170 nm radiation may not be favored due to degradation of the SiCOH film. Further, the energy range 310-370 nm is less useful than the range 150-310 nm, due to the relatively low energy per photon from 310-370 nm. Within the 150-310 nm range, optimum overlap with the absorbance spectrum of the as deposited film and minimum degradation of the film properties (such as hydrophobicity) may be optionally used to select a most effective region of the UV spectrum for changing the SiCOH properties.
[0059] The electron beam treatment step is performed utilizing a source that is capable of generating a uniform electron flux over the wafer, with energies from about 0.5 to about 25 keV and current densities from about 0.1 to about 100 micro Amp/cm2 (preferably about 1 to about 5 microAmp/cm2), while the wafer temperature is maintained at a temperature from about 25° to about 5000C, with temperatures from about 300° to about 45O0C being preferred. The preferred dose of electrons used in the electron beam treatment step is from about 50 to about 500 microcoulombs/cm , with about 100 to about 300 microcoulombs/cm being most preferred.
[0060] The SiCOH dielectric film 12 after curing comprises between about 5 and about 40 atomic percent of Si; between about 5 and about 45 atomic percent of C; between 0 and about 60 atomic percent of O; and between about 10 and about 55 atomic percent of H. The SiCOH dielectric film 12 is thermally stable above 350°C . After post-deposition curing, the SiCOH film 12 preferably has a thickness of not more than 1.3 micrometers and a crack propagation velocity in water of less than 10"9 meters per second.
[0061] Subsequently, the inventive second post treatment including either plasma, thermal, UV or E-beam in an ambient that includes a gas that contains at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond is used. For example, thermal treatment including annealing at a temperature range from about 300° to about 45O0C for a duration from about 1 to about 120 minutes in an ambient gas that includes one of ethylene (C2H4), acetylene (C2H2), propylene (C3H6), and butene (C4H8) as well as an organic gas compound that is selected from one of the following formula:
Figure imgf000017_0001
alkenes: .
alkynes: R1 = R2
with R1, R2, R3, R4 are either saturated hydrocarbon groups (-CH3, -C2H5, and etc.), or hydrogen can be used in the present invention.
[0062] The plasma treatment step which includes the above mentioned hydrocarbon gas including at least one C-C double bond and/or at least one C-C triple bond is performed utilizing a source that is capable of generating atomic hydrogen (H), and optionally CH3 or other hydrocarbon radicals. Downstream plasma sources are preferred over direct plasma exposure. During plasma treatment the wafer temperature is maintained at a temperature from about 25° to about 5000C, with temperatures from about 300° to about 45O0C being preferred.
[0063] The plasma treatment step is performed by introducing a gas into a reactor that can generate a plasma and thereafter it is converted into a plasma. The gas that can be used for the plasma treatment includes at least one of the above mentioned hydrocarbons containing at least one C-C double bond and/or at least one C-C triple bond and an inert gas such as Ar, N, He, Xe or Kr, with He being preferred; hydrogen or related sources of atomic hydrogen, methane, methylsilane, related sources OfCH3 groups, and mixtures thereof. The flow rate of the plasma treatment gas may vary depending on the reactor system being used. The chamber pressure can range anywhere from about 0.05 to about 20 torr, but the preferred range of pressure operation is from about 1 to about 10 torr. The plasma treatment step occurs for a period of time, which is typically from about Vi to about 10 minutes, although longer times may be used within the invention.
[0064] An RF or microwave power source is typically used to generate the above plasma. The RF power source may operate at either the high frequency range (on the order of about 100 W or greater); the low frequency range (less than about 250 W) or a combination thereof may be employed. The high frequency power density can range anywhere from about 0.1 to about 2.0 W/cm2 but the preferred range of operation is from about 0.2 to about 1.0 W/cm2. The low frequency power density can range anywhere from about 0.1 to about 1.0 W/cm2 but the preferred range of operation is from about 0.2 to about 0.5 W/cm2. The chosen power levels must be low enough to avoid significant sputter etching of the exposed dielectric surface (less than 5 nanometers removal).
[0065] For UV and E-beam treatment processes, it is possible to use the same hydrocarbon ambient (double and triple bond hydrocarbon gases) and temperature (about 200° to about 4500C range) as used in the thermal process. With UV and E-beam treatment, it is also possible to combine the first and second inventive post deposition processes into a single two-step post treatment process which includes 1) a first step post-treatment in inert ambient (Ar, He) to remove porogen and form pores, and 2) a second step post-treatment in the inventive double/triple bond hydrocarbon gases to removal any remain Si-H and Si-OH and to form cross-linking -(CHx)- bonding in the pores and film's surface
[0066] The above high energy first and second inventive post deposition processes provide a p-SiCOH dielectric film 12' on the surface of substrate 10. The p-SiCOH dielectric film 12' has a multiplicity of nano-sized pores therein. The nano-sized pores include at least one of Si-OH groups and Si-H groups therein. The nano-sized pores have a pore size from about 0.3 to about 10 nm, with a pore size from about 0.8 to about 2 nm being more preferred.
[0067] The second post treatment step, which is a separate step of treating the p-SiCOH dielectric film in a gaseous ambient that includes at least one C-C double bond, at least one C-C- triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, is employed after the high energy post deposition step. In yet other embodiments of the present invention, treating in the aforementioned gaseous ambient occurs during the high energy post deposition step that removes labile organic groups that forms a porous dielectric material. In yet another embodiment of the present invention, the treating in the aforementioned ambient may occur during and after the high energy post deposition treatment step that removes the organic labile groups. FIG. 1C illustrates a treated p-SiCOH dielectric film 12" of the present invention.
[0068] It is noted that the treating in the aforementioned ambient forms crosslinking -(CHx)- chains, wherein x is 1, 2, or 3 that bond with at least one Si-bonds, which originally came from Si-OH groups and Si-H groups also present in said pores before the post treatment. Hence, the amount of Si-O-H and Si-H bonds within the pores of the dielectric film are reduced due to the reaction between the double and/or triple hydrocarbon gases with the Si- OH and Si-H in the pore. A typical reduction of about 5 % or greater of Si-OH and Si-H bonds originally from the untreated film that can be achieved in the present invention. In some embodiments, the amount of Si-O-H and Si-H bonds on the surface of the dielectric film are also reduced and making the film hydrophobic.
[0069] The second annealing step may include a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal and/or a microwave anneal. The conditions for each of the anneals is the same as mentioned above, expect that a gaseous ambient including at least one C-C- double and/or triple bond is employed.
[0070] In some embodiments of the present invention, the anneal ambient is an unsaturated hydrocarbon. In this embodiment, the unsaturated hydrocarbon contains from about 2 to about 24, preferably 2 to 5, carbon atoms. The carbon atoms may be straight chained or branched. Examples of suitable unsaturated hydrocarbons that can be employed in the present invention include, but are not limited to ethylene, propylene, butylene, ethane, butane, and acetylene.
[0071] In other embodiment of the present invention, the annealing ambient is an organosilicon compound with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups. Examples of suitable organosilicon compounds with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups that can be employed in the present invention include, but are not limited to tetramethyl divinyl disiloxane, dimethyl tetravinyl disiloxane, hexamethyl disiloxane, hexavinyl disiloxane, and hexamethyl disilazane (HMDS).
[0072] In yet another embodiment of the present invention, the annealing ambient comprises a compound having an organosilicon group (R)3-Si-OH with one silanol group bonding wherein R is the same or different and is a saturated hydrocarbon, or vinyl or diene group. Examples of such organosilanes include, but are not limited to divinyl methyl silanol, and diethyl vinyl silanol.
[0073] Of the various gaseous ambients mentioned above, it is preferred to use an unsaturated hydrocarbon ambient, with butene, propylene, ethylene and acetylene being highly preferred examples of such unsaturated hydrocarbon ambients.
[0074] The above ambients may be used alone or mixed together or used in the presence of another gas including an inert gas such as Ar, and/or He. [0075] The amount of gaseous ambient including at least one C-C double/triple bond present during the annealing ambient may vary depending on the type of annealing process used, as well as the surface area of the p-SiCOH dielectric being annealed. The annealing ambient pressure typically ranges from about 1 torr to about 760 torr, and the preferred range is from about 5 to about 100 torr. The flow rates of the hydrocarbon gases range from about 10 to about 1000 seem for the ambient employed.
[0076] The annealing step of the present invention reduces both Si-OH and Si-H bond formation within the pores and on the surface of the p-SiCOH film, increases the film's hydrophobicity, enhances the films stability and reduces the film's stress by crosslinking Si- R-Si bonding formation.
[0077] Electronic devices which can contain the inventive p-SiCOH dielectric film are shown in FIGS. 2-7B. It should be noted that the devices shown in FIGS. 2-7B are merely illustrative examples of the present invention, while an infinite number of other devices may also be formed by the present invention novel methods.
[0078] In FIG. 2, an electronic device 30 built on a silicon substrate 32 is shown. On top of the silicon substrate 32, an insulating material layer 34 is first formed with a first region of metal 36 embedded therein. After a CMP process is conducted on the first region of metal 36, a p-SiCOH dielectric film 38 of the present invention is formed on top of the first layer of insulating material 34 and the first region of metal 36. The first layer of insulating material 34 may be suitably formed of silicon oxide, silicon nitride, doped varieties of these materials, or any other suitable insulating materials. The p-SiCOH dielectric film 38 is then patterned in a photolithography process followed by etching and a conductor layer 40 is deposited thereon. After a CMP process on the first conductor layer 40 is carried out, a second layer of the inventive p-SiCOH film 44 is formed by a overlying the first p-SiCOH dielectric film 38 and the first conductor layer 40. The conductor layer 40 may be a deposit of a metallic material or a nonmetallic conductive material. For instance, a metallic material of aluminum or copper, or a nonmetallic material of nitride or polysilicon. The first conductor 40 is in electrical communication with the first region of metal 36. [0079] A second region of conductor 50 is then formed after a photolithographic process on the p-SiCOH dielectric film 44 is conducted followed by etching and then a deposition process for the second conductor material. The second region of conductor 50 may also be a deposit of either a metallic material or a nonmetallic material, similar to that used in depositing the first conductor layer 40. The second region of conductor 50 is in electrical communication with the first region of conductor 40 and is embedded in the second layer of the SiCOH dielectric film 44. The second layer of the p-SiCOH dielectric film 44 is in intimate contact with the first layer of p-SiCOH dielectric material 38. In this example, the first layer of the p-SiCOH dielectric film 38 is an intralevel dielectric material, while the second layer of the p-SiCOH dielectric film 44 is both an intralevel and an interlevel dielectric. Based on the low dielectric constant of the inventive p-SiCOH dielectric films, superior insulating property can be achieved by the first insulating layer 38 and the second insulating layer 44.
[0080] FIG. 3 shows a present invention electronic device 60 similar to that of electronic device 30 shown in FIG. 2, but with an additional dielectric cap layer 62 deposited between the first insulating material layer 38 and the second insulating material layer 44. The dielectric cap layer 62 can be suitably formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-nitride (SiCN), silicon carbo-oxide (SiCO), Silicon Carbo-oxynitride (SiCON) and their hydrogenated compounds. The additional dielectric cap layer 62 functions as a diffusion barrier layer for preventing diffusion of the first conductor layer 40 into the second insulating material layer 44 or into the lower layers, especially into layers 34 and 32.
[0081] Another alternate embodiment of the present invention electronic device 70 is shown in FIG. 4. In the electronic device 70, two additional dielectric cap layers 72 and 74 which act as a RIE mask and CMP (chemical mechanical polishing) polish stop layer are used. The first dielectric cap layer 72 is deposited on top of the first low k insulating material layer 38 and used as a RIE mask and CMP stop, so the first conductor layer 40 and layer 72 are approximately co-planar after CMP. The function of the second dielectric layer 74 is similar to layer 72, however layer 74 is utilized in planarizing the second conductor layer 50. The polish stop layer 74 can be deposited of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-oxide (SiCO), Silicon Carbo- oxynitride (SiCON) and their hydrogenated compounds. A preferred polish stop layer composition is SiCH or SiCOH for layers 72 or 74. The SiCOH layer may include the inventive p-SiCOH dielectric film. A second dielectric layer can be added on top of the second p-SiCOH dielectric film 44 for the same purposes.
[0082] Still another alternate embodiment of the present invention electronic device 80 is shown in FIG. 5. In this alternate embodiment, an additional layer 82 of dielectric material is deposited and thus dividing the second insulating material layer 44 into two separate layers 84 and 86. The intralevel and interlevel dielectric layer 44 formed of the inventive p-SiCOH material is therefore divided into an interlayer dielectric layer 84 and an intralevel dielectric layer 86 at the boundary between via 92 and interconnect 94. An additional diffusion barrier layer 96 is further deposited on top of the upper dielectric layer 74. The additional benefit provided by this alternate embodiment electronic structure 80 is that dielectric layer 82 acts as an RIE etch stop providing superior interconnect depth control. Thus, the composition of layer 82 is selected to provide etch selectivity with respect to layer 86.
[0083] Still other alternate embodiments may include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate which has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of the insulating material wherein the second layer of insulating material is in intimate contact with the first layer of insulating material, and the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, wherein the third layer of insulating material is in intimate contact with the second layer of insulating material, a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material and a second dielectric cap layer on top of the third layer of insulating material, wherein the first and the second dielectric cap layers are formed of a material that includes atoms of Si, C, O and H, or preferably a p- SiCOH dielectric film of the present invention. [0084] Still other alternate embodiments of the present invention include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor that is in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, and a diffusion barrier layer formed of the dielectric film of the present invention deposited on at least one of the second and third layers of insulating material.
[0085] Still other alternate embodiments include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a reactive ion etching (RIE) hard mask/polish stop layer on top of the second layer of insulating material, and a diffusion barrier layer on top of the RIE hard mask/polish stop layer, wherein the RIE hard mask/polish stop layer and the diffusion barrier layer are formed of the p-SiCOH dielectric film of the present invention.
[0086] Still other alternate embodiments include an electronic structure which has layers of insulating materials as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a first RIE hard mask, polish stop layer on top of the second layer of insulating material, a first diffusion barrier layer on top of the first RIE hard mask/polish stop layer, a second RIE hard mask/polish stop layer on top of the third layer of insulating material, and a second diffusion barrier layer on top of the second RIE hard mask/polish stop layer, wherein the RIE hard mask/polish stop layers and the diffusion barrier layers are formed of the p-SiCOH dielectric film of the present invention.
[0087] Still other alternate embodiments of the present invention includes an electronic structure that has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure similar to that described immediately above but further includes a dielectric cap layer which is formed of the p-SiCOH dielectric material of the present invention situated between an interlevel dielectric layer and an intralevel dielectric layer.
[0088] In some embodiments as shown, for example in FIG. 6, an electronic structure containing at least two metallic conductor elements (labeled as reference numerals 97 and 101) and a p-SiCOH dielectric material (labeled as reference numeral 98). Optionally, metal contacts 95 and 102 are used to make electrical contact to conductors 97 and 101. The inventive p-SiCOH dielectric 98 provides electrical isolation and low capacitance between the two conductors. The electronic structure is made using a conventional technique that is well known to those skilled in the art such as described, for example, in U.S. Patent No. 6,737,727, the entire content of which is incorporated herein by reference.
[0089] The at least two metal conductor elements are patterned in a shape required for a function of a passive or active circuit element including, for example, an inductor, a resistor, a capacitor, or a resonator.
[0090] Additionally, the inventive p-SiCOH dielectric can be used in an electronic sensing structure wherein the optoelectronic sensing element (detector) shown in FIG. 7A or 7B is surrounded by a layer of the inventive SiCOH dielectric material. The electronic structure is made using a conventional technique that is well known to those skilled in the art. Referring to FIG. 7 A, a p-i-n diode structure is shown which can be a high speed Si based photodetector for IR signals. The n+ substrate is 110, and atop this is an intrinsic semiconductor region 112, and within region 112 p+ regions 114 are formed, completing the p-i-n layer sequence. Layer 116 is a dielectric (such as SiO2) used to isolate the metal contacts 118 from the substrate. Contacts 118 provide electrical connection to the p+ regions. The entire structure is covered by the inventive SiCOH dielectric material, 120. This material is transparent in the IR region, and serves as a passivation layer.
[0091] A second optical sensing structure is shown in FIG. 7B, this is a simple p-n junction photodiode, which can be a high speed IR light detector. Referring to FIG. 7B, the metal contact to substrate is 122, and atop this is an n-type semiconductor region 124, and within this region p+ regions 126 are formed, completing the p-n junction structure. Layer 128 is a dielectric (such as SiO2) used to isolate the metal contacts 130 from the substrate. Contacts 130 provide electrical connection to the p+ regions. The entire structure is covered by the inventive p-SiCOH dielectric material, 132. This material is transparent in the IR region, and serves as a passivation layer.
[0092] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

ClaimsWhat is claimed is:
1. A dielectric film comprising elements of Si, C, H and O, said dielectric film having a dielectric constant of about 2.7 or less, a random tri-dimensional covalently bonded network and a multiplicity of nano-sized pores, wherein said multiplicity of nano-sized pores includes crosslinking -(CHx)- chains, wherein x is 1, 2 or 3, that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups originally present in said pores.
2. The dielectric film of Claim 1 wherein said random tri-dimensional covalently bonded network comprises Si-O, Si-C, Si-H, C-H and C-C , Si-OH and Si-H bonds.
3. The dielectric film of Claim 1 wherein said dielectric film comprises from about 5 to about 40 atomic percent of Si, between about 5 and about 45 atomic percent of C, between O and about 50 atomic percent of O, and between about 10 and about 55 atomic percent of H.
4. The dielectric film of Claim 1 wherein said dielectric film is hydrophobic having a reduced number of Si-OH and Si-H bonds located within said pores and on a surface of the dielectric film.
5. The dielectric film of Claim 1 wherein said dielectric film has a saturated or unsaturated hydrocarbon content within said pores and on a surface thereof that is from about 0.1 to about 10 wt %.
6. The dielectric film of Claim 1 wherein said crosslinking -(CHx)- chains are also present on a surface of said dielectric film, said crosslinking -(CHx)- chains bond with Si bonds.
7. The dielectric film of Claim 1 wherein said nano-sized pores have a pore size distribution from about 0.5 to about 10 nm.
8. The dielectric film of Claim 1 wherein said dielectric film is located on a surface of a substrate.
9. The dielectric film of Claim 8 wherein said substrate comprises a semiconducting material, an insulating material, a conductive material or combinations and multilayers thereof.
10. An electronic structure comprising a dielectric film including elements of Si, C, H and O, a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pores, wherein said multiplicity of nano-sized pores includes crosslinking -(CHx)- chains, wherein x is 1,2, or 3, that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups originally present in said pores.
11. The electronic structure of Claim 10 wherein said dielectric film is one of an interconnect dielectric layer, a cap layer and a hard mask layer.
12. The electronic structure of Claim 10 wherein said dielectric film is located on a surface of a substrate.
13. The electronic structure of Claim 12 wherein said substrate comprises a semiconducting material, an insulating material, a conductive material or combinations and multilayers thereof.
14. The electronic structure of Claim 10 wherein said dielectric film is hydrophobic having a reduced number of Si-O-Si bonds located within said pores and on a surface of the dielectric film.
15. The electronic structure of Claim 10 wherein said dielectric film has an unsaturated hydrocarbon content within said pores and on a surface thereof that is from about 0.5 to about 2 wt %.
16. The electronic structure of Claim 10 wherein said crosslinking -(CHx)- chains are also present on a surface of said dielectric film, said crosslinking -(CHx)- chains bond with the Si originated from the Si-OH and Si-H groups present on said surface.
17. A method of fabricating a porous dielectric film comprising:
forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pores, wherein said pores include at least one of Si-OH groups and Si-H groups therein; and
annealing said dielectric film in a gaseous ambient that includes at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, wherein said annealing forms crosslinking -(CHx)- chains, wherein x is 1,2 or 3, that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups originally present in said pores.
18. The method of Claim 17 wherein said forming said dielectric film comprises a deposition step and a high energy post deposition processing step that removes labile functional groups from an as deposited film.
19. The method of Claim 17 wherein said annealing occurs during said high energy post deposition processing step, after said high energy post deposition processing step, or during and after said high energy post deposition processing step.
20. The method of Claim 17 wherein the gaseous ambient is an unsaturated hydrocarbon having from about 2 to about 24 C atoms.
21. The method of Claim 17 wherein the gaseous ambient is an organosilicon compound with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups.
22. The method of Claim 17 wherein the gaseous ambient comprises a compound having an organosilicon group (R)3-Si-OH with silanol group bonding wherein R is the same or different and is a hydrocarbon, vinyl or diene group.
23. The method of Claim 17 wherein said annealing includes a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal, a microwave anneal or any combination thereof.
24. The method of Claim 18 wherein said deposition step includes a plasma enhanced chemical vapor deposition process.
25. A method of forming a porous dielectric material comprising:
forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less and a random covalently bonded tri-dimensional network;
treating said dielectric film to form a multiplicity of nano-sized pores therein, wherein said pores include at least one of Si-OH groups and Si-H groups therein; and
annealing said treated dielectric film in a gaseous ambient that includes at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, wherein said annealing forms crosslinking -(CHx)- chains, wherein x is 1,2 or 3, that bond that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups and Si-H groups originally present in said pores.
26. The method of Claim 25 wherein the gaseous ambient is an unsaturated hydrocarbon having from about 2 to about 24 C atoms.
27. The method of Claim 25 wherein the gaseous ambient is an organosilicon compound with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups.
28. The method of Claim 25 wherein the gaseous ambient comprises a compound having an organosilicon group (R)3-Si-OH with silanol group bonding wherein R is the same or different and is a hydrocarbon, vinyl or diene group.
29. The method of Claim 25 wherein said annealing includes a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal, a microwave anneal or any combination thereof.
30. A method of forming a porous dielectric material comprising:
forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less and a random covalently bonded tri-dimensional network;
treating said dielectric film to form a multiplicity of nano-sized pores therein, wherein said pores include at least some of Si-OH groups and Si-H groups therein wherein during said treating an annealing step is performed in a gaseous ambient that includes at least one C-C double bond, at least one C-C triple bond or a combination of at least one C-C double bond and at least one C-C triple bond, wherein said annealing forms crosslinking -(CHx)- chains, wherein x is 1, 2 or 3, that that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si-OH groups and Si-H groups originally present in said pores.
31. The method of Claim 30 wherein the gaseous ambient is an unsaturated hydrocarbon having from about 2 to about 24 C atoms.
32. The method of Claim 30 wherein the gaseous ambient is an organosilicon compound with fully hydrophobic bonds and with a low strained Si-O-Si bonding structure or with single vinyl double bond (C=C) groups.
33. The method of Claim 30 wherein the gaseous ambient comprises a compound having an organosilicon group (R)3-Si-OH with silanol group bonding wherein R is the same or different and is a hydrocarbon, vinyl or diene group.
34. The method of Claim 30 wherein said annealing includes a thermal anneal, an ultraviolet (UV) anneal, a plasma anneal, a microwave anneal or any combination thereof.
PCT/US2008/072955 2007-08-28 2008-08-13 Improved low k porous sicoh dielectric and integration with post film formation treatment WO2009032488A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/846,182 US20090061237A1 (en) 2007-08-28 2007-08-28 LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
US11/846,182 2007-08-28
US11/846,250 2007-08-28
US11/846,250 US20090061649A1 (en) 2007-08-28 2007-08-28 LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT

Publications (1)

Publication Number Publication Date
WO2009032488A1 true WO2009032488A1 (en) 2009-03-12

Family

ID=40429276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/072955 WO2009032488A1 (en) 2007-08-28 2008-08-13 Improved low k porous sicoh dielectric and integration with post film formation treatment

Country Status (2)

Country Link
TW (1) TW200913067A (en)
WO (1) WO2009032488A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011056550A1 (en) * 2009-10-27 2011-05-12 Silcotek Corp. Chemical vapor deposition coating, article, and method
CN105390371A (en) * 2014-08-21 2016-03-09 西尔科特克公司 Semiconductor fabrication processes
US9340880B2 (en) 2009-10-27 2016-05-17 Silcotek Corp. Semiconductor fabrication process
KR20170119745A (en) * 2010-10-05 2017-10-27 실코텍 코포레이션 Wear resistant coating, article, and method
US11131020B2 (en) 2015-09-01 2021-09-28 Silcotek Corp. Liquid chromatography system and component
US11292924B2 (en) 2014-04-08 2022-04-05 Silcotek Corp. Thermal chemical vapor deposition coated article and process
US11618970B2 (en) 2019-06-14 2023-04-04 Silcotek Corp. Nano-wire growth

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040175957A1 (en) * 2003-03-04 2004-09-09 Lukas Aaron Scott Mechanical enhancement of dense and porous organosilicate materials by UV exposure
US20060165891A1 (en) * 2005-01-21 2006-07-27 International Business Machines Corporation SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same
US7166531B1 (en) * 2005-01-31 2007-01-23 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040175957A1 (en) * 2003-03-04 2004-09-09 Lukas Aaron Scott Mechanical enhancement of dense and porous organosilicate materials by UV exposure
US20060165891A1 (en) * 2005-01-21 2006-07-27 International Business Machines Corporation SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same
US7166531B1 (en) * 2005-01-31 2007-01-23 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101932899B1 (en) * 2009-10-27 2018-12-26 실코텍 코포레이션 Chemical vapor deposition coating, article, and method
KR101911196B1 (en) * 2009-10-27 2018-10-24 실코텍 코포레이션 Chemical vapor deposition coating, article, and method
WO2011056550A1 (en) * 2009-10-27 2011-05-12 Silcotek Corp. Chemical vapor deposition coating, article, and method
US9340880B2 (en) 2009-10-27 2016-05-17 Silcotek Corp. Semiconductor fabrication process
KR101773213B1 (en) * 2009-10-27 2017-08-30 실코텍 코포레이션 Chemical vapor deposition coating, article, and method
US9777368B2 (en) 2009-10-27 2017-10-03 Silcotek Corp. Chemical vapor deposition coating, article, and method
CN102741452A (en) * 2009-10-27 2012-10-17 西尔科特克公司 Chemical vapor deposition coating, article, and method
US10731247B2 (en) 2009-10-27 2020-08-04 Silcotek Corp. Coated article
KR20170119745A (en) * 2010-10-05 2017-10-27 실코텍 코포레이션 Wear resistant coating, article, and method
KR101854162B1 (en) * 2010-10-05 2018-06-20 실코텍 코포레이션 Wear resistant coating, article, and method
US11292924B2 (en) 2014-04-08 2022-04-05 Silcotek Corp. Thermal chemical vapor deposition coated article and process
CN105390371A (en) * 2014-08-21 2016-03-09 西尔科特克公司 Semiconductor fabrication processes
US11131020B2 (en) 2015-09-01 2021-09-28 Silcotek Corp. Liquid chromatography system and component
US11618970B2 (en) 2019-06-14 2023-04-04 Silcotek Corp. Nano-wire growth

Also Published As

Publication number Publication date
TW200913067A (en) 2009-03-16

Similar Documents

Publication Publication Date Title
US9219037B2 (en) Low k porous SiCOH dielectric and integration with post film formation treatment
US20090061237A1 (en) LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
US7030468B2 (en) Low k and ultra low k SiCOH dielectric films and methods to form the same
KR101006329B1 (en) DUV LASER ANNEALING AND STABILIZATION OF SiCOH FILMS
US7049247B2 (en) Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made
US7202564B2 (en) Advanced low dielectric constant organosilicon plasma chemical vapor deposition films
US8097932B2 (en) Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality
US7265437B2 (en) Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties
EP1617957B1 (en) Method of forming an ultra low dielectric constant film
US20070173071A1 (en) SiCOH dielectric
US7357977B2 (en) Ultralow dielectric constant layer with controlled biaxial stress
US20080009141A1 (en) Methods to form SiCOH or SiCNH dielectrics and structures including the same
KR20050010867A (en) An ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device
WO2009032488A1 (en) Improved low k porous sicoh dielectric and integration with post film formation treatment

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08797739

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08797739

Country of ref document: EP

Kind code of ref document: A1