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Publication numberWO2009024761 A3
Publication typeApplication
Application numberPCT/GB2008/002770
Publication date30 Apr 2009
Filing date15 Aug 2008
Priority date17 Aug 2007
Also published asWO2009024761A2
Publication numberPCT/2008/2770, PCT/GB/2008/002770, PCT/GB/2008/02770, PCT/GB/8/002770, PCT/GB/8/02770, PCT/GB2008/002770, PCT/GB2008/02770, PCT/GB2008002770, PCT/GB200802770, PCT/GB8/002770, PCT/GB8/02770, PCT/GB8002770, PCT/GB802770, WO 2009/024761 A3, WO 2009024761 A3, WO 2009024761A3, WO-A3-2009024761, WO2009/024761A3, WO2009024761 A3, WO2009024761A3
InventorsTimothy James Regan
ApplicantTimothy James Regan
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
Stack of integrated circuits
WO 2009024761 A3
A three-dimensional structure including a plurality of integrated circuits (101a-d) stacked substantially vertically one on top of another, said stack of circuits (101a-d) including first and second circuits (101a;113) located at different vertical levels in the stack, wherein the first circuit comprises a master clock circuit (113) that includes clock circuitry arranged to provide clock signals to a plurality of nodes (107) within the master clock circuit, and the structure includes at least one interconnect (115) that is arranged to connect one of the nodes (107) in the master clock circuit to a node (117) in the second circuit (101a), and the master clock circuit (113) is arranged to supply clock signals to the second circuit (101a) via the interconnect (115).
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
EP0827203A2 *22 Jul 19974 Mar 1998International Business Machines CorporationClock skew minimisation system and method for integrated circuits
EP1762943A1 *9 Sep 200514 Mar 2007SGS-THOMSON MICROELECTRONICS S.r.l.Chip-to-chip communication system
US5376825 *18 Nov 199327 Dec 1994Seiko Epson CorporationIntegrated circuit package for flexible computer system alternative architectures
US5818107 *17 Jan 19976 Oct 1998International Business Machines CorporationChip stacking by edge metallization
International ClassificationH01L25/065
Cooperative ClassificationH01L2225/06541, H01L2225/06513, H01L25/0657, H01L2924/0002
European ClassificationH01L25/065S
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