WO2009024761A3 - Stack of integrated circuits - Google Patents
Stack of integrated circuits Download PDFInfo
- Publication number
- WO2009024761A3 WO2009024761A3 PCT/GB2008/002770 GB2008002770W WO2009024761A3 WO 2009024761 A3 WO2009024761 A3 WO 2009024761A3 GB 2008002770 W GB2008002770 W GB 2008002770W WO 2009024761 A3 WO2009024761 A3 WO 2009024761A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- stack
- master clock
- integrated circuits
- circuits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A three-dimensional structure including a plurality of integrated circuits (101a-d) stacked substantially vertically one on top of another, said stack of circuits (101a-d) including first and second circuits (101a;113) located at different vertical levels in the stack, wherein the first circuit comprises a master clock circuit (113) that includes clock circuitry arranged to provide clock signals to a plurality of nodes (107) within the master clock circuit, and the structure includes at least one interconnect (115) that is arranged to connect one of the nodes (107) in the master clock circuit to a node (117) in the second circuit (101a), and the master clock circuit (113) is arranged to supply clock signals to the second circuit (101a) via the interconnect (115).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0716055A GB0716055D0 (en) | 2007-08-17 | 2007-08-17 | Vertical distribution of planar signals in stacked integrated circuits |
GB0716055.9 | 2007-08-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009024761A2 WO2009024761A2 (en) | 2009-02-26 |
WO2009024761A3 true WO2009024761A3 (en) | 2009-04-30 |
Family
ID=38566544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2008/002770 WO2009024761A2 (en) | 2007-08-17 | 2008-08-15 | Stack of integrated circuits |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB0716055D0 (en) |
WO (1) | WO2009024761A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9490787B1 (en) | 2015-06-11 | 2016-11-08 | Infineon Technologies Ag | System and method for integrated circuit clock distribution |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5376825A (en) * | 1990-10-22 | 1994-12-27 | Seiko Epson Corporation | Integrated circuit package for flexible computer system alternative architectures |
EP0827203A2 (en) * | 1996-08-20 | 1998-03-04 | International Business Machines Corporation | Clock skew minimisation system and method for integrated circuits |
US5818107A (en) * | 1997-01-17 | 1998-10-06 | International Business Machines Corporation | Chip stacking by edge metallization |
EP1762943A1 (en) * | 2005-09-09 | 2007-03-14 | STMicroelectronics S.r.l. | Chip-to-chip communication system |
-
2007
- 2007-08-17 GB GB0716055A patent/GB0716055D0/en not_active Ceased
-
2008
- 2008-08-15 WO PCT/GB2008/002770 patent/WO2009024761A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5376825A (en) * | 1990-10-22 | 1994-12-27 | Seiko Epson Corporation | Integrated circuit package for flexible computer system alternative architectures |
EP0827203A2 (en) * | 1996-08-20 | 1998-03-04 | International Business Machines Corporation | Clock skew minimisation system and method for integrated circuits |
US5818107A (en) * | 1997-01-17 | 1998-10-06 | International Business Machines Corporation | Chip stacking by edge metallization |
EP1762943A1 (en) * | 2005-09-09 | 2007-03-14 | STMicroelectronics S.r.l. | Chip-to-chip communication system |
Also Published As
Publication number | Publication date |
---|---|
GB0716055D0 (en) | 2007-09-26 |
WO2009024761A2 (en) | 2009-02-26 |
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