WO2009024761A2

WO2009024761A2 - Stack of integrated circuits

Info

Publication number: WO2009024761A2
Application number: PCT/GB2008/002770
Authority: WO
Inventors: Timothy James Regan
Original assignee: Timothy James Regan
Priority date: 2007-08-17
Filing date: 2008-08-15
Publication date: 2009-02-26
Also published as: GB0716055D0; WO2009024761A3

Abstract

A three-dimensional structure including a plurality of integrated circuits (101a-d) stacked substantially vertically one on top of another, said stack of circuits (101a-d) including first and second circuits (101a;113) located at different vertical levels in the stack, wherein the first circuit comprises a master clock circuit (113) that includes clock circuitry arranged to provide clock signals to a plurality of nodes (107) within the master clock circuit, and the structure includes at least one interconnect (115) that is arranged to connect one of the nodes (107) in the master clock circuit to a node (117) in the second circuit (101a), and the master clock circuit (113) is arranged to supply clock signals to the second circuit (101a) via the interconnect (115).

Description

Stack of Integrated Circuits

The invention relates to a three-dimensional structure including a plurality of integrated circuits stacked on top of each other.

Integrated circuits are typically produced on a single piece of silicon that comprises active and passive components and wires that connect these components together. These circuits are made up of a multitude of layers of silicon to produce the circuit's components. These components are connected through one or more layers of metal. Each metal layer is separated from the other metal layers and the silicon components by insulating layers. Where the wires need to connect to a component, or another wire, holes are made in the insulating layer and filled with metal to make the connection. These holes are commonly known in the industry as "vias".

Placing and connecting electrical components in large planar circuits places restrictions on the efficiency of the circuit design process. As a circuit gets larger, components are placed further apart from one another, thus causing delays in sending signals from one component to another and requiring the use of extra components such as buffers to boost signals where the connection causes the signal to degrade over a long distance.

A further problem occurs where special control signals called "clocks" are required to keep a circuit synchronised. The clock signal may be required to arrive and switch at many places across a large circuit at specific intervals. The clock signals are usually propagated through a circuit by means of a "clock tree" which comprises metal interconnects carrying the signals with buffers and inverters designed to boost these signals as they pass through the circuit. By constructing the circuit in this way, an initial clock pulse is split and replicated many times throughout a circuit to ensure that it arrives at its final destinations at a desired time.

Additionally, clock signals may connect to a repeated structure such as a memory which may require a refresh signal at regular intervals.

A circuit may require a multitude of clocks as well as other control signals such as reset or sleep signals that must be propagated throughout the integrated circuit in a similar manner. Integrating these special signals with the rest of the circuit's components is a complex task that requires powerful design tools and skilled engineering knowledge.

As circuits become larger, more and more layers of metal are required to carry the signals around the circuit. Complex chips may comprise ten or more layers of metal interconnect to allow the various signals to be propagated. Furthermore, the circuitry required to make the clock efficient and arrive at other components at the correct time is complex and places extra burdens on the performance and power consumption of the overall system. These and other control signals may come to comprise a large proportion of the finished circuit, making the integrated circuit larger thereby causing it to consume extra power.

Once the integrated circuit has been manufactured, it will usually be connected with other circuits and placed into a larger system. The individual integrated circuit may be connected through a variety of means such as bond wires, solder bumps or other methods of connection.

In order to alleviate some of the problems of large planar integrated circuits, some systems have been created which comprise of individual circuits placed one on top of another in a stack. This is often referred to in the microchip industry as three-dimensional integration or a three-dimensional stack of circuits. This has the advantage of reducing the distance that must be travelled by individual signals in a horizontal plane to the external connection points of a circuit by allowing signals to be connected between the stacked circuits vertically. The connections between the stacked circuits can be joined using vertical connections such as "through silicon vias" or "TSVs" or other methods of vertical connection. The vertical connections are used to connect signals in the same way as planar signals in a circuit.

The advantage gained in a three-dimensional circuit is that the vertical connections between the circuits in the stack are shorter than the horizontal connections in a large planar circuit. This makes the distribution of signals more efficient.

By arranging circuits in these stacks, systems may be made smaller and faster by integrating many integrated circuits in to a single package by stacking them one upon another. Some signals may only be required in one circuit in the stack but others may be sent throughout the stack in the vertical plane by means of TSVs or other vertical connections. Also, there is no restriction on the number of circuits that can be placed in a three-dimensional stack or the types of components and connections they contain. Traditional circuit design methodologies require each circuit in the stack to have its own clock tree. These are integrated within each circuit in the stack and may also need to be synchronised with other circuits, which is a complex task. The creation and integration of clocks within three-dimensional circuits presents a major challenge to the system designer.

Accordingly the invention seeks to provide a structure that mitigates at least one of the above- mentioned problems or to at least provide an alternative to known structures.

According to one aspect of the invention there is provided a three-dimensional structure including a plurality of integrated circuits stacked substantially vertically one on top of another, said stack of circuits including first and second circuits located at different vertical levels in the stack, wherein the first circuit comprises a master clock circuit that includes clock circuitry arranged to provide clock signals to a plurality of nodes within the master clock circuit, and the structure includes at least one interconnect that is arranged to connect one of the nodes in the master clock circuit to a node in the second circuit, and the master clock circuit is arranged to supply clock signals to the second circuit via the interconnect.

The invention eliminates the requirement for separate clock trees and clock components within each other circuit in the stack that receives the clock signals. This improves the overall system by reducing the complexity of the clocks in the total system and reduces the power the system consumes. It also relieves the system designer from the burden of creating and integrating a clock tree for each circuit in the stack. Thus for at least some of the circuits in the stack, the master clock circuit is the sole provider of clock signals thereto.

In preferred embodiments the clock circuitry includes a clock signal generation circuit and a clock tree connected to the clock signal generation circuit that is arranged to distribute the clock signals across the master clock circuit. The nodes are the points at which the interconnects connect with the clock tree, which is typically at the ends of clock tree branches, which are known as gates. Clock signals may also be connected to transistors in repeated structures such as memory circuits. The clock signals are propagated vertically through the stack via the interconnects, such as Through Silicon Vias (TSVs) or other vertical connections, which connect clock signal supply nodes in the master clock circuit with clock signal receiving nodes in at least one of the other circuits. The clock tree in the master clock circuit can be created without the need to consider other components in the overall system, thereby allowing it to be arranged symmetrically across the whole of the master clock circuit. This is distinct from clock tree distribution in a single planar circuit wherein the clock components must be accommodated amongst the other circuitry in the system.

Advantageously the clock signals for at least some of the nodes in the master clock circuit are synchronised. The clock tree in the master clock circuit provides a multiplicity of clock signal supply nodes across the master clock circuit that are in the same phase and that can distribute synchronised clock signals to clock signal receiving nodes in at least one other circuit in the stack, and preferably a plurality of circuits. Advantageously the clock signals for all of the nodes in the master clock circuit can be synchronised. Advantageously the clock receiving nodes in the other circuits in the stack are synchronised with the nodes in the master clock circuit to which they are connected. Advantageously, multiple clocks of varying frequency and phase can be generated and distributed in this manner.

The second circuit includes circuitry arranged to distribute the clock signals received from the master clock circuit to those components within the second circuit requiring the clock signal. The signals can be distributed by wires, passive components and/or active components. The second circuit can include means for modifying the clock signal received from the master clock circuit. For example, the circuitry can be arranged to subdivide the clocks with different frequencies and supply the modified clock signals to components within the second circuit that require the modified clock signals.

The stack of circuits can include a third circuit located at a different vertical level in the stack from the master and second circuits, and the structure includes at least one interconnect for connecting one of the nodes in the master clock circuit to a node in the third circuit, and wherein the master clock circuit is arranged to supply clock signals to the third circuit via the interconnect. Advantageously the clock signals provided to the second and third circuits can be synchronised.

Advantageously the structure can include a plurality of interconnects for connecting a plurality of nodes in the master clock circuit to a plurality of nodes in at least one of the other circuits in the stack. For example, a plurality of nodes in the master clock circuit can be connected to a plurality of nodes in the second and / or third circuits. This enables the clock signals to be provided to a number of different nodes within each clock signal receiving circuit. Preferably a substantial proportion of the circuits in the stack are connected to nodes in the master clock circuit by interconnects and the master clock circuit is arranged to supply clock signals to each of the circuits via the interconnects. For example, between 40 to 100% of the circuits in the stack are connected to the master clock circuit and are arranged to receive clock signals therefrom. In some embodiments all of the stacked circuits are connected to nodes in the master clock circuit by interconnects and the master clock circuit is arranged to supply clock signals to each of the circuits via the interconnects. Advantageously the clock signals provided to all of the circuits in the stack are synchronised with the master clock circuit. Local distribution of the clock signals within the circuits provides a means of timing or control of the whole stack from the master clock circuit containing the origin of the signals.

The interconnects for connecting circuits at different vertical levels in the stack are arranged substantially vertically. This provides the shortest paths between the nodes. Advantageously at least some of the interconnects can be arranged to pass vertically through another circuit in the stack with or without connecting to that circuit. At least some of the interconnects may comprise vertical connections. The master clock circuit includes upper and lower surfaces and the nodes are provided on the upper and/or lower surfaces for connection with the interconnects. Interconnects within each of the circuits in the stack are arranged substantially horizontally.

Advantageously the clock circuitry can include a Phase Lock Loop (PLL) circuit for generating the clock signals. Alternatively, any other suitable type of clock generation circuit may be used for the master clock circuit. The master clock circuit includes active and/or passive components and wires connecting the components together in the required arrangements. The master clock circuit is arranged to produce pulsed or static clock signals.

The master clock circuit may include a power supply system and the structure includes power interconnects for connecting the master clock circuit to at least one of the other circuits in the stack, and the master clock circuit is arranged to supply power to the or each circuit in the stack that is connected thereto by the power interconnects. The power supply can be connected to a plurality of circuits in the stack and may be connected to all of the circuits in the stack. The master clock circuit may include control systems and the structure includes control interconnects for connecting the master clock circuit to at least one of the other circuits in the stack, and the master clock circuit is arranged to supply control signals to the or each circuit in the stack that is connected thereto by the control interconnects. The master clock circuit may be manufactured independently of the other circuits in the integrated circuit stack and need not be dependent on them for its creation. Likewise, each circuit in the stack may be made independently of all other circuits and may share common connections to the master clock circuit or discrete connections at any point.

Advantageously the master clock circuit can be placed anywhere in the stack of circuits. Preferably the master clock circuit is arranged within the middle third of the stacked circuits or towards the upper or lower end. Preferably the master clock circuit is arranged centrally within the stack since in some applications this can minimise the length of the interconnects. The master clock circuit does not need to be placed on, nor be dependent on, a single substrate layer.

The master clock circuit may include a second clock circuit arranged to provide a second clock signal that is different from the first clock signal generated by the first clock circuit, and is arranged to provide synchronised clock signals to a plurality of nodes in the master clock circuit, wherein the structure includes at least one interconnect for supplying the second clock signal to at least one of the other circuits in the stack. This enables the master clock circuit to provide additional clock signals to parts of the stack requiring it, for example in more complex designs.

Embodiments of the invention will now be described in detail, by way of example only, and with reference to the accompanying drawings, in which:

Figure 1 shows diagrammatically a horizontal chip layout (prior art);

Figure 2 shows diagrammatically the arrangement of Figure 1 broken down into four chips (prior art);

Figure 3 shows diagrammatically the four chips of Figure 2 arranged in a stack to form a three-dimensional structure (prior art); Figure 4 shows diagrammatically a first embodiment of the invention;

Figure 5 shows diagrammatically the clock circuit for the first embodiment; and

Figures 6 shows diagrammatically a second embodiment of the invention.

Figure 1 shows a diagrammatic representation of a large planar circuit 1 containing a clock tree 3 generated by a phase lock loop circuit 5 with the output signals from this circuit 5 distributed through the whole system using buffer components (not shown) and interconnecting wires. Having integrated circuits arranged in this way is common practice.

It is also known in the art to split large planar circuits 1 into smaller circuits and to stack them on top of each other in order to produce a three dimensional semi-conductor structure. This leads to a more compact arrangement. Figure 2 shows the large planar circuit 1 of Figure 1 broken down in to four circuits la-d. Each circuit la-d has its own individual clock tree 3a-d driven by its own phase lock loop (PLL) circuit 5a-d. The clock trees 3a-d are shown greatly simplified for the sake of clarity. The connections shown pass through buffer circuits (not shown) to boost the signals to the gates 7a-d at the end of each branch 9a-d. Each clock tree 3a-d is balanced to ensure that the signal at each gate 7a-d is even across the whole circuit, thus keeping the clock signal in phase and minimising clock skew.

The phase lock loop circuit 5a-d in each chip la-d is independent of the others, even if they share the same frequency. Clock components may take up to 40% of a finished chip and are very complex to design and balance.

Figure 3 shows the four circuits la-d stacked on top of each other to make the three- dimensional system. The gaps between the circuits are expanded for clarity. The components in each circuit la-d are mounted on substrates l la-d. The substrate l la-d of each chip is bonded to the substrate 1 la-d of each adjacent chip 1 la-d. Any connections required between the chips la-d may be made by Through Silicon Vias (TSVs) (not shown).

Figures 4 and 5 show a first embodiment of the invention that includes a stack of integrated circuits including a master clock circuit 113 containing a balanced clock tree 103 that has been generated from a single phase lock loop circuit 105 and then distributed across the master clock circuit 113 and four other circuits 101a-d arranged to receive clock signals from the master clock circuit 113. When compared with the prior art arrangement shown in Figure 3, it can be seen that the clock tree 103 in the master clock circuit 113 replaces the separate clock circuits 5a-d,3a-d from the circuits la-d.

The tree structure 103 includes an arrangement of branches 109 that extend across the surface of the master clock circuit 113 and that terminate in gates 107.

TSVs 115 in the stack distribute the clock signals vertically from the master clock circuit 113 to each of the other circuits 101a-d in the stack requiring those signals. Typically, the TSVs 115 are connected to the clock tree 103 at the gates 107 and they connect to gates 117 in the clock signal receiving circuits 101a-d. For some circuits 101a-d, multiple vertical connections 115 are provided such that clock signals from the master circuit 113 can be provide to multiple positions within the clock receiving circuits 101a-d. Connections may be made vertically from the top circuit in the stack, the master clock circuit 113 in the arrangement shown in Figure 4, to the circuit 1 Old at the bottom of the stack, where required. The clock signals received from the master clock circuit 113 can be further distributed horizontally through the receiving circuits 101a-d as required. The receiving circuits 101a-d can also include circuitry such as dividers, inverters and buffers for modifying the clock signals received from the master circuit 113 to meet the requirements of components within the circuit.

The clock signals provided to each of the gates 107 have the same phase. Clock signals can be taken from the master circuit 113 wherever they are required and arrive in the same phase as the master circuit 113. All branches 109 of the master circuit 113 do not need to be distributed to the other circuits 10 la-d in the stack. Furthermore, it is not necessary for every vertical connection 115 to connect to each of the circuits within the stack.

This invention has a variety of benefits for stacked integrated circuit design, including:

1. The circuit area is reduced in the integrated circuits in the stack that receive clock signals 101a-d from the master clock circuit 113, since they do not include their own clock circuitry thereby reducing the cost of manufacture for each of those circuits.

2. The circuit performance for each integrated circuits 101a-d in the stack that receive clock signals 101a-d from the master clock circuit 113 is improved by a smaller die size. 3. The circuit performance for each integrated circuit in the stack that receives clock signals 101a-d from the master clock circuit 113 is improved by having a synchronised and balanced clock available across the whole area of the circuit.

4. The circuit construction for each integrated circuit in the stack that receives clock signals 101a-d from the master clock circuit 113 is simplified by removing the need for creating clock trees within each circuit in the stack.

5. The power consumed by each integrated circuit in the stack that receives clock signals 101a-d from the master clock circuit 113 is reduced by eliminating duplicated circuitry that controls clock and other functions.

6. The power consumed by the overall system is reduced.

The master clock circuits can be designed and manufactured independently from the other circuits in the stack. They can be made as standard parts for use in a variety of stacked integrated circuits.

It will be apparent to the skilled person that modifications can be made to the above embodiment that fall within the scope of the invention, for example the master clock circuit

113 can contain additional clocks or other signals, such as additional phase lock loop circuits.

These signals can be propagated vertically through the stack by TSVs to at least one other circuit 101a-d in the stack. The circuitry for these signals may be developed and constructed on the master clock circuit substrate independently from the other circuits. When this master clock circuit 113 is placed in the stack, these signals may connect to any other chip via vertical connections.

The master clock circuit 113 can include other control circuits such as reset or sleep signals and control signals can be propagated vertically through the stack by the vertical connections to at least one of the other circuits 101a-d in the stack. Similarly, the master clock circuit 113 can include a power supply system and power can be supplied from the master clock circuit 113 to at least one of the other circuits 101a-d in the stack via vertical connections.

The position of each circuit in the stack is often arbitrary. The master clock circuit and other chip can be placed in any position within the stack. In some instances there may be some overall benefit to the structure by arranging the stack in a particular order, for example by having the master circuit located substantially centrally within the stack (see second embodiment in Figure 6) since this may reduce the lengths of some of the vertical connections.

Apart from the relative positions of the circuits 201a-d,213 in the stack, the arrangement and the method of operation of the embodiment shown in Figure 6 is similar to that shown in Figures 4 and 5. Figure 6 also shows the vertical connections 215 passing through circuits 201b,201c,213 (shown as ref 217).

Claims

1. A three-dimensional structure including a plurality of integrated circuits stacked substantially vertically one on top of another, said stack of circuits including first and second circuits located at different vertical levels in the stack, wherein the first circuit comprises a master clock circuit that includes clock circuitry arranged to provide clock signals to a plurality of nodes within the master clock circuit, and the structure includes at least one interconnect that is arranged to connect one of the nodes in the master clock circuit to a node in the second circuit, and the master clock circuit is arranged to supply clock signals to the second circuit via the interconnect.

2. A three-dimensional structure according to claim 1, wherein the clock signals for at least some of the nodes in the master clock circuit are synchronised.

3. A three-dimensional structure according to claim 1 or 2, wherein the second circuit includes circuitry arranged to distribute the clock signals received from the master clock circuit to those components requiring the clock signal within the second circuit.

4. A three-dimensional structure according to any one of the preceding claims, wherein the second circuit includes means for modifying the clock signal received from the master clock circuit.

5. A three-dimensional structure according to any one of the preceding claims, wherein the stack of circuits includes a third circuit located at a different vertical level in the stack from the master and second circuits, and the structure includes at least one interconnect for connecting one of the nodes in the master clock circuit to a node in the third circuit, and wherein the master clock circuit is arranged to supply clock signals to the third circuit via the interconnect.

6. A three-dimensional structure according to any one of the preceding claims, including a plurality of interconnects for connecting a plurality of nodes in the master clock circuit to a plurality of nodes in at least one of the other circuits in the stack. For example, a plurality of nodes in the master clock circuit can be connected to a plurality of nodes in the second and / or third circuits.

7. A three-dimensional structure according to any one of the preceding claims, wherein a substantial proportion of the circuits in the stack are connected to nodes in the master clock circuit by interconnects and the master clock circuit is arranged to supply clock signals to each of those circuits via the interconnects.

8. A three-dimensional structure according to claim 7, wherein all of the stacked circuits are connected to nodes in the master clock circuit by interconnects and the master clock circuit is arranged to supply clock signals to each of the circuits via the interconnects.

9. A three-dimensional structure according to any one of the preceding claims, wherein the interconnects for connecting circuits at different vertical levels in the stack are arranged substantially vertically.

10. A three-dimensional structure according to any one of the preceding claims, wherein at least some of the interconnects comprise through silicon vias (TSVs) or other vertical connections.

11. A three-dimensional structure according to any one of the preceding claims, wherein the clock circuitry includes a Phase Lock Loop (PLL) or other clock generation circuit.

12. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit includes upper and lower surfaces and the nodes are provided on the upper and/or lower surfaces.

13. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit is arranged to produce pulsed or static clock signals.

14. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit includes a power supply system and the structure includes power interconnects for connecting the master clock circuit to at least one of the other circuits in the stack, and the master clock circuit is arranged to supply power to the or each circuit in the stack that is connected thereto by the power interconnects.

15. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit includes control systems and the structure includes control interconnects for connecting the master clock circuit to at least one of the other circuits in the stack, and the master clock circuit is arranged to supply control signals to the or each circuit in the stack that is connected thereto by the control interconnects.

16. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit is arranged within the middle third of the stacked circuits, and preferably centrally.

17. A three-dimensional structure according to any one of the preceding claims, wherein the master clock circuit includes a second clock circuit arranged to provide a second clock signal that is different from the first clock signal generated by the first clock circuit, and is arranged to provide synchronised clock signals to a plurality of nodes in the master clock circuit, wherein the structure includes at least one interconnect for supplying the second clock signal to at least one of the other circuits in the stack.