WO2009021176A3 - Urgency and time window manipulation to accommodate unpredictable memory operations - Google Patents

Urgency and time window manipulation to accommodate unpredictable memory operations Download PDF

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Publication number
WO2009021176A3
WO2009021176A3 PCT/US2008/072609 US2008072609W WO2009021176A3 WO 2009021176 A3 WO2009021176 A3 WO 2009021176A3 US 2008072609 W US2008072609 W US 2008072609W WO 2009021176 A3 WO2009021176 A3 WO 2009021176A3
Authority
WO
WIPO (PCT)
Prior art keywords
urgency
time window
memory operations
window manipulation
unpredictable memory
Prior art date
Application number
PCT/US2008/072609
Other languages
French (fr)
Other versions
WO2009021176A9 (en
WO2009021176A2 (en
Inventor
James J Tringali
Sergey A Gorobets
Shai Traister
Yosief Ataklti
Original Assignee
Sandisk Corp
James J Tringali
Sergey A Gorobets
Shai Traister
Yosief Ataklti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/864,793 external-priority patent/US8046524B2/en
Application filed by Sandisk Corp, James J Tringali, Sergey A Gorobets, Shai Traister, Yosief Ataklti filed Critical Sandisk Corp
Publication of WO2009021176A2 publication Critical patent/WO2009021176A2/en
Publication of WO2009021176A3 publication Critical patent/WO2009021176A3/en
Publication of WO2009021176A9 publication Critical patent/WO2009021176A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption.
PCT/US2008/072609 2007-08-08 2008-08-08 Urgency and time window manipulation to accommodate unpredictable memory operations WO2009021176A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US95469407P 2007-08-08 2007-08-08
US60/954,694 2007-08-08
US11/864,793 US8046524B2 (en) 2007-08-08 2007-09-28 Managing processing delays in an isochronous system
US11/864,793 2007-09-28
US11/864,740 US8099632B2 (en) 2007-08-08 2007-09-28 Urgency and time window manipulation to accommodate unpredictable memory operations
US11/864,740 2007-09-28

Publications (3)

Publication Number Publication Date
WO2009021176A2 WO2009021176A2 (en) 2009-02-12
WO2009021176A3 true WO2009021176A3 (en) 2009-04-16
WO2009021176A9 WO2009021176A9 (en) 2009-05-28

Family

ID=40053180

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/072609 WO2009021176A2 (en) 2007-08-08 2008-08-08 Urgency and time window manipulation to accommodate unpredictable memory operations

Country Status (1)

Country Link
WO (1) WO2009021176A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8046524B2 (en) 2007-08-08 2011-10-25 Sandisk Technologies Inc. Managing processing delays in an isochronous system
JP2012252558A (en) * 2011-06-03 2012-12-20 Sony Corp Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques
US20060101210A1 (en) * 2004-10-15 2006-05-11 Lance Dover Register-based memory command architecture
US20060161728A1 (en) * 2005-01-20 2006-07-20 Bennett Alan D Scheduling of housekeeping operations in flash memory systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques
US20060101210A1 (en) * 2004-10-15 2006-05-11 Lance Dover Register-based memory command architecture
US20060161728A1 (en) * 2005-01-20 2006-07-20 Bennett Alan D Scheduling of housekeeping operations in flash memory systems

Also Published As

Publication number Publication date
WO2009021176A9 (en) 2009-05-28
WO2009021176A2 (en) 2009-02-12

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