WO2009002905A1 - Array-molded package-on-package having redistribution lines - Google Patents

Array-molded package-on-package having redistribution lines Download PDF

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Publication number
WO2009002905A1
WO2009002905A1 PCT/US2008/067842 US2008067842W WO2009002905A1 WO 2009002905 A1 WO2009002905 A1 WO 2009002905A1 US 2008067842 W US2008067842 W US 2008067842W WO 2009002905 A1 WO2009002905 A1 WO 2009002905A1
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WO
WIPO (PCT)
Prior art keywords
mold
substrate
metal
grooves
pad
Prior art date
Application number
PCT/US2008/067842
Other languages
French (fr)
Inventor
Mark A. Gerber
David N. Walter
Original Assignee
Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Publication of WO2009002905A1 publication Critical patent/WO2009002905A1/en

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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/5317—Laminated device

Definitions

  • This relates in general to the field of semiconductor devices and processes; and, more specifically, to the structure and fabrication method of low-profile, vertically integrated package-on-package integrated circuit assemblies having redistribution lines.
  • the thickness of the package-on-package products as the simple sum of the thicknesses of the semiconductor chips, electric interconnections, and encapsulations is often unacceptably large, especially for hand-held wireless equipments.
  • the products run increasingly into warpage problems caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the plastic substrates, the molding compound, the solder balls, and the printed circuit board. Warpage can lead to some of the most debilitating problems encountered by semiconductor assemblies such as the fracture and separation of solder joints, or the separation of materials followed by moisture ingress.
  • CTE coefficients of thermal expansion
  • the invention provides an electrical routing level outside of the insulating substrate or the leadframe, thus providing the additional routing without adding a metallization level to the thickness of the package.
  • One embodiment of the invention is a semiconductor device with a sheet- like insulating substrate integral with two or more patterned layers of conductive lines and vias, a chip or a stack of chips attached to an assembly site, and contact pads in pad locations.
  • An encapsulated region is on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures at the pad locations for external communication with the pad metal surfaces.
  • the apertures may have not- smooth sidewall surfaces and may be filled with solder material to contact the pads.
  • Surface grooves in the encapsulated region which have smooth bottom and sidewalls and are filled with metal, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.
  • electrical parts such as passive components may be attached to the redistribution lines.
  • Another embodiment of the invention is a mold with top and bottom portions, wherein the top portion forms a cavity for placing semiconductor devices.
  • the device includes a semiconductor chip attached to a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, and contact pads in pad locations.
  • the top mold portion of the mold includes protrusions and recesses; the protrusions are at locations matching the pad locations, and are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold.
  • inserts made of aluminum or steel with ridges operable to create surface grooves in the molded package; in addition, there may be a compliant film inserted in each recess between the top portion and the insert to prevent molding compound from bleeding during the molding operation. Alternatively, a continuous compliant film may cover the top portion surface, including the recesses, to cushion the inserts.
  • the bottom mold portion is without corresponding protrusions and recesses.
  • a semiconductor chip is attached to a sheet-like insulating substrate, preferably integral with two or more patterned layers of conductive lines and vias, and contact pads in pad locations.
  • a mold is provided, which has a top portion with protrusions and recesses; the protrusions are at locations matching the pad locations; placed in the recesses are inserts with ridges operable to create surface grooves in the molded package.
  • the bottom mold portion is without corresponding protrusions.
  • the substrate with the chip is loaded onto the bottom mold portion; the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface.
  • the mold After pressuring molding compound into the cavity to fill the cavity and thereby create an encapsulation, the mold is opened.
  • the encapsulation has apertures to the pad locations and surface grooves (with smooth sidewalls and bottom) extending between selected apertures. Any residual compound may be removed from the pads, and the apertures filled with solder. Further, the grooves may be filled with a metal such as copper, thereby creating routing interconnections between selected apertures.
  • the cavity direct injection mold technique or the liquid compression mold technique may be employed.
  • FIGS. IA to 7 illustrate certain process steps for fabricating an array-molded semiconductor device according to an embodiment of the invention.
  • FIG. IA is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by wire bonding.
  • FIG. IB is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by flip-chip technology.
  • FIG. 1C is a schematic cross section of a sheet-like substrate with contact pads and a plurality of chips flip-assembled for array processing.
  • FIG. 2A shows a schematic cross section of the top portion of an exemplary mold with structural features and inserts according to the invention.
  • FIG. 2B shows a schematic cross section of the top portion of an exemplary mold intended for array-molding with structural features and inserts according to the invention.
  • FIG. 3A shows a schematic cross section of the bottom portion of a mold.
  • FIG. 3B shows a schematic cross section of the bottom portion of a mold intended for array-molding.
  • FIG. 4 illustrates a schematic cross section of the open mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
  • FIG. 5 shows a schematic cross section of the closed mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
  • FIG. 6A illustrates a schematic cross section of a molded semiconductor array after removal from the mold.
  • FIG. 6B shows a magnified schematic cross section of a molded unit after removal from the mold and singulation from the array, displaying the grooves in the encapsulation according to the invention.
  • FIG. 7 is a schematic cross section of a discrete device after removing any molding compound from the contact pads, filling an aperture with solder, filling the grooves with metal and attaching solder bodies for external communication.
  • FIG. 8A shows a schematic cross section of a finished array with features according to the invention.
  • FIG. 8B depicts a schematic top view of a finished array, molded according to the invention, before singulation.
  • FIG. 8C shows a schematic perspective view of a discrete unit singulated from the molded array with features according to the invention.
  • FIG. 9 illustrates a schematic cross section of another embodiment of the invention, wherein a second semiconductor device with solder bodies is attached to the first device (with redistribution lines) so that the aperture-exposed pads of the first device are contacted by the solder bodies of the second device, creating a customized package-on-package semiconductor assembly.
  • FIGS. IA through 7 illustrate schematically the steps of one embodiment of the invention, a method for array-molding semiconductor devices.
  • the steps shown in FIGS. IA and IB show the attachment and assembly of a semiconductor chip on a substrate by wire bonding (FIG. IA) and by flip-chip technology (FIG. IB);
  • FIG. 1C exemplifies a portion of an array of chips attached by flip-chip.
  • a sheet-like substrate 101 with insulating core for example, plastic, glass-fiber reinforced, ceramic
  • insulating core for example, plastic, glass-fiber reinforced, ceramic
  • Substrate 101 has a first surface 101a and a second surface 101b, and a preferred thickness range from 0.05 to 0.5 mm.
  • the first surface 101a includes chip assembly sites 102 and contact pads 103 in pad locations.
  • the metal of the contact pads is preferably copper with a solderable surface (for example, including a layer of gold or palladium).
  • Second surface 101b also has pads 112 with a solderable surface.
  • a plurality of semiconductor chips 130 is provided. In order to attach and electrically connect the chips, they are assembled on each assembly site either by adhesive attachment and wire bonding, or by flip-chip connection.
  • the connecting metal bumps 140 may be made of solder, gold, or copper.
  • FIG. IB illustrates the possibility, to assemble a stack of two or more chips on substrate 101.
  • both the techniques of flip-chip and wire bond may have to be employed; in emerging technology, also through- semiconductor vias (TSVs, metal-filled vias) may be employed.
  • TSVs through- semiconductor vias
  • a mold made of steel or another suitable material which allows the encapsulation of a single device or of an array of devices.
  • the mold has a top portion and a bottom portion; the top portion is manufactured to form a cavity for holding semiconductor devices.
  • the top portion included protrusions and recesses; the bottom portion is without corresponding protrusions.
  • the top portion is intended to process a single device and is designated 201; in FIG. 2B, the top portion is constructed for an array of devices to be processed together as a batch.
  • the bottom portion is intended to process a single device and is designated 301; in FIG.
  • the bottom portion is constructed for an array of devices to be processed together.
  • the top portion 201 includes protrusions 202 at locations matching the pad locations of the device shown in FIG. IA and IB; the bottom portion 301 is without corresponding protrusions.
  • the protrusions are preferably shaped as truncated cones, with the cone surface angled within a preferred range from about 10 to 30 degrees from vertical. The angle is designated 202a in FIG. 2A.
  • the protrusions preferably may have a ridge 203, which may extend along the whole angled side of the cone. Ridge 203 is operable to create a groove or channel in the molded part, which may provide release of gas in the solder ball attachment process, or help in the solder paste reflow process.
  • the height 202b of the protrusion is selected to be suitable to approach the substrate pad metal (103 in FIGS. IA and IB) in the closed mold.
  • the protrusion should approach the pad metal surface in the closed mold to a distance between 0 and about 100 ⁇ m. More preferably, height 202b of the protrusion is sufficient to touch the pad metal surface in the closed mold.
  • the bottom portion 301 in FIG. 3 A and 310 in FIG. 3B of the mold has no protrusions; it is featureless and preferably flat. For some individual devices, it may be an advantage to recess a portion outlined by length 302 and depth 303 sufficient to accommodate the substrate of a discrete device, but for array processing, a featureless flat bottom mold portion is preferable.
  • top portion 201 has inserts 230, which are individually manufactured to fit into the respective recess. They are preferably made of aluminum, steel, or invar so that they can withstand the temperatures and pressures during the molding operation without jamming.
  • the surfaces of the inserts are smooth.
  • Selected inserts have ridges 231, also with smooth surfaces, operable to create surface grooves in the molded package.
  • the preferred height of these ridges is between about 10 and 100 ⁇ m. In terms of cross section, the ridges may be rectangular, triangular, or rounded.
  • the grooves molded by the ridges 231 will have the mirror- image cross sections of the ridges, such as rectangular, triangular, or rounded, and also will have the smooth surfaces of the ridges. In either case, the grooves will be filled with metal such as copper (see below) in order to create conductive redistribution lines between selected apertures to the contact pads. Consequently, it is a technical advantage of the invention that these inserts can be exchanged between molding runs in order to create any desired redistribution pattern of the connection lines in the molded product. This degree of freedom allows a wide choice in selecting semiconductor devices to be joined with the device packaged in the mold of FIGS. 2A and 3A.
  • FIG. 2B illustrates the inserts 230 in each recess of a top mold 210 intended for molding an array.
  • film 232 is positioned between the material of mold 201 and the inserts 230 to prevent bleeding of molding compound during the molding operation.
  • film 232 is adhesive; it is preferably made of heat-tolerant and pressure-tolerant silicone or polymers such as kapton in the thickness range between 15 and 500 ⁇ m.
  • pieces of the compliant, chemically inert, preferably adhesive film 232 may be inserted into each recess.
  • the substrate 101 with the assembled chips 130 is loaded onto the bottom mold portion 310.
  • the second substrate surface 101b is rested on mold portion 310, and the first substrate surface 101a with the contact pads 103 is positioned away from the bottom mold portion 310.
  • Protrusions 202 of the top mold portion 210 are aligned with the respective contact pads 103 of substrate 101.
  • FIG. 5 shows the next process step of closing the mold by clamping the top portion 210 onto the bottom portion 310 so that the protrusions 202 are aligned with the contact pads 103, approaching or touching the pad surface.
  • the top portion 210 resting on the flat bottom portion 310 forms the cavity of the mold for holding the semiconductor devices.
  • the protrusions touch the contact pads; however, material or alignment tolerances may cause a residual distance between 0 and about 100 ⁇ m between the protrusion and the respective pad.
  • FIG. 5 also shows the respective ridge 203 for each protrusion 202 and the inserts 230 with the compliant film 232 over the protrusions-and-recess surface of top portion 210.
  • encapsulation material such as epoxy-based and filler-loaded molding compound is pressured into the cavity to fill the cavity; the runners for supplying the compound, and the gates needed for entering the cavity and controlling the compound flow, are not shown in FIG. 5.
  • encapsulations for the devices of the array are created.
  • FIG. 6A illustrates the encapsulated array
  • FIG. 6B shows an enlarged view of one unit.
  • compound 601 is fully polymerized.
  • the thickness of the molded encapsulation is between 0.2 and 0.7 mm.
  • the encapsulation has apertures 603 to the pad locations.
  • FIGS. 6A and 6B and the top view of FIG. 8C show, the encapsulation has surface grooves 630 extending between selected apertures. Grooves 630 have smooth bottom and sidewalls.
  • the cavity direct injection molding technique or the liquid compression molding technique may be employed. These techniques also use a plastic film similar to film 232 in FIGS. 2A, 2B and 4, held to the top mold portion by vacuum suction.
  • the recesses in the top mold portion are individually operated by spring-loaded movable pistons, creating individual floating cavities.
  • the application of the metal inserts in the recesses according to the invention is analogous to the application of the inserts depicted in FIG. 4.
  • FIG. 6B indicates by dashed contour 602 any residual encapsulation formed on the contact pads 103. These thin deposits (thickness 602a between 0 and about 100 ⁇ m) have to be removed to expose the clean metal surface of pad 103. At least three methods are suitable to remove these unwanted encapsulation layers.
  • the first method employs drilling or vaporizing by laser light. A focused laser beam shines into the encapsulation aperture 603, removes the compound layer while forming particles 604 in a thermal process, and deposits these particles on the otherwise smooth sidewalls 603a; particles 604 attest to the thermal process used to clean up the pads.
  • the second method employs a plasma clean-up process; the plasma leaves a roughened surface 605 on the aperture sidewalls 603a.
  • the third method employs a chemical etch process, which leaves a surface structure 606 recognizable by one skilled in the art. All three methods are material-sensitive and thus controllable to stop at the metal surface of the contact pads.
  • the grooves 630 in the encapsulation surface are filled with metal 710, preferably copper, whereby electrically conductive routing interconnections between the apertures are created.
  • metal 710 preferably copper
  • the preferred method includes the steps of plasma cleaning the encapsulation surface; depositing, by electroless plating or by sputtering, a metal layer (for example copper) on the encapsulation surface including the grooves; electrolytically plating metal up to the thickness sufficient to fill the grooves; and grinding the encapsulation surface to remove the metal from the surface except the grooves.
  • An alternative method includes the steps of plasma cleaning the encapsulation surface; screen printing metal into the grooves, or instance copper; and reflowing the screened metal.
  • reflow bodies such as solder balls 701 are attached to the attachment pads 112 (see FIGS. IA and IB) on the second substrate surface 101b.
  • This step is illustrated in FIG. 7, showing a magnified portion of the array (it should be noted that in the example of FIG. 7, wire bonding has been employed to assemble the chip on the first substrate surface 101a).
  • the mold apertures 703 may be filled with solder paste 704, which contacts the surface of pad metal 103.
  • grooves 705 may help to separate the flux-rich part form the solder-rich part.
  • FIGS. 8A, 8B, and 8C depict the singulation step.
  • the dashed lines 801 in the cross section of FIG. 8A), 802 and 803 (in the top view of FIG. 8B) indicate saw lines of saws, which cut through the substrate 101 and the mold compound 601 to singulate discrete units from the sheet-like substrate of the array. Due to the sawing process step, the individual units have recognizable saw marks on their sides.
  • the perimeter of unit 800 is designated 820.
  • the illustration emphasizes the apertures 703 reaching through the thickness of the encapsulation 801 to the contact pads, but omits the encapsulated assembled chip for clarity reasons; in addition, the gas release channels 810 have been omitted for all apertures except for one row of apertures.
  • the surface 801a of the encapsulation includes the metal- filled routing interconnections 830 of the redistribution grooves.
  • FIG. 8C further indicates the opportunity provided by the redistribution lines, after being filled with metal, to attach additional electrical parts such as passive components on the surface of device 800.
  • part 840 is a passive component attached to two adjacent metal-filled grooves.
  • the invention Based on the metal-filled redistribution lines 830 on the surface of the molding compound, the invention provides an electrical routing level outside of the insulating substrate or the leadframe, thus providing the additional routing without adding a metallization level to the thickness of the package.
  • FIG. 8C further indicates the opportunity to add an insulating film 850 over surface of device 800.
  • the film is preferably made of a plastic material, which can tolerate the high temperatures encountered in solder attachment processes.
  • the film has holes in the locations of the openings 703, which need to be available for solder attachment.
  • the film offers the opportunity to add device symbolization to the top of unit 800. Typically, such symbolization informs about the type of device, electrical characteristics, year and location of manufacturing, producer, etc.
  • a first semiconductor package 901, with assembled chip 901b is manufactured as described above, including the copper- filled redistribution lines 940 and apertures 941, and singulated by sawing from an array-molded substrate (an example of the embodiment has been illustrated in FIG. 8C).
  • a second semiconductor device 902, with assembled chip 902b and with solder bodies 910, is attached to the pads of the first substrate 901a of the first device 901 in order to produce a package- on-package. In this attachment process, the pad surfaces 103 are contacted by the solder bodies 910 of the second device 902.
  • FIG. 9 emphasizes the preferred combination of devices, wherein not only the molding compound 920 of first device 901 extends to the substrate perimeter 903, but also the molding compound 930 of second device 902 extends to the substrate perimeter 904. This combination minimizes the risk of device warpage in the assembly process. While the locations of solder balls 910 of device 902 match the contact pads 103 of device 901, the electrical connections to the desired input/output terminals of device 901 are accomplished by redistribution lines 940, created by the metal-filled grooves in the encapsulation 920 of device 901. The electrical connection of device 902 to device 901 is thus customized. This achievement of the redistribution lines 940 provides a high degree of freedom in selecting devices 902 to form package-on-package products with existing devices 901. Furthermore, the batch -processing method of the invention provides a low-cost process for creating the customized electrical connections.
  • FIGS. 2B and 3B Another embodiment of the invention is an apparatus for the fabrication of a semiconductor device; the apparatus is illustrated in FIGS. 2B and 3B, with more detail illustrated in FIGS. 2A and 3A.
  • a mold has top (201 in FIG. 2A, 210 in FIG. 2B) and bottom (301 in FIG. 3 A, 310 in FIG. 3B) portions.
  • the top portion has a cavity with protrusions and recesses for holding semiconductor devices, the bottom portion is without corresponding protrusions and preferably featureless.
  • the device includes a semiconductor chip attached to a sheet- like insulating substrate, integral with two or more patterned layers of conductive lines and vias, with contact pads in pad locations. When the mold is operated, it is closed by clamping the top portion onto the bottom portion.
  • the recesses in the top mold portion have spring-loaded movable pistons, which can be operated individually so that individual floating cavities are formed.
  • the top portion includes protrusions (202 in FIG. 2A) at locations matching the pad locations.
  • the protrusions are made of the same material (for instance, steel) as the top portion of the mold.
  • the protrusions are preferably shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; a preferable distance from the cone to the pad surface is between 0 and about 100 ⁇ m. More preferably, the height is suitable to touch the pads metal surface in the closed mold.
  • the angle 202a of the cones is preferably between 10 and 30 degrees from vertical.
  • the recesses have inserts 230 with ridges 231, which operate to create surface grooves with smooth sidewalls and bottoms in the molded package. After completion of the molding process, which created all grooves simultaneously as a batch process, these grooves will be filled with metal so that they will become electrically conductive redistribution lines between the metal-filled accesses to the contact pads. The redistribution lines embedded in the encapsulation make an additional metal layer for redistribution unnecessary.
  • the ridges can be customized to serve exactly the input/output requirements of the devices intended to be coupled in a package-on-package assembly.
  • the inserts are preferably made of a metal such as aluminum or steel so that they can withstand the temperatures and pressures during the molding operation.
  • a compliant film positioned over the protrusions and recesses of the top portion and the inserts to prevent molding compound from bleeding during the molding operation.
  • Preferred materials for the compliant film include heat-tolerant and pressure- tolerant silicone and polymers such as kapton in the thickness range between 15 and 500 ⁇ m.
  • the bottom portion of the mold is preferably featureless, in particular in molds for encapsulating whole arrays as shown in FIG. 3B.
  • the bottom part provides support for placing the device substrate in the mold.
  • FIG. 8C a cross section of a magnified portion before singulation is depicted in FIG. 7.
  • a sheet-like insulating substrate 101 has obtained its perimeter 820, preferably by sawing, which leaves recognizable saw marks.
  • the substrate has solder bodies 701 attached.
  • the embodiment has an encapsulated region on the top of the substrate; the encapsulation material covers the whole top substrate area of the device, including the chip, which is attached on the top surface of the substrate (not shown in FIG. 8C).
  • the encapsulation forms contact apertures 703 at the pad locations for permitting external communication with the pad metal surfaces.
  • the surfaces of the aperture sidewalls include compound structures, which have been modified from the otherwise smooth surface by the process employed to clean up the pad metal surfaces and thus bear witness of the selected process.
  • the compound structures on the sidewalls include thermally modified compound particles, such as rounded particles, they indicate that a laser technique has been used to remove an incidental compound layer from the pad surface and thus expose the pad metal.
  • the aperture sidewalls when they have a roughened surface, they indicate that a plasma clean-up process has been used to expose the pad metal.
  • the aperture sidewalls may have surface structures recognizable by one skilled in the art as residues of a chemical etch process used to expose the pad metal.
  • the top surface of the encapsulation has one or more metal-filled redistribution lines 830, which connect selected apertures 703. Lines 830 are customized in order to facilitate the package-on-package assembly of selected semiconductor devices. As pointed out in conjunction with FIG. 9, in the preferred combination of devices for the package-on-package assembly extends not only the encapsulation of the first device to the substrate perimeter, but also the encapsulation of the second device. This matched combination minimizes the risk of device warpage in the assembly process.
  • the invention applies to products using any type and any number of semiconductor chips, discrete or integrated circuits, and the material of the semiconductor chip may comprise silicon, silicon germanium, gallium arsenide, or any other semiconductor or compound material used in integrated circuit manufacturing.
  • the metal protrusions of the top mold portion may be shaped as cylinders, cubes, rhomboids, or any other three-dimensional configuration.
  • the depth to which the inserts are positioned in the recesses influences the thickness of the device encapsulation; and may be varied to modify the contours of the molded devices.

Abstract

A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Description

ARRAY-MOLDED PACKAGE-ON-PACKAGE HAVING REDISTRIBUTION LINES
This relates in general to the field of semiconductor devices and processes; and, more specifically, to the structure and fabrication method of low-profile, vertically integrated package-on-package integrated circuit assemblies having redistribution lines. BACKGROUND
Today's package-on-package semiconductor devices enjoy increasing popularity, because they promise to use components already developed and thus quickly available, they are supposed retain a slim space-saving contour after assembly, and they are expected to be robust in terms of reliability in use-test under variable temperature and moisture conditions. These expectations tend to run quickly into difficulties for various reasons.
The thickness of the package-on-package products as the simple sum of the thicknesses of the semiconductor chips, electric interconnections, and encapsulations is often unacceptably large, especially for hand-held wireless equipments. In contrast, when the thickness is reduced, the products run increasingly into warpage problems caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the plastic substrates, the molding compound, the solder balls, and the printed circuit board. Warpage can lead to some of the most debilitating problems encountered by semiconductor assemblies such as the fracture and separation of solder joints, or the separation of materials followed by moisture ingress.
In addition, the selection of partners for package-on-package products is often limited because their electrical interconnection has to be customized and may require additional metal levels. SUMMARY Applicants recognize an existing need to shrink semiconductor devices both in two and in three dimensions, especially for a device-stacking and package-on-package method for semiconductor devices as well as electronic systems. Specifically, applicants recognize an existing need to design production equipment such as molds to provide flexibility in electrical device interconnection of package-on-package devices. The invention addresses the problem by providing a versatile mold with exchangeable device- specific inserts. These versatile molds further provide low-cost, simplified fabrication methods, and improved testability and thus yield. Using these flexible molds, stacking chips and packages will shorten the time-to-market of innovative products such as vertically integrated semiconductor systems, which utilize available chips of various capabilities (for example processors and memory chips), eliminating the wait for a redesign of chips. Based on the versatile mold equipment, package-on-package devices can be produced with excellent electrical performance, mechanical stability free of warping, and high product reliability. Further, it is a technical advantage that the fabrication method is flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations. Based on the redistribution lines on the surface of the molding compound, the invention provides an electrical routing level outside of the insulating substrate or the leadframe, thus providing the additional routing without adding a metallization level to the thickness of the package.
One embodiment of the invention is a semiconductor device with a sheet- like insulating substrate integral with two or more patterned layers of conductive lines and vias, a chip or a stack of chips attached to an assembly site, and contact pads in pad locations. An encapsulated region is on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures at the pad locations for external communication with the pad metal surfaces. The apertures may have not- smooth sidewall surfaces and may be filled with solder material to contact the pads. Surface grooves in the encapsulated region, which have smooth bottom and sidewalls and are filled with metal, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly. In addition, electrical parts such as passive components may be attached to the redistribution lines.
Another embodiment of the invention is a mold with top and bottom portions, wherein the top portion forms a cavity for placing semiconductor devices. The device includes a semiconductor chip attached to a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, and contact pads in pad locations. The top mold portion of the mold includes protrusions and recesses; the protrusions are at locations matching the pad locations, and are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold.
Placed in the recesses are inserts made of aluminum or steel with ridges operable to create surface grooves in the molded package; in addition, there may be a compliant film inserted in each recess between the top portion and the insert to prevent molding compound from bleeding during the molding operation. Alternatively, a continuous compliant film may cover the top portion surface, including the recesses, to cushion the inserts. The bottom mold portion is without corresponding protrusions and recesses.
Another embodiment of the invention is a method for fabricating a semiconductor device. A semiconductor chip is attached to a sheet-like insulating substrate, preferably integral with two or more patterned layers of conductive lines and vias, and contact pads in pad locations. A mold is provided, which has a top portion with protrusions and recesses; the protrusions are at locations matching the pad locations; placed in the recesses are inserts with ridges operable to create surface grooves in the molded package. The bottom mold portion is without corresponding protrusions. The substrate with the chip is loaded onto the bottom mold portion; the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. After pressuring molding compound into the cavity to fill the cavity and thereby create an encapsulation, the mold is opened. The encapsulation has apertures to the pad locations and surface grooves (with smooth sidewalls and bottom) extending between selected apertures. Any residual compound may be removed from the pads, and the apertures filled with solder. Further, the grooves may be filled with a metal such as copper, thereby creating routing interconnections between selected apertures.
Alternatively, the cavity direct injection mold technique, or the liquid compression mold technique may be employed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. IA to 7 illustrate certain process steps for fabricating an array-molded semiconductor device according to an embodiment of the invention.
FIG. IA is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by wire bonding. FIG. IB is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by flip-chip technology.
FIG. 1C is a schematic cross section of a sheet-like substrate with contact pads and a plurality of chips flip-assembled for array processing. FIG. 2A shows a schematic cross section of the top portion of an exemplary mold with structural features and inserts according to the invention.
FIG. 2B shows a schematic cross section of the top portion of an exemplary mold intended for array-molding with structural features and inserts according to the invention.
FIG. 3A shows a schematic cross section of the bottom portion of a mold. FIG. 3B shows a schematic cross section of the bottom portion of a mold intended for array-molding.
FIG. 4 illustrates a schematic cross section of the open mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
FIG. 5 shows a schematic cross section of the closed mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
FIG. 6A illustrates a schematic cross section of a molded semiconductor array after removal from the mold.
FIG. 6B shows a magnified schematic cross section of a molded unit after removal from the mold and singulation from the array, displaying the grooves in the encapsulation according to the invention.
FIG. 7 is a schematic cross section of a discrete device after removing any molding compound from the contact pads, filling an aperture with solder, filling the grooves with metal and attaching solder bodies for external communication.
FIG. 8A shows a schematic cross section of a finished array with features according to the invention.
FIG. 8B depicts a schematic top view of a finished array, molded according to the invention, before singulation.
FIG. 8C shows a schematic perspective view of a discrete unit singulated from the molded array with features according to the invention. FIG. 9 illustrates a schematic cross section of another embodiment of the invention, wherein a second semiconductor device with solder bodies is attached to the first device (with redistribution lines) so that the aperture-exposed pads of the first device are contacted by the solder bodies of the second device, creating a customized package-on-package semiconductor assembly. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
FIGS. IA through 7 illustrate schematically the steps of one embodiment of the invention, a method for array-molding semiconductor devices. The steps shown in FIGS. IA and IB show the attachment and assembly of a semiconductor chip on a substrate by wire bonding (FIG. IA) and by flip-chip technology (FIG. IB); FIG. 1C exemplifies a portion of an array of chips attached by flip-chip. A sheet-like substrate 101 with insulating core (for example, plastic, glass-fiber reinforced, ceramic) is integral with two or more patterned layers of conductive lines and conductive vias (preferably copper) and contact pads in pad locations (lines 110 do not reach beyond the boundaries of substrate 101). Substrate 101 has a first surface 101a and a second surface 101b, and a preferred thickness range from 0.05 to 0.5 mm. The first surface 101a includes chip assembly sites 102 and contact pads 103 in pad locations. The metal of the contact pads is preferably copper with a solderable surface (for example, including a layer of gold or palladium). Second surface 101b also has pads 112 with a solderable surface.
A plurality of semiconductor chips 130 is provided. In order to attach and electrically connect the chips, they are assembled on each assembly site either by adhesive attachment and wire bonding, or by flip-chip connection. For flip-attachment, the connecting metal bumps 140 may be made of solder, gold, or copper.
By further attaching the additional chip 131 to chip 130, FIG. IB illustrates the possibility, to assemble a stack of two or more chips on substrate 101. In this assembly process, both the techniques of flip-chip and wire bond may have to be employed; in emerging technology, also through- semiconductor vias (TSVs, metal-filled vias) may be employed.
As illustrated in FIG. 2A to 3B, in the next process step a mold made of steel or another suitable material is provided, which allows the encapsulation of a single device or of an array of devices. The mold has a top portion and a bottom portion; the top portion is manufactured to form a cavity for holding semiconductor devices. The top portion included protrusions and recesses; the bottom portion is without corresponding protrusions. In FIG. 2A, the top portion is intended to process a single device and is designated 201; in FIG. 2B, the top portion is constructed for an array of devices to be processed together as a batch. In FIG. 3A, the bottom portion is intended to process a single device and is designated 301; in FIG. 2B, the bottom portion is constructed for an array of devices to be processed together. The top portion 201 includes protrusions 202 at locations matching the pad locations of the device shown in FIG. IA and IB; the bottom portion 301 is without corresponding protrusions. The protrusions are preferably shaped as truncated cones, with the cone surface angled within a preferred range from about 10 to 30 degrees from vertical. The angle is designated 202a in FIG. 2A. Furthermore, the protrusions preferably may have a ridge 203, which may extend along the whole angled side of the cone. Ridge 203 is operable to create a groove or channel in the molded part, which may provide release of gas in the solder ball attachment process, or help in the solder paste reflow process. The height 202b of the protrusion is selected to be suitable to approach the substrate pad metal (103 in FIGS. IA and IB) in the closed mold. Preferably, the protrusion should approach the pad metal surface in the closed mold to a distance between 0 and about 100 μm. More preferably, height 202b of the protrusion is sufficient to touch the pad metal surface in the closed mold. The bottom portion 301 in FIG. 3 A and 310 in FIG. 3B of the mold has no protrusions; it is featureless and preferably flat. For some individual devices, it may be an advantage to recess a portion outlined by length 302 and depth 303 sufficient to accommodate the substrate of a discrete device, but for array processing, a featureless flat bottom mold portion is preferable. The recesses of top portion 201 have inserts 230, which are individually manufactured to fit into the respective recess. They are preferably made of aluminum, steel, or invar so that they can withstand the temperatures and pressures during the molding operation without jamming. The surfaces of the inserts are smooth. Selected inserts have ridges 231, also with smooth surfaces, operable to create surface grooves in the molded package. The preferred height of these ridges is between about 10 and 100 μm. In terms of cross section, the ridges may be rectangular, triangular, or rounded.
The grooves molded by the ridges 231 will have the mirror- image cross sections of the ridges, such as rectangular, triangular, or rounded, and also will have the smooth surfaces of the ridges. In either case, the grooves will be filled with metal such as copper (see below) in order to create conductive redistribution lines between selected apertures to the contact pads. Consequently, it is a technical advantage of the invention that these inserts can be exchanged between molding runs in order to create any desired redistribution pattern of the connection lines in the molded product. This degree of freedom allows a wide choice in selecting semiconductor devices to be joined with the device packaged in the mold of FIGS. 2A and 3A. FIG. 2B illustrates the inserts 230 in each recess of a top mold 210 intended for molding an array.
As FIGS. 2A and 2B show, it is preferred to insert a continuous compliant, chemically inert film 232 over the surface of top bold portion 201. Film 232 is positioned between the material of mold 201 and the inserts 230 to prevent bleeding of molding compound during the molding operation. Preferably, film 232 is adhesive; it is preferably made of heat-tolerant and pressure-tolerant silicone or polymers such as kapton in the thickness range between 15 and 500 μm. Alternatively, pieces of the compliant, chemically inert, preferably adhesive film 232 may be inserted into each recess.
In the next process step (see FIG. 4), the substrate 101 with the assembled chips 130 is loaded onto the bottom mold portion 310. The second substrate surface 101b is rested on mold portion 310, and the first substrate surface 101a with the contact pads 103 is positioned away from the bottom mold portion 310. Protrusions 202 of the top mold portion 210 are aligned with the respective contact pads 103 of substrate 101.
FIG. 5 shows the next process step of closing the mold by clamping the top portion 210 onto the bottom portion 310 so that the protrusions 202 are aligned with the contact pads 103, approaching or touching the pad surface. The top portion 210 resting on the flat bottom portion 310 forms the cavity of the mold for holding the semiconductor devices. Preferably, the protrusions touch the contact pads; however, material or alignment tolerances may cause a residual distance between 0 and about 100 μm between the protrusion and the respective pad. FIG. 5 also shows the respective ridge 203 for each protrusion 202 and the inserts 230 with the compliant film 232 over the protrusions-and-recess surface of top portion 210.
Next, encapsulation material such as epoxy-based and filler-loaded molding compound is pressured into the cavity to fill the cavity; the runners for supplying the compound, and the gates needed for entering the cavity and controlling the compound flow, are not shown in FIG. 5. By this transfer molding step, encapsulations for the devices of the array are created.
After partially polymerizing the compound 601, the mold is opened and the substrate together with the encapsulated array of chips is removed from the mold; FIG. 6A illustrates the encapsulated array, and FIG. 6B shows an enlarged view of one unit. Subsequently, compound 601 is fully polymerized. For many device types, the thickness of the molded encapsulation is between 0.2 and 0.7 mm. As the cross sections of FIGS. 6A and 6B show, the encapsulation has apertures 603 to the pad locations. Furthermore, FIGS. 6A and 6B and the top view of FIG. 8C show, the encapsulation has surface grooves 630 extending between selected apertures. Grooves 630 have smooth bottom and sidewalls. Alternatively, the cavity direct injection molding technique or the liquid compression molding technique may be employed. These techniques also use a plastic film similar to film 232 in FIGS. 2A, 2B and 4, held to the top mold portion by vacuum suction. The recesses in the top mold portion are individually operated by spring-loaded movable pistons, creating individual floating cavities. The application of the metal inserts in the recesses according to the invention is analogous to the application of the inserts depicted in FIG. 4.
FIG. 6B indicates by dashed contour 602 any residual encapsulation formed on the contact pads 103. These thin deposits (thickness 602a between 0 and about 100 μm) have to be removed to expose the clean metal surface of pad 103. At least three methods are suitable to remove these unwanted encapsulation layers. The first method employs drilling or vaporizing by laser light. A focused laser beam shines into the encapsulation aperture 603, removes the compound layer while forming particles 604 in a thermal process, and deposits these particles on the otherwise smooth sidewalls 603a; particles 604 attest to the thermal process used to clean up the pads. The second method employs a plasma clean-up process; the plasma leaves a roughened surface 605 on the aperture sidewalls 603a. The third method employs a chemical etch process, which leaves a surface structure 606 recognizable by one skilled in the art. All three methods are material-sensitive and thus controllable to stop at the metal surface of the contact pads.
In the final process step, illustrated in FIG. 7, the grooves 630 in the encapsulation surface are filled with metal 710, preferably copper, whereby electrically conductive routing interconnections between the apertures are created. Several successful processes are available to fill the grooves with metal. The preferred method includes the steps of plasma cleaning the encapsulation surface; depositing, by electroless plating or by sputtering, a metal layer (for example copper) on the encapsulation surface including the grooves; electrolytically plating metal up to the thickness sufficient to fill the grooves; and grinding the encapsulation surface to remove the metal from the surface except the grooves.
An alternative method includes the steps of plasma cleaning the encapsulation surface; screen printing metal into the grooves, or instance copper; and reflowing the screened metal.
In an additional process step, reflow bodies such as solder balls 701 are attached to the attachment pads 112 (see FIGS. IA and IB) on the second substrate surface 101b. This step is illustrated in FIG. 7, showing a magnified portion of the array (it should be noted that in the example of FIG. 7, wire bonding has been employed to assemble the chip on the first substrate surface 101a).
In an optional process step, the mold apertures 703 may be filled with solder paste 704, which contacts the surface of pad metal 103. During the reflow step of the paste, grooves 705 may help to separate the flux-rich part form the solder-rich part.
FIGS. 8A, 8B, and 8C depict the singulation step. The dashed lines 801 (in the cross section of FIG. 8A), 802 and 803 (in the top view of FIG. 8B) indicate saw lines of saws, which cut through the substrate 101 and the mold compound 601 to singulate discrete units from the sheet-like substrate of the array. Due to the sawing process step, the individual units have recognizable saw marks on their sides.
A discrete unit, generally designated 800, is illustrated in FIG. 8C in a perspective X- ray view. The perimeter of unit 800 is designated 820. The illustration emphasizes the apertures 703 reaching through the thickness of the encapsulation 801 to the contact pads, but omits the encapsulated assembled chip for clarity reasons; in addition, the gas release channels 810 have been omitted for all apertures except for one row of apertures. The surface 801a of the encapsulation includes the metal- filled routing interconnections 830 of the redistribution grooves.
FIG. 8C further indicates the opportunity provided by the redistribution lines, after being filled with metal, to attach additional electrical parts such as passive components on the surface of device 800. Shown in dashed outline, part 840 is a passive component attached to two adjacent metal-filled grooves. Based on the metal-filled redistribution lines 830 on the surface of the molding compound, the invention provides an electrical routing level outside of the insulating substrate or the leadframe, thus providing the additional routing without adding a metallization level to the thickness of the package.
FIG. 8C further indicates the opportunity to add an insulating film 850 over surface of device 800. The film is preferably made of a plastic material, which can tolerate the high temperatures encountered in solder attachment processes. The film has holes in the locations of the openings 703, which need to be available for solder attachment. The film offers the opportunity to add device symbolization to the top of unit 800. Typically, such symbolization informs about the type of device, electrical characteristics, year and location of manufacturing, producer, etc.
The benefit of the redistribution routing becomes evident, when a package-on- package device has to be built as illustrated in FIG. 9. A first semiconductor package 901, with assembled chip 901b, is manufactured as described above, including the copper- filled redistribution lines 940 and apertures 941, and singulated by sawing from an array-molded substrate (an example of the embodiment has been illustrated in FIG. 8C). A second semiconductor device 902, with assembled chip 902b and with solder bodies 910, is attached to the pads of the first substrate 901a of the first device 901 in order to produce a package- on-package. In this attachment process, the pad surfaces 103 are contacted by the solder bodies 910 of the second device 902.
FIG. 9 emphasizes the preferred combination of devices, wherein not only the molding compound 920 of first device 901 extends to the substrate perimeter 903, but also the molding compound 930 of second device 902 extends to the substrate perimeter 904. This combination minimizes the risk of device warpage in the assembly process. While the locations of solder balls 910 of device 902 match the contact pads 103 of device 901, the electrical connections to the desired input/output terminals of device 901 are accomplished by redistribution lines 940, created by the metal-filled grooves in the encapsulation 920 of device 901. The electrical connection of device 902 to device 901 is thus customized. This achievement of the redistribution lines 940 provides a high degree of freedom in selecting devices 902 to form package-on-package products with existing devices 901. Furthermore, the batch -processing method of the invention provides a low-cost process for creating the customized electrical connections.
Another embodiment of the invention is an apparatus for the fabrication of a semiconductor device; the apparatus is illustrated in FIGS. 2B and 3B, with more detail illustrated in FIGS. 2A and 3A. A mold has top (201 in FIG. 2A, 210 in FIG. 2B) and bottom (301 in FIG. 3 A, 310 in FIG. 3B) portions. The top portion has a cavity with protrusions and recesses for holding semiconductor devices, the bottom portion is without corresponding protrusions and preferably featureless. Preferably, the device includes a semiconductor chip attached to a sheet- like insulating substrate, integral with two or more patterned layers of conductive lines and vias, with contact pads in pad locations. When the mold is operated, it is closed by clamping the top portion onto the bottom portion.
When the cavity direct injection molding technique or the liquid compression molding technique is employed, the recesses in the top mold portion have spring-loaded movable pistons, which can be operated individually so that individual floating cavities are formed.
The top portion includes protrusions (202 in FIG. 2A) at locations matching the pad locations. Preferably, the protrusions are made of the same material (for instance, steel) as the top portion of the mold. The protrusions are preferably shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; a preferable distance from the cone to the pad surface is between 0 and about 100 μm. More preferably, the height is suitable to touch the pads metal surface in the closed mold. The angle 202a of the cones is preferably between 10 and 30 degrees from vertical. In addition, it is advantageous to add a ridge to the protrusions (203 in FIG. 2A), which are configured to create, in the molded encapsulation, a gas release channel in the aperture of the contact pads. The recesses have inserts 230 with ridges 231, which operate to create surface grooves with smooth sidewalls and bottoms in the molded package. After completion of the molding process, which created all grooves simultaneously as a batch process, these grooves will be filled with metal so that they will become electrically conductive redistribution lines between the metal-filled accesses to the contact pads. The redistribution lines embedded in the encapsulation make an additional metal layer for redistribution unnecessary.
Since the inserts are exchangeable, the ridges can be customized to serve exactly the input/output requirements of the devices intended to be coupled in a package-on-package assembly. The degree of freedom to select the devices for the assembly, based on the ability to interconnect them in a customized fashion, represents a new opportunity for designing customized package-on-package products.
The inserts are preferably made of a metal such as aluminum or steel so that they can withstand the temperatures and pressures during the molding operation. In addition, it is preferred to include a compliant film positioned over the protrusions and recesses of the top portion and the inserts to prevent molding compound from bleeding during the molding operation. Preferred materials for the compliant film include heat-tolerant and pressure- tolerant silicone and polymers such as kapton in the thickness range between 15 and 500 μm. For the individual spring-loaded pistons of the cavity direct injection mold, the application of the metal inserts in the recesses according to the invention is analogous to the one described above.
The bottom portion of the mold is preferably featureless, in particular in molds for encapsulating whole arrays as shown in FIG. 3B. The bottom part provides support for placing the device substrate in the mold. On the other hand, it may be advantageous for molding discrete devices to have a recess (302 in FIG. 3A) of a certain depth in the bottom part for tightly positioning the device substrate. No molding compound reaches the bottom of the cavity or the bottom surface of the substrate.
Another embodiment of the invention is a semiconductor device, singulated by sawing from an array-molded substrate, and designed to become part of a semiconductor package-on-package device. An example of the embodiment is illustrated in FIG. 8C (a cross section of a magnified portion before singulation is depicted in FIG. 7). A sheet-like insulating substrate 101 has obtained its perimeter 820, preferably by sawing, which leaves recognizable saw marks. The substrate has solder bodies 701 attached.
The embodiment has an encapsulated region on the top of the substrate; the encapsulation material covers the whole top substrate area of the device, including the chip, which is attached on the top surface of the substrate (not shown in FIG. 8C). The encapsulation forms contact apertures 703 at the pad locations for permitting external communication with the pad metal surfaces. The surfaces of the aperture sidewalls include compound structures, which have been modified from the otherwise smooth surface by the process employed to clean up the pad metal surfaces and thus bear witness of the selected process. As an example, when the compound structures on the sidewalls include thermally modified compound particles, such as rounded particles, they indicate that a laser technique has been used to remove an incidental compound layer from the pad surface and thus expose the pad metal. Alternatively, when the aperture sidewalls have a roughened surface, they indicate that a plasma clean-up process has been used to expose the pad metal. In another situation, the aperture sidewalls may have surface structures recognizable by one skilled in the art as residues of a chemical etch process used to expose the pad metal.
The top surface of the encapsulation has one or more metal-filled redistribution lines 830, which connect selected apertures 703. Lines 830 are customized in order to facilitate the package-on-package assembly of selected semiconductor devices. As pointed out in conjunction with FIG. 9, in the preferred combination of devices for the package-on-package assembly extends not only the encapsulation of the first device to the substrate perimeter, but also the encapsulation of the second device. This matched combination minimizes the risk of device warpage in the assembly process.
The invention applies to products using any type and any number of semiconductor chips, discrete or integrated circuits, and the material of the semiconductor chip may comprise silicon, silicon germanium, gallium arsenide, or any other semiconductor or compound material used in integrated circuit manufacturing.
The metal protrusions of the top mold portion may be shaped as cylinders, cubes, rhomboids, or any other three-dimensional configuration. The depth to which the inserts are positioned in the recesses influences the thickness of the device encapsulation; and may be varied to modify the contours of the molded devices.
Those skilled in the relevant art to will appreciate that there many other embodiments and variations are possible within the scope of the claimed invention.

Claims

CLAIMSWhat is claimed is:
1. An apparatus comprising: a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having a first surface with a chip assembly site and contact pads in pad locations and a second surface; a semiconductor chip attached to the assembly site; an encapsulated region on the first surface, extending to the edge of the substrate, enclosing the chip and having contact apertures at the pad locations for external communication with the metal surfaces, the apertures having not-smooth sidewall surfaces; and metal-filled surface grooves in the encapsulated region as routing interconnections between selected apertures, the grooves having smooth sidewall and bottom surfaces.
2. The apparatus according to Claim 1, further including one or more of the following: a) elongated gas release channels; b) solder material in the contact apertures to the pads, contacting the pad metal surfaces; c) another semiconductor device with solder balls attached to the first substrate surface so that the pad surfaces are contacted by the solder balls, creating a package-on-package semiconductor assembly; d) solder balls attached to the second substrate surface; e) additional electrical components attached to adjacent metal-filled surface groove; f) a plastic surface film made of heat-tolerant material.
3. The apparatus according to Claim 1 or 2, wherein the not- smooth aperture sidewall surfaces are characterized by at least one of the following: a) they include compound particles from a laser process; b) they have a plasma-roughened surface; c) they have etch structures from a chemical etch process.
4. The apparatus according to Claim 1 or 2, wherein the semiconductor chip is characterized by at least one of the following: a) it is a stack of two or more semiconductor chips; b) it is attached to the substrate by wire bonding; c) it is attached to the substrate by a flip-chip process.
5. An apparatus for the fabrication of a semiconductor device comprising: a mold having top and bottom portions, the top portion forming a cavity for holding semiconductor devices, wherein the device includes a semiconductor chip attached to a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having contact pads in pad locations; the mold operable to be closed by clamping the top portion onto the bottom portion; the top portion including protrusions and recesses; the protrusions being at locations matching the pad locations, and shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; the recesses having inserts with ridges operable to create surface grooves in the molded package, the ridges having smooth surfaces; and the bottom portion being without corresponding protrusions.
6. The apparatus according to Claim 5, characterized by one or more of the following: a) the protrusions are shaped as truncated cones angled with a range of about 10 to 30 degrees from vertical; b) the protrusions further include a ridge operable to create an aperture having a gas release channel in the aperture; c) the protrusions approach the pad metal surface in the closed mold to a distance between 0 and 100 μm; d) the inserts are made of aluminum or steel so that they can withstand the temperatures and pressures during the molding operation; e) the recesses of the top portion include individually operable spring-loaded pistons.
7. The apparatus according to Claim 5 or 6, further including a compliant film positioned over the surface of the top mold portion, including the protrusions and recesses, between the top portion and the inserts to prevent molding compound from bleeding during the molding operation.
8. A method for fabricating a semiconductor device comprising the steps of: providing a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having a first surface with chip assembly sites and contact pads in pad locations, and a second surface; providing semiconductor chips; attaching a chip to each assembly site; providing a mold having top and bottom portions, the top portion forming a cavity for holding semiconductor devices; the top portion including protrusions and recesses; the protrusions being at locations matching the pad locations and shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; the recesses having inserts with ridges operable to create surface grooves in the molded package, the ridges having smooth surfaces; the bottom portion being without corresponding protrusions; loading the substrate with the chips onto the bottom mold portion, resting the second substrate surface on the mold and positioning the first surface with the contact pads away from the bottom mold portion; closing the mold by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface; pressuring molding compound into the cavity to fill the cavity, thereby creating an encapsulation; opening the mold and removing the substrate together with the encapsulated chips from the mold, the encapsulation having apertures to the pad locations and surface grooves extending between selected apertures, the grooves having smooth bottom and sidewalls; removing any residual compound formed on the pads to expose the metal surface; and filling the grooves with metal, thereby creating routing interconnections.
9. The apparatus according to Claim 8, characterized by at least one of the following: a) the protrusions approach the pad metal surface in the closed cavity to a distance between 0 and 100 μm; b) the inserts are made of aluminum or steel so that they can withstand the temperatures and pressures during the molding operation.
10. The method according to Claim 8, further including a compliant film inserted between the top mold portion, with the protrusions and recesses, and the inserts to prevent mold compound bleeding in the molding operation.
11. The method according to Claim 8, 9 or 10, wherein the step of removing residual compound from the pad surface is performed by at least one of the following: a) the process of shining laser light into the encapsulation apertures, thereby depositing compound particles on the otherwise smooth sidewalls; b) a plasma clean-up process, thereby creating a roughened surface on the aperture sidewalls; c) a chemical etch process, thereby leaving etch structures on the aperture sidewalls.
12. The method according to Claim 8, 9 or 10, further including the step of filling the encapsulation apertures to the pads with solder material, thereby electrically interconnecting selected apertures by means of the metal-filled grooves.
13. The method according to Claim 8, 9 or 10, further including the step of singulating individual units from the sheet-like substrate.
14. The method according to Claim 8, 9 or 10, further including, after the step of filling the grooves, at least one of the following: a) the step of attaching another semiconductor device with solder balls to the first substrate surface of the singulated unit so that the exposed pad surfaces are contacted by the solder bodies, thereby creating a package-on-package semiconductor assembly; b) the step of covering the chip surface with a plastic film made of heat- tolerant material, the film suitable for symbolization; c) the step of attaching an electrical components to adjacent metal-filled surface grooves.
15. The method according to Claim 8, 9 or 10, wherein the step of filling the grooves includes the steps of: plasma cleaning the molded surface; depositing, by electroless plating or by sputtering, a metal layer on the molded surface and the grooves; electrolytically plating metal up to the thickness sufficient to fill the grooves; and grinding the molded surface to remove the metal from the surface except the grooves.
16. The method according to Claim 8, 9 or 10, wherein the step of filling the grooves includes the steps of: plasma cleaning the molded surface; screen printing metal into the grooves; and reflowing the screened metal.
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Families Citing this family (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006052616A1 (en) 2004-11-03 2006-05-18 Tessera, Inc. Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
TWI339865B (en) * 2007-08-17 2011-04-01 Chipmos Technologies Inc A dice rearrangement package method
KR101329355B1 (en) * 2007-08-31 2013-11-20 삼성전자주식회사 stack-type semicondoctor package, method of forming the same and electronic system including the same
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
TWI355220B (en) * 2008-07-14 2011-12-21 Unimicron Technology Corp Circuit board structure
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9293401B2 (en) 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
GB2466255B (en) 2008-12-17 2013-05-22 Antenova Ltd Antennas conducive to semiconductor packaging technology and a process for their manufacture
US8115283B1 (en) 2009-07-14 2012-02-14 Amkor Technology, Inc. Reversible top/bottom MEMS package
US9254532B2 (en) 2009-12-30 2016-02-09 Intel Corporation Methods of fabricating low melting point solder reinforced sealant and structures formed thereby
US8643181B2 (en) * 2010-03-24 2014-02-04 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101163222B1 (en) * 2010-09-13 2012-07-06 에스케이하이닉스 주식회사 Semiconductor package and method for manufacturing the same
KR101695353B1 (en) * 2010-10-06 2017-01-11 삼성전자 주식회사 Semiconductor package and semiconductor package module
US8546193B2 (en) * 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US9171769B2 (en) * 2010-12-06 2015-10-27 Stats Chippac, Ltd. Semiconductor device and method of forming openings through encapsulant to reduce warpage and stress on semiconductor package
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR20120078390A (en) 2010-12-31 2012-07-10 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
EP2624294B1 (en) * 2011-10-12 2017-12-06 NGK Insulators, Ltd. Circuit board for large-capacity module peripheral circuit and large-capacity module containing peripheral circuit using said circuit board
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8610286B2 (en) * 2011-12-08 2013-12-17 Stats Chippac, Ltd. Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
US9460972B2 (en) * 2012-01-09 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9331007B2 (en) 2012-10-16 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US20140162407A1 (en) * 2012-12-10 2014-06-12 Curtis Michael Zwenger Method And System For Semiconductor Packaging
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
KR20140119522A (en) * 2013-04-01 2014-10-10 삼성전자주식회사 Semiconductor package having package on package structure
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US20150115461A1 (en) * 2013-10-30 2015-04-30 United Microelectronics Corp. Semiconductor structure and method for forming the same
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
FR3018630A1 (en) * 2014-03-11 2015-09-18 St Microelectronics Grenoble 2 PERFORATED ELECTRONIC HOUSING AND METHOD OF MANUFACTURE
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9576935B2 (en) * 2014-04-16 2017-02-21 Infineon Technologies Ag Method for fabricating a semiconductor package and semiconductor package
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
KR102373809B1 (en) * 2014-07-02 2022-03-14 삼성전기주식회사 Package structure and manufacturing method thereof
JP6242763B2 (en) * 2014-07-18 2017-12-06 Ｔｏｗａ株式会社 Manufacturing method of electronic component package
US9373585B2 (en) * 2014-09-17 2016-06-21 Invensas Corporation Polymer member based interconnect
US9524956B2 (en) * 2014-10-31 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method
KR101647559B1 (en) * 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 Method of manufactuing semiconductor package and semiconductor package
CN104465423B (en) * 2014-12-08 2017-08-22 杰群电子科技（东莞）有限公司 A kind of Double-lead-frame overlaps designing semiconductor device method for packing
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9666514B2 (en) 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
CN105161433A (en) * 2015-09-28 2015-12-16 中芯长电半导体（江阴）有限公司 Fan-out type wafer grade packaging method
CN105347288B (en) * 2015-10-09 2017-07-28 锐迪科微电子（上海）有限公司 A kind of many device closed structures and its manufacture method for wafer-level packaging
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US9932221B1 (en) 2017-03-02 2018-04-03 Amkor Technology, Inc. Semiconductor package with multiple compartments
US10497650B2 (en) 2017-04-13 2019-12-03 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
TWI638410B (en) * 2017-11-14 2018-10-11 蔡宜興 Method and semi-finished product structure for reducing package substrate warpage
US10741466B2 (en) 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
US10777536B2 (en) 2017-12-08 2020-09-15 Infineon Technologies Ag Semiconductor package with air cavity
US10879144B2 (en) 2018-08-14 2020-12-29 Texas Instruments Incorporated Semiconductor package with multilayer mold
US10734348B2 (en) * 2018-09-21 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same
TWI698941B (en) * 2019-03-21 2020-07-11 力成科技股份有限公司 Two-sided stacked die package and packaging method thereof
US10796981B1 (en) 2019-04-04 2020-10-06 Infineon Technologies Ag Chip to lead interconnect in encapsulant of molded semiconductor package
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
CN112018052A (en) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 Semiconductor package with laser activatable molding compound
US11133244B2 (en) * 2019-06-19 2021-09-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
KR102551352B1 (en) * 2019-06-28 2023-07-04 삼성전자 주식회사 Semiconductor package and method of manufacturing the same
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature
CN116417353B (en) * 2023-04-07 2023-11-03 江苏中科智芯集成科技有限公司 Preparation method of semiconductor packaging structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331737B1 (en) * 1998-08-25 2001-12-18 Texas Instruments Incorporated Method of encapsulating thin semiconductor chip-scale packages
US6933176B1 (en) * 2002-07-19 2005-08-23 Asat Ltd. Ball grid array package and process for manufacturing same
US20060172461A1 (en) * 2002-10-08 2006-08-03 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268101A (en) * 1993-03-17 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate
JPH0883866A (en) * 1994-07-15 1996-03-26 Shinko Electric Ind Co Ltd Production of single side resin sealed semiconductor device and carrier frame therefor
FR2722915B1 (en) * 1994-07-21 1997-01-24 Sgs Thomson Microelectronics BGA INJECTION MOLDING HOUSING
EP1025587A4 (en) * 1997-07-21 2000-10-04 Aguila Technologies Inc Semiconductor flip-chip package and method for the fabrication thereof
JP3516611B2 (en) * 1999-06-29 2004-04-05 シャープ株式会社 Semiconductor device, method of manufacturing the same, and substrate for semiconductor device
US6400574B1 (en) * 2000-05-11 2002-06-04 Micron Technology, Inc. Molded ball grid array
US6420201B1 (en) * 2001-01-03 2002-07-16 Amkor Technology, Inc. Method for forming a bond wire pressure sensor die package
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
JP2003133366A (en) * 2001-10-25 2003-05-09 Texas Instr Japan Ltd Semiconductor device and manufacturing method therefor
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7667338B2 (en) * 2006-08-08 2010-02-23 Lin Paul T Package with solder-filled via holes in molding layers
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US20080284045A1 (en) * 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331737B1 (en) * 1998-08-25 2001-12-18 Texas Instruments Incorporated Method of encapsulating thin semiconductor chip-scale packages
US6933176B1 (en) * 2002-07-19 2005-08-23 Asat Ltd. Ball grid array package and process for manufacturing same
US20060172461A1 (en) * 2002-10-08 2006-08-03 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package

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