WO2008154580A3 - Method for optimized integrated circuit chip interconnection - Google Patents

Method for optimized integrated circuit chip interconnection Download PDF

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Publication number
WO2008154580A3
WO2008154580A3 PCT/US2008/066561 US2008066561W WO2008154580A3 WO 2008154580 A3 WO2008154580 A3 WO 2008154580A3 US 2008066561 W US2008066561 W US 2008066561W WO 2008154580 A3 WO2008154580 A3 WO 2008154580A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit chip
chip interconnection
optimized integrated
stack face
Prior art date
Application number
PCT/US2008/066561
Other languages
French (fr)
Other versions
WO2008154580A2 (en
Inventor
Scott Mcgrath
Simon J S Mcelrea
Terrence Caskey
Lawrence Douglas Andrews
Yong Du
Original Assignee
Vertical Circuits Inc
Scott Mcgrath
Simon J S Mcelrea
Terrence Caskey
Lawrence Douglas Andrews
Yong Du
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits Inc, Scott Mcgrath, Simon J S Mcelrea, Terrence Caskey, Lawrence Douglas Andrews, Yong Du filed Critical Vertical Circuits Inc
Publication of WO2008154580A2 publication Critical patent/WO2008154580A2/en
Publication of WO2008154580A3 publication Critical patent/WO2008154580A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]

Abstract

A method for forming electrical interconnection on stacked die units includes steps of arranging one or more stacked die units so that the arrangement presents die edges to be interconnected at a stack face, and applying a trace of electrical interconnect material at the presented stack face.
PCT/US2008/066561 2007-06-11 2008-06-11 Method for optimized integrated circuit chip interconnection WO2008154580A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US94325207P 2007-06-11 2007-06-11
US60/943,252 2007-06-11

Publications (2)

Publication Number Publication Date
WO2008154580A2 WO2008154580A2 (en) 2008-12-18
WO2008154580A3 true WO2008154580A3 (en) 2009-02-19

Family

ID=40130479

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/066561 WO2008154580A2 (en) 2007-06-11 2008-06-11 Method for optimized integrated circuit chip interconnection

Country Status (1)

Country Link
WO (1) WO2008154580A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940004952Y1 (en) * 1991-09-30 1994-07-23 주식회사 금성사 Jig for laser diode mirror coating
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US20050101039A1 (en) * 2002-10-30 2005-05-12 John Chen Apparatus and method for stacking laser bars for uniform facet coating
US20050230802A1 (en) * 2004-04-13 2005-10-20 Al Vindasius Stacked die BGA or LGA component assembly

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940004952Y1 (en) * 1991-09-30 1994-07-23 주식회사 금성사 Jig for laser diode mirror coating
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US20050101039A1 (en) * 2002-10-30 2005-05-12 John Chen Apparatus and method for stacking laser bars for uniform facet coating
US20050230802A1 (en) * 2004-04-13 2005-10-20 Al Vindasius Stacked die BGA or LGA component assembly

Also Published As

Publication number Publication date
WO2008154580A2 (en) 2008-12-18

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