WO2008114094A1 - Thin profile packaging with exposed die attach adhesive - Google Patents

Thin profile packaging with exposed die attach adhesive Download PDF

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Publication number
WO2008114094A1
WO2008114094A1 PCT/IB2007/050979 IB2007050979W WO2008114094A1 WO 2008114094 A1 WO2008114094 A1 WO 2008114094A1 IB 2007050979 W IB2007050979 W IB 2007050979W WO 2008114094 A1 WO2008114094 A1 WO 2008114094A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
connection conductors
underside
lead frame
underside layer
Prior art date
Application number
PCT/IB2007/050979
Other languages
French (fr)
Inventor
Paul Dijkstra
Roelf Groenhuis
Jan Van Kempen
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Priority to PCT/IB2007/050979 priority Critical patent/WO2008114094A1/en
Publication of WO2008114094A1 publication Critical patent/WO2008114094A1/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions

  • the invention relates to integrated circuit (IC) packaging. More particularly this invention relates to the achieving a thinner packaging profile by mounting an IC device die directly upon exposed die attach adhesive.
  • IC integrated circuit
  • MOSFET metal- oxide- semiconductor field-effect transistors
  • PMOS p- channel MOS
  • NMOS n-channel MOS
  • CMOS complementary MOS
  • BiCMOS transistors bipolar transistors
  • IGFETs insulated-gate FET
  • Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed.
  • the particular structure of a given active device can vary between device types.
  • an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
  • Such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc.
  • the substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
  • the silicon wafer After undergoing the process of fabrication, the silicon wafer has a predetermined number of devices. These devices are tested. Good devices are mapped on the wafer. Good devices are then packaged.
  • the thickness of the wafer substrate may be a challenge as electronic devices become thinner in such devices as wireless phones, laptop computers, watches, etc. Excess dimensions of length, width, and thickness have to be minimized.
  • the wafer substrate is often ground and polished on its backside to reduce the die thickness and to provide a surface to which it may be die attached.
  • the resulting thin substrate may pose challenges in later processing become too brittle to handle with modern automated equipment.
  • Packages encompassing this platform include, but are not limited to, DQFN (Depopulated very-thin Quad Flat-pack No-leads), HVQFN (Heatsink Very-thin Quad Flat-pack No-leads) and BGA (Ball Grid Array), SSON (Shrink Small Outline; No leads), XSON (eXtremely thin Small Outline; No leads) and TFBGA (Thin Fine-pitch Ball Grid Array) packages.
  • the QFN package 10 uses a lead frame 75.
  • Lead frame 75 includes three layers.
  • the first layer 15 and third layer 25 may be copper or a copper-rich alloy.
  • the second layer 20 may be nickel (Ni), molybdenum (Mo), or titanium (Ti).
  • the second layer 20 may be aluminum or an aluminum-rich alloy.
  • IC device 5 is attached with a suitable die-attach material 50 (e.g., laminating compound, or glue) to a die pad 60. Bond wires 40 and 45 connect the IC device to pad landings 30, 35.
  • a suitable die-attach material 50 e.g., laminating compound, or glue
  • Pads (not illustrated) are defined in the first layer 10 of the lead frame provide electrical connection of the IC device to a chosen application.
  • Recesses 55 provide a mechanical anchor (by forming plugs) substantially enhancing the adhesion of molding compound that is used to encapsulate the IC device 5.
  • the technology embraced by the TULIP package platform addresses a need for a robust encapsulation and reduced package thickness.
  • the device packaging thickness significantly decreases the desirability of the finished product.
  • the present invention has been found to be useful in reducing the thickness of packages used in integrated circuit assembly.
  • the invention eliminates the die paddle upon which the IC device is mounted without exposing the die to the outside environment. Eliminating the die paddle reduces the package thickness about 20% for an example package.
  • a semiconductor device that comprises an underside layer having openings.
  • a carrier has a first side opposite a second side, wherein the first side includes a first conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductor.
  • the carrier includes a cavity defined between the first and second sides and exposing a region of the underside layer.
  • An integrated circuit (IC) device includes a die area located in the cavity and is attached to the exposed region of the underside layer, and further includes bonding pads that are wire bonded to the connection conductors. The IC device is encapsulated in a passivating envelope; the passivating envelope extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors.
  • the semiconductor device comprises an underside layer having openings.
  • a carrier has a first side opposite a second side, wherein the first side includes a conductive layer that has a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors, and wherein the underside layer is an adhesive material.
  • the carrier includes a cavity defined between the first and second sides; a region of the underside layer is exposed.
  • An integrated circuit (IC) device includes a die area located in the cavity and is attached to the exposed region of the underside layer; the IC further includes bonding pads that are wire bonded to the connection conductors.
  • a passivating envelope encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors, wherein the side faces have recesses providing attachment to the passivating envelope.
  • the adhesive material may be selected from wafer backside laminate (WBL), glue, or QFN tape.
  • a semiconductor package comprises a lead frame with a first and a second side situated opposite to each other; the lead frame has a first conductive layer on the first side, the first conductive layer is patterned in a predetermined pattern, thereby defining a number of mutually isolated connection conductors, wherein on the second side, contact surfaces are defined in the connection conductors for placement on a substrate.
  • the cavity has an area and depth sufficient to accommodate an IC device, the depth of the cavity is a distance between the first side and second side of the carrier; and the cavity exposes a region of the underside layer.
  • the IC device is attached to the exposed region of the underside layer; the connection conductors have pad lands for electrically coupling the lead frame to bond pads on the IC device.
  • a molding compound encapsulates the IC device; the molding compound extends as far as the lead frame, wherein the molding compound is mechanically anchored into side faces in the connection conductors, the side faces having recesses therein and wherein the exposed region of the underside layer is not covered with molding compound, and the exposed region of the underside layer provides a seal between the molding compound and the IC device.
  • a method for packaging an IC device comprises attaching the IC device to a die attach region in a lead frame, the die attach region having adhesive deposited thereon and curing the adhesive.
  • the IC device is wire bonded to the lead frame.
  • the IC Device and lead frame are encapsulated in a passivating envelope.
  • the encapsulated IC device is etched. Underneath the IC device, adhesive at the die attach region is exposed.
  • FIG. IA depicts in top view a device die mounted on an example TULIP platform
  • FIG. IB (Prior Art) depicts a side view of the device die of FIG. IA;
  • FIGS. 2A - 2B depicts a QFN package in a side view and underside view, respectively, with the die pad;
  • FIGS. 2C - 2D depicts a QFN package in a side view and underside view respectively, with the die pad replaced with an underside layer according to an embodiment of the present invention
  • FIGS. 3A - 3G depicts in cross-section a series of steps in packaging a device die in accordance with an embodiment of the present invention
  • FIG. 4 is a flowchart of a process for assembling an IC device in a TULIP platform package according to an embodiment of the present invention.
  • FIG. 5 is an example array of packages before separation having undergonebackside etch according to an embodiment of the present invention.
  • the present invention has been found to be useful in reducing the thickness of packages used to package integrated circuit devices.
  • the invention eliminates the die paddle upon which the IC device is mounted without exposing the die to the outside environment.
  • the three-layer lead frame is configured to remove the two top layers of the lead frame and provide a mounting surface in lieu of the die paddle.
  • the IC device is attached to the mounting surface with WBL (Wafer Back Laminate) or glue.
  • a 0.5mm thick XSON package thickness is reduced 20% to a
  • SSON Packages may range from 2 input/output pins to about 200 input/output pins.
  • the body height thickness of a DHVQFN product before application of the present invention is about 0.85mm for a 0.5mm lead pitch.
  • the QFN tape is used as the WBL material. The body height is reduced from 0.85mm to about 0.4mm.
  • FIGS. 2A - 2B In an example package, a DHVQFN package 200 has been assembled. IC device 220 has been attached onto die pad 225 of lead frame 210. Wire bonds 230 connect the IC device 220 to pad landings 215.
  • the IC device 220 and lead frame 210 are encapsulated with a passivating envelope 205.
  • the passivating envelope is usually an encapsulating molding compound (EMC) suitable for a given package and manufacturing process.
  • EMC 205 is mechanically anchored to the lead frame 210 via recesses 240 defined in the lead frame 210.
  • the die pad 225 acts a built-in heat sink 225 to aid in dissipating heat generated by the energized IC device 220.
  • Pad landings 215 provide electrical connection of the packaged device to a printed circuit board substrate when soldered thereto.
  • the height of the assembled package is about 0.85mm.
  • FIG. 2A is a side view of FIG. 2B as indicated by dashed
  • a QFN package 300 uses QFN tape as a die attach adhesive in lieu of a die pad 225.
  • IC device 320 is mounted on the tape 325 to the lead frame 310 and encapsulated with a passivating envelope 305 of EMC.
  • Wire bonds 330 connect the IC device 320 to pad landings 315.
  • Pad landings 315 provide electrical connection of the packaged device 300 to a printed circuit board substrate when soldered thereto.
  • the EMC 305 is mechanically anchored to the lead frame 315 via recesses 340 defined in the lead frame 310.
  • FIG. 2C is a side view of FIG. 2D as indicated by dashed-line Y.
  • EMC 305 may be removed.
  • the die attach adhesive 325 is exposed.
  • the remaining adhesive 325 serves to seal the IC device 320 within the package 300.
  • the height of the assembled package is about 0.4mm.
  • the QFN tape may be replaced with wafer back laminate (WBL) material or glue.
  • the lead frame 315 may be of multiple metal layers (e.g., three layers as in the TULIP platform). The overall thickness of this lead frame may be sufficiently thin to yield the about 0.4mm finished height.
  • the lead frame may be prepared so that a thin bottom layer of lead frame serves as a die pad in addition to die attach adhesive. The advantages of a metal underside along with the thin profile of the die attach adhesive provides for a thinner device with a heat sink in the vicinity of the IC device underside.
  • the underside of the IC device 320 may be exposed and can provide cooling in lieu of the die pad 225 (that provides a heat sink) of the package of FIGS. 2A - 2B.
  • the heat sink component 225 has been eliminated as well as the die pad in the lead frame 215.
  • a lead frame 100 having three layers 105, 110, and 115 may be used, as depicted in FIG. 3 A.
  • the first layer 105 and third layer 115 may be copper or a copper- rich alloy.
  • the second layer 110 may be nickel (Ni), molybdenum (Mo), or titanium (Ti).
  • the second layer 110 may be aluminum or an aluminum-rich alloy.
  • the process of Kloen et al. may be used to define a die cavity 110a and the configuration of the lead frame 100 and the location of lead frame recesses 135 which will provide additional anchoring strength to the molding compound used to encapsulate the lead frame 100.
  • the configuration of the lead frame 100 includes the mapping out of the number of pads, location of power/ground, etc. to form mutually isolated connection conductors 145. Design techniques known in the art are used.
  • the die pad 60 (as depicted in FIG. IB) is, however, is omitted.
  • Two layers 105 and 110 may be etched to leave the third copper layer 115.
  • the copper layer 115 remains to provide a die attach location 115a.
  • Areas 135 that are ultimate location of recesses are defined, as well. As shown in FIG. 3C, with a selective etch, the recesses 135 are formed such that the aluminum second layer 110 forms an indentation with respect to the copper first layer 105 and third layer 115.
  • IC device 125 is attached with an adhesive layer 120 is applied to the die attach location 115a.
  • wire bonds 130 connect the IC device 125 (at bond pads 125a) to defined locations on the lead frame 100.
  • the wire bonded IC device is encapsulated in a molding compound 140 as shown in FIG. 3F.
  • the molding compound 140 has sealed the IC device 125 to the lead frame 100.
  • the molding compound 140 has additional anchoring at the recesses 135.
  • the third copper layer 115 is etched away, exposing the WBL layer 120 or the die attach glue layer 120.
  • Contacts 115b couple the mutually isolated connection conductors 145 of the lead frame 100 to corresponding wirebonded connections 130 of the IC device die 125.
  • an IC device may be packaged.
  • a lead frame suitable for a given application is selected 5.
  • the IC die is attached lead frame to the lead frame with an adhesive 10.
  • the adhesive may be a glue or sticky tape (e.g., QFN tape applied as a die carrier). After attaching the die, the adhesive is cured. The die is then wire bonded 15.
  • the bonded die and lead frame assembly is encapsulated in a passivating envelope. In a particular example process, the assembly is tablet molded and post cured 20. Tablet molding (or map molding) is applied in QFN-type packages to encapsulate in one step, all IC devices in a strip.
  • the maps in the strip are encapsulated in the mold compound, later separate devices are sawn out of the map.
  • the strip is baked in an oven at about 150oC. Often a weight is placed on the strip to enhance the curing of the mold compound and the flatness of the strip.
  • the encapsulated IC device undergoes a back etch 25. The etch isolates the contact pads of the lead frame and exposes the underside of the IC die up to the die attach adhesive.
  • the IC devices undergo electrical test 30 in an "in-strip test.”
  • the IC devices are separated and taped 35. Defective devices are discarded.
  • the package IC device strip may be arranged, as in the example in an array 400 of FIG. 4.
  • the IC device 405 IC die 415 is covered by exposed die attach adhesive 415. Lines A and B and C and D indicate where the IC device(s) 405 are separated from one-another in the array 400.

Abstract

In an example embodiment, a semiconductor device comprises an underside layer having openings. A carrier has a first side opposite a second side; the first side includes a first conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors; the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate. The openings in the underside layer permit access to the connection conductors. The carrier includes a cavity defined between the first and second sides and exposing a region of the underside layer. An integrated circuit (IC) device including a die area is located in the cavity and is attached to the exposed region of the underside layer, and further includes bonding pads that are wire bonded to the connection conductors. A passivating envelope encapsulates the IC device and extends as far as the carrier; the passivating envelope is mechanically anchored into side faces in the connection conductors.

Description

THIN PROFILE PACKAGING WITH EXPOSED DIE ATTACH ADHESIVE
The invention relates to integrated circuit (IC) packaging. More particularly this invention relates to the achieving a thinner packaging profile by mounting an IC device die directly upon exposed die attach adhesive.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher- function devices in more compact areas. For many applications realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
Many varieties of semiconductor devices have been manufactured with various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal- oxide- semiconductor field-effect transistors (MOSFET), such as p- channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors. Such MOSFET devices include an insulating material between a conductive gate and silicon-like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET).
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
Furthermore, such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc. The substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
After undergoing the process of fabrication, the silicon wafer has a predetermined number of devices. These devices are tested. Good devices are mapped on the wafer. Good devices are then packaged. However, in some applications, the thickness of the wafer substrate may be a challenge as electronic devices become thinner in such devices as wireless phones, laptop computers, watches, etc. Excess dimensions of length, width, and thickness have to be minimized. Thus in meeting the challenge of excessive thickness, prior to separating out individual IC devices, the wafer substrate is often ground and polished on its backside to reduce the die thickness and to provide a surface to which it may be die attached. However, the resulting thin substrate may pose challenges in later processing become too brittle to handle with modern automated equipment. As wafer substrates approach 30 cm and larger, substrate thickness further increases (owing to strength requirements in the wafer fabrication and handling). The challenge of packaging the more complex and thicker device die becomes more demanding. Although the complex requirements of the devices, such as RF, pin outs, functionality, etc. have been addressed by modern packaging, there continues the balancing of application requirements with the physical dimensional limitations of electronic packaging.
One example package platform that is suitable for high performance devices, may be found in International Application published under the Patent Cooperation Treaty (PCT) titled, "Semiconductor Device and Method of Manufacturing Same," of KIo en et al. (International Publication Number, WO 03/085731, Publication Date: 16-October-2003) and in US Patent Application 10/510,591 filed on October 8, 2004 titled, "Semiconductor Device and Method of Manufacturing Same," of the same inventors. This package is a known as a Thin Universal Leadless Industrial Package (i.e., TULIP). Another example package may be found in International Application published under the PCT titled, "Carrier, Method of Manufacturing a Carrier and an Electronic Device," of Groenhuis et al. (International Publication Number, WO 03/085728, Publication Date: 16-October-2003) and in US Patent Application 10/510,588 filed on October 8, 2004 titled, "Carrier, Method of Manufacturing a Carrier and an Electronic Device," of the same inventors. These references are incorporated by reference in their entirety. Packages encompassing this platform include, but are not limited to, DQFN (Depopulated very-thin Quad Flat-pack No-leads), HVQFN (Heatsink Very-thin Quad Flat-pack No-leads) and BGA (Ball Grid Array), SSON (Shrink Small Outline; No leads), XSON (eXtremely thin Small Outline; No leads) and TFBGA (Thin Fine-pitch Ball Grid Array) packages.
Refer to FIG. IA. In an example QFN package 10, an IC device 5 has been placed therein. In this particular example, there are two sets of pad landings 30, 35. Refer to FIG. IB. The QFN package 10 uses a lead frame 75. Lead frame 75 includes three layers. The first layer 15 and third layer 25 may be copper or a copper-rich alloy. In one example package, the second layer 20 may be nickel (Ni), molybdenum (Mo), or titanium (Ti). In another example package, the second layer 20 may be aluminum or an aluminum-rich alloy. IC device 5 is attached with a suitable die-attach material 50 (e.g., laminating compound, or glue) to a die pad 60. Bond wires 40 and 45 connect the IC device to pad landings 30, 35. The pad landings connect to the lead frame 75. Pads (not illustrated) are defined in the first layer 10 of the lead frame provide electrical connection of the IC device to a chosen application. Recesses 55 provide a mechanical anchor (by forming plugs) substantially enhancing the adhesion of molding compound that is used to encapsulate the IC device 5.
The technology embraced by the TULIP package platform addresses a need for a robust encapsulation and reduced package thickness. However, in some demanding applications, the device packaging thickness significantly decreases the desirability of the finished product. There is exists a need for a package and method that may achieve a thinner device die thickness and avoid the issues inherent in the reducing of wafer substrate thickness prior to packaging and sealing.
The present invention has been found to be useful in reducing the thickness of packages used in integrated circuit assembly. The invention eliminates the die paddle upon which the IC device is mounted without exposing the die to the outside environment. Eliminating the die paddle reduces the package thickness about 20% for an example package.
In an example embodiment, there is a semiconductor device that comprises an underside layer having openings. A carrier has a first side opposite a second side, wherein the first side includes a first conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductor. The carrier includes a cavity defined between the first and second sides and exposing a region of the underside layer. An integrated circuit (IC) device includes a die area located in the cavity and is attached to the exposed region of the underside layer, and further includes bonding pads that are wire bonded to the connection conductors. The IC device is encapsulated in a passivating envelope; the passivating envelope extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors.
In another example embodiment, there is a semiconductor device. The semiconductor device comprises an underside layer having openings. A carrier has a first side opposite a second side, wherein the first side includes a conductive layer that has a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors, and wherein the underside layer is an adhesive material. The carrier includes a cavity defined between the first and second sides; a region of the underside layer is exposed. An integrated circuit (IC) device includes a die area located in the cavity and is attached to the exposed region of the underside layer; the IC further includes bonding pads that are wire bonded to the connection conductors. A passivating envelope encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors, wherein the side faces have recesses providing attachment to the passivating envelope. A feature of this embodiment includes that the adhesive material may be selected from wafer backside laminate (WBL), glue, or QFN tape.
In another embodiment according to the present invention, a semiconductor package comprises a lead frame with a first and a second side situated opposite to each other; the lead frame has a first conductive layer on the first side, the first conductive layer is patterned in a predetermined pattern, thereby defining a number of mutually isolated connection conductors, wherein on the second side, contact surfaces are defined in the connection conductors for placement on a substrate. There is an underside layer in contact with the second side, the underside layer has openings defined therein, the openings permit access to the connection conductors. Defined in the lead frame there is a cavity, the cavity has an area and depth sufficient to accommodate an IC device, the depth of the cavity is a distance between the first side and second side of the carrier; and the cavity exposes a region of the underside layer. The IC device is attached to the exposed region of the underside layer; the connection conductors have pad lands for electrically coupling the lead frame to bond pads on the IC device. A molding compound encapsulates the IC device; the molding compound extends as far as the lead frame, wherein the molding compound is mechanically anchored into side faces in the connection conductors, the side faces having recesses therein and wherein the exposed region of the underside layer is not covered with molding compound, and the exposed region of the underside layer provides a seal between the molding compound and the IC device.
In yet another embodiment, there is a method for packaging an IC device. The method comprises attaching the IC device to a die attach region in a lead frame, the die attach region having adhesive deposited thereon and curing the adhesive. The IC device is wire bonded to the lead frame. The IC Device and lead frame are encapsulated in a passivating envelope. The encapsulated IC device is etched. Underneath the IC device, adhesive at the die attach region is exposed. The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows.
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
FIG. IA (Prior Art) depicts in top view a device die mounted on an example TULIP platform;
FIG. IB (Prior Art) depicts a side view of the device die of FIG. IA;
FIGS. 2A - 2B depicts a QFN package in a side view and underside view, respectively, with the die pad;
FIGS. 2C - 2D depicts a QFN package in a side view and underside view respectively, with the die pad replaced with an underside layer according to an embodiment of the present invention;
FIGS. 3A - 3G depicts in cross-section a series of steps in packaging a device die in accordance with an embodiment of the present invention;
FIG. 4 is a flowchart of a process for assembling an IC device in a TULIP platform package according to an embodiment of the present invention; and
FIG. 5 is an example array of packages before separation having undergonebackside etch according to an embodiment of the present invention.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims
The present invention has been found to be useful in reducing the thickness of packages used to package integrated circuit devices. The invention eliminates the die paddle upon which the IC device is mounted without exposing the die to the outside environment. For example, in the TULIP package platform, the three-layer lead frame is configured to remove the two top layers of the lead frame and provide a mounting surface in lieu of the die paddle. The IC device is attached to the mounting surface with WBL (Wafer Back Laminate) or glue.
For example, a 0.5mm thick XSON package thickness is reduced 20% to a
0.4mm maximum SSON package, yet the attributes of the TULIP platform are preserved. SSON Packages may range from 2 input/output pins to about 200 input/output pins. In another example package, the body height thickness of a DHVQFN product before application of the present invention is about 0.85mm for a 0.5mm lead pitch. In applying the present invention, the die pad being eliminated, the QFN tape is used as the WBL material. The body height is reduced from 0.85mm to about 0.4mm.
Refer to FIGS. 2A - 2B. In an example package, a DHVQFN package 200 has been assembled. IC device 220 has been attached onto die pad 225 of lead frame 210. Wire bonds 230 connect the IC device 220 to pad landings 215. The IC device 220 and lead frame 210 are encapsulated with a passivating envelope 205. The passivating envelope is usually an encapsulating molding compound (EMC) suitable for a given package and manufacturing process. The EMC 205 is mechanically anchored to the lead frame 210 via recesses 240 defined in the lead frame 210. The die pad 225 acts a built-in heat sink 225 to aid in dissipating heat generated by the energized IC device 220. Pad landings 215 provide electrical connection of the packaged device to a printed circuit board substrate when soldered thereto. The height of the assembled package is about 0.85mm. FIG. 2A is a side view of FIG. 2B as indicated by dashed-line X.
Refer to FIGS. 2C - 2D. In an example, embodiment according to the present invention, a QFN package 300 uses QFN tape as a die attach adhesive in lieu of a die pad 225. IC device 320 is mounted on the tape 325 to the lead frame 310 and encapsulated with a passivating envelope 305 of EMC. Wire bonds 330 connect the IC device 320 to pad landings 315. Pad landings 315 provide electrical connection of the packaged device 300 to a printed circuit board substrate when soldered thereto. The EMC 305 is mechanically anchored to the lead frame 315 via recesses 340 defined in the lead frame 310. FIG. 2C is a side view of FIG. 2D as indicated by dashed-line Y.
After an under side etch of the QFN package 300, EMC 305 may be removed. The die attach adhesive 325 is exposed. The remaining adhesive 325 serves to seal the IC device 320 within the package 300. The height of the assembled package is about 0.4mm.
In another example embodiment according to the present invention, the QFN tape may be replaced with wafer back laminate (WBL) material or glue. In yet another example embodiment, the lead frame 315 may be of multiple metal layers (e.g., three layers as in the TULIP platform). The overall thickness of this lead frame may be sufficiently thin to yield the about 0.4mm finished height. The lead frame may be prepared so that a thin bottom layer of lead frame serves as a die pad in addition to die attach adhesive. The advantages of a metal underside along with the thin profile of the die attach adhesive provides for a thinner device with a heat sink in the vicinity of the IC device underside.
In another example embodiment according to the present invention, the underside of the IC device 320 may be exposed and can provide cooling in lieu of the die pad 225 (that provides a heat sink) of the package of FIGS. 2A - 2B. In the aforementioned example, the heat sink component 225 has been eliminated as well as the die pad in the lead frame 215.
Refer to FIGS. 3 A - 3G. In an example embodiment according to the present invention, a lead frame 100 having three layers 105, 110, and 115 may be used, as depicted in FIG. 3 A. The first layer 105 and third layer 115 may be copper or a copper- rich alloy. In one example package, the second layer 110 may be nickel (Ni), molybdenum (Mo), or titanium (Ti). In another example package, the second layer 110 may be aluminum or an aluminum-rich alloy.
In FIG. 3B, the process of Kloen et al. may be used to define a die cavity 110a and the configuration of the lead frame 100 and the location of lead frame recesses 135 which will provide additional anchoring strength to the molding compound used to encapsulate the lead frame 100. The configuration of the lead frame 100 includes the mapping out of the number of pads, location of power/ground, etc. to form mutually isolated connection conductors 145. Design techniques known in the art are used. The die pad 60 (as depicted in FIG. IB) is, however, is omitted. Two layers 105 and 110 may be etched to leave the third copper layer 115. The copper layer 115 remains to provide a die attach location 115a. Areas 135 that are ultimate location of recesses are defined, as well. As shown in FIG. 3C, with a selective etch, the recesses 135 are formed such that the aluminum second layer 110 forms an indentation with respect to the copper first layer 105 and third layer 115. In FIG. 3D, IC device 125 is attached with an adhesive layer 120 is applied to the die attach location 115a. In FIG. 3E, wire bonds 130 connect the IC device 125 (at bond pads 125a) to defined locations on the lead frame 100. The wire bonded IC device is encapsulated in a molding compound 140 as shown in FIG. 3F. The molding compound 140 has sealed the IC device 125 to the lead frame 100. In addition to the molding compound's adhesive strength, the molding compound 140 has additional anchoring at the recesses 135. Refer to 3G. The third copper layer 115 is etched away, exposing the WBL layer 120 or the die attach glue layer 120. Contacts 115b couple the mutually isolated connection conductors 145 of the lead frame 100 to corresponding wirebonded connections 130 of the IC device die 125.
Refer to FIG. 4. In an example embodiment according to the present invention, an IC device may be packaged. A lead frame suitable for a given application is selected 5. The IC die is attached lead frame to the lead frame with an adhesive 10. The adhesive may be a glue or sticky tape (e.g., QFN tape applied as a die carrier). After attaching the die, the adhesive is cured. The die is then wire bonded 15. The bonded die and lead frame assembly is encapsulated in a passivating envelope. In a particular example process, the assembly is tablet molded and post cured 20. Tablet molding (or map molding) is applied in QFN-type packages to encapsulate in one step, all IC devices in a strip. The maps in the strip are encapsulated in the mold compound, later separate devices are sawn out of the map. During post-cure, the strip is baked in an oven at about 150oC. Often a weight is placed on the strip to enhance the curing of the mold compound and the flatness of the strip. The encapsulated IC device undergoes a back etch 25. The etch isolates the contact pads of the lead frame and exposes the underside of the IC die up to the die attach adhesive. The IC devices undergo electrical test 30 in an "in-strip test." The IC devices are separated and taped 35. Defective devices are discarded. The package IC device strip may be arranged, as in the example in an array 400 of FIG. 4. The IC device 405 IC die 415 is covered by exposed die attach adhesive 415. Lines A and B and C and D indicate where the IC device(s) 405 are separated from one-another in the array 400.
While the present invention has been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention, which is set forth in the following claims.

Claims

Claims
1. A semiconductor device comprising:
an underside layer having openings;
a carrier having a first side opposite a second side, wherein the first side includes a conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors;
the carrier including a cavity defined between the first and second sides and exposing a region of the underside layer;
an integrated circuit (IC) device including a die area located in the cavity and attached to the exposed region of the underside layer, and further including bonding pads that are wire bonded to the connection conductors; and
a passivating envelope that encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors.
2. The semiconductor device as recited in claim 1, wherein the side faces have recesses therein, the recesses providing attachment to the passivating envelope.
3. The semiconductor device as recited in claim 1, wherein in the conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer, the second conductive layer comprising a material that can be etched in an etchant that leaves the first conductive layer and the third conductive layer substantially intact.
4. The semiconductor device as recited in claim 3, wherein the third conductive layer is used as the underside layer.
5. The semiconductor device as recited in claim 4, wherein the IC device is attached to the exposed region of the underside layer with one of the following: wafer backside laminate (WBL), glue, and QFN tape.
6. The semiconductor device as recited in claim 5, wherein the third conductive layer used as the underside layer is patterned, defining:
an area in the exposed region corresponding to the die area of the IC device; and
the contact surfaces corresponding to the connection conductors for placement over a substrate.
7. A semiconductor device comprising:
an underside layer having openings;
a carrier having a first side opposite a second side, wherein the first side includes a conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors, and wherein the underside layer is an adhesive material,
the carrier including a cavity defined between the first and second sides and exposing a region of the underside layer;
an integrated circuit (IC) device including a die area located in the cavity and attached to the exposed region of the underside layer, and further including bonding pads that are wire bonded to the connection conductors; and
a passivating envelope that encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors, wherein the side faces having recesses providing attachment to the passivating envelope.
8. The semiconductor device of claim 7, wherein the adhesive material is selected from one of the following: wafer backside laminate (WBL), glue, QFN tape.
9. A semiconductor package comprising:
a lead frame with a first and a second side situated opposite to each other, the lead frame having a first conductive layer on the first side, the first conductive layer is patterned in a predetermined pattern, thereby defining a number of mutually isolated connection conductors, wherein on the second side, contact surfaces are defined in the connection conductors for placement on a substrate;
an underside layer in contact with the second side, the underside layer having openings defined therein, the openings permitting access to the connection conductors; a cavity defined in the lead frame, the cavity having an area and depth sufficient to accommodate an IC device, the depth of the cavity being a distance between the first side and second side of the carrier, and the cavity exposing a region of the underside layer, the IC device being attached to the exposed region of the underside layer, the connection conductors having pad lands for electrically coupling the lead frame to bond pads on the IC device; and
a molding compound encapsulating the IC device, the molding compound extending as far as the lead frame, wherein the molding compound is mechanically anchored into side faces in the connection conductors, the side faces having recesses therein and wherein the exposed region of the underside layer is not covered with molding compound, and the exposed region of the underside layer provides a seal between the molding compound and the IC device.
10. The semiconductor package as recited in claim 7, wherein the underside layer is selected from the following: wafer backside laminate (WBL), glue, and QFN tape.
11. A method for packaging an IC device, the method comprising:
attaching the IC device to a die attach region in a lead frame, the die attach region having adhesive deposited thereon and curing the adhesive;
wire bonding the IC device to the lead frame;
encapsulating the IC device and lead frame with a passivating envelope; and
etching the encapsulated IC device and exposing the adhesive underneath the IC device.
12. The method as recited in claim 11, further comprising,
in-strip testing (30) of the IC devices; and
separating and taping (35) packaged devices.
13. The method as recited in claim 10, wherein during etching of the encapsulated IC device, the adhesive underneath the IC device is removed completely.
PCT/IB2007/050979 2007-03-20 2007-03-20 Thin profile packaging with exposed die attach adhesive WO2008114094A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IB2007/050979 WO2008114094A1 (en) 2007-03-20 2007-03-20 Thin profile packaging with exposed die attach adhesive

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2007/050979 WO2008114094A1 (en) 2007-03-20 2007-03-20 Thin profile packaging with exposed die attach adhesive

Publications (1)

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WO2008114094A1 true WO2008114094A1 (en) 2008-09-25

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