WO2008094888A1 - Fabrication process for nanotube-cmos integration - Google Patents

Fabrication process for nanotube-cmos integration Download PDF

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Publication number
WO2008094888A1
WO2008094888A1 PCT/US2008/052273 US2008052273W WO2008094888A1 WO 2008094888 A1 WO2008094888 A1 WO 2008094888A1 US 2008052273 W US2008052273 W US 2008052273W WO 2008094888 A1 WO2008094888 A1 WO 2008094888A1
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Prior art keywords
nanotube
cmos
nanotubes
protective layer
electrical contacts
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PCT/US2008/052273
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French (fr)
Inventor
Peter J. Burke
Steffen Mckernan
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Steffen Mckernan
Burke Peter J
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Application filed by Steffen Mckernan, Burke Peter J filed Critical Steffen Mckernan
Publication of WO2008094888A1 publication Critical patent/WO2008094888A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • This disclosure relates generally to the field of nanotube coated wafers and, more particularly, to a process for preparing nanotube coated wafers with electrical contacts and dielectric which is compatible with follow-on industry standard CMOS processing steps.
  • CNT field-effect transistor (FET) devices both single walled nanotubes (SWNTS) and multiwalled nanotubes (MWNTs) have promise in electronics.
  • CNT FET performance may be superior to Si CMOS performance, especially in analog applications requiring high frequency, power density, linearity and low noise.
  • Si CMOS is a mature, well-developed technology which can possess superior characteristic over carbon nanotube devices in other metrics, especially for digital logic and circuit density.
  • a method for preparing nanotube coated wafers with electrical contacts and a dielectric in a manner that is compatible with follow-on industry standard CMOS processing steps.
  • a process for fabricating CNT FET devices comprising providing nanotube coated wafers for subsequent CMOS processing steps (e.g., by providing the nanotube coated wafer to a semiconductor foundry) that (1 ) are fully compatible with existing semiconductor foundry equipment, (2) provide protection for the nanotubes already deposited on the wafer from certain subsequent CMOS processing steps that could otherwise be damaging (e.g., pre-processing cleaning steps in CMOS), and (3) do not expose existing semiconductor processing equipment to any new materials, i.e., all of the materials used in forming the CNT FETs that would be exposed to subsequent CMOS processing are industry standard and well-characterized to CMOS processes.
  • a method for preparing nanotube coated wafers with electrical contacts and a dielectric suitable for subsequent CMOS processing.
  • a dielectric such as a pad dielectric
  • Catalysts are then deposited on the pad dielectric.
  • Nanotubes are then deposited using techniques such as CVD, adjacent to the catalysts on the pad dielectric.
  • Electrical contacts are then deposited in contact with the nanotubes.
  • a protective dielectric layer such as SiN, is deposited over the nanotubes.
  • a nanotube coated wafer formed in this manner is compatible with follow-on industry standard CMOS processing steps.
  • the nanotube protection layer can also serve as a gate electrode in the CMOS circuitry that is subsequently formed on the wafer.
  • FIGS. 1-6 illustrate a process for preparing nanotube coated wafers with electrical contacts and a dielectric which is compatible with follow-on industry standard CMOS processing steps in accordance with one or more embodiments of the present disclosure.
  • the present disclosure is directed to a method for preparing nanotube coated wafers with electrical contacts and a dielectric which are compatible with follow-on industry standard CMOS processing steps.
  • numerous embodiments are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art, that these and other embodiments may be practiced without these specific details. In other instances, well-known features have not been described in detail in order not to obscure the invention.
  • a method for preparing nanotube coated wafers will be described with reference to the cross-sectional views in the process flow diagrams illustrated in FIGS. 1-6.
  • a pad dielectric 102 is deposited via industry standard methods on a cleaned, bare silicon (Si) wafer 100, where the pad dielectric 102 may comprise an oxide, nitride or other dielectric material as commonly used in the semiconductor industry.
  • the Si wafer 100 comprises 150 mm, p- type, ⁇ 100>, 36-63 ohm-cm Si.
  • the wafer 100 may be formed of any type of Si or other wafer material as commonly used in CMOS processes.
  • the wafer 102 will include a nanotube circuitry region 104 and a CMOS circuitry region 106.
  • Catalysts 108 are then deposited on a portion of the pad dielectric 102 in the nanotube circuitry region 104, where the catalysts 108 are useful in promoting synthesis of nanotubes.
  • catalysts 108 comprise a transition metal such as Fe, Ni, or Cu.
  • Nanotubes 110 are then deposited using industry standard methods (e.g., using CVD techniques) on the pad dielectric 102 adjacent to the catalysts 108.
  • Nanotubes 110 may comprise any type of nanotubes, including but not limited carbon nanotubes (CNTs), single walled nanotubes (SWNTS) and multiwalled nanotubes (MWNTs).
  • Electrical contacts 112 are deposited on the nanotubes 110.
  • a layer of copper or any other industry standard metal can be deposited on top of the electrical contacts 112 in order to prevent of the electrical contacts 112 from being exposed during later processing of the wafer 100.
  • a protective layer 114 is then deposited over the surface of the nanotube circuitry region 104 and the CMOS circuitry region 106.
  • the protective layer 114 may comprise a nitride layer, such as SiN, or another protective material commonly used in
  • the protective layer 114 serves as the dielectric layer for nanotube devices requiring a gate, such as a transistor. In one or more embodiments, the protective layer 114 serves as a protecting layer to prevent the nanotubes 110 from being damaged during subsequent processes performed on the wafer 100 in conventional CMOS fabrication processes. For instance, the protective layer 114 provides protection against acid (HF) cleaning steps and other CMOS processes. In one or more embodiments, the protective layer 114 further keeps CMOS processing equipment used for subsequent CMOS process steps from being exposed to any new materials that are not normally encountered in CMOS processes. In this manner, the protective layer 114 includes materials that are normally encountered in subsequent CMOS processing steps and serves as a barrier to the materials in the nanotube circuitry region 104 underneath the protective layer 114.
  • HF acid
  • the CMOS circuitry region 106 will not contain any nanotubes 110 but will contain only industry standard materials typically used in CMOS processes (e.g., will only comprise materials such as Si/SiO2/SiN). Further, the nanotube circuitry region 104 will be covered by a protective layer 114 composing a material that is also typically used in CMOS processes. Thereby, a nanotube coated wafer 100 formed with electrical contacts 112 and a dielectric 114 in accordance with one or more embodiments described herein is then compatible with any follow-on industry standard CMOS processing steps.
  • CMOS process used by the UC Berkeley Microlab as described in the electronic document baseline_xsection_2005_UCBerkeley.pdf as stored at http://microlab/berkeley.edu/baseline, the contents of which are incorporated herein by reference.
  • the UC Berkeley Microlab CMOS process describes using a certain starting material for the Si CMOS process (e.g,. as shown on slide 2 of the document), where the present disclosure teaches a process of generating a modified resultant material (together with buried nanotube devices in the nanotube circuitry region 104 that could be used for the starting material for the UC Berkeley Microlab CMOS process.
  • the present invention is not intended to be limited to the UC Berkeley Microlab CMOS process but could be used as the starting material with any subsequent industry CMOS process.
  • the electrical contacts 112 can be deposited in such a way that a consistent map of devices is produced with known locations of electrical contact pads 112 so that these devices can be electrically connected to other circuits created in later CMOS processing steps or other processing steps.
  • the contact pads 112 for other circuits are preferably made with a material that has maximum compatibility with the subsequent processes.
  • Known electrical characteristics of these nanotube devices can then be added to and utilized in a design kit to further simplify the design of more functional circuits with a mixture of elements and interconnections.
  • the protective layer 114 may completely cover the surface of the wafer 100 or alternatively only cover those portions to be protected (e.g., only the nanotube circuitry region 104).
  • a gate electrode (not shown) can be created before depositing the protective layer 114.
  • the further processing of the wafer 100 that is performed may include removing nanotube 110 devices on areas of the wafer 100 where nanotube 110 devices are not needed.
  • the process for preparing a nanotube coated wafer 100 as described herein provides electrically contacted nanotubes 110 on a wafer 100 for subsequent CMOS processing without introducing new materials to be encountered during the subsequent CMOS processing. Therefore, the prepared nanotube coated wafer 100 can be utilized with the industry standards for Si CMOS fabrication processes in order to achieve successful integration of CNTs with CMOS processes.
  • nanotube gates of poly-Si can be provided, similar to those used in CMOS circuitry, and CNTs may interconnect in substantially the same manner as CMOS circuitry, with the exception that the contact to Pd nanotube source/drain electrodes in the nanotube circuitry region 104 would require a hole in silicon nitride.
  • CMOS circuitry similar to those used in CMOS circuitry
  • CNTs may interconnect in substantially the same manner as CMOS circuitry, with the exception that the contact to Pd nanotube source/drain electrodes in the nanotube circuitry region 104 would require a hole in silicon nitride.
  • Various aspects of the above-described process can be utilized for any circuit in which CNT-CMOS integration is required, e.g. RF mixed signal chips for wireless communications and wired communications circuitry.

Abstract

A method is provided for preparing a nanotube coated wafer with electrical contacts and a dielectric that is compatible with follow-on industry standard CMOS processing steps. In one or more embodiments of the present disclosure, a process is provided for fabricating CNT FET devices comprising providing nanotube coated wafers for subsequent CMOS processing steps (e.g., by providing the nanotube coated wafer to a semiconductor foundry) that (1 ) are fully compatible with existing semiconductor foundry equipment, (2) provide protection for the nanotubes already in place on the wafer from certain CMOS processing steps that could otherwise be damaging (e.g., pre-processing cleaning steps in CMOS), and (3) do not expose existing semiconductor processing equipment to any new materials, i.e. all exposed materials are industry standard to CMOS processing and well-characterized.

Description

FABRICATION PROCESS FOR NANOTUBE-CMOS INTEGRATION
TECHNICAL FIELD
[0001] This disclosure relates generally to the field of nanotube coated wafers and, more particularly, to a process for preparing nanotube coated wafers with electrical contacts and dielectric which is compatible with follow-on industry standard CMOS processing steps.
BACKGROUND
[0002] Carbon nanotube (CNT) field-effect transistor (FET) devices, both single walled nanotubes (SWNTS) and multiwalled nanotubes (MWNTs), have promise in electronics. In some applications, CNT FET performance may be superior to Si CMOS performance, especially in analog applications requiring high frequency, power density, linearity and low noise. However, Si CMOS is a mature, well-developed technology which can possess superior characteristic over carbon nanotube devices in other metrics, especially for digital logic and circuit density.
[0003] Prior attempts to integrate Si CMOS with CNT FETs in order to capitalize on the benefits associated with both technologies have suffered many drawbacks. One such prior approach is described in the article, "Monolithic Integration of Carbon Nanotube Devices with Silicon Mos Technology," by Y. C. Tseng, P. Q. Xuan, A. Javey, R. Malloy, Q. Wang, J. Bokor and H. J. Dai, Nano Letters, 4, pp. 123-127, (2004). This approach first fabricated Si MOS circuitry, including several layers of interconnects, and then grew carbon nanotubes on top of this circuitry. To grow high quality single walled carbon nanotubes (SWNTs) using chemical vapor deposition (CVD) generally requires growth temperatures of 900 °C or more. These high temperatures tend to damage standard Si MOS circuitry, including but not limited to the interconnect metal (Cu) typically used Si MOS circuitry. For this reason, this prior approach used a refractory metal (Mo) for the interconnects, which is not standard in Si MOS industry processes and which has a higher resistivity than Cu. Hence, Mo is not an ideal interconnect material for Si MOS circuitry, and this approach of integrating Si CMOS with CNT FETs has severe drawbacks.
[0004] Another approach of integrating Si CMOS with CNT FETs involved SWNT CVD techniques that synthesized SWNTs on top of pre-existing Si CMOS circuitry, as described in "Catalytic Chemical Vapor Deposition of Single-Wall Carbon Nanotubes at Low Temperatures", M. Cantoro, S. Hofmann, S. Pisana, V. Scardaci, A. Parvez, C. Ducati, A. C. Ferrari, A. M. Blackburn, K. Y. Wang and J. Robertson, Nano Letters, 6, 1107-1112, (2006). This approach has suffered the drawback that the SWNTs so synthesized may have a much higher defect density, which would result in lower mobility and hence lower speed for the SWNT FET devices.
[0005] Another approach attempting to integrate CNTs with CMOS processes involved dissolving nanotubes in a solution and then positioning them into place using a deposition from solution technique onto a pre-fabhcated Si CMOS circuit. The dissolved nanotubes from this approach are undesirable in that they can generally be full of defects, which again limits the mobility and ultimately the speed of CNT FET devices.
SUMMARY
[0006] According to a feature of the disclosure, a method is provided for preparing nanotube coated wafers with electrical contacts and a dielectric in a manner that is compatible with follow-on industry standard CMOS processing steps.
[0007] In one or more embodiments of the present disclosure, a process is provided for fabricating CNT FET devices comprising providing nanotube coated wafers for subsequent CMOS processing steps (e.g., by providing the nanotube coated wafer to a semiconductor foundry) that (1 ) are fully compatible with existing semiconductor foundry equipment, (2) provide protection for the nanotubes already deposited on the wafer from certain subsequent CMOS processing steps that could otherwise be damaging (e.g., pre-processing cleaning steps in CMOS), and (3) do not expose existing semiconductor processing equipment to any new materials, i.e., all of the materials used in forming the CNT FETs that would be exposed to subsequent CMOS processing are industry standard and well-characterized to CMOS processes.
[0008] In one or more embodiments, a method is provided for preparing nanotube coated wafers with electrical contacts and a dielectric suitable for subsequent CMOS processing. Initially, a dielectric, such as a pad dielectric, is deposited on a cleaned, bare silicon (Si) wafer. Catalysts are then deposited on the pad dielectric. Nanotubes are then deposited using techniques such as CVD, adjacent to the catalysts on the pad dielectric. Electrical contacts are then deposited in contact with the nanotubes. Lastly, a protective dielectric layer, such as SiN, is deposited over the nanotubes. A nanotube coated wafer formed in this manner is compatible with follow-on industry standard CMOS processing steps. In one or more embodiments, the nanotube protection layer can also serve as a gate electrode in the CMOS circuitry that is subsequently formed on the wafer.
DRAWINGS
[0009] The above-mentioned features and objects of the present disclosure will become more apparent with reference to the following description taken in conjunction with the accompanying drawings wherein like reference numerals denote like elements and in which:
[0010] FIGS. 1-6 illustrate a process for preparing nanotube coated wafers with electrical contacts and a dielectric which is compatible with follow-on industry standard CMOS processing steps in accordance with one or more embodiments of the present disclosure.
DETAILED DESCRIPTION
[0011] The present disclosure is directed to a method for preparing nanotube coated wafers with electrical contacts and a dielectric which are compatible with follow-on industry standard CMOS processing steps. In the following description, numerous embodiments are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art, that these and other embodiments may be practiced without these specific details. In other instances, well-known features have not been described in detail in order not to obscure the invention.
[0012] In one or more embodiments, a method for preparing nanotube coated wafers will be described with reference to the cross-sectional views in the process flow diagrams illustrated in FIGS. 1-6. Initially, a pad dielectric 102 is deposited via industry standard methods on a cleaned, bare silicon (Si) wafer 100, where the pad dielectric 102 may comprise an oxide, nitride or other dielectric material as commonly used in the semiconductor industry. In one embodiment, the Si wafer 100 comprises 150 mm, p- type, <100>, 36-63 ohm-cm Si. However, it is understood that the wafer 100 may be formed of any type of Si or other wafer material as commonly used in CMOS processes. The wafer 102 will include a nanotube circuitry region 104 and a CMOS circuitry region 106.
[0013] Catalysts 108 are then deposited on a portion of the pad dielectric 102 in the nanotube circuitry region 104, where the catalysts 108 are useful in promoting synthesis of nanotubes. In one or more embodiments, catalysts 108 comprise a transition metal such as Fe, Ni, or Cu. Nanotubes 110 are then deposited using industry standard methods (e.g., using CVD techniques) on the pad dielectric 102 adjacent to the catalysts 108. Nanotubes 110 may comprise any type of nanotubes, including but not limited carbon nanotubes (CNTs), single walled nanotubes (SWNTS) and multiwalled nanotubes (MWNTs). Electrical contacts 112 (e.g., Pd or another metal commonly used with nanotubes) are deposited on the nanotubes 110. In one embodiment, a layer of copper or any other industry standard metal (not shown) can be deposited on top of the electrical contacts 112 in order to prevent of the electrical contacts 112 from being exposed during later processing of the wafer 100.
[0014] A protective layer 114 is then deposited over the surface of the nanotube circuitry region 104 and the CMOS circuitry region 106. The protective layer 114 may comprise a nitride layer, such as SiN, or another protective material commonly used in
CMOS processes. In one or more embodiments, the protective layer 114 serves as the dielectric layer for nanotube devices requiring a gate, such as a transistor. In one or more embodiments, the protective layer 114 serves as a protecting layer to prevent the nanotubes 110 from being damaged during subsequent processes performed on the wafer 100 in conventional CMOS fabrication processes. For instance, the protective layer 114 provides protection against acid (HF) cleaning steps and other CMOS processes. In one or more embodiments, the protective layer 114 further keeps CMOS processing equipment used for subsequent CMOS process steps from being exposed to any new materials that are not normally encountered in CMOS processes. In this manner, the protective layer 114 includes materials that are normally encountered in subsequent CMOS processing steps and serves as a barrier to the materials in the nanotube circuitry region 104 underneath the protective layer 114.
[0015] In one or more embodiments, after the above process steps have been completed to form the components of the nanotube circuitry region 104, the CMOS circuitry region 106 will not contain any nanotubes 110 but will contain only industry standard materials typically used in CMOS processes (e.g., will only comprise materials such as Si/SiO2/SiN). Further, the nanotube circuitry region 104 will be covered by a protective layer 114 composing a material that is also typically used in CMOS processes. Thereby, a nanotube coated wafer 100 formed with electrical contacts 112 and a dielectric 114 in accordance with one or more embodiments described herein is then compatible with any follow-on industry standard CMOS processing steps. One example of an industry standard CMOS process is the CMOS process used by the UC Berkeley Microlab as described in the electronic document baseline_xsection_2005_UCBerkeley.pdf as stored at http://microlab/berkeley.edu/baseline, the contents of which are incorporated herein by reference. The UC Berkeley Microlab CMOS process describes using a certain starting material for the Si CMOS process (e.g,. as shown on slide 2 of the document), where the present disclosure teaches a process of generating a modified resultant material (together with buried nanotube devices in the nanotube circuitry region 104 that could be used for the starting material for the UC Berkeley Microlab CMOS process. However, it is understood that the present invention is not intended to be limited to the UC Berkeley Microlab CMOS process but could be used as the starting material with any subsequent industry CMOS process.
[0016] In one or more embodiments, the electrical contacts 112 can be deposited in such a way that a consistent map of devices is produced with known locations of electrical contact pads 112 so that these devices can be electrically connected to other circuits created in later CMOS processing steps or other processing steps. The contact pads 112 for other circuits are preferably made with a material that has maximum compatibility with the subsequent processes. Known electrical characteristics of these nanotube devices can then be added to and utilized in a design kit to further simplify the design of more functional circuits with a mixture of elements and interconnections.
[0017] In one or more embodiments, the protective layer 114 may completely cover the surface of the wafer 100 or alternatively only cover those portions to be protected (e.g., only the nanotube circuitry region 104). In or more embodiments, a gate electrode (not shown) can be created before depositing the protective layer 114. In one or more embodiments, the further processing of the wafer 100 that is performed may include removing nanotube 110 devices on areas of the wafer 100 where nanotube 110 devices are not needed.
[0018] In one or more embodiments, the process for preparing a nanotube coated wafer 100 as described herein provides electrically contacted nanotubes 110 on a wafer 100 for subsequent CMOS processing without introducing new materials to be encountered during the subsequent CMOS processing. Therefore, the prepared nanotube coated wafer 100 can be utilized with the industry standards for Si CMOS fabrication processes in order to achieve successful integration of CNTs with CMOS processes. In one or more embodiments, nanotube gates of poly-Si can be provided, similar to those used in CMOS circuitry, and CNTs may interconnect in substantially the same manner as CMOS circuitry, with the exception that the contact to Pd nanotube source/drain electrodes in the nanotube circuitry region 104 would require a hole in silicon nitride. [0019] Various aspects of the above-described process can be utilized for any circuit in which CNT-CMOS integration is required, e.g. RF mixed signal chips for wireless communications and wired communications circuitry.
[0020] While the system and method have been described in terms of what are presently considered to be specific embodiments, the disclosure need not be limited to the disclosed embodiments. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. The present disclosure includes any and all embodiments of the following claims.

Claims

1. A method for nanotube-CMOS integration, comprising: preparing a nanotube coated wafer for subsequent CMOS processing steps on the nanotube coated wafer.
2. The method of claim 1 , wherein the nanotube coated wafer is prepared with electrical contacts and a dielectric.
3. The method of claim 1 , wherein the nanotube coated wafer is prepared by: depositing a pad dielectric on a silicon wafer, depositing a catalyst on the pad dielectric, depositing nanotubes on the pad dielectric adjacent to the catalyst, depositing electrical contacts in contact with the nanotubes, and depositing a protective layer over the nanotubes and electrical contacts, where in the protective layer is a dielectric material.
4. The method of claim 3, further comprising depositing the nanotubes with a CVD process.
5. The method of claim 3, wherein the electrical contacts comprise Palladium (Pd).
6. The method of claim 3, further comprising depositing a metal layer over the electrical contacts before depositing the protective layer.
7. The method of claim 3, wherein the protective layer is SiN.
8. The method of claim 1 , wherein the prepared nanotube coated wafer is compatible with CMOS processing steps.
9. The method of claim 8, wherein the prepared nanotube coated wafer shields nanotube-specific materials from the subsequent CMOS processing steps.
10. An apparatus for use in CMOS processing comprising: a CMOS circuitry area on a substrate wafer suitable for CMOS circuitry-forming processes; and a nanotube circuitry area, comprising a substrate, a dielectric over the substrate, a catalyst over the dielectric, nanotubes over the dielectric adjacent to the catalyst, electrical contacts in contact with the nanotubes, and a protective layer over the nanotubes and electrical contacts, where in the protective layer is a dielectric material.
11. The apparatus of claim 10, wherein the protective layer shields the nanotubes and electrical contacts from exposure to CMOS circuitry-forming processes.
12. The apparatus of claim 10, wherein the electrical contacts comprise Palladium (Pd).
13. The apparatus of claim 10, further comprising a metal layer deposited between the electrical contacts and the protective layer.
14. The apparatus of claim 10, wherein the protective layer is SiN.
15. The apparatus of claim 10, wherein the protective layer is a material compatible with CMOS processing steps.
16. The apparatus of claim 10, further comprising a PoIy-Si gate electrode formed over the nanotubes.
17. A method for nanotube-CMOS integration, comprising: preparing a nanotube circuitry area on a wafer, forming a protective layer over the nanotube circuitry area using a CMOS processing material to protect the nanotube circuitry area from CMOS processing steps; performing CMOS processing steps on a CMOS circuitry area of the same wafer having the prepared nanotube circuitry area.
18. The method of claim 17, further comprising shielding CMOS processing equipment utilized in performing the CMOS processing steps from nanotube-specific materials used to form the nanotube circuitry area
PCT/US2008/052273 2007-01-30 2008-01-29 Fabrication process for nanotube-cmos integration WO2008094888A1 (en)

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US88730207P 2007-01-30 2007-01-30
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630772B1 (en) * 1998-09-21 2003-10-07 Agere Systems Inc. Device comprising carbon nanotube field emitter structure and process for forming device
US6969651B1 (en) * 2004-03-26 2005-11-29 Lsi Logic Corporation Layout design and process to form nanotube cell for nanotube memory applications
US7045421B2 (en) * 2003-04-22 2006-05-16 Nantero, Inc. Process for making bit selectable devices having elements made with nanotubes

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630772B1 (en) * 1998-09-21 2003-10-07 Agere Systems Inc. Device comprising carbon nanotube field emitter structure and process for forming device
US7045421B2 (en) * 2003-04-22 2006-05-16 Nantero, Inc. Process for making bit selectable devices having elements made with nanotubes
US6969651B1 (en) * 2004-03-26 2005-11-29 Lsi Logic Corporation Layout design and process to form nanotube cell for nanotube memory applications

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