WO2008091974A1 - Semiconductor device with a vertical mosfet including a superlattice and related methods - Google Patents

Semiconductor device with a vertical mosfet including a superlattice and related methods Download PDF

Info

Publication number
WO2008091974A1
WO2008091974A1 PCT/US2008/051856 US2008051856W WO2008091974A1 WO 2008091974 A1 WO2008091974 A1 WO 2008091974A1 US 2008051856 W US2008051856 W US 2008051856W WO 2008091974 A1 WO2008091974 A1 WO 2008091974A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
superlattice
semiconductor device
gate
forming
Prior art date
Application number
PCT/US2008/051856
Other languages
French (fr)
Inventor
Kalipatnam Vivek Rao
Original Assignee
Mears Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mears Technologies, Inc. filed Critical Mears Technologies, Inc.
Publication of WO2008091974A1 publication Critical patent/WO2008091974A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of semiconductors, and, more particularly, to semiconductor devices comprising superlattices and associated methods.
  • U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n- channel MOSFET is asserted to have a higher mobility.
  • U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxiaily grown. The direction of main current flow is perpendicular to the layers of the superlattice.
  • U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
  • U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionaliy present in the silicon lattice at a percentage that places the channel layer under tensile stress.
  • U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxiaily grown semiconductor layer sandwiched between the barriers.
  • Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
  • An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen.
  • the Si/O superlattice is disclosed as useful in a silicon quantum and light- emitting devices.
  • a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
  • the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
  • the insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.
  • APBG Aperiodic Photonic Band-Gap
  • material parameters for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics.
  • Other parameters such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
  • a semiconductor device which may include a substrate and at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on the substrate and including at least one superlattice.
  • the superlattice may include a plurality of laterally stacked groups of layers transverse to the substrate.
  • the vertical MOSFET(s) may further include a gate laterally adjacent the at least one superlattice, and regions vertically above and below the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction.
  • each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
  • the vertical MOSFET(s) may therefore have improved mobility as well as other structural and functional advantages.
  • the at least one superlattice may include a pair of spaced- apart superlattices, and the at least one vertical MOSFET may further include a semiconductor fin between the spaced-apart superlattices.
  • the gate may at least partially surround the at least one superlattice, and the gate may include a gate electrode layer and a gate dielectric layer between the gate electrode layer and the at least one superlattice.
  • the substrate may be a semiconductor-on-insulator (SOI) substrate.
  • the regions may include at least one drain region, above the at least one superlattice; and at least one source region, below the superlattice. More particularly, the at least one source region may include a plurality of laterally spaced- apart source regions.
  • the semiconductor device may further include a dielectric layer overlying the at least one vertical MOSFET, a respective contact for each of the regions on the dielectric layer, and a respective via extending between each of the contacts and a corresponding region through the dielectric layer.
  • the at least one vertical MOSFET may include a plurality thereof.
  • the plurality of MOSFETS may define an inverter, for example.
  • at least one n-channel vertical MOSFET and at least one p-channel vertical MOSFET may be included.
  • a respective shallow trench isolation (STI) region may be included between adjacent vertical MOSFETs.
  • the base semiconductor may include silicon, and the at least one non-semiconductor monolayer may include oxygen, in some embodiments, the at least one non-semiconductor monolayer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
  • a related method for making a semiconductor device may include forming at least one vertical MOSFET on a substrate by at least forming at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate, forming a gate laterally adjacent the at ieast one superlattice, and forming regions vertically above and crizow the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction.
  • each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor layer.
  • FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with the present invention.
  • FiG. 2 is a perspective schematic atomic diagram of a portion of the superiattice shown in FlG. 1.
  • FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superiattice in accordance with the invention.
  • FIG. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superiattice as shown in FIGS. 1-2.
  • FiG. 4B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.
  • FIG. 4C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 3.
  • FIG. 5 is a schematic cross-sectional diagram of a vertical MOSFET including a vertical superlattice channel in accordance with the present invention.
  • FIG. 6 is a schematic cross-sectionai diagram of an alternative embodiment of a vertical MOSFET including a vertical superlattice channel in accordance with the present invention.
  • FIG. 7 is a schematic cross-sectional diagram of a vertical inverter including vertical superlattice channels in the MOSFETs thereof in accordance with the present invention.
  • the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level. Further, the invention relates to the identification, creation, and use of improved materials for use in semiconductor devices. [0029] Applicants theorize, without wishing to be bound thereto, that certain superiattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", M "1 and M ⁇ ! for electrons and holes respectively, defined as:
  • f is the Fermi-Dirac distribution
  • EF is the Fermi energy
  • T is the temperature
  • E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
  • the indices i and j refer to Cartesian coordinates x, y and z
  • the integrals are taken over the Brillouin zone (B.Z.)
  • the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
  • Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
  • the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport.
  • the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
  • the conductivity effective mass for electrons/hoies as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
  • the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or moiecular level and may be formed using known techniques of atomic or molecular iayer deposition.
  • the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross- sectiona! view of FIG. 1.
  • Each group of layers 45a-45n of the superiattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon.
  • the energy band-modifying layers 50 are indicated by stippling in FIG. 1 for clarity of illustration.
  • the energy band-modifying layer 50 illustratively includes one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • constrained within a crystal lattice of adjacent base semiconductor portions it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, with the chemical bonds traversing the intervening non-semiconductor monolayer(s) therebetween, as seen in FIG. 2.
  • this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a ⁇ 46n through atomic layer deposition techniques so that not ali (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below.
  • the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non- semiconductor monolayer.
  • non-semiconductor monolayer in other embodiments, more than one such non-semiconductor monolayer may be possible.
  • reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
  • energy band- modifying layers 50 and adjacent base semiconductor portions 4 ⁇ a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction.
  • the band- modifying layers 50 may also cause the superlattice 25 to have a common energy band structure.
  • the band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
  • this superlattice structure may also advantageously act as a barrier to dopant and/or material bleed between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces bleeding of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
  • semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present, in some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.
  • the superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
  • the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
  • the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
  • Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IM-V semiconductors, and Group M-Vl semiconductors.
  • Group IV semiconductors aiso includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
  • the base semiconductor may comprise at least one of silicon and germanium, for example.
  • Each energy band-modifying layer 50 may comprise a non-semiconductor sefected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
  • the non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
  • the non- semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example
  • the term monolayer is meant to include a single atomic layer and also a single molecular layer.
  • the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage).
  • a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.
  • this one half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0044] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as wili be appreciated by those skilled in the art.
  • the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
  • the 4/1 repeating structure shown in FIGS. 1 and 2, for Si/O has been modeled to indicate an enhanced mobility for eiectrons and holes in the X direction.
  • the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
  • the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.
  • other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
  • the lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
  • the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will aiso be appreciated by those skilled in the art.
  • FIG. 3 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described.
  • a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'.
  • the energy band-modifying layers 50' may each include a single monolayer.
  • the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
  • all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
  • FIGS. 4A-4C band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.
  • FIG. 4A shows the calculated band structure from the gamma point (G) for both bulk silicon ⁇ represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines).
  • the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit ceil of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
  • the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
  • the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
  • the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
  • the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
  • FIG. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superiattice 25 (dotted lines).
  • FIG. 4C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 3 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
  • MOSFET is meant to include FETs with both metal and non-metal (e.g., semiconductor) gates, as will be appreciated by those skilled in the art.
  • the various layers of the superiattice 25 are stacked in a direction transverse to, or as in the illustrated embodiment, orthogonal to the substrate 21, as opposed to parallel to the substrate. Further details on vertical superiattice structures and methods for forming these structures are provided in co- pending U.S. Patent Application No. 11/426,976 and U.S. Patent No. 7,202,494, both of which are assigned to the present Assignee and are hereby incorporated herein in their entireties by reference.
  • silicon fins 75 may be formed or etched on the substrate 21. Thereafter, epitaxial deposition of semiconductor monolayers and non-semiconductor monolayers onto the fins 75 is performed to form the vertical superlattice 25.
  • the vertical superlattice may be cylindrical and surround ⁇ or partially surround) the fin 75, and in other embodiments a pair of spaced-apart superlattices may be formed on opposing sides of the fin, for example.
  • the substrate 21 is a silicon substrate with an epitaxial silicon layer 24 thereon, although other suitable semiconductor materials (e.g., germanium, etc.) maybe used in other embodiments. Moreover, in some embodiments the epitaxial layer 24 may be omitted, as will be appreciated by those skilled in the art.
  • a source region 22 is formed in the epitaxial layer 24 around the vertical superlattice 25, and a drain region 23 is formed above (i.e., on top of) the superlattice.
  • a source extension region(s) 26 is also formed in the epitaxial layer 24 beneath the vertical superlattice 25.
  • a cylindrical gate 35 illustratively surrounds the vertical superlattice 25 and includes an insulating layer 37 surrounding the superlattice, and a gate electrode layer 36 surrounding the gate insulating layer.
  • the insulating layer 37 may not be needed because of the above-described structure of the superlattice. It should be noted that the gate 35 need not completely surround the vertical channel 25 in all embodiments.
  • an alternative embodiment of a vertical MOSFET 20' illustratively includes source and drain contacts 30', 31' that are connected to the source 22' and drain 23' respectively by vias 60', 61' through a dielectric layer 63'.
  • shallow trench isolation (ST!) regions 62' including oxide/TEOS are also illustratively included between adjacent transistor ceils, ft should be noted that while NMOS transistors are illustrated in the above-described examples, PMOS and CMOS configurations are also possible, as will be appreciated by those skilled in the art.
  • the inverter 70" illustratively includes an NMOS transistor 20n"vertically stacked on a PMOS transistor 2Op", each of which includes a respective vertical superlattice 25n"and 25p".
  • a common gate electrode 36c" (Vin) is coupled to both vertical superfattices 25p" and 25n" on a right side of the illustrated transistor stack, while respective gate electrodes 36n” and 36 ⁇ " (Vin) for the NMOS and PMOS transistors 2On", 2Op" are coupled to the respective vertical superlattices on the left side thereof in the iliustrated embodiment.
  • Vss line 71" is coupled to the NMOS transistor 2On
  • Vout line 72" is coupled to the PMOS transistor 2Op
  • a Vdd line is coupled to the substrate 21", as shown.
  • other configurations beside the exemplary inverter 70" shown in FIG. 7 may be used in different embodiments (e.g., the NMOS transistor 2On” may be vertically stacked on the PMOS transistor 2Op", etc.).

Abstract

A semiconductor device includes at least one vertical MOSFET (20) on a substrate. The vertical MOSFET includes at least one superlattice (25) including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET (s) further includes a gate (35, 36, 37) laterally adjacent the superlattice, and regions (23, 22, 26) vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice includes stacked base semiconductor monolayers defining a base semiconductor portion and at least one non- semi conductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non semiconductor monolayer. A CMOS (70') including a pair of such vertical MOSFETs is moreover disclosed.

Description

SEMICONDUCTOR DEVICE WITH A VERTICAL WIOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS
Field of the Invention
[0001] The present invention relates to the field of semiconductors, and, more particularly, to semiconductor devices comprising superlattices and associated methods.
Background of the Invention
[0002] Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed siiicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. Patent Application No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based upon similar strained silicon technology.
[0003] U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n- channel MOSFET is asserted to have a higher mobility.
[0004] U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxiaily grown. The direction of main current flow is perpendicular to the layers of the superlattice. [0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionaliy present in the silicon lattice at a percentage that places the channel layer under tensile stress.
[0006] U.S. Patent No. 5,216,262 to Tsu discloses a quantum weil structure comprising two barrier regions and a thin epitaxiaily grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
[0007] An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light- emitting devices. In particular, a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 πm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to Luo et al. entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu. [0008] Published International Application WO 02/103,767 A1 to Wang, Tsu and Lofgren, discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer. [0009] Published Great Britain Patent Application 2,347,520 to Mears et al. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
[0010] Despite considerable efforts at materials engineering to increase the mobility of charge carriers in semiconductor devices, there is still a need for greater improvements. Greater mobiiity may increase device speed and/or reduce device power consumption. With greater mobility, device performance can also be maintained despite the continued shift to smaller devices and new device configurations.
Summary of the Invention
[0011] In view of the foregoing background, it is therefore an object of the present invention to provide a system and related methods for making vertical MOSFET devices having enhanced characteristics such as mobility lift, for example. [0012] This and other objects, features, and advantages are provided by a semiconductor device which may include a substrate and at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on the substrate and including at least one superlattice. The superlattice may include a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the at least one superlattice, and regions vertically above and below the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction. More particularly, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. Because of the enhanced band-engineered properties of the superlattice, the vertical MOSFET(s) may therefore have improved mobility as weil as other structural and functional advantages. [0013] More particularly, the at least one superlattice may include a pair of spaced- apart superlattices, and the at least one vertical MOSFET may further include a semiconductor fin between the spaced-apart superlattices. Additionally, the gate may at least partially surround the at least one superlattice, and the gate may include a gate electrode layer and a gate dielectric layer between the gate electrode layer and the at least one superlattice.
[0014] By way of example, the substrate may be a semiconductor-on-insulator (SOI) substrate. In addition, the regions may include at least one drain region, above the at least one superlattice; and at least one source region, below the superlattice. More particularly, the at least one source region may include a plurality of laterally spaced- apart source regions.
[0015] The semiconductor device may further include a dielectric layer overlying the at least one vertical MOSFET, a respective contact for each of the regions on the dielectric layer, and a respective via extending between each of the contacts and a corresponding region through the dielectric layer. Additionally, the at least one vertical MOSFET may include a plurality thereof. The plurality of MOSFETS may define an inverter, for example. Moreover, at least one n-channel vertical MOSFET and at least one p-channel vertical MOSFET may be included. Also, a respective shallow trench isolation (STI) region may be included between adjacent vertical MOSFETs. [0016] By way of example, the base semiconductor may include silicon, and the at least one non-semiconductor monolayer may include oxygen, in some embodiments, the at least one non-semiconductor monolayer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen. [0017] A related method for making a semiconductor device may include forming at least one vertical MOSFET on a substrate by at least forming at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate, forming a gate laterally adjacent the at ieast one superlattice, and forming regions vertically above and beiow the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction. More particularly, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor layer.
Brief Description of the Drawings
[0018] FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with the present invention. [0019] FiG. 2 is a perspective schematic atomic diagram of a portion of the superiattice shown in FlG. 1.
[0020] FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superiattice in accordance with the invention. [0021] FIG. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superiattice as shown in FIGS. 1-2.
[0022] FiG. 4B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2. [0023] FIG. 4C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 3.
[0024] FIG. 5 is a schematic cross-sectional diagram of a vertical MOSFET including a vertical superlattice channel in accordance with the present invention. [0025] FIG. 6 is a schematic cross-sectionai diagram of an alternative embodiment of a vertical MOSFET including a vertical superlattice channel in accordance with the present invention.
[0026] FIG. 7 is a schematic cross-sectional diagram of a vertical inverter including vertical superlattice channels in the MOSFETs thereof in accordance with the present invention.
Detailed Description of the Preferred Embodiments
[0027] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.
[0028] The present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level. Further, the invention relates to the identification, creation, and use of improved materials for use in semiconductor devices. [0029] Applicants theorize, without wishing to be bound thereto, that certain superiattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", M"1 and M^! for electrons and holes respectively, defined as:
Figure imgf000007_0001
for electrons and:
Figure imgf000008_0001
for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
[0030] Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicants theorize without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/hoies as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials. [0031] Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, the Applicants have identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below. [0032] Referring now to FIGS. 1 and 2, the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or moiecular level and may be formed using known techniques of atomic or molecular iayer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross- sectiona! view of FIG. 1.
[0033] Each group of layers 45a-45n of the superiattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. The energy band-modifying layers 50 are indicated by stippling in FIG. 1 for clarity of illustration.
[0034] The energy band-modifying layer 50 illustratively includes one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within a crystal lattice of adjacent base semiconductor portions" it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, with the chemical bonds traversing the intervening non-semiconductor monolayer(s) therebetween, as seen in FIG. 2. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a~46n through atomic layer deposition techniques so that not ali (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers 46 of semiconductor material are deposited on or over a- non- semiconductor monolayer 50, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non- semiconductor monolayer.
[0035] in other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
[0036] Applicants theorize without wishing to be bound thereto that energy band- modifying layers 50 and adjacent base semiconductor portions 4βa-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band- modifying layers 50 may also cause the superlattice 25 to have a common energy band structure. The band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice. [0037] Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material bleed between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces bleeding of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
[0038] It is also theorized that semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present, in some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.
[0039] The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers. [0040] Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IM-V semiconductors, and Group M-Vl semiconductors. Of course, the term Group IV semiconductors aiso includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.
[0041] Each energy band-modifying layer 50 may comprise a non-semiconductor sefected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non- semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example
[0042] It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of FIG. 2, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.
[0043] In other embodiments and/or with different materials this one half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0044] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as wili be appreciated by those skilled in the art.
[0045] it is theorized without Applicants wishing to be bound thereto that for a superlattice, such as the Si/O superiattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown in FIGS. 1 and 2, for Si/O has been modeled to indicate an enhanced mobility for eiectrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46. Similarly, the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44. [0046] While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
[0047] The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will aiso be appreciated by those skilled in the art.
[0048] indeed, referring now additionally to FIG. 3, another embodiment of a superlattice 25' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'. The energy band-modifying layers 50' may each include a single monolayer. For such a superlattice 25' including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of FIG. 3 not specifically mentioned are similar to those discussed above with reference to FIG. 1 and need no further discussion herein. [0049] In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
[0050] in FIGS. 4A-4C, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction." However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light. [0051] FIG. 4A shows the calculated band structure from the gamma point (G) for both bulk silicon {represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines). The directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit ceil of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
[0052] It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer. [0053] FIG. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superiattice 25 (dotted lines). This figure illustrates the enhanced curvature of the vaience band in the (100) direction. [0054] FIG. 4C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 3 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
[0055] Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the 5/1/3/1 superiattice 25' should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior. [0056] Using the above-described measures, one can select materials having improved band structures for specific purposes. One such example would be a vertical MOSFET 20 including a vertical superiattice 25 providing a vertical channel of the MOSFET is now first described with reference to FIG. 5. As used herein, "MOSFET" is meant to include FETs with both metal and non-metal (e.g., semiconductor) gates, as will be appreciated by those skilled in the art. The various layers of the superiattice 25 are stacked in a direction transverse to, or as in the illustrated embodiment, orthogonal to the substrate 21, as opposed to parallel to the substrate. Further details on vertical superiattice structures and methods for forming these structures are provided in co- pending U.S. Patent Application No. 11/426,976 and U.S. Patent No. 7,202,494, both of which are assigned to the present Assignee and are hereby incorporated herein in their entireties by reference.
[0057] By way of example, following shallow trench isolation (ST!) processing/formation, silicon fins 75 may be formed or etched on the substrate 21. Thereafter, epitaxial deposition of semiconductor monolayers and non-semiconductor monolayers onto the fins 75 is performed to form the vertical superlattice 25. However, other suitable approaches may also be used, as will be appreciated by those skilled in the art. In some embodiments, the vertical superlattice may be cylindrical and surround {or partially surround) the fin 75, and in other embodiments a pair of spaced-apart superlattices may be formed on opposing sides of the fin, for example. [0058] In one embodiment, the substrate 21 is a silicon substrate with an epitaxial silicon layer 24 thereon, although other suitable semiconductor materials (e.g., germanium, etc.) maybe used in other embodiments. Moreover, in some embodiments the epitaxial layer 24 may be omitted, as will be appreciated by those skilled in the art. A source region 22 is formed in the epitaxial layer 24 around the vertical superlattice 25, and a drain region 23 is formed above (i.e., on top of) the superlattice. A source extension region(s) 26 is also formed in the epitaxial layer 24 beneath the vertical superlattice 25. A cylindrical gate 35 illustratively surrounds the vertical superlattice 25 and includes an insulating layer 37 surrounding the superlattice, and a gate electrode layer 36 surrounding the gate insulating layer. In other embodiments, the insulating layer 37 may not be needed because of the above-described structure of the superlattice. It should be noted that the gate 35 need not completely surround the vertical channel 25 in all embodiments.
[0059] Turning now additionally to FlG. 6, an alternative embodiment of a vertical MOSFET 20' illustratively includes source and drain contacts 30', 31' that are connected to the source 22' and drain 23' respectively by vias 60', 61' through a dielectric layer 63'. Moreover, shallow trench isolation (ST!) regions 62' including oxide/TEOS are also illustratively included between adjacent transistor ceils, ft should be noted that while NMOS transistors are illustrated in the above-described examples, PMOS and CMOS configurations are also possible, as will be appreciated by those skilled in the art.
[0060] An exemplary inverter configuration 70" is now described with reference to FIG. 7. The inverter 70" illustratively includes an NMOS transistor 20n"vertically stacked on a PMOS transistor 2Op", each of which includes a respective vertical superlattice 25n"and 25p". A common gate electrode 36c" (Vin) is coupled to both vertical superfattices 25p" and 25n" on a right side of the illustrated transistor stack, while respective gate electrodes 36n" and 36ρ" (Vin) for the NMOS and PMOS transistors 2On", 2Op" are coupled to the respective vertical superlattices on the left side thereof in the iliustrated embodiment. Moreover, a Vss line 71" is coupled to the NMOS transistor 2On", a Vout line 72" is coupled to the PMOS transistor 2Op", and a Vdd line is coupled to the substrate 21", as shown. Here again, it should be noted that other configurations beside the exemplary inverter 70" shown in FIG. 7 may be used in different embodiments (e.g., the NMOS transistor 2On" may be vertically stacked on the PMOS transistor 2Op", etc.).
[0061 J Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

THAT WHICH IS CLAIMED IS:
1. A semiconductor device comprising: a substrate; and at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on said substrate and comprising at least one superlattice comprising a plurality of laterally stacked groups of layers transverse to said substrate, a gate laterally adjacent said at least one superlattice, and regions vertically above and below said at least one superlattice and cooperating with said gate for causing transport of charge carriers through said at least one superlattice in the vertical direction, each group of layers of said superiattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at feast some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
2. The semiconductor device of Claim 1 wherein said at least one superlattice comprises a pair of spaced-apart superlattices; and further comprising a semiconductor fin between said spaced-apart superlattices.
3. The semiconductor device of Claim 1 wherein said gate at least partially surrounds said at least one superlattice.
4. The semiconductor device of Claim 1 wherein said gate comprises a gate electrode layer and a gate dielectric layer between said gate electrode layer and said at least one superiattice.
5. The semiconductor device of Claim 1 wherein said substrate comprises a semiconductor-on-insulator (SOl) substrate.
6. The semiconductor device of Claim 1 wherein said regions comprise at least one drain region and at least one source region.
7. The semiconductor device of Claim 7 wherein said at (east one source region comprises a plurality of laterally spaced-apart source regions.
8. The semiconductor device of Claim 1 wherein said base semiconductor comprises silicon.
9. The semiconductor device of Claim 1 wherein said at least one non- semiconductor monolayer comprises oxygen.
10. The semiconductor device of Claim 1 wherein said at least one non- semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
11. The semiconductor device of Claim 1 further comprising: a dielectric layer overlying said at least one vertical MOSFET; a respective contact for each of said regions on said dielectric layer; and a respective via extending between each of said contacts and a corresponding region through said dielectric layer.
12. The semiconductor device of Claim 1 wherein said at least one vertical MOSFET comprises a plurality thereof defining an inverter.
13. The semiconductor device of Claim 1 wherein said at least one vertical MOSFET comprises at least one n-channel vertical MOSFET and at least one p-channel vertical MOSFET.
14. The semiconductor device of Claim 1 wherein said at least one vertical MOSFET comprises a plurality thereof; and further comprising a respective shallow trench isolation (STI) region between adjacent vertical MOSFETs.
15. A semiconductor device comprising: a substrate; and at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on said substrate and comprising a pair of spaced-apart superlattices each comprising a plurality of laterally stacked groups of layers transverse to said substrate, and a semiconductor fin between said superlattices, a gate at least partially surrounding said at least one superlattice, and regions vertically above and below said at least one superlattice and cooperating with said gate for causing transport of charge carriers through said at least one superlattice in the vertical direction, each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
16. The semiconductor device of Claim 15 wherein said regions comprise at least one drain region and at least one source region.
17. The semiconductor device of Claim 15 wherein said base semiconductor comprises silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.
18. The semiconductor device of Claim 15 further comprising: a dielectric layer overlying said at least one vertical MOSFET; a respective contact for each of said regions on said dielectric layer; and a respective via extending between each of said contacts and a corresponding region through said dielectric layer.
19. The semiconductor device of Claim 15 wherein said at least one vertical MOSFET comprises a plurality thereof defining an inverter.
20. A method for making a semiconductor device comprising: forming at least one vertical Metal Oxide Semiconductor Field Effect
Transistor (MOSFET) on a substrate by at least forming at least one superiattice comprising a plurality of laterally stacked groups of layers transverse to the substrate; forming a gate laterally adjacent the at least one superlattice, and forming regions vertically above and below the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
21. The method of Claim 20 wherein forming the at least one superlattice further comprises forming a pair of spaced-apart superiattices with a semiconductor fin therebetween.
22. The method of Claim 20 wherein forming the gate further comprises forming the gate to at least partially surround the at least one superlattice.
23. The method of Claim 20 wherein forming the regions comprises forming at least one drain region and at least one source region.
24. The method of Claim 20 wherein the base semiconductor comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.
25. The method of Claim 20 further comprising: forming a dielectric layer overlying the at least one vertical MOSFET; forming a respective contact for each of the regions on the dielectric layer; and forming a respective via extending between each of the contacts and a corresponding region through the dielectric layer.
26. The method of Claim 20 wherein forming the at least one vertical MOSFET comprises forming a plurality thereof defining an inverter.
PCT/US2008/051856 2007-01-24 2008-01-24 Semiconductor device with a vertical mosfet including a superlattice and related methods WO2008091974A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US88637507P 2007-01-24 2007-01-24
US60/886,375 2007-01-24
US12/018,260 US7781827B2 (en) 2007-01-24 2008-01-23 Semiconductor device with a vertical MOSFET including a superlattice and related methods
US12/018,260 2008-01-23

Publications (1)

Publication Number Publication Date
WO2008091974A1 true WO2008091974A1 (en) 2008-07-31

Family

ID=39410485

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/051856 WO2008091974A1 (en) 2007-01-24 2008-01-24 Semiconductor device with a vertical mosfet including a superlattice and related methods

Country Status (3)

Country Link
US (1) US7781827B2 (en)
TW (1) TW200837950A (en)
WO (1) WO2008091974A1 (en)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101226685B1 (en) * 2007-11-08 2013-01-25 삼성전자주식회사 Vertical type semiconductor device and Method of manufacturing the same
KR101394157B1 (en) 2008-04-08 2014-05-14 삼성전자주식회사 Vertical pillar transistor, DRAM device including the same, method for forming the vertical pillar transistor and method for forming a semiconductor layer
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
CN103426758B (en) * 2012-05-15 2016-02-24 中芯国际集成电路制造(上海)有限公司 Deeply exhaust slot field-effect transistor and preparation method thereof
KR20150020848A (en) * 2013-08-19 2015-02-27 에스케이하이닉스 주식회사 PMOS Transistor Improved Current-drivability With Vertical Channel, Variable Resistive Memory Device Including the same And Method of Manufacturing PMOS Transistor
KR101855023B1 (en) 2013-11-22 2018-05-04 아토메라 인코포레이티드 Vertical semiconductor devices including superlattice punch through stop layer and related methods
CN105900241B (en) 2013-11-22 2020-07-24 阿托梅拉公司 Semiconductor device including superlattice depletion layer stack and related methods
US9153647B1 (en) 2014-03-17 2015-10-06 International Business Machines Corporation Integrated circuit having heterostructure FinFET with tunable device parameters and method to fabricate same
WO2015191561A1 (en) 2014-06-09 2015-12-17 Mears Technologies, Inc. Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9653457B2 (en) * 2015-01-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked device and associated layout structure
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
JP2016225614A (en) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 Semiconductor device
WO2016196600A1 (en) 2015-06-02 2016-12-08 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
US10002962B2 (en) 2016-04-27 2018-06-19 International Business Machines Corporation Vertical FET structure
WO2017197108A1 (en) 2016-05-11 2017-11-16 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10014391B2 (en) 2016-06-28 2018-07-03 International Business Machines Corporation Vertical transport field effect transistor with precise gate length definition
US10249745B2 (en) 2016-08-08 2019-04-02 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
US10107854B2 (en) 2016-08-17 2018-10-23 Atomera Incorporated Semiconductor device including threshold voltage measurement circuitry
US11088033B2 (en) 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
US11081484B2 (en) 2016-09-30 2021-08-03 Institute of Microelectronics, Chinese Academy of Sciences IC unit and method of manufacturing the same, and electronic device including the same
CN106298778A (en) 2016-09-30 2017-01-04 中国科学院微电子研究所 Semiconductor device and manufacture method thereof and include the electronic equipment of this device
US9748381B1 (en) 2016-10-11 2017-08-29 International Business Machines Corporation Pillar formation for heat dissipation and isolation in vertical field effect transistors
US10014409B1 (en) * 2016-12-29 2018-07-03 Globalfoundries Inc. Method and structure to provide integrated long channel vertical FinFET device
US11081398B2 (en) 2016-12-29 2021-08-03 Globaleoundries U.S. Inc. Method and structure to provide integrated long channel vertical FinFet device
US10410880B2 (en) 2017-05-16 2019-09-10 Atomera Incorporated Semiconductor device including a superlattice as a gettering layer
US10636879B2 (en) 2017-06-13 2020-04-28 Atomera Incorporated Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
EP3669401B1 (en) 2017-08-18 2023-08-02 Atomera Incorporated Manufacturing method for a semiconductor device including the removal of non-monocrystalline stringer adjacent a superlattice-sti interface
US10367028B2 (en) 2017-12-15 2019-07-30 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10355151B2 (en) 2017-12-15 2019-07-16 Atomera Incorporated CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10608027B2 (en) 2017-12-15 2020-03-31 Atomera Incorporated Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10608043B2 (en) 2017-12-15 2020-03-31 Atomera Incorporation Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10361243B2 (en) 2017-12-15 2019-07-23 Atomera Incorporated Method for making CMOS image sensor including superlattice to enhance infrared light absorption
US10615209B2 (en) 2017-12-15 2020-04-07 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10529757B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated CMOS image sensor including pixels with read circuitry having a superlattice
US10276625B1 (en) 2017-12-15 2019-04-30 Atomera Incorporated CMOS image sensor including superlattice to enhance infrared light absorption
US10461118B2 (en) 2017-12-15 2019-10-29 Atomera Incorporated Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10304881B1 (en) 2017-12-15 2019-05-28 Atomera Incorporated CMOS image sensor with buried superlattice layer to reduce crosstalk
US10396223B2 (en) 2017-12-15 2019-08-27 Atomera Incorporated Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
US10529768B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated Method for making CMOS image sensor including pixels with read circuitry having a superlattice
US10777451B2 (en) 2018-03-08 2020-09-15 Atomera Incorporated Semiconductor device including enhanced contact structures having a superlattice
US10727049B2 (en) 2018-03-09 2020-07-28 Atomera Incorporated Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
US10468245B2 (en) 2018-03-09 2019-11-05 Atomera Incorporated Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
WO2019199926A1 (en) 2018-04-12 2019-10-17 Atomera Incorporated Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
EP3776073A1 (en) 2018-04-12 2021-02-17 Atomera Incorporated Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
US10593798B2 (en) 2018-08-05 2020-03-17 International Business Machines Corporation Vertical transistor with one atomic layer gate length
US10586864B2 (en) * 2018-08-05 2020-03-10 International Business Machines Corporation Vertical transistor with one-dimensional edge contacts
US10811498B2 (en) 2018-08-30 2020-10-20 Atomera Incorporated Method for making superlattice structures with reduced defect densities
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities
US10580866B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
US10593761B1 (en) 2018-11-16 2020-03-17 Atomera Incorporated Method for making a semiconductor device having reduced contact resistance
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10840337B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making a FINFET having reduced contact resistance
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10580867B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
US10840336B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US10784341B2 (en) 2019-01-21 2020-09-22 Northrop Grumnian Systems Corporation Castellated superjunction transistors
US10804387B1 (en) 2019-03-21 2020-10-13 Northrop Grumman Systems Corporation Vertical superlattice transistors
US10916642B2 (en) 2019-04-18 2021-02-09 Globalfoundries U.S. Inc. Heterojunction bipolar transistor with emitter base junction oxide interface
US11329154B2 (en) 2019-04-23 2022-05-10 Atomera Incorporated Semiconductor device including a superlattice and an asymmetric channel and related methods
US10937868B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
US11183565B2 (en) 2019-07-17 2021-11-23 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
US10937888B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
US10825902B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Varactor with hyper-abrupt junction region including spaced-apart superlattices
US10825901B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including a superlattice
US10868120B1 (en) 2019-07-17 2020-12-15 Atomera Incorporated Method for making a varactor with hyper-abrupt junction region including a superlattice
US10840388B1 (en) 2019-07-17 2020-11-17 Atomera Incorporated Varactor with hyper-abrupt junction region including a superlattice
US10879357B1 (en) 2019-07-17 2020-12-29 Atomera Incorporated Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
US11264499B2 (en) 2019-09-16 2022-03-01 Globalfoundries U.S. Inc. Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
US11158722B2 (en) 2019-12-30 2021-10-26 Globalfoundries U.S. Inc. Transistors with lattice structure
US11437486B2 (en) 2020-01-14 2022-09-06 Atomera Incorporated Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
US11417764B2 (en) * 2020-01-29 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interface profile control in epitaxial structures for semiconductor devices
US11302823B2 (en) 2020-02-26 2022-04-12 Atomera Incorporated Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
US11177351B2 (en) 2020-02-26 2021-11-16 Atomera Incorporated Semiconductor device including a superlattice with different non-semiconductor material monolayers
US11075078B1 (en) 2020-03-06 2021-07-27 Atomera Incorporated Method for making a semiconductor device including a superlattice within a recessed etch
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
US11569368B2 (en) 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11837634B2 (en) 2020-07-02 2023-12-05 Atomera Incorporated Semiconductor device including superlattice with oxygen and carbon monolayers
CN112397581B (en) * 2020-11-18 2022-06-10 光华临港工程应用技术研发(上海)有限公司 Tunnel field effect transistor and manufacturing method thereof
EP4295409A1 (en) 2021-03-03 2023-12-27 Atomera Incorporated Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice and associated methods
US11810784B2 (en) 2021-04-21 2023-11-07 Atomera Incorporated Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11923418B2 (en) 2021-04-21 2024-03-05 Atomera Incorporated Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
US11862717B2 (en) 2021-08-24 2024-01-02 Globalfoundries U.S. Inc. Lateral bipolar transistor structure with superlattice layer and method to form same
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311050A (en) * 1990-11-30 1994-05-10 Kabushiki Kaisha Toshiba Semiconductor vertical MOSFET inverter circuit
US20050272239A1 (en) * 2003-06-26 2005-12-08 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485128A (en) 1981-11-20 1984-11-27 Chronar Corporation Bandgap control in amorphous semiconductors
JPH0656887B2 (en) 1982-02-03 1994-07-27 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US4594603A (en) 1982-04-22 1986-06-10 Board Of Trustees Of The University Of Illinois Semiconductor device with disordered active region
JPS6127681A (en) 1984-07-17 1986-02-07 Res Dev Corp Of Japan Field effect transistor having channel part of superlattice construction
US4882609A (en) 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
JPS61210679A (en) 1985-03-15 1986-09-18 Sony Corp Semiconductor device
JPS61220339A (en) 1985-03-26 1986-09-30 Nippon Telegr & Teleph Corp <Ntt> Control of characteristics of semiconductor material
JPS62219665A (en) 1986-03-20 1987-09-26 Fujitsu Ltd Superlattice thin-film transistor
US4908678A (en) 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5081513A (en) 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5216262A (en) 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices
JPH0643482A (en) 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd Space optical modulating element and its production
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US5606177A (en) 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5576221A (en) 1993-12-20 1996-11-19 Nec Corporation Manufacturing method of semiconductor device
US5466949A (en) 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
US5627386A (en) 1994-08-11 1997-05-06 The United States Of America As Represented By The Secretary Of The Army Silicon nanostructure light-emitting diode
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5577061A (en) 1994-12-16 1996-11-19 Hughes Aircraft Company Superlattice cladding layers for mid-infrared lasers
FR2734097B1 (en) 1995-05-12 1997-06-06 Thomson Csf SEMICONDUCTOR LASER
US6326650B1 (en) 1995-08-03 2001-12-04 Jeremy Allam Method of forming a semiconductor structure
US6584245B1 (en) 1996-05-06 2003-06-24 Teracomm Research, Inc High speed data link including a superconductive plate assembly for use in a data transmission scheme and method
US6344271B1 (en) 1998-11-06 2002-02-05 Nanoenergy Corporation Materials and products using nanostructured non-stoichiometric substances
EP0843361A1 (en) 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
WO1998026316A1 (en) 1996-12-13 1998-06-18 Massachusetts Institute Of Technology Tunable microcavity using nonlinear materials in a photonic crystal
US5994164A (en) 1997-03-18 1999-11-30 The Penn State Research Foundation Nanostructure tailoring of material properties using controlled crystallization
US6255150B1 (en) 1997-10-23 2001-07-03 Texas Instruments Incorporated Use of crystalline SiOx barriers for Si-based resonant tunneling diodes
US6376337B1 (en) 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3443343B2 (en) 1997-12-03 2003-09-02 松下電器産業株式会社 Semiconductor device
JP3547037B2 (en) 1997-12-04 2004-07-28 株式会社リコー Semiconductor laminated structure and semiconductor light emitting device
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
JP3854731B2 (en) 1998-03-30 2006-12-06 シャープ株式会社 Microstructure manufacturing method
US6888175B1 (en) 1998-05-29 2005-05-03 Massachusetts Institute Of Technology Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers
RU2142665C1 (en) 1998-08-10 1999-12-10 Швейкин Василий Иванович Injection laser
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
JP3592981B2 (en) 1999-01-14 2004-11-24 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
KR100683877B1 (en) 1999-03-04 2007-02-15 니치아 카가쿠 고교 가부시키가이샤 Nitride Semiconductor Laser Element
GB9905196D0 (en) 1999-03-05 1999-04-28 Fujitsu Telecommunications Eur Aperiodic gratings
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6570898B2 (en) 1999-09-29 2003-05-27 Xerox Corporation Structure and method for index-guided buried heterostructure AlGalnN laser diodes
US6501092B1 (en) 1999-10-25 2002-12-31 Intel Corporation Integrated semiconductor superlattice optical modulator
RU2173003C2 (en) 1999-11-25 2001-08-27 Септре Электроникс Лимитед Method for producing silicon nanostructure, lattice of silicon quantum conducting tunnels, and devices built around them
DE10025264A1 (en) 2000-05-22 2001-11-29 Max Planck Gesellschaft Field effect transistor based on embedded cluster structures and method for its production
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6521549B1 (en) 2000-11-28 2003-02-18 Lsi Logic Corporation Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6690699B2 (en) 2001-03-02 2004-02-10 Lucent Technologies Inc Quantum cascade laser with relaxation-stabilized injection
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
AU2003222003A1 (en) 2002-03-14 2003-09-29 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6816530B2 (en) 2002-09-30 2004-11-09 Lucent Technologies Inc. Nonlinear semiconductor light sources
US7023010B2 (en) 2003-04-21 2006-04-04 Nanodynamics, Inc. Si/C superlattice useful for semiconductor devices
US7202494B2 (en) * 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311050A (en) * 1990-11-30 1994-05-10 Kabushiki Kaisha Toshiba Semiconductor vertical MOSFET inverter circuit
US20050272239A1 (en) * 2003-06-26 2005-12-08 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MIYANO S ET AL: "NUMERICAL ANALYSIS OF A CYLINDRICAL THIN-PILLAR TRANSISTOR (CYNTHIA)", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 39, no. 8, August 1992 (1992-08-01), IEEE, New York, NY, USA, pages 1876 - 1881, XP000294798, ISSN: 0018-9383 *
RISCH L ET AL: "VERTICAL MOS TRANSISTORS WITH 70NM CHANNEL LENGTH", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 43, no. 9, September 1996 (1996-09-01), IEEE, New York, NY, USA, pages 1495 - 1498, XP000636266, ISSN: 0018-9383 *

Also Published As

Publication number Publication date
US20080179664A1 (en) 2008-07-31
TW200837950A (en) 2008-09-16
US7781827B2 (en) 2010-08-24

Similar Documents

Publication Publication Date Title
US7781827B2 (en) Semiconductor device with a vertical MOSFET including a superlattice and related methods
CN111133582B (en) Method for manufacturing semiconductor device having embedded insulating layer formed by annealing superlattice
EP3218937B1 (en) Method of manufacturing a semiconductor device including a superlattice and replacement metal gate structure
US9406753B2 (en) Semiconductor devices including superlattice depletion layer stack and related methods
EP3776073A1 (en) Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
WO2019199926A1 (en) Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
EP3072158A1 (en) Vertical semiconductor devices including superlattice punch through stop layer and related methods
WO2007098138A2 (en) Semiconductor device comprising a lattice matching layer and associated methods
EP1941548A1 (en) Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods
AU2006270126A1 (en) Semiconductor device including a channel with a non-semiconductor monolayer and associated methods
AU2006265096A1 (en) Semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer and associated methods
US20220376047A1 (en) Semiconductor device including a superlattice providing metal work function tuning
AU2006295395A1 (en) Field-effect semiconductor device including superlattice regions
CA2612127A1 (en) Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods
CN114258594A (en) Semiconductor device having a hyperabrupt junction region including a superlattice and related methods
CN114258593A (en) Semiconductor device having hyperabrupt junction regions with spaced superlattices and related methods
CN114270535A (en) Varactor having a hyperabrupt junction region including a superlattice and related methods
CN114270534A (en) Varactor having hyperabrupt junction regions with spaced superlattices and related methods
AU2006270324A1 (en) Semiconductor device including a strained superlattice and overlying stress layer and related methods
CA2612118A1 (en) Semiconductor device including a strained superlattice layer above a stress layer and associated methods

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08713958

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08713958

Country of ref document: EP

Kind code of ref document: A1