WO2008063761A3 - Method of packaging a device using a dielectric layer - Google Patents

Method of packaging a device using a dielectric layer Download PDF

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Publication number
WO2008063761A3
WO2008063761A3 PCT/US2007/080523 US2007080523W WO2008063761A3 WO 2008063761 A3 WO2008063761 A3 WO 2008063761A3 US 2007080523 W US2007080523 W US 2007080523W WO 2008063761 A3 WO2008063761 A3 WO 2008063761A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric layer
major surface
packaging
encapsulant
sides
Prior art date
Application number
PCT/US2007/080523
Other languages
French (fr)
Other versions
WO2008063761A2 (en
Inventor
Marc A Mangrum
Kenneth R Burch
Original Assignee
Freescale Semiconductor Inc
Marc A Mangrum
Kenneth R Burch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Marc A Mangrum, Kenneth R Burch filed Critical Freescale Semiconductor Inc
Priority to CN2007800395574A priority Critical patent/CN101530012B/en
Priority to JP2009537256A priority patent/JP2010510665A/en
Publication of WO2008063761A2 publication Critical patent/WO2008063761A2/en
Publication of WO2008063761A3 publication Critical patent/WO2008063761A3/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
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    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

A method is for packaging a first device (14, 46) having a first major surface and a second major surface. An encapsulant (18) is formed over a second major surface of the first device (14, 46) and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer (20) is formed over the first major surface of the first device (14). a side contact interface (36, 16; 48, 56, 46; 48, 56, 70, 72) is formed having at least a portion over the first dielectric layer (20). The encapsulant (18) is cut to form a plurality of sides of encapsulant (62, 64). A portion of the encapsulant (18) is removed along a first side (64) of the plurality of sides to expose a portion of the side contact interface (72, 46, 16) along the first side of the plurality of sides.
PCT/US2007/080523 2006-11-17 2007-10-05 Method of packaging a device using a dielectric layer WO2008063761A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2007800395574A CN101530012B (en) 2006-11-17 2007-10-05 Method of packaging a device using a dielectric layer
JP2009537256A JP2010510665A (en) 2006-11-17 2007-10-05 Method for packaging a device using a dielectric layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/561,241 US7476563B2 (en) 2006-11-17 2006-11-17 Method of packaging a device using a dielectric layer
US11/561,241 2006-11-17

Publications (2)

Publication Number Publication Date
WO2008063761A2 WO2008063761A2 (en) 2008-05-29
WO2008063761A3 true WO2008063761A3 (en) 2008-08-14

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PCT/US2007/080523 WO2008063761A2 (en) 2006-11-17 2007-10-05 Method of packaging a device using a dielectric layer

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US (1) US7476563B2 (en)
JP (1) JP2010510665A (en)
CN (1) CN101530012B (en)
TW (1) TWI415240B (en)
WO (1) WO2008063761A2 (en)

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