WO2008063761A2 - Method of packaging a device using a dielectric layer - Google Patents
Method of packaging a device using a dielectric layer Download PDFInfo
- Publication number
- WO2008063761A2 WO2008063761A2 PCT/US2007/080523 US2007080523W WO2008063761A2 WO 2008063761 A2 WO2008063761 A2 WO 2008063761A2 US 2007080523 W US2007080523 W US 2007080523W WO 2008063761 A2 WO2008063761 A2 WO 2008063761A2
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- WIPO (PCT)
- Prior art keywords
- forming
- encapsulant
- dielectric layer
- major surface
- sides
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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Definitions
- This invention relates generally to packaging a device, and more specifically, to packaging a device using a dielectric layer.
- PCB printed circuit board
- the PCB with the devices is used in products, such as computers or cellular phones. Since there is a desire to decrease the size of products, such as computers and cellular phones, there is a need to decrease the size of the PCB and the package device without sacrificing functionality. In many cases, additional functionality is desired. For example, it may be desirable to have more than one device in a package. In addition, cost is a concern. Therefore, a need exists for a cost-effective packaging method that can increase functionality.
- FIG. 1 illustrates a cross-section of an aggregated site including a portion of an adhesive, a first device, and a second device in accordance with an embodiment of the invention.
- FIG. 2 illustrates the aggregated site of FIG. 1 after forming an encapsulant over the die and the second device in accordance with one embodiment.
- FIG. 3 illustrates the aggregated site of FIG. 2 after removing the adhesive in accordance with one embodiment.
- FIG. 4 illustrates the aggregated site of FIG. 3 after forming a first dielectric layer in accordance with one embodiment.
- FIG. 5 illustrates the aggregated site of FIG. 4 after forming a via-holes in accordance with one embodiment.
- FIG. 6 illustrates the aggregated site of FIG. 5 after forming vias and interconnects in accordance with one embodiment.
- FIG. 7 illustrates the aggregate site of FIG. 6 after forming the second dielectric layer in accordance with one embodiment.
- FIG. 8 illustrates the aggregate site of FIG. 7 after forming a via-hole in the second dielectric layer in accordance with one embodiment.
- FIG. 9 illustrates the aggregate site of FIG. 8 after forming a third device over the second dielectric layer in accordance with one embodiment.
- FIG. 10 illustrates the aggregate site of FIG. 9 after forming an interconnect in accordance with one embodiment.
- FIG. 11 illustrates the aggregate site of FIG. 10 after forming a layer in accordance with one embodiment.
- FIG. 12 illustrates the aggregate site of FIG. 11 with singulation lines in accordance with one embodiment
- FIG. 13 illustrates the aggregate site of FIG. 12 after cutting along the singulation lines to form minor surfaces in accordance with one embodiment.
- FIG. 14 illustrates the aggregate site of FIG. 13 after removing a portion of the encapsulant and the layer along one of the plurality of sides that were formed when cutting to expose a portion of a side contact interface in accordance with one embodiment.
- FIG. 15 illustrates the minor surface of the aggregate site of FIG. 14 after exposing side contact interfaces in accordance with one embodiment.
- FIG. 16 illustrates an aggregate site with another side contact interface in accordance with one embodiment.
- FIG. 17 illustrates the minor surface of the aggregate site of FIG. 16 in accordance with one embodiment.
- a side contact interface is formed in a package.
- the side contact interface may include a conductive element that is exposed on the side or a minor surface.
- the conductive element may be capable of being aligned with other connectors, such as sockets or similar interface components.
- the side contact interface may include a resistor or capacitor, for example, to enhance the performance of the package.
- the capacitor or resistor may be used to improve electrostatic discharge (ESD) performance or modify impedance.
- the conductive element is a conductive portion of a resistor, capacitor, and an end of an interconnect, a conductive slug, the like, or combinations of the above.
- FIG. 1 illustrates a cross section of an aggregated site 10 including a portion of an adhesive 12, a die 14, and a resistor 16 in accordance with an embodiment of the invention.
- the die 14 includes contacts (e.g., pads) 13, which are exposed on one side (i.e., the front side) of the die 14.
- the resistor 16 includes contacts 15, which extend from one side of the resistor 16 to another.
- the adhesive 12, in one embodiment is a tape.
- the aggregated site 10 is a portion of a panel, which in one embodiment includes a plurality of identical aggregated sites 10 and in another embodiment includes plurality of aggregated sites 10 that are not all identical to each other.
- the panel is formed by placing die that have passed testing requirements, such as electrical, mechanical, or both, (i.e., known good die), discrete devices, the like, or combinations of the above on an adhesive 12.
- die may be placed in an array to form a panel. Any arrangement of the die may be used.
- the die may be arranged in a grid to form a circular shape, much like the arrangement of die on a wafer.
- the panel is essentially reconstructed with known good die.
- the aggregated site 10 will become a (single) package.
- the package will include the die 14 and the resistor 16.
- FIG. 2 illustrates the aggregated site 10 after forming an encapsulant 18 over the die 14 and the resistor 16 in accordance with one embodiment.
- the encapsulant can be epoxy-based and heat curable. In one embodiment, the encapsulant is approximately 300 to approximately 500 microns thick. Because the adhesive 12 is in contact with one side of the die 14 and one side of the resistor 16, the encapsulant 18 is formed on the (five) sides of the die 14 and the resistor 16 that are not in contact with the adhesive 12. In the embodiment shown, the five sides of the die 14 that are in contact with the encapsulant 18 include all sides of the die 14 except the side that has the pads 13 exposed. Hence, the encapsulant 18 is formed over and adjacent the sides of the die 14 and the resistor 16. Thus, the encapsulant 18 is formed between the die 14 and the resistor 16.
- FIG. 3 illustrates the aggregated site 10 after removing the adhesive 12 in accordance with one embodiment.
- the adhesive 12 can be removed using any process, such as heat (e.g., UV (ultraviolet) light and IR (infrared) light), a solvent, the like or combinations of the above.
- heat e.g., UV (ultraviolet) light and IR (infrared) light
- a solvent e.g., IR (infrared) light
- the aggregated site 10 is flipped over so that the pads 13 of the die 14 are on top and exposed.
- FIG. 4 illustrates the aggregated site 10 after forming a first dielectric layer 20 over the die 14 and the resistors 16 in accordance with one embodiment.
- the first dielectric layer 20 may be a conventional spun-on polymer or any other suitable material formed by any suitable process. In one embodiment, the first dielectric layer 10 may be approximately 20 microns thick of a spun-on polymer.
- FIG. 5 illustrates the aggregated site 10 after forming a resistor via-hole 22 and die via-holes 24 in accordance with one embodiment.
- the resistor and die via- holes 22 and 24 are formed by patterning and etching the first dielectric layer 20 to expose at least a portion of one of the contacts 15 and at least a portion of each of the pads 13.
- the resistor via-hole 22 is formed over the contact 15 that is closest to the die 14 (i.e., the inner contact 15).
- a resistor via-hole is not formed in the embodiment illustrated to the other contact 15 (i.e., the outer contact 15) because this contact 15 will be exposed during later processing to form a connector to couple the resistor to an external device.
- FIG. 6 illustrates the aggregated site 10 after forming via 28 to contact 15 of the resistor 16 and die vias 30, 32, and 34 to the die 14 and interconnects 36, 38, and 40 in accordance with one embodiment.
- the vias are conductors formed within the via-holes.
- the material used to fill the resistor and die vias 28, 30, 32, and 34 and form the interconnects 36, 38, and 40 can be any conductive material, such as copper.
- the material can be deposited using any suitable process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, the like, and combinations of the above) to fill the via-holes 22 and 24 and form a thick enough material over the first dielectric layer 20.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the material that lies outside the resistor and die vias 28, 30, 32, and 34 and over the first dielectric layer 20 may be patterned to form the interconnects 36, 38, and 40.
- the interconnect 36 couples the resistor 16 to the die 14 through the resistor via 28 and the die via 30.
- the interconnect 38 travels in a direction that is in and out of the page and may couple the die 14 to other devices that are not illustrated.
- the interconnect 40 travels to the right of the die 14 and in a direction that is in and out of the page and may couple the die 14 to other devices that are not illustrated.
- the length of the interconnects 28 and 40 need not be the same.
- the interconnects 36, 38, and 40 illustrated in FIG. 6 are merely examples of the interconnects that can be formed.
- FIG. 7 illustrates the aggregate site 10 after forming the second dielectric layer 42.
- the second dielectric layer 42 may be a spun-on polymer or another suitable material.
- the second dielectric layer 42 may be the same material or a different material than the first dielectric layer 20 and may or may not be formed by the same process as the first dielectric layer 20.
- the second dielectric layer 42 is formed over the interconnects 36, 38, and 40. In one embodiment, the second dielectric layer 42 is approximately 20 microns thick.
- FIG. 8 illustrates the aggregate site 10 after forming a via-hole 44 in the second dielectric layer 42 in accordance with one embodiment.
- the via-hole 44 may be formed by patterning and etching the second dielectric layer 42.
- the via-hole 44 in the embodiment illustrated, exposes at least a portion of the interconnect 38.
- the via-hole 44 can be formed over another interconnect, such as the interconnect 40.
- FIG. 9 illustrates the aggregate site 10 after forming a resistor 46 over the second dielectric layer 42 in accordance with on embodiment.
- the resistor 46 includes contacts 45, which are similar to the contacts 15 of the resistor 16.
- the resistor 46 may be placed using a pick-and-place tool over and approximately in-line with the resistor 16. In this embodiment, the ends of the contact 45 and the ends of the contacts 15 are approximately in line with each other.
- Conventional pick-and- place tools can place the resistor 46 within approximately 10 or less microns of a predetermined location and therefore the resistors 46 and 16 may be substantially in line with each other. However, the resistors 46 and 16 may not be in line with each other.
- FIG. 10 illustrates the aggregate site 10 after forming an interconnect 50 in accordance with one embodiment.
- the interconnect 50 may be any conductive material, such as copper.
- a material is deposited (e.g., by CVD, ALD, plating, the like, or combinations of the above) and then patterned.
- the interconnect 50 couples the resistor 46 (i.e., its inner contact 45) to the die 14 through vias 48 and 32, contacts 14 and 45, and the interconnect 38.
- the via 48 is formed by patterning the second dielectric layer 42, forming a conductive material over the aggregate site 10 and patterning the conductive material to form the via 48.
- the via 48 in one embodiment, is formed before placing the resistor 46 and in another embodiment, it is formed after placing the resistor 46.
- a photoresist layer such as a thick film type, may be formed over the aggregate site 10 covering the resistor 46 but exposing the contact 45 that will be coupled to the subsequently formed interconnect 50. The photoresist may define the trace routing for the aggregate site 10.
- a conductive material such as copper, is formed. Even if the resistor 46 is not covered by the photoresist layer the conductive material may not adhere to it if the resistor 46, for example, has a ceramic body. Next, the photoresist can be removed to form the interconnect 50.
- FIG. 11 illustrates the aggregate site 10 after forming a layer 52 in accordance with one embodiment.
- the layer 52 may be formed by the same processes and be of the same materials as the second dielectric layer 42 or the first dielectric layer 20.
- the third dielectric layer 20 is an encapsulant material.
- FIG. 12 illustrates the aggregate site 10 with singulation lines 54 and 56 in accordance with one embodiment.
- the singulation line 54 singulates the aggregate site 10 near the resistors 16 and 46, but does not expose the resistors 16 and 46.
- the singulation line 54 singulates the aggregate site within 0.025 inches of the closest edge of the resistors 16 and 46.
- the singulation is within the accuracy limits of the singulation and placement processes. The singulation can occur by any process, such as with a saw, laser or other means.
- the singulation line 56 cuts the aggregate site 10 near the die 14, but does not expose the die 14.
- the encapsulant 18 (and the third dielectric layer 20 if it is an encapsulant) is cut to form a plurality of sides of the encapsulant 18 (and the third dielectric layer 20 if is an encapsulant).
- FIG. 13 illustrates the aggregate site 10 after cutting along the singulation lines 54 and 56 to form minor surfaces 64 and 62 in accordance with an embodiment.
- the aggregate site 10 has major surfaces 58 and 60 and minor surfaces 62 and 64.
- the major surfaces 58 and 60 are opposite each other and the minor surfaces 62 and 64 are opposite each other.
- the major surface 58 is the top of the aggregate site 10 and the major surface 60 is the bottom of the aggregate site 10.
- the minor surfaces 62 and 64 are the edges of the aggregate site 10.
- FIG. 14 illustrates the aggregate site 10 after removing a portion of the encapsulant 18 and the layer 52 along one of the plurality of sides that were formed when cutting to expose a portion of a side contact interface in accordance with one embodiment.
- the removal can occur by various processes, such as with a laser or by etching away portions of the encapsulant 18 and the dielectric layer 52.
- the first side contact interface includes the interconnect 36, the resistor via 28, and the resistor 16.
- the first side contact interface is exposed along a minor surface 64 of the aggregate site 10, which is now a package, and coupled to the die 14, which is surrounded on five sides by encapsulant, through the die via 30.
- the second side contact interface includes the interconnect 38, the via 48, the interconnect 50, and the resistor 46.
- the second side contact interface is coupled to the die 14 through the die via 32.
- the side contact interfaces are exposed along a minor surface 64 and are coupled to a device, such as the die 14, through a via; any additional vias or interconnects that are used for the coupling are part of the side contact interface.
- FIG. 15 illustrates the minor surface 64 of the aggregate site 10 after exposing side contact interfaces.
- the multiple contacts 15 and 45 together form a connector (or multiple connectors) that can be used to couple the package 10 to another device.
- the package 10 can be coupled via the connector to a cell phone, a computer, or another device.
- FIG. 16 illustrates the aggregate site 10, which is a package at this stage, with an external interconnect 72 in accordance with another embodiment.
- the aggregate site 10 does not include the resistor 16.
- the interconnect 36 is not coupled to the resistor 16 and instead, may be coupled to another device (not shown) in the aggregate site 10. Alternatively, the interconnect 36 may not be present.
- the aggregate site 10 includes an external interconnect 72 that is coupled to the resistor 46. In the embodiment illustrated, the external interconnect 72 is coupled to the contact 45 that is closest to the edge of the aggregate site 10 (i.e., the outer contact 45) through a resistor via 70.
- the resistor via 70 and the external interconnect 72 can be formed by patterning the layer 52 to form a resistor via-hole and then filling the via-hole with a conductive material, such as copper.
- the conductive material is formed over the layer 52.
- the conductive material that is over the layer 52 may then be patterned to form the external interconnect 72.
- a layer 74 which can be any dielectric layer or an encapsulant, is formed.
- the side contact interface includes the interconnect 50, the resistor 46 (with its contacts 45), the via 70, and the external interconnect 72.
- the aggregate site 10 is cut as in FIG. 12. As shown in FIG. 16, the aggregate site 10 can be cut to expose the external interconnect 72.
- a portion of the external interconnect 72 is removed during the cutting process. It is preferable, that the cutting does not remove a portion of the resistor 46. Hence, the resistor 46 and the external interconnect 72 may be staggered, as shown in FIG. 16. After cutting the aggregate site 10 to form the package, portions of a dielectric or encapsulant may not be removed. In other words, the resistor 46 may not be exposed. The major portion 58 is now over the layer 74, not the layer 52.
- FIG. 17 illustrates the minor surface 64 of the aggregate site 10 after exposing the external interconnect 72 in accordance with one embodiment.
- the resistor 46 is not exposed.
- the resistor(s) 46 are exposed along with the external interconnect 72.
- the plurality of external interconnect 72 are used as the connector interface.
- the resistor(s) 46 are not part of the connector interface because they are not exposed.
- the resistor(s) 46 are part of the connector interface in the embodiment illustrated, because the resistor(s) 46 are coupled to the external interconnect.
- the resistor(s) 46 are not present and hence, the external interconnect is coupled to the interconnect 50 without a resistor.
- the resistors 16 and 46 can be other elements such as capacitors, inductors, conductive slugs, the like, or combinations of the above.
- the exposed portion of the side contact interface that is used as a connector or part of a connector can be a portion (e.g., an end portion) of an interconnect.
- FIGs. 9-15 illustrate two resistors (resistors 16 and 46) any number of resistors may be used. For example, only one resistor may be present.
- the resistor 16 is in the same horizontal plane or layer as the die 14, the resistor 16 can be in a different layer than the die 14.
- the resistor 16 can be in a layer above the die 14 or the die 14 can be in a layer above the resistor 16.
- the resistors 16 and 46 are in different layers, they can be in the same layer as each other.
- the singulation line 54 is chosen so that the resistors 16 and 46 are not exposed after the cutting process.
- the singulation line 54 can be chosen so that the resistors 16 and 46 are exposed after the cutting process.
- portions of the contacts 15 and 45 may be removed during the cutting process.
- portions of the encapsulant 18 and the layer 52 are removed.
- portions of the dielectric layers 20 and 42 and additional portions of the encapsulant 18 and the layers 52 are removed.
- solder balls or other external connections may be formed on the major surfaces 58 and 60 or minor surfaces 62 and 64 of the package. In one embodiment, solder balls are formed on the major surface 60 and the side contact interface is coupled to an antennae because the side contact interfaces is a shorter electrical path out of the package than the solder balls.
- any number of die, discrete devices (e.g., resistors, etc.), conductive plugs, the like, or combinations of the above can be formed in the package. The number of resistors and die illustrated in the figures are for illustration purposes only.
- only one die may be formed in the package and have a side contact interface that may or may not include a discrete device, such as resistors.
- the side contact interface may be flush or recessed with respect to the minor surfaces 64 or 62.
- each one can be flush or recessed any distance and they all need not be flush or recessed the same distance.
- side contact interfaces are only shown exposed on the minor surface 62, side contact interface(s) may be exposed on the minor surface 64 alternatively or in addition to those exposed on the minor surface 62.
- side contact interfaces illustrated are only examples of various side contact interfaces.
- a side contact interface is exposed on a minor surface of the package.
- the side contact interface may terminate with an interconnect, resistor, capacitor, inductor, slug, or the like.
- the side contact interface allows for electrical connections at the edge of the package.
- the side contact interface is coupled to a device within the package and is capable of being coupled to an external device. For example, a user may plug an external device into the side contact interface.
- the resulting package may be a redistributed chip package (RCP) because the interconnects are routed or redistributed among one or more layers to minimize the area of the package.
- RCP redistributed chip package
Abstract
Description
Claims
Priority Applications (2)
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JP2009537256A JP2010510665A (en) | 2006-11-17 | 2007-10-05 | Method for packaging a device using a dielectric layer |
CN2007800395574A CN101530012B (en) | 2006-11-17 | 2007-10-05 | Method of packaging a device using a dielectric layer |
Applications Claiming Priority (2)
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US11/561,241 | 2006-11-17 | ||
US11/561,241 US7476563B2 (en) | 2006-11-17 | 2006-11-17 | Method of packaging a device using a dielectric layer |
Publications (2)
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WO2008063761A2 true WO2008063761A2 (en) | 2008-05-29 |
WO2008063761A3 WO2008063761A3 (en) | 2008-08-14 |
Family
ID=39417421
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PCT/US2007/080523 WO2008063761A2 (en) | 2006-11-17 | 2007-10-05 | Method of packaging a device using a dielectric layer |
Country Status (5)
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US (1) | US7476563B2 (en) |
JP (1) | JP2010510665A (en) |
CN (1) | CN101530012B (en) |
TW (1) | TWI415240B (en) |
WO (1) | WO2008063761A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US7476563B2 (en) | 2009-01-13 |
TW200832665A (en) | 2008-08-01 |
CN101530012A (en) | 2009-09-09 |
JP2010510665A (en) | 2010-04-02 |
WO2008063761A3 (en) | 2008-08-14 |
CN101530012B (en) | 2012-07-04 |
TWI415240B (en) | 2013-11-11 |
US20080119013A1 (en) | 2008-05-22 |
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