WO2008060455A3 - Methods for nanowire alignment and deposition - Google Patents

Methods for nanowire alignment and deposition Download PDF

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Publication number
WO2008060455A3
WO2008060455A3 PCT/US2007/023625 US2007023625W WO2008060455A3 WO 2008060455 A3 WO2008060455 A3 WO 2008060455A3 US 2007023625 W US2007023625 W US 2007023625W WO 2008060455 A3 WO2008060455 A3 WO 2008060455A3
Authority
WO
WIPO (PCT)
Prior art keywords
nanowires
methods
provides methods
deposition
energizing
Prior art date
Application number
PCT/US2007/023625
Other languages
French (fr)
Other versions
WO2008060455A2 (en
Inventor
Samuel Martin
Xiangfeng Duan
Katsumasa Fujii
James M Hamilton
Hiroshi Iwata
Francisco Leon
Jeffrey Miller
Tetsu Negishi
Hiroshi Ohki
J Wallace Parce
Cheri X Y Pereira
Paul John Schuele
Akihide Shibata
David P Stumbo
Yasunobu Okada
Original Assignee
Nanosys Inc
Sharp Kk
Samuel Martin
Xiangfeng Duan
Katsumasa Fujii
James M Hamilton
Hiroshi Iwata
Francisco Leon
Jeffrey Miller
Tetsu Negishi
Hiroshi Ohki
J Wallace Parce
Cheri X Y Pereira
Paul John Schuele
Akihide Shibata
David P Stumbo
Yasunobu Okada
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanosys Inc, Sharp Kk, Samuel Martin, Xiangfeng Duan, Katsumasa Fujii, James M Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J Wallace Parce, Cheri X Y Pereira, Paul John Schuele, Akihide Shibata, David P Stumbo, Yasunobu Okada filed Critical Nanosys Inc
Priority to JP2009533413A priority Critical patent/JP5009993B2/en
Publication of WO2008060455A2 publication Critical patent/WO2008060455A2/en
Publication of WO2008060455A3 publication Critical patent/WO2008060455A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95053—Bonding environment
    • H01L2224/95085—Bonding environment being a liquid, e.g. for fluidic self-assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/84—Manufacture, treatment, or detection of nanostructure
    • Y10S977/882—Assembling of separate components, e.g. by attaching
    • Y10S977/883—Fluidic self-assembly, FSA

Abstract

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
PCT/US2007/023625 2006-11-09 2007-11-09 Methods for nanowire alignment and deposition WO2008060455A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009533413A JP5009993B2 (en) 2006-11-09 2007-11-09 Nanowire arrangement method and deposition method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US85776506P 2006-11-09 2006-11-09
US60/857,765 2006-11-09
US92405707P 2007-04-27 2007-04-27
US60/924,057 2007-04-27

Publications (2)

Publication Number Publication Date
WO2008060455A2 WO2008060455A2 (en) 2008-05-22
WO2008060455A3 true WO2008060455A3 (en) 2008-11-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/023625 WO2008060455A2 (en) 2006-11-09 2007-11-09 Methods for nanowire alignment and deposition

Country Status (4)

Country Link
US (2) US7968474B2 (en)
JP (1) JP5009993B2 (en)
TW (1) TWI463713B (en)
WO (1) WO2008060455A2 (en)

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