WO2008057692A3 - System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop - Google Patents

System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop Download PDF

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Publication number
WO2008057692A3
WO2008057692A3 PCT/US2007/080772 US2007080772W WO2008057692A3 WO 2008057692 A3 WO2008057692 A3 WO 2008057692A3 US 2007080772 W US2007080772 W US 2007080772W WO 2008057692 A3 WO2008057692 A3 WO 2008057692A3
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WO
WIPO (PCT)
Prior art keywords
stop
nanoscale
providing
highly selective
layer
Prior art date
Application number
PCT/US2007/080772
Other languages
French (fr)
Other versions
WO2008057692A2 (en
Inventor
Darwin G Enicks
Original Assignee
Atmel Corp
Darwin G Enicks
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp, Darwin G Enicks filed Critical Atmel Corp
Publication of WO2008057692A2 publication Critical patent/WO2008057692A2/en
Publication of WO2008057692A3 publication Critical patent/WO2008057692A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Abstract

A method for forming an etch- stop layer and a resulting structure (500) fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full- width half -maximum (FWHM) thickness value (501, 503) of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.
PCT/US2007/080772 2006-10-26 2007-10-09 System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop WO2008057692A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/553,313 2006-10-26
US11/553,313 US7569913B2 (en) 2006-10-26 2006-10-26 Boron etch-stop layer and methods related thereto

Publications (2)

Publication Number Publication Date
WO2008057692A2 WO2008057692A2 (en) 2008-05-15
WO2008057692A3 true WO2008057692A3 (en) 2008-07-03

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/080772 WO2008057692A2 (en) 2006-10-26 2007-10-09 System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop

Country Status (3)

Country Link
US (2) US7569913B2 (en)
TW (1) TW200828431A (en)
WO (1) WO2008057692A2 (en)

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US8173526B2 (en) 2006-10-31 2012-05-08 Atmel Corporation Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator
US8530934B2 (en) 2005-11-07 2013-09-10 Atmel Corporation Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto

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US20070054460A1 (en) * 2005-06-23 2007-03-08 Atmel Corporation System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop
US20080050883A1 (en) * 2006-08-25 2008-02-28 Atmel Corporation Hetrojunction bipolar transistor (hbt) with periodic multilayer base
US20060292809A1 (en) * 2005-06-23 2006-12-28 Enicks Darwin G Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection
US20070102834A1 (en) * 2005-11-07 2007-05-10 Enicks Darwin G Strain-compensated metastable compound base heterojunction bipolar transistor
US20070148890A1 (en) * 2005-12-27 2007-06-28 Enicks Darwin G Oxygen enhanced metastable silicon germanium film layer
US20070262295A1 (en) * 2006-05-11 2007-11-15 Atmel Corporation A method for manipulation of oxygen within semiconductor materials
US7495250B2 (en) * 2006-10-26 2009-02-24 Atmel Corporation Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto
US7569913B2 (en) 2006-10-26 2009-08-04 Atmel Corporation Boron etch-stop layer and methods related thereto
US8148230B2 (en) * 2009-07-15 2012-04-03 Sandisk 3D Llc Method of making damascene diodes using selective etching methods
JP5554142B2 (en) * 2010-05-14 2014-07-23 株式会社豊田中央研究所 Method for vapor phase growth of semiconductor film
EP2617050A2 (en) * 2010-09-15 2013-07-24 Praxair Technology, Inc. Method for extending lifetime of an ion source
CN103890906B (en) * 2011-08-15 2017-06-09 阿卜杜拉国王科技大学 For the method for the flexible silicon base of manufacturing machine
KR102131581B1 (en) * 2012-03-27 2020-07-08 노벨러스 시스템즈, 인코포레이티드 Tungsten feature fill
US9466729B1 (en) 2015-05-08 2016-10-11 Qualcomm Incorporated Etch stop region based fabrication of bonded semiconductor structures
US20170148726A1 (en) * 2015-11-03 2017-05-25 Applied Materials, Inc. Semiconductor processing method and semiconductor device
US10163719B2 (en) * 2015-12-15 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming self-alignment contact
US9842913B1 (en) 2016-05-18 2017-12-12 Globalfoundries Inc. Integrated circuit fabrication with boron etch-stop layer
US10249538B1 (en) 2017-10-03 2019-04-02 Globalfoundries Inc. Method of forming vertical field effect transistors with different gate lengths and a resulting structure

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Cited By (3)

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US8173526B2 (en) 2006-10-31 2012-05-08 Atmel Corporation Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator

Also Published As

Publication number Publication date
US7569913B2 (en) 2009-08-04
US20080099840A1 (en) 2008-05-01
WO2008057692A2 (en) 2008-05-15
US20080237716A1 (en) 2008-10-02
TW200828431A (en) 2008-07-01

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