WO2008035142A1

WO2008035142A1 - Multiple-display device and a method for displaying multiple images

Info

Publication number: WO2008035142A1
Application number: PCT/IB2006/053407
Authority: WO
Inventors: Roman Mostinski; Mark Gutman; Joseph Rabinowicz; Leonid Smolyansky; Edward Vaiberman
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2006-09-20
Filing date: 2006-09-20
Publication date: 2008-03-27

Abstract

A multiple-display device (10), the device (10) includes multiple displays (300(1)- 300 (m)), a memory unit (20) adapted to store a group of images representations characterized by different initial image representation formats, and a multiple-display controller (100) that is connected to the multiple displays (300(1)- 300 (m)) by a shared data bus (250) and by multiple control buses (260(1)- 260 (m)), wherein each display out of the multiple displays is connected to the multiple- display controller (100) by a dedicated control bus; wherein the multiple-display controller (100) is adapted to: (i) select multiple images representations and to determine multiple target displays; (ii) convert a format of each selected image representation from an input format to an intermediate format; (iii) process intermediate formatted selected images representations, (iv) convert a format of each processed selected image representation from the intermediate format to a display compatible format that corresponds to a target display on which the processed selected image is to be displayed; such as to provide multiple output image representations; and (v) control a provision of each output image representation over the shared bus (250) while sending control signals to the target displays over the multiple control buses.

Description

MULTIPLE-DISPLAY DEVICE AND A METHOD FOR DISPLAYING

MULTIPLE IMAGES

FIELD OF THE INVENTION

The invention relates to a multiple-display device and to methods for displaying multiple images on multiple displays .

BACKGROUND OF THE INVENTION

Mobile devices such as mobile phones, media players and the like are required to display a large amount of information of various types. Multiple image data formats, multiple displays and multiple frame image memory units dramatically increase the complexity, die real-estate and cost of image storage, image processing and display.

The costs of mobile devices are expected to decrease while they are supposed to support more and more functions .

There is a need to provide efficient methods for displaying multiple images on multiple displays.

SUMMARY OF THE PRESENT INVENTION

A method for displaying multiple images on multiple displays and a multiple-display device, as described in the accompanying claims .

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:

FIG. 1 illustrates a device according to an embodiment of the invention; FIG. 2 is a timing diagram of multiple control and data signals that propagate over a shared data bus and multiple control busses, according to an embodiment of the invention; and FIG. 3 is a flow chart of a method for displaying multiple images on multiple displays, according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS The following figures illustrate exemplary embodiments of the invention. They are not intended to limit the scope of the invention but rather assist in understanding some of the embodiments of the invention. It is further noted that all the figures are out of scale.

FIG. 1 illustrates multiple-display device 10, according to an embodiment of the invention.

Multiple-display device 10 includes multiple displays 300(1)- 300 (m) , a memory unit 20 and a multiple- display controller 100. Multiple-display controller 100 is connected between memory unit 20 and between multiple displays 300(1)- 300 (m) . Multiple-display controller 100 is connected to multiple displays 300(1)- 300 (m) by shared data bus 250 and is also connected to each display by a dedicated control bus out of multiple control buses 260 (I)- 260 (m) .

Storage unit 20 is adapted to store a group of images representations characterized by different initial image representation formats. Accordingly, at least two images are represented by different formats.

Multiple-display controller 100 is adapted to: (i) Select multiple images representations out of the stored image representations, and to determine multiple target displays. The target displays are selected from multiple displays 300(1)- 300 (m) . The determination includes determining which images will be eventually displayed on which displays, (ii) Convert a format of each selected image representation from an input format to an intermediate format, (iii) Process intermediate formatted selected images representations, (iv) Convert a format of each processed selected image representation from the intermediate format to a display compatible format that corresponds to a target display on which the processed selected image is to be displayed; such as to provide multiple output image representations, (v) Control a provision of each output image representation over the shared bus while sending control signals to the target displays over the multiple control buses.

Multiple-display controller 100 includes DMA engine 110, programmable format converter 120, multiple input storage components 130(1) - 130 (n) , pixel processor 140, output storage components 150 (1) - 150 (m) , pixel formatter 160, output multiplexer 170, multiple display timing controllers (200(1)- 200 (m) ), display synchronizer 180, controller 190 and control multiplexer 210.

DMA engine 110 is connected between memory unit 20 and programmable format converter 120. Multiple input storage components 130 (1) - 130 (n) are connected between the programmable format converter 120 and pixel processor 140. Pixel processor is also connected to multiple output storage components 150 (1) - 150 (m) . Output multiplexer 170 is connected between pixel formatter 160 and multiple output storage components 150 (1) - 150 (m) .

It is noted that the number (n) of input storage components 130 (1) - 130 (n) can differ from the number (m) of the output storage components 150 (1) - 150 (m) . Controller 190 is connected to DMA engine 110, to programmable format converter 120, to multiple display timing controllers 200(1)- 200 (m) and to synchronizer 180. Synchronizer 180 can receive indications from various storage components that indicate their status- whether an input storage component is empty and whether an output storage component stores valid data. In response the DMA engine 110 can be instructed to fetch data, the pixel processor 140 can be requested to process image representation and sent it to an output memory components, and the like. Either one of the storage components can be a FIFO, but this is not necessarily so.

Controller 190 is adapted to coordinate the operation of the various circuits of Multiple-display controller 100. It can determine which images will be eventually displayed on which displays and send control signals accordingly. These control signal can indicate, for example, the following: (i) Which image representation will be fetched, by DMA engine 110, from memory unit, (ii) Which image processing process to apply on the image representation, (iii) Which timing signals should be sent, by multiple display timing controllers 200(1)- 200 (m). The controller 190 also determines when each of the mentioned above operations should occur. Multiple-display controller 100 can fetch and process multiple image representations simultaneously. The image processing is done after image representation format is converted to an intermediate format. Pixel processor 140 is adapted to process, at high speed, multiple image representations. Pixel processor 140 provides multiple processed image representations to multiple output storage components 150(1)- 150 (m) . These output storage components provide these image representations to pixel converter 160 that converts the format of the image representations according to the target display to which these image representations will be sent . Control signals can be sent to different displays by different display timing controllers over different buses. It is noted that at least some of the control signals can be shared between displays or otherwise be conveyed over a shared control bus. The control display multiplexer 210 allows multiplexing control signals over an optional control shared bus. Control display multiplexer 210 also enables to control multiple displays by a single display timing controller, by either sending the same control signals to the multiple displays or by applying time division multiplexing.

Multiple displays 300 (1) -300 (m) receive a section signal (also referred to as chip select signal) that indicates, at each given moment, the target display that is the target of the data representation that propagates over shared bus 250.

Conveniently, Multiple-display controller 100 can cause multiple images that originate from a single image representation to be send to multiple target displays. Accordingly, pixel processor 140 can process a single image representation that will then be sent to multiple output memory components (out of output memory components 150(1)- 150 (m) ). It is noted that displays 200(1)- 200 (m) can include synchronous and asynchronous displays. In order to control these displays the different display timing controllers 200(1)- 200 (m) can be programmed according to the characteristics of these displays. Generating control signals for synchronous and asynchronous displays is known in the art and requires no further explanation.

Pixel processor 140 is adapted to perform at least one of the following operations or a combination thereof: pixel combining, addition of text to an image; color space conversion, gamma correction and image transformation .

The following example will further illustrates the operation of device 10. Assuming, for example, that a first image should be displayed on a synchronized display (for example - display 200 (1) ) and that a second and third images should be displayed on two asynchronous displays (for example - displays 200(2) and 200 (m) ). Accordingly, three initial image representations (IIR1- IIR3) are sent to memory unit 20.

Synchronous display 200 (1) needs to receive in a synchronous manner, control signals such as synchronization signals VSYNC, HSYNC. An output image representation (OIRl) aimed to display 200 (1) should be synchronized to these synchronization signals. Multi- display controller 10 conveniently sends the synchronous display 200 (1) output representations of images according to these synchronization signals, even if it has to stop the provision of image data to an asynchronous display. Additionally or alternatively, multiple-display controller schedules the provision of output image representations in response to the timing of the synchronous signals. This scheduling can allows seamless provision of data to the different displays. Assuming that the second initial input image representation is ready before the first initial input image representation. Controller 100 will retrieve IIR2 from memory unit 20, by DMA engine 110, convert it to a second intermediate format image representation and provide it to pixel processor 140 via one of the input memory components. The result of the processing are sent to an output memory components out of output memory components 150(1)- 150 (m) .

Once second initial image representation is ready it is also fetched, format converted, and processed. It is noted that the provision of the first output image representation to display 200 (1) can interrupt a provision of portions of the second output image representation to display 200(2).

The same applies to the processing of the third initial image representation and its provision to display 200 (m) . Accordingly, controller 10 can execute, substantially in parallel, fetching, conversion to an intermediate format and optionally even pixel processing as well as storage of the pixel processing results of different image representations using different data paths. The timing of pixel formatting and provision of output image representation over shared bus 250 is executed in a serial manner.

FIG. 2 is a timing diagram 380 of multiple control and data signals that propagate over a shared data bus and multiple control busses, according to an embodiment of the invention.

Timing diagram 380 illustrate sixteen clock cycles (cl-cl6) of a clock signal 382, synchronous display data valid signal 384, two asynchronous display control signals 386 and 388, write signal 390 and data signals 392. Synchronous display data valid signal 384 is at a high level during clock cycles cl-c9 and is negated at the beginning of clO.

First asynchronous display control signal 386 is negated between c2-c4. Second asynchronous display control signal 388 is negated between c5-c8.

Write signal 390 is negated during c2, c3, c6, and c8.

FIG. 3 is a flow chart of method 400 for displaying multiple images on multiple displays, according to an embodiment of the invention.

Method starts by stage 410 of storing a group of images representations characterized by different initial image representation formats. It is noted that stage 410 can be followed by stage 420 but can also be executed while other stages of method 400 are executed. Referring to the example set forth in previous drawings, storage unit 20 can receive and then store multiple image representations of different formats. Stage 420 includes selecting multiple images representations and determining multiple target displays. Referring to the example set forth in previous drawings, the determination can be made by controller 190, can be sent to controller 190, and the like. Stage 420 is followed by stage 430 of converting a format of each selected image representation from an input format to an intermediate format. Referring to the example set forth in previous drawings, the conversion is executed by programmable format converter 120. Conveniently, stage 430 of converting is followed by stage 435 of storing intermediate formatted selected images representations in multiple input storage components . Stage 430 is followed by stage 440 of processing intermediate formatted selected images representations. Referring to the example set forth in previous drawings, the processing is executed by pixel processor 140. Conveniently, stage 440 of processing includes: pixel combining, addition of text to an image; color space conversion, gamma correction and image transformation .

Conveniently, stage 440 of applying a second conversion is followed by a stage 445 of storing multiple output image representations at multiple output storage components, each output storage component associated with a single target display.

Referring to the example set forth in previous drawings, the multiple output image representations are stored at output memory components 150(1)- 150 (m) .

Stage 440 is followed by stage 450 of applying a second conversion to convert a format of each processed selected image representation from the intermediate format to a display compatible format that corresponds to a target display on which the processed selected image is to be displayed such as to provide multiple output image representations .

Referring to the example set forth in previous drawings, the conversion is executed by pixel formatter 160.

Stage 450 is followed by stage 460 of providing to a shared bus coupled to the multiple target displays the multiple output image representations while sending control signals to the target displays over multiple control buses.

Referring to the example set forth in previous drawings, image representations are sent over shared bus 250 while control signals are sent over buses 260(1)-

260 (m) to displays 300(1)- 300 (m) .

Conveniently, stage 460 of providing includes generating control signals by multiple display timing controllers, each display timing controller being coupled to a single target display by a dedicated control bus. Referring to the example set forth in previous drawings, the control signals can be generated by multiple display timing controllers 200(1)- 200 (m) . Conveniently, stage 460 of providing includes time division multiplexing between output image representations .

Conveniently, stage 420 of selecting is followed by duplicating a single image representation to provide image representation duplicates. In this case stage 460 of providing includes providing multiple output image representations that originate from the multiple image representation duplicates.

Conveniently, stage 460 of providing includes providing at least one image representation and control signals to at least one synchronous target display and providing at least one image representation and control signals to at least one asynchronous target display.

Variations, modifications, and other implementations of what is described herein will occur to those of ordinary skill in the art without departing from the spirit and the scope of the invention as claimed.

Accordingly, the invention is to be defined not by the preceding illustrative description but instead by the spirit and scope of the following claims.

Claims

WE CLAIM

1. A multiple-display device (10), the device (10) comprises multiple displays (300(1)- 300 (m) ) and a memory unit (20) adapted to store a group of images representations characterized by different initial image representation formats; the multiple-display device (10) is characterized by comprising: a multiple-display controller (100) coupled to the multiple displays (300(1)- 300 (m) ) by a shared data bus (250) and by multiple control buses (260(1)- 260 (m) ) , wherein each display out of the multiple displays is coupled to the multiple-display controller (100) by a dedicated control bus; wherein the multiple-display controller (100) is adapted to:

(i) select multiple images representations and to determine multiple target displays ; (ii) convert a format of each selected image representation from an input format to an intermediate format;

(iii) process intermediate formatted selected images representations, (iv) convert a format of each processed selected image representation from the intermediate format to a display compatible format that corresponds to a target display on which the processed selected image is to be displayed; such as to provide multiple output image representations; and

(v) control a provision of each output image representation over the shared bus (250) while sending control signals to the target displays over the multiple control buses.

2. The device (10) according to claim 1 wherein the multiple-display controller (100) comprises an output multiplexer (170) adapted to multiplex output image representations and to provide, at a given moment, output image representation aimed to a selected target display.

3. The device (10) according to any claim of claims 1-2 wherein the multiple-display controller (100) is adapted to generate multiple output image representations to be displayed by multiple target displays in response to a single input image representation.

4. The device (10) according to any claim of claims 1-3 wherein the multiple-display controller (100) comprises multiple display timing controllers (200(1)- 200 (m) ), each adapted to send control signals to a corresponding target display.

5. The device (10) according to any claim of claims 1-4 wherein the multiple-display controller (100) is adapted to control synchronous target displays and asynchronous target displays.

6. The device (10) according to any claim of claims 1-5 wherein the multiple-display controller (100) comprises a pixel processor (140) coupled between multiple input storage components (130 (1) - 130 (n) ) that store intermediate formatted image representations and between multiple output storage components (150 (1) - 150 (m) ) , each associated with a single target display.

7. The device (10) according to claim 6 wherein the pixel processor (140) is adapted to perform: pixel combining, addition of text to an image; color space conversion, gamma correction and image transformation.

8. The device (10) according to claim 7 wherein an amount of input storage components differs from an amount of output storage components.

9. A method (400) for displaying multiple images, the method (400) comprises storing (410) a group of images representations characterized by different initial image representation formats; the method (400) is characterized by comprising: selecting (420) multiple images representations and determining multiple target displays; converting (430) a format of each selected image representation from an input format to an intermediate format; processing (440) intermediate formatted selected images representations; applying a second conversion (450) to convert a format of each processed selected image representation from the intermediate format to a display compatible format that corresponds to a target display on which the processed selected image is to be displayed such as to provide multiple output image representations; and providing (460) to a shared bus coupled to the multiple target displays the multiple output image representations while sending control signals to the target displays over multiple control buses.

10. The method (400) according to claim 9 wherein the providing (460) comprises time division multiplexing between output image representations.

11. The method (400) according to any claim of claims 9- 10 wherein the selecting (420) is followed by duplicating a single image representation to provide image representation duplicates; and wherein the providing (460) comprises providing multiple output image representations that originate from the multiple image representation duplicates.

12. The method (400) according to any claim of claims 9-

11 wherein the providing (460) comprises generating control signals by multiple display timing controllers, each display timing controller being coupled to a single target display by a dedicated control bus.

13. The method (400) according to any claim of claims 9-

12 wherein the providing (460) comprises providing at least one image representation and control signals to at least one synchronous target display and providing at least one image representation and control signals to at least one asynchronous target display.

14. The method (400) according to any claim of claims 9- 13 converting (430) is followed by storing (435) intermediate formatted selected images representations in multiple input storage components and wherein the stage of processing (440) is followed by a stage of storing multiple output image representations at multiple output storage components, each output storage component associated with a single target display.

15. The method (400) according to claim 14 wherein the processing (440) comprises: pixel combining, addition of text to an image; color space conversion, gamma correction and image transformation.